1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
31 * dwc3_gadget_set_test_mode - enables usb2 test modes
32 * @dwc: pointer to our context structure
33 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
35 * Caller should take care of locking. This function will return 0 on
36 * success or -EINVAL if wrong Test Selector is passed.
38 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
43 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
57 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
63 * dwc3_gadget_get_link_state - gets current state of usb link
64 * @dwc: pointer to our context structure
66 * Caller should take care of locking. This function will
67 * return the link state on success (>= 0) or -ETIMEDOUT.
69 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
75 return DWC3_DSTS_USBLNKST(reg);
79 * dwc3_gadget_set_link_state - sets usb link to a particular state
80 * @dwc: pointer to our context structure
81 * @state: the state to put link into
83 * Caller should take care of locking. This function will
84 * return 0 on success or -ETIMEDOUT.
86 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
92 * Wait until device controller is ready. Only applies to 1.94a and
95 if (dwc->revision >= DWC3_REVISION_194A) {
97 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
98 if (reg & DWC3_DSTS_DCNRD)
108 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
109 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
111 /* set requested state */
112 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
113 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116 * The following code is racy when called from dwc3_gadget_wakeup,
117 * and is not needed, at least on newer versions
119 if (dwc->revision >= DWC3_REVISION_194A)
122 /* wait for a change in DSTS */
125 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
127 if (DWC3_DSTS_USBLNKST(reg) == state)
137 * dwc3_ep_inc_trb - increment a trb index.
138 * @index: Pointer to the TRB index to increment.
140 * The index should never point to the link TRB. After incrementing,
141 * if it is point to the link TRB, wrap around to the beginning. The
142 * link TRB is always at the last TRB entry.
144 static void dwc3_ep_inc_trb(u8 *index)
147 if (*index == (DWC3_TRB_NUM - 1))
152 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
153 * @dep: The endpoint whose enqueue pointer we're incrementing
155 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
157 dwc3_ep_inc_trb(&dep->trb_enqueue);
161 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
162 * @dep: The endpoint whose enqueue pointer we're incrementing
164 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
166 dwc3_ep_inc_trb(&dep->trb_dequeue);
169 void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
170 struct dwc3_request *req, int status)
172 struct dwc3 *dwc = dep->dwc;
174 req->started = false;
175 list_del(&req->list);
178 if (req->request.status == -EINPROGRESS)
179 req->request.status = status;
182 usb_gadget_unmap_request_by_dev(dwc->sysdev,
183 &req->request, req->direction);
186 trace_dwc3_gadget_giveback(req);
189 pm_runtime_put(dwc->dev);
193 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
194 * @dep: The endpoint to whom the request belongs to
195 * @req: The request we're giving back
196 * @status: completion code for the request
198 * Must be called with controller's lock held and interrupts disabled. This
199 * function will unmap @req and call its ->complete() callback to notify upper
200 * layers that it has completed.
202 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
205 struct dwc3 *dwc = dep->dwc;
207 dwc3_gadget_del_and_unmap_request(dep, req, status);
209 spin_unlock(&dwc->lock);
210 usb_gadget_giveback_request(&dep->endpoint, &req->request);
211 spin_lock(&dwc->lock);
215 * dwc3_send_gadget_generic_command - issue a generic command for the controller
216 * @dwc: pointer to the controller context
217 * @cmd: the command to be issued
218 * @param: command parameter
220 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
221 * and wait for its completion.
223 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
230 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
231 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
234 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
235 if (!(reg & DWC3_DGCMD_CMDACT)) {
236 status = DWC3_DGCMD_STATUS(reg);
248 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
256 * dwc3_send_gadget_ep_cmd - issue an endpoint command
257 * @dep: the endpoint to which the command is going to be issued
258 * @cmd: the command to be issued
259 * @params: parameters to the command
261 * Caller should handle locking. This function will issue @cmd with given
262 * @params to @dep and wait for its completion.
264 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
265 struct dwc3_gadget_ep_cmd_params *params)
267 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
268 struct dwc3 *dwc = dep->dwc;
277 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
278 * we're issuing an endpoint command, we must check if
279 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
281 * We will also set SUSPHY bit to what it was before returning as stated
282 * by the same section on Synopsys databook.
284 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
285 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
286 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
288 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
289 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
296 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
297 dwc->link_state == DWC3_LINK_STATE_U2 ||
298 dwc->link_state == DWC3_LINK_STATE_U3);
300 if (unlikely(needs_wakeup)) {
301 ret = __dwc3_gadget_wakeup(dwc);
302 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
307 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
309 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
312 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
313 * not relying on XferNotReady, we can make use of a special "No
314 * Response Update Transfer" command where we should clear both CmdAct
317 * With this, we don't need to wait for command completion and can
318 * straight away issue further commands to the endpoint.
320 * NOTICE: We're making an assumption that control endpoints will never
321 * make use of Update Transfer command. This is a safe assumption
322 * because we can never have more than one request at a time with
323 * Control Endpoints. If anybody changes that assumption, this chunk
324 * needs to be updated accordingly.
326 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
327 !usb_endpoint_xfer_isoc(desc))
328 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
330 cmd |= DWC3_DEPCMD_CMDACT;
332 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
334 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
335 if (!(reg & DWC3_DEPCMD_CMDACT)) {
336 cmd_status = DWC3_DEPCMD_STATUS(reg);
338 switch (cmd_status) {
342 case DEPEVT_TRANSFER_NO_RESOURCE:
345 case DEPEVT_TRANSFER_BUS_EXPIRY:
347 * SW issues START TRANSFER command to
348 * isochronous ep with future frame interval. If
349 * future interval time has already passed when
350 * core receives the command, it will respond
351 * with an error status of 'Bus Expiry'.
353 * Instead of always returning -EINVAL, let's
354 * give a hint to the gadget driver that this is
355 * the case by returning -EAGAIN.
360 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
369 cmd_status = -ETIMEDOUT;
372 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
375 switch (DWC3_DEPCMD_CMD(cmd)) {
376 case DWC3_DEPCMD_STARTTRANSFER:
377 dep->flags |= DWC3_EP_TRANSFER_STARTED;
379 case DWC3_DEPCMD_ENDTRANSFER:
380 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
388 if (unlikely(susphy)) {
389 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
390 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
391 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
397 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
399 struct dwc3 *dwc = dep->dwc;
400 struct dwc3_gadget_ep_cmd_params params;
401 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
404 * As of core revision 2.60a the recommended programming model
405 * is to set the ClearPendIN bit when issuing a Clear Stall EP
406 * command for IN endpoints. This is to prevent an issue where
407 * some (non-compliant) hosts may not send ACK TPs for pending
408 * IN transfers due to a mishandled error condition. Synopsys
411 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
412 (dwc->gadget.speed >= USB_SPEED_SUPER))
413 cmd |= DWC3_DEPCMD_CLEARPENDIN;
415 memset(¶ms, 0, sizeof(params));
417 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
420 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
421 struct dwc3_trb *trb)
423 u32 offset = (char *) trb - (char *) dep->trb_pool;
425 return dep->trb_pool_dma + offset;
428 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
430 struct dwc3 *dwc = dep->dwc;
435 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
436 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
437 &dep->trb_pool_dma, GFP_KERNEL);
438 if (!dep->trb_pool) {
439 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
447 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
449 struct dwc3 *dwc = dep->dwc;
451 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
452 dep->trb_pool, dep->trb_pool_dma);
454 dep->trb_pool = NULL;
455 dep->trb_pool_dma = 0;
458 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
460 struct dwc3_gadget_ep_cmd_params params;
462 memset(¶ms, 0x00, sizeof(params));
464 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
466 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 * dwc3_gadget_start_config - configure ep resources
472 * @dwc: pointer to our controller context structure
473 * @dep: endpoint that is being enabled
475 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
476 * completion, it will set Transfer Resource for all available endpoints.
478 * The assignment of transfer resources cannot perfectly follow the data book
479 * due to the fact that the controller driver does not have all knowledge of the
480 * configuration in advance. It is given this information piecemeal by the
481 * composite gadget framework after every SET_CONFIGURATION and
482 * SET_INTERFACE. Trying to follow the databook programming model in this
483 * scenario can cause errors. For two reasons:
485 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
486 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
487 * incorrect in the scenario of multiple interfaces.
489 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
490 * endpoint on alt setting (8.1.6).
492 * The following simplified method is used instead:
494 * All hardware endpoints can be assigned a transfer resource and this setting
495 * will stay persistent until either a core reset or hibernation. So whenever we
496 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
497 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
498 * guaranteed that there are as many transfer resources as endpoints.
500 * This function is called for each endpoint when it is being enabled but is
501 * triggered only when called for EP0-out, which always happens first, and which
502 * should only happen in one of the above conditions.
504 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
506 struct dwc3_gadget_ep_cmd_params params;
515 memset(¶ms, 0x00, sizeof(params));
516 cmd = DWC3_DEPCMD_DEPSTARTCFG;
519 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
524 struct dwc3_ep *dep = dwc->eps[i];
529 ret = dwc3_gadget_set_xfer_resource(dep);
537 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
539 const struct usb_ss_ep_comp_descriptor *comp_desc;
540 const struct usb_endpoint_descriptor *desc;
541 struct dwc3_gadget_ep_cmd_params params;
542 struct dwc3 *dwc = dep->dwc;
544 comp_desc = dep->endpoint.comp_desc;
545 desc = dep->endpoint.desc;
547 memset(¶ms, 0x00, sizeof(params));
549 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
550 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
552 /* Burst size is only needed in SuperSpeed mode */
553 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
554 u32 burst = dep->endpoint.maxburst;
555 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
558 params.param0 |= action;
559 if (action == DWC3_DEPCFG_ACTION_RESTORE)
560 params.param2 |= dep->saved_state;
562 if (usb_endpoint_xfer_control(desc))
563 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
565 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
566 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
568 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
569 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
570 | DWC3_DEPCFG_STREAM_EVENT_EN;
571 dep->stream_capable = true;
574 if (!usb_endpoint_xfer_control(desc))
575 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
578 * We are doing 1:1 mapping for endpoints, meaning
579 * Physical Endpoints 2 maps to Logical Endpoint 2 and
580 * so on. We consider the direction bit as part of the physical
581 * endpoint number. So USB endpoint 0x81 is 0x03.
583 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
586 * We must use the lower 16 TX FIFOs even though
590 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
592 if (desc->bInterval) {
593 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
594 dep->interval = 1 << (desc->bInterval - 1);
597 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601 * __dwc3_gadget_ep_enable - initializes a hw endpoint
602 * @dep: endpoint to be initialized
603 * @action: one of INIT, MODIFY or RESTORE
605 * Caller should take care of locking. Execute all necessary commands to
606 * initialize a HW endpoint so it can be used by a gadget driver.
608 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
610 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
611 struct dwc3 *dwc = dep->dwc;
616 if (!(dep->flags & DWC3_EP_ENABLED)) {
617 ret = dwc3_gadget_start_config(dep);
622 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (!(dep->flags & DWC3_EP_ENABLED)) {
627 struct dwc3_trb *trb_st_hw;
628 struct dwc3_trb *trb_link;
630 dep->type = usb_endpoint_type(desc);
631 dep->flags |= DWC3_EP_ENABLED;
632 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
634 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
635 reg |= DWC3_DALEPENA_EP(dep->number);
636 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
638 init_waitqueue_head(&dep->wait_end_transfer);
640 if (usb_endpoint_xfer_control(desc))
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
663 if (usb_endpoint_xfer_bulk(desc) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
683 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
684 WARN_ON_ONCE(!dep->resource_index);
688 trace_dwc3_gadget_ep_enable(dep);
693 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
694 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
696 struct dwc3_request *req;
698 dwc3_stop_active_transfer(dep, true);
700 /* - giveback all requests to gadget driver */
701 while (!list_empty(&dep->started_list)) {
702 req = next_request(&dep->started_list);
704 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
707 while (!list_empty(&dep->pending_list)) {
708 req = next_request(&dep->pending_list);
710 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 * __dwc3_gadget_ep_disable - disables a hw endpoint
716 * @dep: the endpoint to disable
718 * This function undoes what __dwc3_gadget_ep_enable did and also removes
719 * requests which are currently being processed by the hardware and those which
720 * are not yet scheduled.
722 * Caller should take care of locking.
724 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
726 struct dwc3 *dwc = dep->dwc;
729 trace_dwc3_gadget_ep_disable(dep);
731 dwc3_remove_requests(dwc, dep);
733 /* make sure HW endpoint isn't stalled */
734 if (dep->flags & DWC3_EP_STALL)
735 __dwc3_gadget_ep_set_halt(dep, 0, false);
737 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
738 reg &= ~DWC3_DALEPENA_EP(dep->number);
739 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
741 dep->stream_capable = false;
743 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
745 /* Clear out the ep descriptors for non-ep0 */
746 if (dep->number > 1) {
747 dep->endpoint.comp_desc = NULL;
748 dep->endpoint.desc = NULL;
754 /* -------------------------------------------------------------------------- */
756 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
757 const struct usb_endpoint_descriptor *desc)
762 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767 /* -------------------------------------------------------------------------- */
769 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
770 const struct usb_endpoint_descriptor *desc)
777 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
778 pr_debug("dwc3: invalid parameters\n");
782 if (!desc->wMaxPacketSize) {
783 pr_debug("dwc3: missing wMaxPacketSize\n");
787 dep = to_dwc3_ep(ep);
790 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
791 "%s is already enabled\n",
795 spin_lock_irqsave(&dwc->lock, flags);
796 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
797 spin_unlock_irqrestore(&dwc->lock, flags);
802 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
810 pr_debug("dwc3: invalid parameters\n");
814 dep = to_dwc3_ep(ep);
817 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
818 "%s is already disabled\n",
822 spin_lock_irqsave(&dwc->lock, flags);
823 ret = __dwc3_gadget_ep_disable(dep);
824 spin_unlock_irqrestore(&dwc->lock, flags);
829 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
832 struct dwc3_request *req;
833 struct dwc3_ep *dep = to_dwc3_ep(ep);
835 req = kzalloc(sizeof(*req), gfp_flags);
839 req->epnum = dep->number;
842 trace_dwc3_alloc_request(req);
844 return &req->request;
847 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
848 struct usb_request *request)
850 struct dwc3_request *req = to_dwc3_request(request);
852 trace_dwc3_free_request(req);
857 * dwc3_ep_prev_trb - returns the previous TRB in the ring
858 * @dep: The endpoint with the TRB ring
859 * @index: The index of the current TRB in the ring
861 * Returns the TRB prior to the one pointed to by the index. If the
862 * index is 0, we will wrap backwards, skip the link TRB, and return
863 * the one just before that.
865 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
870 tmp = DWC3_TRB_NUM - 1;
872 return &dep->trb_pool[tmp - 1];
875 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
877 struct dwc3_trb *tmp;
881 * If enqueue & dequeue are equal than it is either full or empty.
883 * One way to know for sure is if the TRB right before us has HWO bit
884 * set or not. If it has, then we're definitely full and can't fit any
885 * more transfers in our ring.
887 if (dep->trb_enqueue == dep->trb_dequeue) {
888 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
889 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
892 return DWC3_TRB_NUM - 1;
895 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
896 trbs_left &= (DWC3_TRB_NUM - 1);
898 if (dep->trb_dequeue < dep->trb_enqueue)
904 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
905 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
906 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
908 struct dwc3 *dwc = dep->dwc;
909 struct usb_gadget *gadget = &dwc->gadget;
910 enum usb_device_speed speed = gadget->speed;
912 dwc3_ep_inc_enq(dep);
914 trb->size = DWC3_TRB_SIZE_LENGTH(length);
915 trb->bpl = lower_32_bits(dma);
916 trb->bph = upper_32_bits(dma);
918 switch (usb_endpoint_type(dep->endpoint.desc)) {
919 case USB_ENDPOINT_XFER_CONTROL:
920 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
923 case USB_ENDPOINT_XFER_ISOC:
925 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
928 * USB Specification 2.0 Section 5.9.2 states that: "If
929 * there is only a single transaction in the microframe,
930 * only a DATA0 data packet PID is used. If there are
931 * two transactions per microframe, DATA1 is used for
932 * the first transaction data packet and DATA0 is used
933 * for the second transaction data packet. If there are
934 * three transactions per microframe, DATA2 is used for
935 * the first transaction data packet, DATA1 is used for
936 * the second, and DATA0 is used for the third."
938 * IOW, we should satisfy the following cases:
940 * 1) length <= maxpacket
943 * 2) maxpacket < length <= (2 * maxpacket)
946 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
947 * - DATA2, DATA1, DATA0
949 if (speed == USB_SPEED_HIGH) {
950 struct usb_ep *ep = &dep->endpoint;
951 unsigned int mult = 2;
952 unsigned int maxp = usb_endpoint_maxp(ep->desc);
954 if (length <= (2 * maxp))
960 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
963 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
966 /* always enable Interrupt on Missed ISOC */
967 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
970 case USB_ENDPOINT_XFER_BULK:
971 case USB_ENDPOINT_XFER_INT:
972 trb->ctrl = DWC3_TRBCTL_NORMAL;
976 * This is only possible with faulty memory because we
977 * checked it already :)
979 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
980 usb_endpoint_type(dep->endpoint.desc));
983 /* always enable Continue on Short Packet */
984 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
985 trb->ctrl |= DWC3_TRB_CTRL_CSP;
988 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
991 if ((!no_interrupt && !chain) ||
992 (dwc3_calc_trbs_left(dep) == 0))
993 trb->ctrl |= DWC3_TRB_CTRL_IOC;
996 trb->ctrl |= DWC3_TRB_CTRL_CHN;
998 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
999 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1001 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1003 trace_dwc3_prepare_trb(dep, trb);
1007 * dwc3_prepare_one_trb - setup one TRB from one request
1008 * @dep: endpoint for which this request is prepared
1009 * @req: dwc3_request pointer
1010 * @chain: should this TRB be chained to the next?
1011 * @node: only for isochronous endpoints. First TRB needs different type.
1013 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1014 struct dwc3_request *req, unsigned chain, unsigned node)
1016 struct dwc3_trb *trb;
1017 unsigned int length;
1019 unsigned stream_id = req->request.stream_id;
1020 unsigned short_not_ok = req->request.short_not_ok;
1021 unsigned no_interrupt = req->request.no_interrupt;
1023 if (req->request.num_sgs > 0) {
1024 length = sg_dma_len(req->start_sg);
1025 dma = sg_dma_address(req->start_sg);
1027 length = req->request.length;
1028 dma = req->request.dma;
1031 trb = &dep->trb_pool[dep->trb_enqueue];
1034 dwc3_gadget_move_started_request(req);
1036 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1039 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1040 stream_id, short_not_ok, no_interrupt);
1043 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1044 struct dwc3_request *req)
1046 struct scatterlist *sg = req->start_sg;
1047 struct scatterlist *s;
1050 unsigned int remaining = req->request.num_mapped_sgs
1051 - req->num_queued_sgs;
1053 for_each_sg(sg, s, remaining, i) {
1054 unsigned int length = req->request.length;
1055 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1056 unsigned int rem = length % maxp;
1057 unsigned chain = true;
1062 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1063 struct dwc3 *dwc = dep->dwc;
1064 struct dwc3_trb *trb;
1066 req->unaligned = true;
1068 /* prepare normal TRB */
1069 dwc3_prepare_one_trb(dep, req, true, i);
1071 /* Now prepare one extra TRB to align transfer size */
1072 trb = &dep->trb_pool[dep->trb_enqueue];
1073 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1074 maxp - rem, false, 0,
1075 req->request.stream_id,
1076 req->request.short_not_ok,
1077 req->request.no_interrupt);
1079 dwc3_prepare_one_trb(dep, req, chain, i);
1083 * There can be a situation where all sgs in sglist are not
1084 * queued because of insufficient trb number. To handle this
1085 * case, update start_sg to next sg to be queued, so that
1086 * we have free trbs we can continue queuing from where we
1087 * previously stopped
1090 req->start_sg = sg_next(s);
1092 req->num_queued_sgs++;
1094 if (!dwc3_calc_trbs_left(dep))
1099 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1100 struct dwc3_request *req)
1102 unsigned int length = req->request.length;
1103 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1104 unsigned int rem = length % maxp;
1106 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1107 struct dwc3 *dwc = dep->dwc;
1108 struct dwc3_trb *trb;
1110 req->unaligned = true;
1112 /* prepare normal TRB */
1113 dwc3_prepare_one_trb(dep, req, true, 0);
1115 /* Now prepare one extra TRB to align transfer size */
1116 trb = &dep->trb_pool[dep->trb_enqueue];
1117 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1118 false, 0, req->request.stream_id,
1119 req->request.short_not_ok,
1120 req->request.no_interrupt);
1121 } else if (req->request.zero && req->request.length &&
1122 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1123 struct dwc3 *dwc = dep->dwc;
1124 struct dwc3_trb *trb;
1128 /* prepare normal TRB */
1129 dwc3_prepare_one_trb(dep, req, true, 0);
1131 /* Now prepare one extra TRB to handle ZLP */
1132 trb = &dep->trb_pool[dep->trb_enqueue];
1133 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1134 false, 0, req->request.stream_id,
1135 req->request.short_not_ok,
1136 req->request.no_interrupt);
1138 dwc3_prepare_one_trb(dep, req, false, 0);
1143 * dwc3_prepare_trbs - setup TRBs from requests
1144 * @dep: endpoint for which requests are being prepared
1146 * The function goes through the requests list and sets up TRBs for the
1147 * transfers. The function returns once there are no more TRBs available or
1148 * it runs out of requests.
1150 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1152 struct dwc3_request *req, *n;
1154 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1157 * We can get in a situation where there's a request in the started list
1158 * but there weren't enough TRBs to fully kick it in the first time
1159 * around, so it has been waiting for more TRBs to be freed up.
1161 * In that case, we should check if we have a request with pending_sgs
1162 * in the started list and prepare TRBs for that request first,
1163 * otherwise we will prepare TRBs completely out of order and that will
1166 list_for_each_entry(req, &dep->started_list, list) {
1167 if (req->num_pending_sgs > 0)
1168 dwc3_prepare_one_trb_sg(dep, req);
1170 if (!dwc3_calc_trbs_left(dep))
1174 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1175 struct dwc3 *dwc = dep->dwc;
1178 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1183 req->sg = req->request.sg;
1184 req->start_sg = req->sg;
1185 req->num_queued_sgs = 0;
1186 req->num_pending_sgs = req->request.num_mapped_sgs;
1188 if (req->num_pending_sgs > 0)
1189 dwc3_prepare_one_trb_sg(dep, req);
1191 dwc3_prepare_one_trb_linear(dep, req);
1193 if (!dwc3_calc_trbs_left(dep))
1198 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1200 struct dwc3_gadget_ep_cmd_params params;
1201 struct dwc3_request *req;
1206 if (!dwc3_calc_trbs_left(dep))
1209 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1211 dwc3_prepare_trbs(dep);
1212 req = next_request(&dep->started_list);
1214 dep->flags |= DWC3_EP_PENDING_REQUEST;
1218 memset(¶ms, 0, sizeof(params));
1221 params.param0 = upper_32_bits(req->trb_dma);
1222 params.param1 = lower_32_bits(req->trb_dma);
1223 cmd = DWC3_DEPCMD_STARTTRANSFER;
1225 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1226 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1228 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1229 DWC3_DEPCMD_PARAM(dep->resource_index);
1232 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1235 * FIXME we need to iterate over the list of requests
1236 * here and stop, unmap, free and del each of the linked
1237 * requests instead of what we do now.
1240 memset(req->trb, 0, sizeof(struct dwc3_trb));
1241 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1246 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1247 WARN_ON_ONCE(!dep->resource_index);
1253 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1257 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1258 return DWC3_DSTS_SOFFN(reg);
1261 static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1263 if (list_empty(&dep->pending_list)) {
1264 dev_info(dep->dwc->dev, "%s: ran out of requests\n",
1266 dep->flags |= DWC3_EP_PENDING_REQUEST;
1271 * Schedule the first trb for one interval in the future or at
1272 * least 4 microframes.
1274 dep->frame_number += max_t(u32, 4, dep->interval);
1275 __dwc3_gadget_kick_transfer(dep);
1278 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1280 struct dwc3 *dwc = dep->dwc;
1282 if (!dep->endpoint.desc) {
1283 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1288 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1289 &req->request, req->dep->name))
1292 pm_runtime_get(dwc->dev);
1294 req->request.actual = 0;
1295 req->request.status = -EINPROGRESS;
1296 req->direction = dep->direction;
1297 req->epnum = dep->number;
1299 trace_dwc3_ep_queue(req);
1301 list_add_tail(&req->list, &dep->pending_list);
1304 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1305 * wait for a XferNotReady event so we will know what's the current
1306 * (micro-)frame number.
1308 * Without this trick, we are very, very likely gonna get Bus Expiry
1309 * errors which will force us issue EndTransfer command.
1311 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1312 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1313 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1316 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1317 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1318 __dwc3_gadget_start_isoc(dep);
1324 return __dwc3_gadget_kick_transfer(dep);
1327 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1330 struct dwc3_request *req = to_dwc3_request(request);
1331 struct dwc3_ep *dep = to_dwc3_ep(ep);
1332 struct dwc3 *dwc = dep->dwc;
1334 unsigned long flags;
1338 spin_lock_irqsave(&dwc->lock, flags);
1339 ret = __dwc3_gadget_ep_queue(dep, req);
1340 spin_unlock_irqrestore(&dwc->lock, flags);
1345 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1346 struct usb_request *request)
1348 struct dwc3_request *req = to_dwc3_request(request);
1349 struct dwc3_request *r = NULL;
1351 struct dwc3_ep *dep = to_dwc3_ep(ep);
1352 struct dwc3 *dwc = dep->dwc;
1354 unsigned long flags;
1357 trace_dwc3_ep_dequeue(req);
1359 spin_lock_irqsave(&dwc->lock, flags);
1361 list_for_each_entry(r, &dep->pending_list, list) {
1367 list_for_each_entry(r, &dep->started_list, list) {
1372 /* wait until it is processed */
1373 dwc3_stop_active_transfer(dep, true);
1376 * If request was already started, this means we had to
1377 * stop the transfer. With that we also need to ignore
1378 * all TRBs used by the request, however TRBs can only
1379 * be modified after completion of END_TRANSFER
1380 * command. So what we do here is that we wait for
1381 * END_TRANSFER completion and only after that, we jump
1382 * over TRBs by clearing HWO and incrementing dequeue
1385 * Note that we have 2 possible types of transfers here:
1387 * i) Linear buffer request
1388 * ii) SG-list based request
1390 * SG-list based requests will have r->num_pending_sgs
1391 * set to a valid number (> 0). Linear requests,
1392 * normally use a single TRB.
1394 * For each of these two cases, if r->unaligned flag is
1395 * set, one extra TRB has been used to align transfer
1396 * size to wMaxPacketSize.
1398 * All of these cases need to be taken into
1399 * consideration so we don't mess up our TRB ring
1402 wait_event_lock_irq(dep->wait_end_transfer,
1403 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1409 if (r->num_pending_sgs) {
1410 struct dwc3_trb *trb;
1413 for (i = 0; i < r->num_pending_sgs; i++) {
1415 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1416 dwc3_ep_inc_deq(dep);
1419 if (r->unaligned || r->zero) {
1420 trb = r->trb + r->num_pending_sgs + 1;
1421 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1422 dwc3_ep_inc_deq(dep);
1425 struct dwc3_trb *trb = r->trb;
1427 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1428 dwc3_ep_inc_deq(dep);
1430 if (r->unaligned || r->zero) {
1432 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1433 dwc3_ep_inc_deq(dep);
1438 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1445 /* giveback the request */
1447 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1450 spin_unlock_irqrestore(&dwc->lock, flags);
1455 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1457 struct dwc3_gadget_ep_cmd_params params;
1458 struct dwc3 *dwc = dep->dwc;
1461 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1462 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1466 memset(¶ms, 0x00, sizeof(params));
1469 struct dwc3_trb *trb;
1471 unsigned transfer_in_flight;
1474 if (dep->flags & DWC3_EP_STALL)
1477 if (dep->number > 1)
1478 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1480 trb = &dwc->ep0_trb[dep->trb_enqueue];
1482 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1483 started = !list_empty(&dep->started_list);
1485 if (!protocol && ((dep->direction && transfer_in_flight) ||
1486 (!dep->direction && started))) {
1490 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1493 dev_err(dwc->dev, "failed to set STALL on %s\n",
1496 dep->flags |= DWC3_EP_STALL;
1498 if (!(dep->flags & DWC3_EP_STALL))
1501 ret = dwc3_send_clear_stall_ep_cmd(dep);
1503 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1506 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1512 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1514 struct dwc3_ep *dep = to_dwc3_ep(ep);
1515 struct dwc3 *dwc = dep->dwc;
1517 unsigned long flags;
1521 spin_lock_irqsave(&dwc->lock, flags);
1522 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1523 spin_unlock_irqrestore(&dwc->lock, flags);
1528 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1530 struct dwc3_ep *dep = to_dwc3_ep(ep);
1531 struct dwc3 *dwc = dep->dwc;
1532 unsigned long flags;
1535 spin_lock_irqsave(&dwc->lock, flags);
1536 dep->flags |= DWC3_EP_WEDGE;
1538 if (dep->number == 0 || dep->number == 1)
1539 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1541 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1542 spin_unlock_irqrestore(&dwc->lock, flags);
1547 /* -------------------------------------------------------------------------- */
1549 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1550 .bLength = USB_DT_ENDPOINT_SIZE,
1551 .bDescriptorType = USB_DT_ENDPOINT,
1552 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1555 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1556 .enable = dwc3_gadget_ep0_enable,
1557 .disable = dwc3_gadget_ep0_disable,
1558 .alloc_request = dwc3_gadget_ep_alloc_request,
1559 .free_request = dwc3_gadget_ep_free_request,
1560 .queue = dwc3_gadget_ep0_queue,
1561 .dequeue = dwc3_gadget_ep_dequeue,
1562 .set_halt = dwc3_gadget_ep0_set_halt,
1563 .set_wedge = dwc3_gadget_ep_set_wedge,
1566 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1567 .enable = dwc3_gadget_ep_enable,
1568 .disable = dwc3_gadget_ep_disable,
1569 .alloc_request = dwc3_gadget_ep_alloc_request,
1570 .free_request = dwc3_gadget_ep_free_request,
1571 .queue = dwc3_gadget_ep_queue,
1572 .dequeue = dwc3_gadget_ep_dequeue,
1573 .set_halt = dwc3_gadget_ep_set_halt,
1574 .set_wedge = dwc3_gadget_ep_set_wedge,
1577 /* -------------------------------------------------------------------------- */
1579 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1581 struct dwc3 *dwc = gadget_to_dwc(g);
1583 return __dwc3_gadget_get_frame(dwc);
1586 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1597 * According to the Databook Remote wakeup request should
1598 * be issued only when the device is in early suspend state.
1600 * We can check that via USB Link State bits in DSTS register.
1602 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1604 speed = reg & DWC3_DSTS_CONNECTSPD;
1605 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1606 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1609 link_state = DWC3_DSTS_USBLNKST(reg);
1611 switch (link_state) {
1612 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1613 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1619 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1621 dev_err(dwc->dev, "failed to put link in Recovery\n");
1625 /* Recent versions do this automatically */
1626 if (dwc->revision < DWC3_REVISION_194A) {
1627 /* write zeroes to Link Change Request */
1628 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1629 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1630 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1633 /* poll until Link State changes to ON */
1637 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1639 /* in HS, means ON */
1640 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1644 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1645 dev_err(dwc->dev, "failed to send remote wakeup\n");
1652 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1654 struct dwc3 *dwc = gadget_to_dwc(g);
1655 unsigned long flags;
1658 spin_lock_irqsave(&dwc->lock, flags);
1659 ret = __dwc3_gadget_wakeup(dwc);
1660 spin_unlock_irqrestore(&dwc->lock, flags);
1665 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1668 struct dwc3 *dwc = gadget_to_dwc(g);
1669 unsigned long flags;
1671 spin_lock_irqsave(&dwc->lock, flags);
1672 g->is_selfpowered = !!is_selfpowered;
1673 spin_unlock_irqrestore(&dwc->lock, flags);
1678 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1683 if (pm_runtime_suspended(dwc->dev))
1686 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1688 if (dwc->revision <= DWC3_REVISION_187A) {
1689 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1690 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1693 if (dwc->revision >= DWC3_REVISION_194A)
1694 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1695 reg |= DWC3_DCTL_RUN_STOP;
1697 if (dwc->has_hibernation)
1698 reg |= DWC3_DCTL_KEEP_CONNECT;
1700 dwc->pullups_connected = true;
1702 reg &= ~DWC3_DCTL_RUN_STOP;
1704 if (dwc->has_hibernation && !suspend)
1705 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1707 dwc->pullups_connected = false;
1710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1713 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1714 reg &= DWC3_DSTS_DEVCTRLHLT;
1715 } while (--timeout && !(!is_on ^ !reg));
1723 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1725 struct dwc3 *dwc = gadget_to_dwc(g);
1726 unsigned long flags;
1732 * Per databook, when we want to stop the gadget, if a control transfer
1733 * is still in process, complete it and get the core into setup phase.
1735 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1736 reinit_completion(&dwc->ep0_in_setup);
1738 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1739 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1741 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1746 spin_lock_irqsave(&dwc->lock, flags);
1747 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1748 spin_unlock_irqrestore(&dwc->lock, flags);
1753 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1757 /* Enable all but Start and End of Frame IRQs */
1758 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1759 DWC3_DEVTEN_EVNTOVERFLOWEN |
1760 DWC3_DEVTEN_CMDCMPLTEN |
1761 DWC3_DEVTEN_ERRTICERREN |
1762 DWC3_DEVTEN_WKUPEVTEN |
1763 DWC3_DEVTEN_CONNECTDONEEN |
1764 DWC3_DEVTEN_USBRSTEN |
1765 DWC3_DEVTEN_DISCONNEVTEN);
1767 if (dwc->revision < DWC3_REVISION_250A)
1768 reg |= DWC3_DEVTEN_ULSTCNGEN;
1770 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1773 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1775 /* mask all interrupts */
1776 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1779 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1780 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1783 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1784 * @dwc: pointer to our context structure
1786 * The following looks like complex but it's actually very simple. In order to
1787 * calculate the number of packets we can burst at once on OUT transfers, we're
1788 * gonna use RxFIFO size.
1790 * To calculate RxFIFO size we need two numbers:
1791 * MDWIDTH = size, in bits, of the internal memory bus
1792 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1794 * Given these two numbers, the formula is simple:
1796 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1798 * 24 bytes is for 3x SETUP packets
1799 * 16 bytes is a clock domain crossing tolerance
1801 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1803 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1810 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1811 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1813 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1814 nump = min_t(u32, nump, 16);
1817 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1818 reg &= ~DWC3_DCFG_NUMP_MASK;
1819 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1820 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1823 static int __dwc3_gadget_start(struct dwc3 *dwc)
1825 struct dwc3_ep *dep;
1830 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1831 * the core supports IMOD, disable it.
1833 if (dwc->imod_interval) {
1834 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1835 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1836 } else if (dwc3_has_imod(dwc)) {
1837 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1841 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1842 * field instead of letting dwc3 itself calculate that automatically.
1844 * This way, we maximize the chances that we'll be able to get several
1845 * bursts of data without going through any sort of endpoint throttling.
1847 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1848 if (dwc3_is_usb31(dwc))
1849 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1851 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1853 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1855 dwc3_gadget_setup_nump(dwc);
1857 /* Start with SuperSpeed Default */
1858 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1861 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1863 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1868 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1870 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1874 /* begin to receive SETUP packets */
1875 dwc->ep0state = EP0_SETUP_PHASE;
1876 dwc3_ep0_out_start(dwc);
1878 dwc3_gadget_enable_irq(dwc);
1883 __dwc3_gadget_ep_disable(dwc->eps[0]);
1889 static int dwc3_gadget_start(struct usb_gadget *g,
1890 struct usb_gadget_driver *driver)
1892 struct dwc3 *dwc = gadget_to_dwc(g);
1893 unsigned long flags;
1897 irq = dwc->irq_gadget;
1898 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1899 IRQF_SHARED, "dwc3", dwc->ev_buf);
1901 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1906 spin_lock_irqsave(&dwc->lock, flags);
1907 if (dwc->gadget_driver) {
1908 dev_err(dwc->dev, "%s is already bound to %s\n",
1910 dwc->gadget_driver->driver.name);
1915 dwc->gadget_driver = driver;
1917 if (pm_runtime_active(dwc->dev))
1918 __dwc3_gadget_start(dwc);
1920 spin_unlock_irqrestore(&dwc->lock, flags);
1925 spin_unlock_irqrestore(&dwc->lock, flags);
1932 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1934 dwc3_gadget_disable_irq(dwc);
1935 __dwc3_gadget_ep_disable(dwc->eps[0]);
1936 __dwc3_gadget_ep_disable(dwc->eps[1]);
1939 static int dwc3_gadget_stop(struct usb_gadget *g)
1941 struct dwc3 *dwc = gadget_to_dwc(g);
1942 unsigned long flags;
1946 spin_lock_irqsave(&dwc->lock, flags);
1948 if (pm_runtime_suspended(dwc->dev))
1951 __dwc3_gadget_stop(dwc);
1953 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1954 struct dwc3_ep *dep = dwc->eps[epnum];
1960 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1963 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
1964 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1965 dwc->lock, msecs_to_jiffies(5));
1968 /* Timed out or interrupted! There's nothing much
1969 * we can do so we just log here and print which
1970 * endpoints timed out at the end.
1972 tmo_eps |= 1 << epnum;
1973 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
1979 "end transfer timed out on endpoints 0x%x [bitmap]\n",
1984 dwc->gadget_driver = NULL;
1985 spin_unlock_irqrestore(&dwc->lock, flags);
1987 free_irq(dwc->irq_gadget, dwc->ev_buf);
1992 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1993 enum usb_device_speed speed)
1995 struct dwc3 *dwc = gadget_to_dwc(g);
1996 unsigned long flags;
1999 spin_lock_irqsave(&dwc->lock, flags);
2000 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2001 reg &= ~(DWC3_DCFG_SPEED_MASK);
2004 * WORKAROUND: DWC3 revision < 2.20a have an issue
2005 * which would cause metastability state on Run/Stop
2006 * bit if we try to force the IP to USB2-only mode.
2008 * Because of that, we cannot configure the IP to any
2009 * speed other than the SuperSpeed
2013 * STAR#9000525659: Clock Domain Crossing on DCTL in
2016 if (dwc->revision < DWC3_REVISION_220A &&
2017 !dwc->dis_metastability_quirk) {
2018 reg |= DWC3_DCFG_SUPERSPEED;
2022 reg |= DWC3_DCFG_LOWSPEED;
2024 case USB_SPEED_FULL:
2025 reg |= DWC3_DCFG_FULLSPEED;
2027 case USB_SPEED_HIGH:
2028 reg |= DWC3_DCFG_HIGHSPEED;
2030 case USB_SPEED_SUPER:
2031 reg |= DWC3_DCFG_SUPERSPEED;
2033 case USB_SPEED_SUPER_PLUS:
2034 if (dwc3_is_usb31(dwc))
2035 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2037 reg |= DWC3_DCFG_SUPERSPEED;
2040 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2042 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2043 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2045 reg |= DWC3_DCFG_SUPERSPEED;
2048 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2050 spin_unlock_irqrestore(&dwc->lock, flags);
2053 static const struct usb_gadget_ops dwc3_gadget_ops = {
2054 .get_frame = dwc3_gadget_get_frame,
2055 .wakeup = dwc3_gadget_wakeup,
2056 .set_selfpowered = dwc3_gadget_set_selfpowered,
2057 .pullup = dwc3_gadget_pullup,
2058 .udc_start = dwc3_gadget_start,
2059 .udc_stop = dwc3_gadget_stop,
2060 .udc_set_speed = dwc3_gadget_set_speed,
2063 /* -------------------------------------------------------------------------- */
2065 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2067 struct dwc3 *dwc = dep->dwc;
2069 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2070 dep->endpoint.maxburst = 1;
2071 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2072 if (!dep->direction)
2073 dwc->gadget.ep0 = &dep->endpoint;
2075 dep->endpoint.caps.type_control = true;
2080 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2082 struct dwc3 *dwc = dep->dwc;
2087 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2088 /* MDWIDTH is represented in bits, we need it in bytes */
2091 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2092 if (dwc3_is_usb31(dwc))
2093 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2095 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2097 /* FIFO Depth is in MDWDITH bytes. Multiply */
2100 kbytes = size / 1024;
2105 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2106 * internal overhead. We don't really know how these are used,
2107 * but documentation say it exists.
2109 size -= mdwidth * (kbytes + 1);
2112 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2114 dep->endpoint.max_streams = 15;
2115 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2116 list_add_tail(&dep->endpoint.ep_list,
2117 &dwc->gadget.ep_list);
2118 dep->endpoint.caps.type_iso = true;
2119 dep->endpoint.caps.type_bulk = true;
2120 dep->endpoint.caps.type_int = true;
2122 return dwc3_alloc_trb_pool(dep);
2125 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2127 struct dwc3 *dwc = dep->dwc;
2129 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2130 dep->endpoint.max_streams = 15;
2131 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2132 list_add_tail(&dep->endpoint.ep_list,
2133 &dwc->gadget.ep_list);
2134 dep->endpoint.caps.type_iso = true;
2135 dep->endpoint.caps.type_bulk = true;
2136 dep->endpoint.caps.type_int = true;
2138 return dwc3_alloc_trb_pool(dep);
2141 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2143 struct dwc3_ep *dep;
2144 bool direction = epnum & 1;
2146 u8 num = epnum >> 1;
2148 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2153 dep->number = epnum;
2154 dep->direction = direction;
2155 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2156 dwc->eps[epnum] = dep;
2158 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2159 direction ? "in" : "out");
2161 dep->endpoint.name = dep->name;
2163 if (!(dep->number > 1)) {
2164 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2165 dep->endpoint.comp_desc = NULL;
2168 spin_lock_init(&dep->lock);
2171 ret = dwc3_gadget_init_control_endpoint(dep);
2173 ret = dwc3_gadget_init_in_endpoint(dep);
2175 ret = dwc3_gadget_init_out_endpoint(dep);
2180 dep->endpoint.caps.dir_in = direction;
2181 dep->endpoint.caps.dir_out = !direction;
2183 INIT_LIST_HEAD(&dep->pending_list);
2184 INIT_LIST_HEAD(&dep->started_list);
2189 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2193 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2195 for (epnum = 0; epnum < total; epnum++) {
2198 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2206 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2208 struct dwc3_ep *dep;
2211 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2212 dep = dwc->eps[epnum];
2216 * Physical endpoints 0 and 1 are special; they form the
2217 * bi-directional USB endpoint 0.
2219 * For those two physical endpoints, we don't allocate a TRB
2220 * pool nor do we add them the endpoints list. Due to that, we
2221 * shouldn't do these two operations otherwise we would end up
2222 * with all sorts of bugs when removing dwc3.ko.
2224 if (epnum != 0 && epnum != 1) {
2225 dwc3_free_trb_pool(dep);
2226 list_del(&dep->endpoint.ep_list);
2233 /* -------------------------------------------------------------------------- */
2235 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2236 struct dwc3_request *req, struct dwc3_trb *trb,
2237 const struct dwc3_event_depevt *event, int status, int chain)
2241 dwc3_ep_inc_deq(dep);
2243 trace_dwc3_complete_trb(dep, trb);
2246 * If we're in the middle of series of chained TRBs and we
2247 * receive a short transfer along the way, DWC3 will skip
2248 * through all TRBs including the last TRB in the chain (the
2249 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2250 * bit and SW has to do it manually.
2252 * We're going to do that here to avoid problems of HW trying
2253 * to use bogus TRBs for transfers.
2255 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2256 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2259 * If we're dealing with unaligned size OUT transfer, we will be left
2260 * with one TRB pending in the ring. We need to manually clear HWO bit
2263 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2264 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2268 count = trb->size & DWC3_TRB_SIZE_MASK;
2269 req->remaining += count;
2271 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2274 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2277 if (event->status & DEPEVT_STATUS_IOC)
2283 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2284 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2287 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2288 struct scatterlist *sg = req->sg;
2289 struct scatterlist *s;
2290 unsigned int pending = req->num_pending_sgs;
2294 for_each_sg(sg, s, pending, i) {
2295 trb = &dep->trb_pool[dep->trb_dequeue];
2297 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2300 req->sg = sg_next(s);
2301 req->num_pending_sgs--;
2303 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2304 trb, event, status, true);
2312 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2313 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2316 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2318 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2319 event, status, false);
2322 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2324 return req->request.actual == req->request.length;
2327 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2328 const struct dwc3_event_depevt *event,
2329 struct dwc3_request *req, int status)
2333 if (req->num_pending_sgs)
2334 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2337 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2340 if (req->unaligned || req->zero) {
2341 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2343 req->unaligned = false;
2347 req->request.actual = req->request.length - req->remaining;
2349 if (!dwc3_gadget_ep_request_completed(req) &&
2350 req->num_pending_sgs) {
2351 __dwc3_gadget_kick_transfer(dep);
2355 dwc3_gadget_giveback(dep, req, status);
2361 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2362 const struct dwc3_event_depevt *event, int status)
2364 struct dwc3_request *req;
2365 struct dwc3_request *tmp;
2367 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2370 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2377 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2378 const struct dwc3_event_depevt *event)
2382 mask = ~(dep->interval - 1);
2383 cur_uf = event->parameters & mask;
2384 dep->frame_number = cur_uf;
2387 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2388 const struct dwc3_event_depevt *event)
2390 struct dwc3 *dwc = dep->dwc;
2391 unsigned status = 0;
2394 dwc3_gadget_endpoint_frame_from_event(dep, event);
2396 if (event->status & DEPEVT_STATUS_BUSERR)
2397 status = -ECONNRESET;
2399 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2402 if (list_empty(&dep->started_list))
2406 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2409 dwc3_stop_active_transfer(dep, true);
2410 dep->flags = DWC3_EP_ENABLED;
2414 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2415 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2417 if (dwc->revision < DWC3_REVISION_183A) {
2421 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2424 if (!(dep->flags & DWC3_EP_ENABLED))
2427 if (!list_empty(&dep->started_list))
2431 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2433 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2439 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2440 const struct dwc3_event_depevt *event)
2442 dwc3_gadget_endpoint_frame_from_event(dep, event);
2443 __dwc3_gadget_start_isoc(dep);
2446 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2447 const struct dwc3_event_depevt *event)
2449 struct dwc3_ep *dep;
2450 u8 epnum = event->endpoint_number;
2453 dep = dwc->eps[epnum];
2455 if (!(dep->flags & DWC3_EP_ENABLED)) {
2456 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2459 /* Handle only EPCMDCMPLT when EP disabled */
2460 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2464 if (epnum == 0 || epnum == 1) {
2465 dwc3_ep0_interrupt(dwc, event);
2469 switch (event->endpoint_event) {
2470 case DWC3_DEPEVT_XFERINPROGRESS:
2471 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2473 case DWC3_DEPEVT_XFERNOTREADY:
2474 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2476 case DWC3_DEPEVT_EPCMDCMPLT:
2477 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2479 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2480 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2481 wake_up(&dep->wait_end_transfer);
2484 case DWC3_DEPEVT_STREAMEVT:
2485 case DWC3_DEPEVT_XFERCOMPLETE:
2486 case DWC3_DEPEVT_RXTXFIFOEVT:
2491 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2493 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2494 spin_unlock(&dwc->lock);
2495 dwc->gadget_driver->disconnect(&dwc->gadget);
2496 spin_lock(&dwc->lock);
2500 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2502 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2503 spin_unlock(&dwc->lock);
2504 dwc->gadget_driver->suspend(&dwc->gadget);
2505 spin_lock(&dwc->lock);
2509 static void dwc3_resume_gadget(struct dwc3 *dwc)
2511 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2512 spin_unlock(&dwc->lock);
2513 dwc->gadget_driver->resume(&dwc->gadget);
2514 spin_lock(&dwc->lock);
2518 static void dwc3_reset_gadget(struct dwc3 *dwc)
2520 if (!dwc->gadget_driver)
2523 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2524 spin_unlock(&dwc->lock);
2525 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2526 spin_lock(&dwc->lock);
2530 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2532 struct dwc3 *dwc = dep->dwc;
2533 struct dwc3_gadget_ep_cmd_params params;
2537 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2538 !dep->resource_index)
2542 * NOTICE: We are violating what the Databook says about the
2543 * EndTransfer command. Ideally we would _always_ wait for the
2544 * EndTransfer Command Completion IRQ, but that's causing too
2545 * much trouble synchronizing between us and gadget driver.
2547 * We have discussed this with the IP Provider and it was
2548 * suggested to giveback all requests here, but give HW some
2549 * extra time to synchronize with the interconnect. We're using
2550 * an arbitrary 100us delay for that.
2552 * Note also that a similar handling was tested by Synopsys
2553 * (thanks a lot Paul) and nothing bad has come out of it.
2554 * In short, what we're doing is:
2556 * - Issue EndTransfer WITH CMDIOC bit set
2559 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2560 * supports a mode to work around the above limitation. The
2561 * software can poll the CMDACT bit in the DEPCMD register
2562 * after issuing a EndTransfer command. This mode is enabled
2563 * by writing GUCTL2[14]. This polling is already done in the
2564 * dwc3_send_gadget_ep_cmd() function so if the mode is
2565 * enabled, the EndTransfer command will have completed upon
2566 * returning from this function and we don't need to delay for
2569 * This mode is NOT available on the DWC_usb31 IP.
2572 cmd = DWC3_DEPCMD_ENDTRANSFER;
2573 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2574 cmd |= DWC3_DEPCMD_CMDIOC;
2575 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2576 memset(¶ms, 0, sizeof(params));
2577 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2579 dep->resource_index = 0;
2581 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2582 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2587 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2591 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2592 struct dwc3_ep *dep;
2595 dep = dwc->eps[epnum];
2599 if (!(dep->flags & DWC3_EP_STALL))
2602 dep->flags &= ~DWC3_EP_STALL;
2604 ret = dwc3_send_clear_stall_ep_cmd(dep);
2609 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2613 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2614 reg &= ~DWC3_DCTL_INITU1ENA;
2615 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2617 reg &= ~DWC3_DCTL_INITU2ENA;
2618 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2620 dwc3_disconnect_gadget(dwc);
2622 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2623 dwc->setup_packet_pending = false;
2624 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2626 dwc->connected = false;
2629 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2633 dwc->connected = true;
2636 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2637 * would cause a missing Disconnect Event if there's a
2638 * pending Setup Packet in the FIFO.
2640 * There's no suggested workaround on the official Bug
2641 * report, which states that "unless the driver/application
2642 * is doing any special handling of a disconnect event,
2643 * there is no functional issue".
2645 * Unfortunately, it turns out that we _do_ some special
2646 * handling of a disconnect event, namely complete all
2647 * pending transfers, notify gadget driver of the
2648 * disconnection, and so on.
2650 * Our suggested workaround is to follow the Disconnect
2651 * Event steps here, instead, based on a setup_packet_pending
2652 * flag. Such flag gets set whenever we have a SETUP_PENDING
2653 * status for EP0 TRBs and gets cleared on XferComplete for the
2658 * STAR#9000466709: RTL: Device : Disconnect event not
2659 * generated if setup packet pending in FIFO
2661 if (dwc->revision < DWC3_REVISION_188A) {
2662 if (dwc->setup_packet_pending)
2663 dwc3_gadget_disconnect_interrupt(dwc);
2666 dwc3_reset_gadget(dwc);
2668 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2669 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2670 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2671 dwc->test_mode = false;
2672 dwc3_clear_stall_all_ep(dwc);
2674 /* Reset device address to zero */
2675 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2676 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2677 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2680 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2682 struct dwc3_ep *dep;
2687 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2688 speed = reg & DWC3_DSTS_CONNECTSPD;
2692 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2693 * each time on Connect Done.
2695 * Currently we always use the reset value. If any platform
2696 * wants to set this to a different value, we need to add a
2697 * setting and update GCTL.RAMCLKSEL here.
2701 case DWC3_DSTS_SUPERSPEED_PLUS:
2702 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2703 dwc->gadget.ep0->maxpacket = 512;
2704 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2706 case DWC3_DSTS_SUPERSPEED:
2708 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2709 * would cause a missing USB3 Reset event.
2711 * In such situations, we should force a USB3 Reset
2712 * event by calling our dwc3_gadget_reset_interrupt()
2717 * STAR#9000483510: RTL: SS : USB3 reset event may
2718 * not be generated always when the link enters poll
2720 if (dwc->revision < DWC3_REVISION_190A)
2721 dwc3_gadget_reset_interrupt(dwc);
2723 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2724 dwc->gadget.ep0->maxpacket = 512;
2725 dwc->gadget.speed = USB_SPEED_SUPER;
2727 case DWC3_DSTS_HIGHSPEED:
2728 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2729 dwc->gadget.ep0->maxpacket = 64;
2730 dwc->gadget.speed = USB_SPEED_HIGH;
2732 case DWC3_DSTS_FULLSPEED:
2733 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2734 dwc->gadget.ep0->maxpacket = 64;
2735 dwc->gadget.speed = USB_SPEED_FULL;
2737 case DWC3_DSTS_LOWSPEED:
2738 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2739 dwc->gadget.ep0->maxpacket = 8;
2740 dwc->gadget.speed = USB_SPEED_LOW;
2744 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2746 /* Enable USB2 LPM Capability */
2748 if ((dwc->revision > DWC3_REVISION_194A) &&
2749 (speed != DWC3_DSTS_SUPERSPEED) &&
2750 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2751 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2752 reg |= DWC3_DCFG_LPM_CAP;
2753 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2755 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2756 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2758 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2761 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2762 * DCFG.LPMCap is set, core responses with an ACK and the
2763 * BESL value in the LPM token is less than or equal to LPM
2766 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2767 && dwc->has_lpm_erratum,
2768 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2770 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2771 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2773 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2775 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2776 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2777 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2781 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2783 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2788 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2790 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2795 * Configure PHY via GUSB3PIPECTLn if required.
2797 * Update GTXFIFOSIZn
2799 * In both cases reset values should be sufficient.
2803 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2806 * TODO take core out of low power mode when that's
2810 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2811 spin_unlock(&dwc->lock);
2812 dwc->gadget_driver->resume(&dwc->gadget);
2813 spin_lock(&dwc->lock);
2817 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2818 unsigned int evtinfo)
2820 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2821 unsigned int pwropt;
2824 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2825 * Hibernation mode enabled which would show up when device detects
2826 * host-initiated U3 exit.
2828 * In that case, device will generate a Link State Change Interrupt
2829 * from U3 to RESUME which is only necessary if Hibernation is
2832 * There are no functional changes due to such spurious event and we
2833 * just need to ignore it.
2837 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2840 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2841 if ((dwc->revision < DWC3_REVISION_250A) &&
2842 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2843 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2844 (next == DWC3_LINK_STATE_RESUME)) {
2850 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2851 * on the link partner, the USB session might do multiple entry/exit
2852 * of low power states before a transfer takes place.
2854 * Due to this problem, we might experience lower throughput. The
2855 * suggested workaround is to disable DCTL[12:9] bits if we're
2856 * transitioning from U1/U2 to U0 and enable those bits again
2857 * after a transfer completes and there are no pending transfers
2858 * on any of the enabled endpoints.
2860 * This is the first half of that workaround.
2864 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2865 * core send LGO_Ux entering U0
2867 if (dwc->revision < DWC3_REVISION_183A) {
2868 if (next == DWC3_LINK_STATE_U0) {
2872 switch (dwc->link_state) {
2873 case DWC3_LINK_STATE_U1:
2874 case DWC3_LINK_STATE_U2:
2875 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2876 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2877 | DWC3_DCTL_ACCEPTU2ENA
2878 | DWC3_DCTL_INITU1ENA
2879 | DWC3_DCTL_ACCEPTU1ENA);
2882 dwc->u1u2 = reg & u1u2;
2886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2896 case DWC3_LINK_STATE_U1:
2897 if (dwc->speed == USB_SPEED_SUPER)
2898 dwc3_suspend_gadget(dwc);
2900 case DWC3_LINK_STATE_U2:
2901 case DWC3_LINK_STATE_U3:
2902 dwc3_suspend_gadget(dwc);
2904 case DWC3_LINK_STATE_RESUME:
2905 dwc3_resume_gadget(dwc);
2912 dwc->link_state = next;
2915 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2916 unsigned int evtinfo)
2918 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2920 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2921 dwc3_suspend_gadget(dwc);
2923 dwc->link_state = next;
2926 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2927 unsigned int evtinfo)
2929 unsigned int is_ss = evtinfo & BIT(4);
2932 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2933 * have a known issue which can cause USB CV TD.9.23 to fail
2936 * Because of this issue, core could generate bogus hibernation
2937 * events which SW needs to ignore.
2941 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2942 * Device Fallback from SuperSpeed
2944 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2947 /* enter hibernation here */
2950 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2951 const struct dwc3_event_devt *event)
2953 switch (event->type) {
2954 case DWC3_DEVICE_EVENT_DISCONNECT:
2955 dwc3_gadget_disconnect_interrupt(dwc);
2957 case DWC3_DEVICE_EVENT_RESET:
2958 dwc3_gadget_reset_interrupt(dwc);
2960 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2961 dwc3_gadget_conndone_interrupt(dwc);
2963 case DWC3_DEVICE_EVENT_WAKEUP:
2964 dwc3_gadget_wakeup_interrupt(dwc);
2966 case DWC3_DEVICE_EVENT_HIBER_REQ:
2967 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2968 "unexpected hibernation event\n"))
2971 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2973 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2974 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2976 case DWC3_DEVICE_EVENT_EOPF:
2977 /* It changed to be suspend event for version 2.30a and above */
2978 if (dwc->revision >= DWC3_REVISION_230A) {
2980 * Ignore suspend event until the gadget enters into
2981 * USB_STATE_CONFIGURED state.
2983 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2984 dwc3_gadget_suspend_interrupt(dwc,
2988 case DWC3_DEVICE_EVENT_SOF:
2989 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2990 case DWC3_DEVICE_EVENT_CMD_CMPL:
2991 case DWC3_DEVICE_EVENT_OVERFLOW:
2994 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2998 static void dwc3_process_event_entry(struct dwc3 *dwc,
2999 const union dwc3_event *event)
3001 trace_dwc3_event(event->raw, dwc);
3003 if (!event->type.is_devspec)
3004 dwc3_endpoint_interrupt(dwc, &event->depevt);
3005 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3006 dwc3_gadget_interrupt(dwc, &event->devt);
3008 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3011 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3013 struct dwc3 *dwc = evt->dwc;
3014 irqreturn_t ret = IRQ_NONE;
3020 if (!(evt->flags & DWC3_EVENT_PENDING))
3024 union dwc3_event event;
3026 event.raw = *(u32 *) (evt->cache + evt->lpos);
3028 dwc3_process_event_entry(dwc, &event);
3031 * FIXME we wrap around correctly to the next entry as
3032 * almost all entries are 4 bytes in size. There is one
3033 * entry which has 12 bytes which is a regular entry
3034 * followed by 8 bytes data. ATM I don't know how
3035 * things are organized if we get next to the a
3036 * boundary so I worry about that once we try to handle
3039 evt->lpos = (evt->lpos + 4) % evt->length;
3044 evt->flags &= ~DWC3_EVENT_PENDING;
3047 /* Unmask interrupt */
3048 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3049 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3050 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3052 if (dwc->imod_interval) {
3053 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3054 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3060 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3062 struct dwc3_event_buffer *evt = _evt;
3063 struct dwc3 *dwc = evt->dwc;
3064 unsigned long flags;
3065 irqreturn_t ret = IRQ_NONE;
3067 spin_lock_irqsave(&dwc->lock, flags);
3068 ret = dwc3_process_event_buf(evt);
3069 spin_unlock_irqrestore(&dwc->lock, flags);
3074 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3076 struct dwc3 *dwc = evt->dwc;
3081 if (pm_runtime_suspended(dwc->dev)) {
3082 pm_runtime_get(dwc->dev);
3083 disable_irq_nosync(dwc->irq_gadget);
3084 dwc->pending_events = true;
3089 * With PCIe legacy interrupt, test shows that top-half irq handler can
3090 * be called again after HW interrupt deassertion. Check if bottom-half
3091 * irq event handler completes before caching new event to prevent
3094 if (evt->flags & DWC3_EVENT_PENDING)
3097 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3098 count &= DWC3_GEVNTCOUNT_MASK;
3103 evt->flags |= DWC3_EVENT_PENDING;
3105 /* Mask interrupt */
3106 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3107 reg |= DWC3_GEVNTSIZ_INTMASK;
3108 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3110 amount = min(count, evt->length - evt->lpos);
3111 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3114 memcpy(evt->cache, evt->buf, count - amount);
3116 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3118 return IRQ_WAKE_THREAD;
3121 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3123 struct dwc3_event_buffer *evt = _evt;
3125 return dwc3_check_event_buf(evt);
3128 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3130 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3133 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3137 if (irq == -EPROBE_DEFER)
3140 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3144 if (irq == -EPROBE_DEFER)
3147 irq = platform_get_irq(dwc3_pdev, 0);
3151 if (irq != -EPROBE_DEFER)
3152 dev_err(dwc->dev, "missing peripheral IRQ\n");
3162 * dwc3_gadget_init - initializes gadget related registers
3163 * @dwc: pointer to our controller context structure
3165 * Returns 0 on success otherwise negative errno.
3167 int dwc3_gadget_init(struct dwc3 *dwc)
3172 irq = dwc3_gadget_get_irq(dwc);
3178 dwc->irq_gadget = irq;
3180 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3181 sizeof(*dwc->ep0_trb) * 2,
3182 &dwc->ep0_trb_addr, GFP_KERNEL);
3183 if (!dwc->ep0_trb) {
3184 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3189 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3190 if (!dwc->setup_buf) {
3195 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3196 &dwc->bounce_addr, GFP_KERNEL);
3202 init_completion(&dwc->ep0_in_setup);
3204 dwc->gadget.ops = &dwc3_gadget_ops;
3205 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3206 dwc->gadget.sg_supported = true;
3207 dwc->gadget.name = "dwc3-gadget";
3208 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3211 * FIXME We might be setting max_speed to <SUPER, however versions
3212 * <2.20a of dwc3 have an issue with metastability (documented
3213 * elsewhere in this driver) which tells us we can't set max speed to
3214 * anything lower than SUPER.
3216 * Because gadget.max_speed is only used by composite.c and function
3217 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3218 * to happen so we avoid sending SuperSpeed Capability descriptor
3219 * together with our BOS descriptor as that could confuse host into
3220 * thinking we can handle super speed.
3222 * Note that, in fact, we won't even support GetBOS requests when speed
3223 * is less than super speed because we don't have means, yet, to tell
3224 * composite.c that we are USB 2.0 + LPM ECN.
3226 if (dwc->revision < DWC3_REVISION_220A &&
3227 !dwc->dis_metastability_quirk)
3228 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3231 dwc->gadget.max_speed = dwc->maximum_speed;
3234 * REVISIT: Here we should clear all pending IRQs to be
3235 * sure we're starting from a well known location.
3238 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3242 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3244 dev_err(dwc->dev, "failed to register udc\n");
3251 dwc3_gadget_free_endpoints(dwc);
3254 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3258 kfree(dwc->setup_buf);
3261 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3262 dwc->ep0_trb, dwc->ep0_trb_addr);
3268 /* -------------------------------------------------------------------------- */
3270 void dwc3_gadget_exit(struct dwc3 *dwc)
3272 usb_del_gadget_udc(&dwc->gadget);
3273 dwc3_gadget_free_endpoints(dwc);
3274 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3276 kfree(dwc->setup_buf);
3277 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3278 dwc->ep0_trb, dwc->ep0_trb_addr);
3281 int dwc3_gadget_suspend(struct dwc3 *dwc)
3283 if (!dwc->gadget_driver)
3286 dwc3_gadget_run_stop(dwc, false, false);
3287 dwc3_disconnect_gadget(dwc);
3288 __dwc3_gadget_stop(dwc);
3293 int dwc3_gadget_resume(struct dwc3 *dwc)
3297 if (!dwc->gadget_driver)
3300 ret = __dwc3_gadget_start(dwc);
3304 ret = dwc3_gadget_run_stop(dwc, true, false);
3311 __dwc3_gadget_stop(dwc);
3317 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3319 if (dwc->pending_events) {
3320 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3321 dwc->pending_events = false;
3322 enable_irq(dwc->irq_gadget);