1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
237 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
238 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
241 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
242 if (!(reg & DWC3_DGCMD_CMDACT)) {
243 status = DWC3_DGCMD_STATUS(reg);
255 trace_dwc3_gadget_generic_cmd(cmd, param, status);
260 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
263 * dwc3_send_gadget_ep_cmd - issue an endpoint command
264 * @dep: the endpoint to which the command is going to be issued
265 * @cmd: the command to be issued
266 * @params: parameters to the command
268 * Caller should handle locking. This function will issue @cmd with given
269 * @params to @dep and wait for its completion.
271 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
272 struct dwc3_gadget_ep_cmd_params *params)
274 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
275 struct dwc3 *dwc = dep->dwc;
277 u32 saved_config = 0;
284 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
285 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
288 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
289 * settings. Restore them after the command is completed.
291 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
293 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
294 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
295 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
296 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
297 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
300 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
301 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
302 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
306 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
309 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
312 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
313 dwc->link_state == DWC3_LINK_STATE_U2 ||
314 dwc->link_state == DWC3_LINK_STATE_U3);
316 if (unlikely(needs_wakeup)) {
317 ret = __dwc3_gadget_wakeup(dwc);
318 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
323 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
324 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
342 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
343 !usb_endpoint_xfer_isoc(desc))
344 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
346 cmd |= DWC3_DEPCMD_CMDACT;
348 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
350 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
351 if (!(reg & DWC3_DEPCMD_CMDACT)) {
352 cmd_status = DWC3_DEPCMD_STATUS(reg);
354 switch (cmd_status) {
358 case DEPEVT_TRANSFER_NO_RESOURCE:
359 dev_WARN(dwc->dev, "No resource for %s\n",
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
387 cmd_status = -ETIMEDOUT;
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
392 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
394 dep->flags |= DWC3_EP_TRANSFER_STARTED;
396 if (ret != -ETIMEDOUT)
397 dwc3_gadget_ep_get_transfer_index(dep);
401 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
411 struct dwc3 *dwc = dep->dwc;
412 struct dwc3_gadget_ep_cmd_params params;
413 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
416 * As of core revision 2.60a the recommended programming model
417 * is to set the ClearPendIN bit when issuing a Clear Stall EP
418 * command for IN endpoints. This is to prevent an issue where
419 * some (non-compliant) hosts may not send ACK TPs for pending
420 * IN transfers due to a mishandled error condition. Synopsys
423 if (dep->direction &&
424 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
425 (dwc->gadget.speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
428 memset(¶ms, 0, sizeof(params));
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
438 return dep->trb_pool_dma + offset;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
443 struct dwc3 *dwc = dep->dwc;
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
475 memset(¶ms, 0x00, sizeof(params));
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
541 ret = dwc3_gadget_set_xfer_resource(dep);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
559 memset(¶ms, 0x00, sizeof(params));
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
567 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
570 params.param0 |= action;
571 if (action == DWC3_DEPCFG_ACTION_RESTORE)
572 params.param2 |= dep->saved_state;
574 if (usb_endpoint_xfer_control(desc))
575 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
577 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
580 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
581 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
582 | DWC3_DEPCFG_XFER_COMPLETE_EN
583 | DWC3_DEPCFG_STREAM_EVENT_EN;
584 dep->stream_capable = true;
587 if (!usb_endpoint_xfer_control(desc))
588 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
591 * We are doing 1:1 mapping for endpoints, meaning
592 * Physical Endpoints 2 maps to Logical Endpoint 2 and
593 * so on. We consider the direction bit as part of the physical
594 * endpoint number. So USB endpoint 0x81 is 0x03.
596 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
599 * We must use the lower 16 TX FIFOs even though
603 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
605 if (desc->bInterval) {
606 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
607 dep->interval = 1 << (desc->bInterval - 1);
610 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
613 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
617 * __dwc3_gadget_ep_enable - initializes a hw endpoint
618 * @dep: endpoint to be initialized
619 * @action: one of INIT, MODIFY or RESTORE
621 * Caller should take care of locking. Execute all necessary commands to
622 * initialize a HW endpoint so it can be used by a gadget driver.
624 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
626 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
627 struct dwc3 *dwc = dep->dwc;
632 if (!(dep->flags & DWC3_EP_ENABLED)) {
633 ret = dwc3_gadget_start_config(dep);
638 ret = dwc3_gadget_set_ep_config(dep, action);
642 if (!(dep->flags & DWC3_EP_ENABLED)) {
643 struct dwc3_trb *trb_st_hw;
644 struct dwc3_trb *trb_link;
646 dep->type = usb_endpoint_type(desc);
647 dep->flags |= DWC3_EP_ENABLED;
649 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
650 reg |= DWC3_DALEPENA_EP(dep->number);
651 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653 if (usb_endpoint_xfer_control(desc))
656 /* Initialize the TRB ring */
657 dep->trb_dequeue = 0;
658 dep->trb_enqueue = 0;
659 memset(dep->trb_pool, 0,
660 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
662 /* Link TRB. The HWO bit is never reset */
663 trb_st_hw = &dep->trb_pool[0];
665 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
666 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
667 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
668 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
669 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
673 * Issue StartTransfer here with no-op TRB so we can always rely on No
674 * Response Update Transfer command.
676 if (usb_endpoint_xfer_bulk(desc) ||
677 usb_endpoint_xfer_int(desc)) {
678 struct dwc3_gadget_ep_cmd_params params;
679 struct dwc3_trb *trb;
683 memset(¶ms, 0, sizeof(params));
684 trb = &dep->trb_pool[0];
685 trb_dma = dwc3_trb_dma_offset(dep, trb);
687 params.param0 = upper_32_bits(trb_dma);
688 params.param1 = lower_32_bits(trb_dma);
690 cmd = DWC3_DEPCMD_STARTTRANSFER;
692 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
696 if (dep->stream_capable) {
698 * For streams, at start, there maybe a race where the
699 * host primes the endpoint before the function driver
700 * queues a request to initiate a stream. In that case,
701 * the controller will not see the prime to generate the
702 * ERDY and start stream. To workaround this, issue a
703 * no-op TRB as normal, but end it immediately. As a
704 * result, when the function driver queues the request,
705 * the next START_TRANSFER command will cause the
706 * controller to generate an ERDY to initiate the
709 dwc3_stop_active_transfer(dep, true, true);
712 * All stream eps will reinitiate stream on NoStream
713 * rejection until we can determine that the host can
714 * prime after the first transfer.
716 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
721 trace_dwc3_gadget_ep_enable(dep);
726 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
728 struct dwc3_request *req;
730 dwc3_stop_active_transfer(dep, true, false);
732 /* - giveback all requests to gadget driver */
733 while (!list_empty(&dep->started_list)) {
734 req = next_request(&dep->started_list);
736 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
739 while (!list_empty(&dep->pending_list)) {
740 req = next_request(&dep->pending_list);
742 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
745 while (!list_empty(&dep->cancelled_list)) {
746 req = next_request(&dep->cancelled_list);
748 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
753 * __dwc3_gadget_ep_disable - disables a hw endpoint
754 * @dep: the endpoint to disable
756 * This function undoes what __dwc3_gadget_ep_enable did and also removes
757 * requests which are currently being processed by the hardware and those which
758 * are not yet scheduled.
760 * Caller should take care of locking.
762 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
764 struct dwc3 *dwc = dep->dwc;
767 trace_dwc3_gadget_ep_disable(dep);
769 dwc3_remove_requests(dwc, dep);
771 /* make sure HW endpoint isn't stalled */
772 if (dep->flags & DWC3_EP_STALL)
773 __dwc3_gadget_ep_set_halt(dep, 0, false);
775 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
776 reg &= ~DWC3_DALEPENA_EP(dep->number);
777 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
779 dep->stream_capable = false;
783 /* Clear out the ep descriptors for non-ep0 */
784 if (dep->number > 1) {
785 dep->endpoint.comp_desc = NULL;
786 dep->endpoint.desc = NULL;
792 /* -------------------------------------------------------------------------- */
794 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
795 const struct usb_endpoint_descriptor *desc)
800 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
805 /* -------------------------------------------------------------------------- */
807 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
808 const struct usb_endpoint_descriptor *desc)
815 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
816 pr_debug("dwc3: invalid parameters\n");
820 if (!desc->wMaxPacketSize) {
821 pr_debug("dwc3: missing wMaxPacketSize\n");
825 dep = to_dwc3_ep(ep);
828 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
829 "%s is already enabled\n",
833 spin_lock_irqsave(&dwc->lock, flags);
834 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
835 spin_unlock_irqrestore(&dwc->lock, flags);
840 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
848 pr_debug("dwc3: invalid parameters\n");
852 dep = to_dwc3_ep(ep);
855 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
856 "%s is already disabled\n",
860 spin_lock_irqsave(&dwc->lock, flags);
861 ret = __dwc3_gadget_ep_disable(dep);
862 spin_unlock_irqrestore(&dwc->lock, flags);
867 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
870 struct dwc3_request *req;
871 struct dwc3_ep *dep = to_dwc3_ep(ep);
873 req = kzalloc(sizeof(*req), gfp_flags);
877 req->direction = dep->direction;
878 req->epnum = dep->number;
880 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
882 trace_dwc3_alloc_request(req);
884 return &req->request;
887 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
888 struct usb_request *request)
890 struct dwc3_request *req = to_dwc3_request(request);
892 trace_dwc3_free_request(req);
897 * dwc3_ep_prev_trb - returns the previous TRB in the ring
898 * @dep: The endpoint with the TRB ring
899 * @index: The index of the current TRB in the ring
901 * Returns the TRB prior to the one pointed to by the index. If the
902 * index is 0, we will wrap backwards, skip the link TRB, and return
903 * the one just before that.
905 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
910 tmp = DWC3_TRB_NUM - 1;
912 return &dep->trb_pool[tmp - 1];
915 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
917 struct dwc3_trb *tmp;
921 * If enqueue & dequeue are equal than it is either full or empty.
923 * One way to know for sure is if the TRB right before us has HWO bit
924 * set or not. If it has, then we're definitely full and can't fit any
925 * more transfers in our ring.
927 if (dep->trb_enqueue == dep->trb_dequeue) {
928 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
929 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
932 return DWC3_TRB_NUM - 1;
935 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
936 trbs_left &= (DWC3_TRB_NUM - 1);
938 if (dep->trb_dequeue < dep->trb_enqueue)
944 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
945 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
946 unsigned stream_id, unsigned short_not_ok,
947 unsigned no_interrupt, unsigned is_last)
949 struct dwc3 *dwc = dep->dwc;
950 struct usb_gadget *gadget = &dwc->gadget;
951 enum usb_device_speed speed = gadget->speed;
953 trb->size = DWC3_TRB_SIZE_LENGTH(length);
954 trb->bpl = lower_32_bits(dma);
955 trb->bph = upper_32_bits(dma);
957 switch (usb_endpoint_type(dep->endpoint.desc)) {
958 case USB_ENDPOINT_XFER_CONTROL:
959 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
962 case USB_ENDPOINT_XFER_ISOC:
964 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
967 * USB Specification 2.0 Section 5.9.2 states that: "If
968 * there is only a single transaction in the microframe,
969 * only a DATA0 data packet PID is used. If there are
970 * two transactions per microframe, DATA1 is used for
971 * the first transaction data packet and DATA0 is used
972 * for the second transaction data packet. If there are
973 * three transactions per microframe, DATA2 is used for
974 * the first transaction data packet, DATA1 is used for
975 * the second, and DATA0 is used for the third."
977 * IOW, we should satisfy the following cases:
979 * 1) length <= maxpacket
982 * 2) maxpacket < length <= (2 * maxpacket)
985 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
986 * - DATA2, DATA1, DATA0
988 if (speed == USB_SPEED_HIGH) {
989 struct usb_ep *ep = &dep->endpoint;
990 unsigned int mult = 2;
991 unsigned int maxp = usb_endpoint_maxp(ep->desc);
993 if (length <= (2 * maxp))
999 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1002 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1005 /* always enable Interrupt on Missed ISOC */
1006 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1009 case USB_ENDPOINT_XFER_BULK:
1010 case USB_ENDPOINT_XFER_INT:
1011 trb->ctrl = DWC3_TRBCTL_NORMAL;
1015 * This is only possible with faulty memory because we
1016 * checked it already :)
1018 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1019 usb_endpoint_type(dep->endpoint.desc));
1023 * Enable Continue on Short Packet
1024 * when endpoint is not a stream capable
1026 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1027 if (!dep->stream_capable)
1028 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1031 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1034 if ((!no_interrupt && !chain) ||
1035 (dwc3_calc_trbs_left(dep) == 1))
1036 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1039 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1040 else if (dep->stream_capable && is_last)
1041 trb->ctrl |= DWC3_TRB_CTRL_LST;
1043 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1044 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1046 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1048 dwc3_ep_inc_enq(dep);
1050 trace_dwc3_prepare_trb(dep, trb);
1054 * dwc3_prepare_one_trb - setup one TRB from one request
1055 * @dep: endpoint for which this request is prepared
1056 * @req: dwc3_request pointer
1057 * @chain: should this TRB be chained to the next?
1058 * @node: only for isochronous endpoints. First TRB needs different type.
1060 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1061 struct dwc3_request *req, unsigned chain, unsigned node)
1063 struct dwc3_trb *trb;
1064 unsigned int length;
1066 unsigned stream_id = req->request.stream_id;
1067 unsigned short_not_ok = req->request.short_not_ok;
1068 unsigned no_interrupt = req->request.no_interrupt;
1069 unsigned is_last = req->request.is_last;
1071 if (req->request.num_sgs > 0) {
1072 length = sg_dma_len(req->start_sg);
1073 dma = sg_dma_address(req->start_sg);
1075 length = req->request.length;
1076 dma = req->request.dma;
1079 trb = &dep->trb_pool[dep->trb_enqueue];
1082 dwc3_gadget_move_started_request(req);
1084 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1089 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1090 stream_id, short_not_ok, no_interrupt, is_last);
1093 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1094 struct dwc3_request *req)
1096 struct scatterlist *sg = req->start_sg;
1097 struct scatterlist *s;
1100 unsigned int remaining = req->request.num_mapped_sgs
1101 - req->num_queued_sgs;
1103 for_each_sg(sg, s, remaining, i) {
1104 unsigned int length = req->request.length;
1105 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1106 unsigned int rem = length % maxp;
1107 unsigned chain = true;
1110 * IOMMU driver is coalescing the list of sgs which shares a
1111 * page boundary into one and giving it to USB driver. With
1112 * this the number of sgs mapped is not equal to the number of
1113 * sgs passed. So mark the chain bit to false if it isthe last
1116 if (i == remaining - 1)
1119 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1123 req->needs_extra_trb = true;
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, i);
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1132 maxp - rem, false, 1,
1133 req->request.stream_id,
1134 req->request.short_not_ok,
1135 req->request.no_interrupt,
1136 req->request.is_last);
1138 dwc3_prepare_one_trb(dep, req, chain, i);
1142 * There can be a situation where all sgs in sglist are not
1143 * queued because of insufficient trb number. To handle this
1144 * case, update start_sg to next sg to be queued, so that
1145 * we have free trbs we can continue queuing from where we
1146 * previously stopped
1149 req->start_sg = sg_next(s);
1151 req->num_queued_sgs++;
1153 if (!dwc3_calc_trbs_left(dep))
1158 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1159 struct dwc3_request *req)
1161 unsigned int length = req->request.length;
1162 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1163 unsigned int rem = length % maxp;
1165 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1166 struct dwc3 *dwc = dep->dwc;
1167 struct dwc3_trb *trb;
1169 req->needs_extra_trb = true;
1171 /* prepare normal TRB */
1172 dwc3_prepare_one_trb(dep, req, true, 0);
1174 /* Now prepare one extra TRB to align transfer size */
1175 trb = &dep->trb_pool[dep->trb_enqueue];
1177 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1178 false, 1, req->request.stream_id,
1179 req->request.short_not_ok,
1180 req->request.no_interrupt,
1181 req->request.is_last);
1182 } else if (req->request.zero && req->request.length &&
1183 (IS_ALIGNED(req->request.length, maxp))) {
1184 struct dwc3 *dwc = dep->dwc;
1185 struct dwc3_trb *trb;
1187 req->needs_extra_trb = true;
1189 /* prepare normal TRB */
1190 dwc3_prepare_one_trb(dep, req, true, 0);
1192 /* Now prepare one extra TRB to handle ZLP */
1193 trb = &dep->trb_pool[dep->trb_enqueue];
1195 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1196 false, 1, req->request.stream_id,
1197 req->request.short_not_ok,
1198 req->request.no_interrupt,
1199 req->request.is_last);
1201 dwc3_prepare_one_trb(dep, req, false, 0);
1206 * dwc3_prepare_trbs - setup TRBs from requests
1207 * @dep: endpoint for which requests are being prepared
1209 * The function goes through the requests list and sets up TRBs for the
1210 * transfers. The function returns once there are no more TRBs available or
1211 * it runs out of requests.
1213 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1215 struct dwc3_request *req, *n;
1217 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1220 * We can get in a situation where there's a request in the started list
1221 * but there weren't enough TRBs to fully kick it in the first time
1222 * around, so it has been waiting for more TRBs to be freed up.
1224 * In that case, we should check if we have a request with pending_sgs
1225 * in the started list and prepare TRBs for that request first,
1226 * otherwise we will prepare TRBs completely out of order and that will
1229 list_for_each_entry(req, &dep->started_list, list) {
1230 if (req->num_pending_sgs > 0)
1231 dwc3_prepare_one_trb_sg(dep, req);
1233 if (!dwc3_calc_trbs_left(dep))
1237 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1238 * burst capability may try to read and use TRBs beyond the
1239 * active transfer instead of stopping.
1241 if (dep->stream_capable && req->request.is_last)
1245 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1246 struct dwc3 *dwc = dep->dwc;
1249 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1254 req->sg = req->request.sg;
1255 req->start_sg = req->sg;
1256 req->num_queued_sgs = 0;
1257 req->num_pending_sgs = req->request.num_mapped_sgs;
1259 if (req->num_pending_sgs > 0)
1260 dwc3_prepare_one_trb_sg(dep, req);
1262 dwc3_prepare_one_trb_linear(dep, req);
1264 if (!dwc3_calc_trbs_left(dep))
1268 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1269 * burst capability may try to read and use TRBs beyond the
1270 * active transfer instead of stopping.
1272 if (dep->stream_capable && req->request.is_last)
1277 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1279 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1281 struct dwc3_gadget_ep_cmd_params params;
1282 struct dwc3_request *req;
1287 if (!dwc3_calc_trbs_left(dep))
1290 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1292 dwc3_prepare_trbs(dep);
1293 req = next_request(&dep->started_list);
1295 dep->flags |= DWC3_EP_PENDING_REQUEST;
1299 memset(¶ms, 0, sizeof(params));
1302 params.param0 = upper_32_bits(req->trb_dma);
1303 params.param1 = lower_32_bits(req->trb_dma);
1304 cmd = DWC3_DEPCMD_STARTTRANSFER;
1306 if (dep->stream_capable)
1307 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1309 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1310 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1312 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1313 DWC3_DEPCMD_PARAM(dep->resource_index);
1316 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1318 struct dwc3_request *tmp;
1323 dwc3_stop_active_transfer(dep, true, true);
1325 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1326 dwc3_gadget_move_cancelled_request(req);
1328 /* If ep isn't started, then there's no end transfer pending */
1329 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1330 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1335 if (dep->stream_capable && req->request.is_last)
1336 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1341 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1345 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1346 return DWC3_DSTS_SOFFN(reg);
1350 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1351 * @dep: isoc endpoint
1353 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1354 * microframe number reported by the XferNotReady event for the future frame
1355 * number to start the isoc transfer.
1357 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1358 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1359 * XferNotReady event are invalid. The driver uses this number to schedule the
1360 * isochronous transfer and passes it to the START TRANSFER command. Because
1361 * this number is invalid, the command may fail. If BIT[15:14] matches the
1362 * internal 16-bit microframe, the START TRANSFER command will pass and the
1363 * transfer will start at the scheduled time, if it is off by 1, the command
1364 * will still pass, but the transfer will start 2 seconds in the future. For all
1365 * other conditions, the START TRANSFER command will fail with bus-expiry.
1367 * In order to workaround this issue, we can test for the correct combination of
1368 * BIT[15:14] by sending START TRANSFER commands with different values of
1369 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1370 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1371 * As the result, within the 4 possible combinations for BIT[15:14], there will
1372 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1373 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1374 * value is the correct combination.
1376 * Since there are only 4 outcomes and the results are ordered, we can simply
1377 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1378 * deduce the smaller successful combination.
1380 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1381 * of BIT[15:14]. The correct combination is as follow:
1383 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1384 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1385 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1386 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1388 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1391 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1397 while (dep->combo_num < 2) {
1398 struct dwc3_gadget_ep_cmd_params params;
1399 u32 test_frame_number;
1403 * Check if we can start isoc transfer on the next interval or
1404 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1406 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1407 test_frame_number |= dep->combo_num << 14;
1408 test_frame_number += max_t(u32, 4, dep->interval);
1410 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1411 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1413 cmd = DWC3_DEPCMD_STARTTRANSFER;
1414 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1415 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1417 /* Redo if some other failure beside bus-expiry is received */
1418 if (cmd_status && cmd_status != -EAGAIN) {
1419 dep->start_cmd_status = 0;
1424 /* Store the first test status */
1425 if (dep->combo_num == 0)
1426 dep->start_cmd_status = cmd_status;
1431 * End the transfer if the START_TRANSFER command is successful
1432 * to wait for the next XferNotReady to test the command again
1434 if (cmd_status == 0) {
1435 dwc3_stop_active_transfer(dep, true, true);
1440 /* test0 and test1 are both completed at this point */
1441 test0 = (dep->start_cmd_status == 0);
1442 test1 = (cmd_status == 0);
1444 if (!test0 && test1)
1446 else if (!test0 && !test1)
1448 else if (test0 && !test1)
1450 else if (test0 && test1)
1453 dep->frame_number &= DWC3_FRNUMBER_MASK;
1454 dep->frame_number |= dep->combo_num << 14;
1455 dep->frame_number += max_t(u32, 4, dep->interval);
1457 /* Reinitialize test variables */
1458 dep->start_cmd_status = 0;
1461 return __dwc3_gadget_kick_transfer(dep);
1464 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1466 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1467 struct dwc3 *dwc = dep->dwc;
1471 if (list_empty(&dep->pending_list) &&
1472 list_empty(&dep->started_list)) {
1473 dep->flags |= DWC3_EP_PENDING_REQUEST;
1477 if (!dwc->dis_start_transfer_quirk &&
1478 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1479 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1480 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1481 return dwc3_gadget_start_isoc_quirk(dep);
1484 if (desc->bInterval <= 14 &&
1485 dwc->gadget.speed >= USB_SPEED_HIGH) {
1486 u32 frame = __dwc3_gadget_get_frame(dwc);
1487 bool rollover = frame <
1488 (dep->frame_number & DWC3_FRNUMBER_MASK);
1491 * frame_number is set from XferNotReady and may be already
1492 * out of date. DSTS only provides the lower 14 bit of the
1493 * current frame number. So add the upper two bits of
1494 * frame_number and handle a possible rollover.
1495 * This will provide the correct frame_number unless more than
1496 * rollover has happened since XferNotReady.
1499 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1502 dep->frame_number += BIT(14);
1505 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1506 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1508 ret = __dwc3_gadget_kick_transfer(dep);
1514 * After a number of unsuccessful start attempts due to bus-expiry
1515 * status, issue END_TRANSFER command and retry on the next XferNotReady
1518 if (ret == -EAGAIN) {
1519 struct dwc3_gadget_ep_cmd_params params;
1522 cmd = DWC3_DEPCMD_ENDTRANSFER |
1523 DWC3_DEPCMD_CMDIOC |
1524 DWC3_DEPCMD_PARAM(dep->resource_index);
1526 dep->resource_index = 0;
1527 memset(¶ms, 0, sizeof(params));
1529 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1531 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1537 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1539 struct dwc3 *dwc = dep->dwc;
1541 if (!dep->endpoint.desc) {
1542 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1547 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1548 &req->request, req->dep->name))
1551 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1552 "%s: request %pK already in flight\n",
1553 dep->name, &req->request))
1556 pm_runtime_get(dwc->dev);
1558 req->request.actual = 0;
1559 req->request.status = -EINPROGRESS;
1561 trace_dwc3_ep_queue(req);
1563 list_add_tail(&req->list, &dep->pending_list);
1564 req->status = DWC3_REQUEST_STATUS_QUEUED;
1566 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1569 /* Start the transfer only after the END_TRANSFER is completed */
1570 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1571 dep->flags |= DWC3_EP_DELAY_START;
1576 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1577 * wait for a XferNotReady event so we will know what's the current
1578 * (micro-)frame number.
1580 * Without this trick, we are very, very likely gonna get Bus Expiry
1581 * errors which will force us issue EndTransfer command.
1583 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1584 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1585 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1588 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1589 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1590 return __dwc3_gadget_start_isoc(dep);
1595 return __dwc3_gadget_kick_transfer(dep);
1598 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1601 struct dwc3_request *req = to_dwc3_request(request);
1602 struct dwc3_ep *dep = to_dwc3_ep(ep);
1603 struct dwc3 *dwc = dep->dwc;
1605 unsigned long flags;
1609 spin_lock_irqsave(&dwc->lock, flags);
1610 ret = __dwc3_gadget_ep_queue(dep, req);
1611 spin_unlock_irqrestore(&dwc->lock, flags);
1616 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1620 /* If req->trb is not set, then the request has not started */
1625 * If request was already started, this means we had to
1626 * stop the transfer. With that we also need to ignore
1627 * all TRBs used by the request, however TRBs can only
1628 * be modified after completion of END_TRANSFER
1629 * command. So what we do here is that we wait for
1630 * END_TRANSFER completion and only after that, we jump
1631 * over TRBs by clearing HWO and incrementing dequeue
1634 for (i = 0; i < req->num_trbs; i++) {
1635 struct dwc3_trb *trb;
1637 trb = &dep->trb_pool[dep->trb_dequeue];
1638 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1639 dwc3_ep_inc_deq(dep);
1645 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1647 struct dwc3_request *req;
1648 struct dwc3_request *tmp;
1650 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1651 dwc3_gadget_ep_skip_trbs(dep, req);
1652 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1656 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1657 struct usb_request *request)
1659 struct dwc3_request *req = to_dwc3_request(request);
1660 struct dwc3_request *r = NULL;
1662 struct dwc3_ep *dep = to_dwc3_ep(ep);
1663 struct dwc3 *dwc = dep->dwc;
1665 unsigned long flags;
1668 trace_dwc3_ep_dequeue(req);
1670 spin_lock_irqsave(&dwc->lock, flags);
1672 list_for_each_entry(r, &dep->cancelled_list, list) {
1677 list_for_each_entry(r, &dep->pending_list, list) {
1679 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1684 list_for_each_entry(r, &dep->started_list, list) {
1686 struct dwc3_request *t;
1688 /* wait until it is processed */
1689 dwc3_stop_active_transfer(dep, true, true);
1692 * Remove any started request if the transfer is
1695 list_for_each_entry_safe(r, t, &dep->started_list, list)
1696 dwc3_gadget_move_cancelled_request(r);
1702 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1706 spin_unlock_irqrestore(&dwc->lock, flags);
1711 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1713 struct dwc3_gadget_ep_cmd_params params;
1714 struct dwc3 *dwc = dep->dwc;
1715 struct dwc3_request *req;
1716 struct dwc3_request *tmp;
1719 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1720 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1724 memset(¶ms, 0x00, sizeof(params));
1727 struct dwc3_trb *trb;
1729 unsigned transfer_in_flight;
1732 if (dep->number > 1)
1733 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1735 trb = &dwc->ep0_trb[dep->trb_enqueue];
1737 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1738 started = !list_empty(&dep->started_list);
1740 if (!protocol && ((dep->direction && transfer_in_flight) ||
1741 (!dep->direction && started))) {
1745 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1748 dev_err(dwc->dev, "failed to set STALL on %s\n",
1751 dep->flags |= DWC3_EP_STALL;
1754 * Don't issue CLEAR_STALL command to control endpoints. The
1755 * controller automatically clears the STALL when it receives
1758 if (dep->number <= 1) {
1759 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1763 ret = dwc3_send_clear_stall_ep_cmd(dep);
1765 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1770 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1772 dwc3_stop_active_transfer(dep, true, true);
1774 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1775 dwc3_gadget_move_cancelled_request(req);
1777 list_for_each_entry_safe(req, tmp, &dep->pending_list, list)
1778 dwc3_gadget_move_cancelled_request(req);
1780 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) {
1781 dep->flags &= ~DWC3_EP_DELAY_START;
1782 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1789 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1791 struct dwc3_ep *dep = to_dwc3_ep(ep);
1792 struct dwc3 *dwc = dep->dwc;
1794 unsigned long flags;
1798 spin_lock_irqsave(&dwc->lock, flags);
1799 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1800 spin_unlock_irqrestore(&dwc->lock, flags);
1805 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1807 struct dwc3_ep *dep = to_dwc3_ep(ep);
1808 struct dwc3 *dwc = dep->dwc;
1809 unsigned long flags;
1812 spin_lock_irqsave(&dwc->lock, flags);
1813 dep->flags |= DWC3_EP_WEDGE;
1815 if (dep->number == 0 || dep->number == 1)
1816 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1818 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1819 spin_unlock_irqrestore(&dwc->lock, flags);
1824 /* -------------------------------------------------------------------------- */
1826 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1827 .bLength = USB_DT_ENDPOINT_SIZE,
1828 .bDescriptorType = USB_DT_ENDPOINT,
1829 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1832 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1833 .enable = dwc3_gadget_ep0_enable,
1834 .disable = dwc3_gadget_ep0_disable,
1835 .alloc_request = dwc3_gadget_ep_alloc_request,
1836 .free_request = dwc3_gadget_ep_free_request,
1837 .queue = dwc3_gadget_ep0_queue,
1838 .dequeue = dwc3_gadget_ep_dequeue,
1839 .set_halt = dwc3_gadget_ep0_set_halt,
1840 .set_wedge = dwc3_gadget_ep_set_wedge,
1843 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1844 .enable = dwc3_gadget_ep_enable,
1845 .disable = dwc3_gadget_ep_disable,
1846 .alloc_request = dwc3_gadget_ep_alloc_request,
1847 .free_request = dwc3_gadget_ep_free_request,
1848 .queue = dwc3_gadget_ep_queue,
1849 .dequeue = dwc3_gadget_ep_dequeue,
1850 .set_halt = dwc3_gadget_ep_set_halt,
1851 .set_wedge = dwc3_gadget_ep_set_wedge,
1854 /* -------------------------------------------------------------------------- */
1856 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1858 struct dwc3 *dwc = gadget_to_dwc(g);
1860 return __dwc3_gadget_get_frame(dwc);
1863 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1873 * According to the Databook Remote wakeup request should
1874 * be issued only when the device is in early suspend state.
1876 * We can check that via USB Link State bits in DSTS register.
1878 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1880 link_state = DWC3_DSTS_USBLNKST(reg);
1882 switch (link_state) {
1883 case DWC3_LINK_STATE_RESET:
1884 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1885 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1886 case DWC3_LINK_STATE_RESUME:
1892 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1894 dev_err(dwc->dev, "failed to put link in Recovery\n");
1898 /* Recent versions do this automatically */
1899 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
1900 /* write zeroes to Link Change Request */
1901 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1902 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1903 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1906 /* poll until Link State changes to ON */
1910 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1912 /* in HS, means ON */
1913 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1917 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1918 dev_err(dwc->dev, "failed to send remote wakeup\n");
1925 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1927 struct dwc3 *dwc = gadget_to_dwc(g);
1928 unsigned long flags;
1931 spin_lock_irqsave(&dwc->lock, flags);
1932 ret = __dwc3_gadget_wakeup(dwc);
1933 spin_unlock_irqrestore(&dwc->lock, flags);
1938 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1941 struct dwc3 *dwc = gadget_to_dwc(g);
1942 unsigned long flags;
1944 spin_lock_irqsave(&dwc->lock, flags);
1945 g->is_selfpowered = !!is_selfpowered;
1946 spin_unlock_irqrestore(&dwc->lock, flags);
1951 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1956 if (pm_runtime_suspended(dwc->dev))
1959 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1961 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
1962 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1963 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1966 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
1967 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1968 reg |= DWC3_DCTL_RUN_STOP;
1970 if (dwc->has_hibernation)
1971 reg |= DWC3_DCTL_KEEP_CONNECT;
1973 dwc->pullups_connected = true;
1975 reg &= ~DWC3_DCTL_RUN_STOP;
1977 if (dwc->has_hibernation && !suspend)
1978 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1980 dwc->pullups_connected = false;
1983 dwc3_gadget_dctl_write_safe(dwc, reg);
1986 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1987 reg &= DWC3_DSTS_DEVCTRLHLT;
1988 } while (--timeout && !(!is_on ^ !reg));
1996 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1998 struct dwc3 *dwc = gadget_to_dwc(g);
1999 unsigned long flags;
2005 * Per databook, when we want to stop the gadget, if a control transfer
2006 * is still in process, complete it and get the core into setup phase.
2008 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2009 reinit_completion(&dwc->ep0_in_setup);
2011 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2012 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2014 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
2019 spin_lock_irqsave(&dwc->lock, flags);
2020 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2021 spin_unlock_irqrestore(&dwc->lock, flags);
2026 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2030 /* Enable all but Start and End of Frame IRQs */
2031 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2032 DWC3_DEVTEN_EVNTOVERFLOWEN |
2033 DWC3_DEVTEN_CMDCMPLTEN |
2034 DWC3_DEVTEN_ERRTICERREN |
2035 DWC3_DEVTEN_WKUPEVTEN |
2036 DWC3_DEVTEN_CONNECTDONEEN |
2037 DWC3_DEVTEN_USBRSTEN |
2038 DWC3_DEVTEN_DISCONNEVTEN);
2040 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2041 reg |= DWC3_DEVTEN_ULSTCNGEN;
2043 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2046 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2048 /* mask all interrupts */
2049 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2052 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2053 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2056 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2057 * @dwc: pointer to our context structure
2059 * The following looks like complex but it's actually very simple. In order to
2060 * calculate the number of packets we can burst at once on OUT transfers, we're
2061 * gonna use RxFIFO size.
2063 * To calculate RxFIFO size we need two numbers:
2064 * MDWIDTH = size, in bits, of the internal memory bus
2065 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2067 * Given these two numbers, the formula is simple:
2069 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2071 * 24 bytes is for 3x SETUP packets
2072 * 16 bytes is a clock domain crossing tolerance
2074 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2076 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2083 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2084 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
2085 if (DWC3_IP_IS(DWC32))
2086 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2088 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2089 nump = min_t(u32, nump, 16);
2092 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2093 reg &= ~DWC3_DCFG_NUMP_MASK;
2094 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2095 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2098 static int __dwc3_gadget_start(struct dwc3 *dwc)
2100 struct dwc3_ep *dep;
2105 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2106 * the core supports IMOD, disable it.
2108 if (dwc->imod_interval) {
2109 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2110 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2111 } else if (dwc3_has_imod(dwc)) {
2112 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2116 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2117 * field instead of letting dwc3 itself calculate that automatically.
2119 * This way, we maximize the chances that we'll be able to get several
2120 * bursts of data without going through any sort of endpoint throttling.
2122 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2123 if (DWC3_IP_IS(DWC3))
2124 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2126 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2128 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2130 dwc3_gadget_setup_nump(dwc);
2132 /* Start with SuperSpeed Default */
2133 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2136 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2138 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2143 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2145 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2149 /* begin to receive SETUP packets */
2150 dwc->ep0state = EP0_SETUP_PHASE;
2151 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2152 dwc3_ep0_out_start(dwc);
2154 dwc3_gadget_enable_irq(dwc);
2159 __dwc3_gadget_ep_disable(dwc->eps[0]);
2165 static int dwc3_gadget_start(struct usb_gadget *g,
2166 struct usb_gadget_driver *driver)
2168 struct dwc3 *dwc = gadget_to_dwc(g);
2169 unsigned long flags;
2173 irq = dwc->irq_gadget;
2174 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2175 IRQF_SHARED, "dwc3", dwc->ev_buf);
2177 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2182 spin_lock_irqsave(&dwc->lock, flags);
2183 if (dwc->gadget_driver) {
2184 dev_err(dwc->dev, "%s is already bound to %s\n",
2186 dwc->gadget_driver->driver.name);
2191 dwc->gadget_driver = driver;
2193 if (pm_runtime_active(dwc->dev))
2194 __dwc3_gadget_start(dwc);
2196 spin_unlock_irqrestore(&dwc->lock, flags);
2201 spin_unlock_irqrestore(&dwc->lock, flags);
2208 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2210 dwc3_gadget_disable_irq(dwc);
2211 __dwc3_gadget_ep_disable(dwc->eps[0]);
2212 __dwc3_gadget_ep_disable(dwc->eps[1]);
2215 static int dwc3_gadget_stop(struct usb_gadget *g)
2217 struct dwc3 *dwc = gadget_to_dwc(g);
2218 unsigned long flags;
2220 spin_lock_irqsave(&dwc->lock, flags);
2222 if (pm_runtime_suspended(dwc->dev))
2225 __dwc3_gadget_stop(dwc);
2228 dwc->gadget_driver = NULL;
2229 spin_unlock_irqrestore(&dwc->lock, flags);
2231 free_irq(dwc->irq_gadget, dwc->ev_buf);
2236 static void dwc3_gadget_config_params(struct usb_gadget *g,
2237 struct usb_dcd_config_params *params)
2239 struct dwc3 *dwc = gadget_to_dwc(g);
2241 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2242 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2244 /* Recommended BESL */
2245 if (!dwc->dis_enblslpm_quirk) {
2247 * If the recommended BESL baseline is 0 or if the BESL deep is
2248 * less than 2, Microsoft's Windows 10 host usb stack will issue
2249 * a usb reset immediately after it receives the extended BOS
2250 * descriptor and the enumeration will fail. To maintain
2251 * compatibility with the Windows' usb stack, let's set the
2252 * recommended BESL baseline to 1 and clamp the BESL deep to be
2255 params->besl_baseline = 1;
2256 if (dwc->is_utmi_l1_suspend)
2258 clamp_t(u8, dwc->hird_threshold, 2, 15);
2261 /* U1 Device exit Latency */
2262 if (dwc->dis_u1_entry_quirk)
2263 params->bU1devExitLat = 0;
2265 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2267 /* U2 Device exit Latency */
2268 if (dwc->dis_u2_entry_quirk)
2269 params->bU2DevExitLat = 0;
2271 params->bU2DevExitLat =
2272 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2275 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2276 enum usb_device_speed speed)
2278 struct dwc3 *dwc = gadget_to_dwc(g);
2279 unsigned long flags;
2282 spin_lock_irqsave(&dwc->lock, flags);
2283 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2284 reg &= ~(DWC3_DCFG_SPEED_MASK);
2287 * WORKAROUND: DWC3 revision < 2.20a have an issue
2288 * which would cause metastability state on Run/Stop
2289 * bit if we try to force the IP to USB2-only mode.
2291 * Because of that, we cannot configure the IP to any
2292 * speed other than the SuperSpeed
2296 * STAR#9000525659: Clock Domain Crossing on DCTL in
2299 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2300 !dwc->dis_metastability_quirk) {
2301 reg |= DWC3_DCFG_SUPERSPEED;
2305 reg |= DWC3_DCFG_LOWSPEED;
2307 case USB_SPEED_FULL:
2308 reg |= DWC3_DCFG_FULLSPEED;
2310 case USB_SPEED_HIGH:
2311 reg |= DWC3_DCFG_HIGHSPEED;
2313 case USB_SPEED_SUPER:
2314 reg |= DWC3_DCFG_SUPERSPEED;
2316 case USB_SPEED_SUPER_PLUS:
2317 if (DWC3_IP_IS(DWC3))
2318 reg |= DWC3_DCFG_SUPERSPEED;
2320 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2323 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2325 if (DWC3_IP_IS(DWC3))
2326 reg |= DWC3_DCFG_SUPERSPEED;
2328 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2331 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2333 spin_unlock_irqrestore(&dwc->lock, flags);
2336 static const struct usb_gadget_ops dwc3_gadget_ops = {
2337 .get_frame = dwc3_gadget_get_frame,
2338 .wakeup = dwc3_gadget_wakeup,
2339 .set_selfpowered = dwc3_gadget_set_selfpowered,
2340 .pullup = dwc3_gadget_pullup,
2341 .udc_start = dwc3_gadget_start,
2342 .udc_stop = dwc3_gadget_stop,
2343 .udc_set_speed = dwc3_gadget_set_speed,
2344 .get_config_params = dwc3_gadget_config_params,
2347 /* -------------------------------------------------------------------------- */
2349 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2351 struct dwc3 *dwc = dep->dwc;
2353 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2354 dep->endpoint.maxburst = 1;
2355 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2356 if (!dep->direction)
2357 dwc->gadget.ep0 = &dep->endpoint;
2359 dep->endpoint.caps.type_control = true;
2364 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2366 struct dwc3 *dwc = dep->dwc;
2370 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2371 if (DWC3_IP_IS(DWC32))
2372 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2374 /* MDWIDTH is represented in bits, we need it in bytes */
2377 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2378 if (DWC3_IP_IS(DWC3))
2379 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2381 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2383 /* FIFO Depth is in MDWDITH bytes. Multiply */
2387 * To meet performance requirement, a minimum TxFIFO size of 3x
2388 * MaxPacketSize is recommended for endpoints that support burst and a
2389 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2390 * support burst. Use those numbers and we can calculate the max packet
2393 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2398 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2400 dep->endpoint.max_streams = 15;
2401 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2402 list_add_tail(&dep->endpoint.ep_list,
2403 &dwc->gadget.ep_list);
2404 dep->endpoint.caps.type_iso = true;
2405 dep->endpoint.caps.type_bulk = true;
2406 dep->endpoint.caps.type_int = true;
2408 return dwc3_alloc_trb_pool(dep);
2411 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2413 struct dwc3 *dwc = dep->dwc;
2417 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2418 if (DWC3_IP_IS(DWC32))
2419 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2421 /* MDWIDTH is represented in bits, convert to bytes */
2424 /* All OUT endpoints share a single RxFIFO space */
2425 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2426 if (DWC3_IP_IS(DWC3))
2427 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2429 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2431 /* FIFO depth is in MDWDITH bytes */
2435 * To meet performance requirement, a minimum recommended RxFIFO size
2436 * is defined as follow:
2437 * RxFIFO size >= (3 x MaxPacketSize) +
2438 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2440 * Then calculate the max packet limit as below.
2442 size -= (3 * 8) + 16;
2448 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2449 dep->endpoint.max_streams = 15;
2450 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2451 list_add_tail(&dep->endpoint.ep_list,
2452 &dwc->gadget.ep_list);
2453 dep->endpoint.caps.type_iso = true;
2454 dep->endpoint.caps.type_bulk = true;
2455 dep->endpoint.caps.type_int = true;
2457 return dwc3_alloc_trb_pool(dep);
2460 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2462 struct dwc3_ep *dep;
2463 bool direction = epnum & 1;
2465 u8 num = epnum >> 1;
2467 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2472 dep->number = epnum;
2473 dep->direction = direction;
2474 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2475 dwc->eps[epnum] = dep;
2477 dep->start_cmd_status = 0;
2479 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2480 direction ? "in" : "out");
2482 dep->endpoint.name = dep->name;
2484 if (!(dep->number > 1)) {
2485 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2486 dep->endpoint.comp_desc = NULL;
2490 ret = dwc3_gadget_init_control_endpoint(dep);
2492 ret = dwc3_gadget_init_in_endpoint(dep);
2494 ret = dwc3_gadget_init_out_endpoint(dep);
2499 dep->endpoint.caps.dir_in = direction;
2500 dep->endpoint.caps.dir_out = !direction;
2502 INIT_LIST_HEAD(&dep->pending_list);
2503 INIT_LIST_HEAD(&dep->started_list);
2504 INIT_LIST_HEAD(&dep->cancelled_list);
2509 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2513 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2515 for (epnum = 0; epnum < total; epnum++) {
2518 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2526 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2528 struct dwc3_ep *dep;
2531 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2532 dep = dwc->eps[epnum];
2536 * Physical endpoints 0 and 1 are special; they form the
2537 * bi-directional USB endpoint 0.
2539 * For those two physical endpoints, we don't allocate a TRB
2540 * pool nor do we add them the endpoints list. Due to that, we
2541 * shouldn't do these two operations otherwise we would end up
2542 * with all sorts of bugs when removing dwc3.ko.
2544 if (epnum != 0 && epnum != 1) {
2545 dwc3_free_trb_pool(dep);
2546 list_del(&dep->endpoint.ep_list);
2553 /* -------------------------------------------------------------------------- */
2555 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2556 struct dwc3_request *req, struct dwc3_trb *trb,
2557 const struct dwc3_event_depevt *event, int status, int chain)
2561 dwc3_ep_inc_deq(dep);
2563 trace_dwc3_complete_trb(dep, trb);
2567 * If we're in the middle of series of chained TRBs and we
2568 * receive a short transfer along the way, DWC3 will skip
2569 * through all TRBs including the last TRB in the chain (the
2570 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2571 * bit and SW has to do it manually.
2573 * We're going to do that here to avoid problems of HW trying
2574 * to use bogus TRBs for transfers.
2576 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2577 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2580 * For isochronous transfers, the first TRB in a service interval must
2581 * have the Isoc-First type. Track and report its interval frame number.
2583 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2584 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2585 unsigned int frame_number;
2587 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2588 frame_number &= ~(dep->interval - 1);
2589 req->request.frame_number = frame_number;
2593 * If we're dealing with unaligned size OUT transfer, we will be left
2594 * with one TRB pending in the ring. We need to manually clear HWO bit
2598 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2599 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2603 count = trb->size & DWC3_TRB_SIZE_MASK;
2604 req->remaining += count;
2606 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2609 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2612 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2613 (trb->ctrl & DWC3_TRB_CTRL_LST))
2619 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2620 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2623 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2624 struct scatterlist *sg = req->sg;
2625 struct scatterlist *s;
2626 unsigned int pending = req->num_pending_sgs;
2630 for_each_sg(sg, s, pending, i) {
2631 trb = &dep->trb_pool[dep->trb_dequeue];
2633 req->sg = sg_next(s);
2634 req->num_pending_sgs--;
2636 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2637 trb, event, status, true);
2645 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2646 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2649 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2651 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2652 event, status, false);
2655 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2657 return req->num_pending_sgs == 0;
2660 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2661 const struct dwc3_event_depevt *event,
2662 struct dwc3_request *req, int status)
2666 if (req->num_pending_sgs)
2667 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2670 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2673 if (req->needs_extra_trb) {
2674 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2676 req->needs_extra_trb = false;
2679 req->request.actual = req->request.length - req->remaining;
2681 if (!dwc3_gadget_ep_request_completed(req))
2684 dwc3_gadget_giveback(dep, req, status);
2690 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2691 const struct dwc3_event_depevt *event, int status)
2693 struct dwc3_request *req;
2694 struct dwc3_request *tmp;
2696 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2699 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2706 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2708 struct dwc3_request *req;
2710 if (!list_empty(&dep->pending_list))
2714 * We only need to check the first entry of the started list. We can
2715 * assume the completed requests are removed from the started list.
2717 req = next_request(&dep->started_list);
2721 return !dwc3_gadget_ep_request_completed(req);
2724 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2725 const struct dwc3_event_depevt *event)
2727 dep->frame_number = event->parameters;
2730 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
2731 const struct dwc3_event_depevt *event, int status)
2733 struct dwc3 *dwc = dep->dwc;
2734 bool no_started_trb = true;
2736 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2738 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2741 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2742 list_empty(&dep->started_list) &&
2743 (list_empty(&dep->pending_list) || status == -EXDEV))
2744 dwc3_stop_active_transfer(dep, true, true);
2745 else if (dwc3_gadget_ep_should_continue(dep))
2746 if (__dwc3_gadget_kick_transfer(dep) == 0)
2747 no_started_trb = false;
2751 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2752 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2754 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
2758 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2761 if (!(dep->flags & DWC3_EP_ENABLED))
2764 if (!list_empty(&dep->started_list))
2765 return no_started_trb;
2768 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2770 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2775 return no_started_trb;
2778 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2779 const struct dwc3_event_depevt *event)
2783 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2784 dwc3_gadget_endpoint_frame_from_event(dep, event);
2786 if (event->status & DEPEVT_STATUS_BUSERR)
2787 status = -ECONNRESET;
2789 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
2792 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
2795 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
2796 const struct dwc3_event_depevt *event)
2800 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2802 if (event->status & DEPEVT_STATUS_BUSERR)
2803 status = -ECONNRESET;
2805 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
2806 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2809 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2810 const struct dwc3_event_depevt *event)
2812 dwc3_gadget_endpoint_frame_from_event(dep, event);
2815 * The XferNotReady event is generated only once before the endpoint
2816 * starts. It will be generated again when END_TRANSFER command is
2817 * issued. For some controller versions, the XferNotReady event may be
2818 * generated while the END_TRANSFER command is still in process. Ignore
2819 * it and wait for the next XferNotReady event after the command is
2822 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2825 (void) __dwc3_gadget_start_isoc(dep);
2828 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
2829 const struct dwc3_event_depevt *event)
2831 struct dwc3 *dwc = dep->dwc;
2833 if (event->status == DEPEVT_STREAMEVT_FOUND) {
2834 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
2838 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
2839 switch (event->parameters) {
2840 case DEPEVT_STREAM_PRIME:
2842 * If the host can properly transition the endpoint state from
2843 * idle to prime after a NoStream rejection, there's no need to
2844 * force restarting the endpoint to reinitiate the stream. To
2845 * simplify the check, assume the host follows the USB spec if
2846 * it primed the endpoint more than once.
2848 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
2849 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
2850 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
2852 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
2856 case DEPEVT_STREAM_NOSTREAM:
2857 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
2858 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
2859 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
2863 * If the host rejects a stream due to no active stream, by the
2864 * USB and xHCI spec, the endpoint will be put back to idle
2865 * state. When the host is ready (buffer added/updated), it will
2866 * prime the endpoint to inform the usb device controller. This
2867 * triggers the device controller to issue ERDY to restart the
2868 * stream. However, some hosts don't follow this and keep the
2869 * endpoint in the idle state. No prime will come despite host
2870 * streams are updated, and the device controller will not be
2871 * triggered to generate ERDY to move the next stream data. To
2872 * workaround this and maintain compatibility with various
2873 * hosts, force to reinitate the stream until the host is ready
2874 * instead of waiting for the host to prime the endpoint.
2876 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
2877 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
2879 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
2881 dep->flags |= DWC3_EP_DELAY_START;
2882 dwc3_stop_active_transfer(dep, true, true);
2889 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
2892 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2893 const struct dwc3_event_depevt *event)
2895 struct dwc3_ep *dep;
2896 u8 epnum = event->endpoint_number;
2899 dep = dwc->eps[epnum];
2901 if (!(dep->flags & DWC3_EP_ENABLED)) {
2902 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2905 /* Handle only EPCMDCMPLT when EP disabled */
2906 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2910 if (epnum == 0 || epnum == 1) {
2911 dwc3_ep0_interrupt(dwc, event);
2915 switch (event->endpoint_event) {
2916 case DWC3_DEPEVT_XFERINPROGRESS:
2917 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2919 case DWC3_DEPEVT_XFERNOTREADY:
2920 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2922 case DWC3_DEPEVT_EPCMDCMPLT:
2923 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2925 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2926 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2927 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2928 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2929 if ((dep->flags & DWC3_EP_DELAY_START) &&
2930 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2931 __dwc3_gadget_kick_transfer(dep);
2933 dep->flags &= ~DWC3_EP_DELAY_START;
2936 case DWC3_DEPEVT_XFERCOMPLETE:
2937 dwc3_gadget_endpoint_transfer_complete(dep, event);
2939 case DWC3_DEPEVT_STREAMEVT:
2940 dwc3_gadget_endpoint_stream_event(dep, event);
2942 case DWC3_DEPEVT_RXTXFIFOEVT:
2947 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2949 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2950 spin_unlock(&dwc->lock);
2951 dwc->gadget_driver->disconnect(&dwc->gadget);
2952 spin_lock(&dwc->lock);
2956 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2958 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2959 spin_unlock(&dwc->lock);
2960 dwc->gadget_driver->suspend(&dwc->gadget);
2961 spin_lock(&dwc->lock);
2965 static void dwc3_resume_gadget(struct dwc3 *dwc)
2967 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2968 spin_unlock(&dwc->lock);
2969 dwc->gadget_driver->resume(&dwc->gadget);
2970 spin_lock(&dwc->lock);
2974 static void dwc3_reset_gadget(struct dwc3 *dwc)
2976 if (!dwc->gadget_driver)
2979 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2980 spin_unlock(&dwc->lock);
2981 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2982 spin_lock(&dwc->lock);
2986 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2989 struct dwc3_gadget_ep_cmd_params params;
2993 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
2994 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2998 * NOTICE: We are violating what the Databook says about the
2999 * EndTransfer command. Ideally we would _always_ wait for the
3000 * EndTransfer Command Completion IRQ, but that's causing too
3001 * much trouble synchronizing between us and gadget driver.
3003 * We have discussed this with the IP Provider and it was
3004 * suggested to giveback all requests here.
3006 * Note also that a similar handling was tested by Synopsys
3007 * (thanks a lot Paul) and nothing bad has come out of it.
3008 * In short, what we're doing is issuing EndTransfer with
3009 * CMDIOC bit set and delay kicking transfer until the
3010 * EndTransfer command had completed.
3012 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3013 * supports a mode to work around the above limitation. The
3014 * software can poll the CMDACT bit in the DEPCMD register
3015 * after issuing a EndTransfer command. This mode is enabled
3016 * by writing GUCTL2[14]. This polling is already done in the
3017 * dwc3_send_gadget_ep_cmd() function so if the mode is
3018 * enabled, the EndTransfer command will have completed upon
3019 * returning from this function.
3021 * This mode is NOT available on the DWC_usb31 IP.
3024 cmd = DWC3_DEPCMD_ENDTRANSFER;
3025 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3026 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3027 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3028 memset(¶ms, 0, sizeof(params));
3029 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3031 dep->resource_index = 0;
3034 * The END_TRANSFER command will cause the controller to generate a
3035 * NoStream Event, and it's not due to the host DP NoStream rejection.
3036 * Ignore the next NoStream event.
3038 if (dep->stream_capable)
3039 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3042 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3044 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3047 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3051 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3052 struct dwc3_ep *dep;
3055 dep = dwc->eps[epnum];
3059 if (!(dep->flags & DWC3_EP_STALL))
3062 dep->flags &= ~DWC3_EP_STALL;
3064 ret = dwc3_send_clear_stall_ep_cmd(dep);
3069 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3073 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3075 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3076 reg &= ~DWC3_DCTL_INITU1ENA;
3077 reg &= ~DWC3_DCTL_INITU2ENA;
3078 dwc3_gadget_dctl_write_safe(dwc, reg);
3080 dwc3_disconnect_gadget(dwc);
3082 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3083 dwc->setup_packet_pending = false;
3084 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
3086 dwc->connected = false;
3089 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3093 dwc->connected = true;
3096 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3097 * would cause a missing Disconnect Event if there's a
3098 * pending Setup Packet in the FIFO.
3100 * There's no suggested workaround on the official Bug
3101 * report, which states that "unless the driver/application
3102 * is doing any special handling of a disconnect event,
3103 * there is no functional issue".
3105 * Unfortunately, it turns out that we _do_ some special
3106 * handling of a disconnect event, namely complete all
3107 * pending transfers, notify gadget driver of the
3108 * disconnection, and so on.
3110 * Our suggested workaround is to follow the Disconnect
3111 * Event steps here, instead, based on a setup_packet_pending
3112 * flag. Such flag gets set whenever we have a SETUP_PENDING
3113 * status for EP0 TRBs and gets cleared on XferComplete for the
3118 * STAR#9000466709: RTL: Device : Disconnect event not
3119 * generated if setup packet pending in FIFO
3121 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3122 if (dwc->setup_packet_pending)
3123 dwc3_gadget_disconnect_interrupt(dwc);
3126 dwc3_reset_gadget(dwc);
3128 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3129 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3130 dwc3_gadget_dctl_write_safe(dwc, reg);
3131 dwc->test_mode = false;
3132 dwc3_clear_stall_all_ep(dwc);
3134 /* Reset device address to zero */
3135 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3136 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3137 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3140 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3142 struct dwc3_ep *dep;
3147 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3148 speed = reg & DWC3_DSTS_CONNECTSPD;
3152 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3153 * each time on Connect Done.
3155 * Currently we always use the reset value. If any platform
3156 * wants to set this to a different value, we need to add a
3157 * setting and update GCTL.RAMCLKSEL here.
3161 case DWC3_DSTS_SUPERSPEED_PLUS:
3162 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3163 dwc->gadget.ep0->maxpacket = 512;
3164 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
3166 case DWC3_DSTS_SUPERSPEED:
3168 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3169 * would cause a missing USB3 Reset event.
3171 * In such situations, we should force a USB3 Reset
3172 * event by calling our dwc3_gadget_reset_interrupt()
3177 * STAR#9000483510: RTL: SS : USB3 reset event may
3178 * not be generated always when the link enters poll
3180 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3181 dwc3_gadget_reset_interrupt(dwc);
3183 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3184 dwc->gadget.ep0->maxpacket = 512;
3185 dwc->gadget.speed = USB_SPEED_SUPER;
3187 case DWC3_DSTS_HIGHSPEED:
3188 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3189 dwc->gadget.ep0->maxpacket = 64;
3190 dwc->gadget.speed = USB_SPEED_HIGH;
3192 case DWC3_DSTS_FULLSPEED:
3193 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3194 dwc->gadget.ep0->maxpacket = 64;
3195 dwc->gadget.speed = USB_SPEED_FULL;
3197 case DWC3_DSTS_LOWSPEED:
3198 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
3199 dwc->gadget.ep0->maxpacket = 8;
3200 dwc->gadget.speed = USB_SPEED_LOW;
3204 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
3206 /* Enable USB2 LPM Capability */
3208 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3209 (speed != DWC3_DSTS_SUPERSPEED) &&
3210 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3211 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3212 reg |= DWC3_DCFG_LPM_CAP;
3213 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3215 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3216 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3218 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3219 (dwc->is_utmi_l1_suspend << 4));
3222 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3223 * DCFG.LPMCap is set, core responses with an ACK and the
3224 * BESL value in the LPM token is less than or equal to LPM
3227 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3228 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3230 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3231 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3233 dwc3_gadget_dctl_write_safe(dwc, reg);
3235 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3236 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3237 dwc3_gadget_dctl_write_safe(dwc, reg);
3241 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3243 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3248 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3250 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3255 * Configure PHY via GUSB3PIPECTLn if required.
3257 * Update GTXFIFOSIZn
3259 * In both cases reset values should be sufficient.
3263 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3266 * TODO take core out of low power mode when that's
3270 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3271 spin_unlock(&dwc->lock);
3272 dwc->gadget_driver->resume(&dwc->gadget);
3273 spin_lock(&dwc->lock);
3277 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3278 unsigned int evtinfo)
3280 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3281 unsigned int pwropt;
3284 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3285 * Hibernation mode enabled which would show up when device detects
3286 * host-initiated U3 exit.
3288 * In that case, device will generate a Link State Change Interrupt
3289 * from U3 to RESUME which is only necessary if Hibernation is
3292 * There are no functional changes due to such spurious event and we
3293 * just need to ignore it.
3297 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3300 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3301 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3302 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3303 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3304 (next == DWC3_LINK_STATE_RESUME)) {
3310 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3311 * on the link partner, the USB session might do multiple entry/exit
3312 * of low power states before a transfer takes place.
3314 * Due to this problem, we might experience lower throughput. The
3315 * suggested workaround is to disable DCTL[12:9] bits if we're
3316 * transitioning from U1/U2 to U0 and enable those bits again
3317 * after a transfer completes and there are no pending transfers
3318 * on any of the enabled endpoints.
3320 * This is the first half of that workaround.
3324 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3325 * core send LGO_Ux entering U0
3327 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3328 if (next == DWC3_LINK_STATE_U0) {
3332 switch (dwc->link_state) {
3333 case DWC3_LINK_STATE_U1:
3334 case DWC3_LINK_STATE_U2:
3335 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3336 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3337 | DWC3_DCTL_ACCEPTU2ENA
3338 | DWC3_DCTL_INITU1ENA
3339 | DWC3_DCTL_ACCEPTU1ENA);
3342 dwc->u1u2 = reg & u1u2;
3346 dwc3_gadget_dctl_write_safe(dwc, reg);
3356 case DWC3_LINK_STATE_U1:
3357 if (dwc->speed == USB_SPEED_SUPER)
3358 dwc3_suspend_gadget(dwc);
3360 case DWC3_LINK_STATE_U2:
3361 case DWC3_LINK_STATE_U3:
3362 dwc3_suspend_gadget(dwc);
3364 case DWC3_LINK_STATE_RESUME:
3365 dwc3_resume_gadget(dwc);
3372 dwc->link_state = next;
3375 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3376 unsigned int evtinfo)
3378 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3380 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3381 dwc3_suspend_gadget(dwc);
3383 dwc->link_state = next;
3386 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3387 unsigned int evtinfo)
3389 unsigned int is_ss = evtinfo & BIT(4);
3392 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3393 * have a known issue which can cause USB CV TD.9.23 to fail
3396 * Because of this issue, core could generate bogus hibernation
3397 * events which SW needs to ignore.
3401 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3402 * Device Fallback from SuperSpeed
3404 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3407 /* enter hibernation here */
3410 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3411 const struct dwc3_event_devt *event)
3413 switch (event->type) {
3414 case DWC3_DEVICE_EVENT_DISCONNECT:
3415 dwc3_gadget_disconnect_interrupt(dwc);
3417 case DWC3_DEVICE_EVENT_RESET:
3418 dwc3_gadget_reset_interrupt(dwc);
3420 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3421 dwc3_gadget_conndone_interrupt(dwc);
3423 case DWC3_DEVICE_EVENT_WAKEUP:
3424 dwc3_gadget_wakeup_interrupt(dwc);
3426 case DWC3_DEVICE_EVENT_HIBER_REQ:
3427 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3428 "unexpected hibernation event\n"))
3431 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3433 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3434 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3436 case DWC3_DEVICE_EVENT_EOPF:
3437 /* It changed to be suspend event for version 2.30a and above */
3438 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3440 * Ignore suspend event until the gadget enters into
3441 * USB_STATE_CONFIGURED state.
3443 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3444 dwc3_gadget_suspend_interrupt(dwc,
3448 case DWC3_DEVICE_EVENT_SOF:
3449 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3450 case DWC3_DEVICE_EVENT_CMD_CMPL:
3451 case DWC3_DEVICE_EVENT_OVERFLOW:
3454 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3458 static void dwc3_process_event_entry(struct dwc3 *dwc,
3459 const union dwc3_event *event)
3461 trace_dwc3_event(event->raw, dwc);
3463 if (!event->type.is_devspec)
3464 dwc3_endpoint_interrupt(dwc, &event->depevt);
3465 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3466 dwc3_gadget_interrupt(dwc, &event->devt);
3468 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3471 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3473 struct dwc3 *dwc = evt->dwc;
3474 irqreturn_t ret = IRQ_NONE;
3480 if (!(evt->flags & DWC3_EVENT_PENDING))
3484 union dwc3_event event;
3486 event.raw = *(u32 *) (evt->cache + evt->lpos);
3488 dwc3_process_event_entry(dwc, &event);
3491 * FIXME we wrap around correctly to the next entry as
3492 * almost all entries are 4 bytes in size. There is one
3493 * entry which has 12 bytes which is a regular entry
3494 * followed by 8 bytes data. ATM I don't know how
3495 * things are organized if we get next to the a
3496 * boundary so I worry about that once we try to handle
3499 evt->lpos = (evt->lpos + 4) % evt->length;
3504 evt->flags &= ~DWC3_EVENT_PENDING;
3507 /* Unmask interrupt */
3508 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3509 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3510 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3512 if (dwc->imod_interval) {
3513 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3514 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3520 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3522 struct dwc3_event_buffer *evt = _evt;
3523 struct dwc3 *dwc = evt->dwc;
3524 unsigned long flags;
3525 irqreturn_t ret = IRQ_NONE;
3527 spin_lock_irqsave(&dwc->lock, flags);
3528 ret = dwc3_process_event_buf(evt);
3529 spin_unlock_irqrestore(&dwc->lock, flags);
3534 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3536 struct dwc3 *dwc = evt->dwc;
3541 if (pm_runtime_suspended(dwc->dev)) {
3542 pm_runtime_get(dwc->dev);
3543 disable_irq_nosync(dwc->irq_gadget);
3544 dwc->pending_events = true;
3549 * With PCIe legacy interrupt, test shows that top-half irq handler can
3550 * be called again after HW interrupt deassertion. Check if bottom-half
3551 * irq event handler completes before caching new event to prevent
3554 if (evt->flags & DWC3_EVENT_PENDING)
3557 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3558 count &= DWC3_GEVNTCOUNT_MASK;
3563 evt->flags |= DWC3_EVENT_PENDING;
3565 /* Mask interrupt */
3566 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3567 reg |= DWC3_GEVNTSIZ_INTMASK;
3568 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3570 amount = min(count, evt->length - evt->lpos);
3571 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3574 memcpy(evt->cache, evt->buf, count - amount);
3576 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3578 return IRQ_WAKE_THREAD;
3581 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3583 struct dwc3_event_buffer *evt = _evt;
3585 return dwc3_check_event_buf(evt);
3588 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3590 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3593 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3597 if (irq == -EPROBE_DEFER)
3600 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3604 if (irq == -EPROBE_DEFER)
3607 irq = platform_get_irq(dwc3_pdev, 0);
3619 * dwc3_gadget_init - initializes gadget related registers
3620 * @dwc: pointer to our controller context structure
3622 * Returns 0 on success otherwise negative errno.
3624 int dwc3_gadget_init(struct dwc3 *dwc)
3629 irq = dwc3_gadget_get_irq(dwc);
3635 dwc->irq_gadget = irq;
3637 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3638 sizeof(*dwc->ep0_trb) * 2,
3639 &dwc->ep0_trb_addr, GFP_KERNEL);
3640 if (!dwc->ep0_trb) {
3641 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3646 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3647 if (!dwc->setup_buf) {
3652 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3653 &dwc->bounce_addr, GFP_KERNEL);
3659 init_completion(&dwc->ep0_in_setup);
3661 dwc->gadget.ops = &dwc3_gadget_ops;
3662 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3663 dwc->gadget.sg_supported = true;
3664 dwc->gadget.name = "dwc3-gadget";
3665 dwc->gadget.lpm_capable = true;
3668 * FIXME We might be setting max_speed to <SUPER, however versions
3669 * <2.20a of dwc3 have an issue with metastability (documented
3670 * elsewhere in this driver) which tells us we can't set max speed to
3671 * anything lower than SUPER.
3673 * Because gadget.max_speed is only used by composite.c and function
3674 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3675 * to happen so we avoid sending SuperSpeed Capability descriptor
3676 * together with our BOS descriptor as that could confuse host into
3677 * thinking we can handle super speed.
3679 * Note that, in fact, we won't even support GetBOS requests when speed
3680 * is less than super speed because we don't have means, yet, to tell
3681 * composite.c that we are USB 2.0 + LPM ECN.
3683 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
3684 !dwc->dis_metastability_quirk)
3685 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3688 dwc->gadget.max_speed = dwc->maximum_speed;
3691 * REVISIT: Here we should clear all pending IRQs to be
3692 * sure we're starting from a well known location.
3695 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3699 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3701 dev_err(dwc->dev, "failed to register udc\n");
3705 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3710 dwc3_gadget_free_endpoints(dwc);
3713 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3717 kfree(dwc->setup_buf);
3720 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3721 dwc->ep0_trb, dwc->ep0_trb_addr);
3727 /* -------------------------------------------------------------------------- */
3729 void dwc3_gadget_exit(struct dwc3 *dwc)
3731 usb_del_gadget_udc(&dwc->gadget);
3732 dwc3_gadget_free_endpoints(dwc);
3733 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3735 kfree(dwc->setup_buf);
3736 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3737 dwc->ep0_trb, dwc->ep0_trb_addr);
3740 int dwc3_gadget_suspend(struct dwc3 *dwc)
3742 if (!dwc->gadget_driver)
3745 dwc3_gadget_run_stop(dwc, false, false);
3746 dwc3_disconnect_gadget(dwc);
3747 __dwc3_gadget_stop(dwc);
3752 int dwc3_gadget_resume(struct dwc3 *dwc)
3756 if (!dwc->gadget_driver)
3759 ret = __dwc3_gadget_start(dwc);
3763 ret = dwc3_gadget_run_stop(dwc, true, false);
3770 __dwc3_gadget_stop(dwc);
3776 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3778 if (dwc->pending_events) {
3779 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3780 dwc->pending_events = false;
3781 enable_irq(dwc->irq_gadget);