1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
180 req->needs_extra_trb = false;
182 if (req->request.status == -EINPROGRESS)
183 req->request.status = status;
186 usb_gadget_unmap_request_by_dev(dwc->sysdev,
187 &req->request, req->direction);
190 trace_dwc3_gadget_giveback(req);
193 pm_runtime_put(dwc->dev);
197 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
198 * @dep: The endpoint to whom the request belongs to
199 * @req: The request we're giving back
200 * @status: completion code for the request
202 * Must be called with controller's lock held and interrupts disabled. This
203 * function will unmap @req and call its ->complete() callback to notify upper
204 * layers that it has completed.
206 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209 struct dwc3 *dwc = dep->dwc;
211 dwc3_gadget_del_and_unmap_request(dep, req, status);
212 req->status = DWC3_REQUEST_STATUS_COMPLETED;
214 spin_unlock(&dwc->lock);
215 usb_gadget_giveback_request(&dep->endpoint, &req->request);
216 spin_lock(&dwc->lock);
220 * dwc3_send_gadget_generic_command - issue a generic command for the controller
221 * @dwc: pointer to the controller context
222 * @cmd: the command to be issued
223 * @param: command parameter
225 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
226 * and wait for its completion.
228 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
235 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
236 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
239 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
240 if (!(reg & DWC3_DGCMD_CMDACT)) {
241 status = DWC3_DGCMD_STATUS(reg);
253 trace_dwc3_gadget_generic_cmd(cmd, param, status);
258 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
261 * dwc3_send_gadget_ep_cmd - issue an endpoint command
262 * @dep: the endpoint to which the command is going to be issued
263 * @cmd: the command to be issued
264 * @params: parameters to the command
266 * Caller should handle locking. This function will issue @cmd with given
267 * @params to @dep and wait for its completion.
269 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
270 struct dwc3_gadget_ep_cmd_params *params)
272 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
273 struct dwc3 *dwc = dep->dwc;
275 u32 saved_config = 0;
282 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
283 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
286 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
287 * settings. Restore them after the command is completed.
289 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
291 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
292 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
293 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
294 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
295 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
298 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
299 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
300 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
304 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
307 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
310 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
311 dwc->link_state == DWC3_LINK_STATE_U2 ||
312 dwc->link_state == DWC3_LINK_STATE_U3);
314 if (unlikely(needs_wakeup)) {
315 ret = __dwc3_gadget_wakeup(dwc);
316 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
323 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
326 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
327 * not relying on XferNotReady, we can make use of a special "No
328 * Response Update Transfer" command where we should clear both CmdAct
331 * With this, we don't need to wait for command completion and can
332 * straight away issue further commands to the endpoint.
334 * NOTICE: We're making an assumption that control endpoints will never
335 * make use of Update Transfer command. This is a safe assumption
336 * because we can never have more than one request at a time with
337 * Control Endpoints. If anybody changes that assumption, this chunk
338 * needs to be updated accordingly.
340 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
341 !usb_endpoint_xfer_isoc(desc))
342 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
344 cmd |= DWC3_DEPCMD_CMDACT;
346 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
348 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
349 if (!(reg & DWC3_DEPCMD_CMDACT)) {
350 cmd_status = DWC3_DEPCMD_STATUS(reg);
352 switch (cmd_status) {
356 case DEPEVT_TRANSFER_NO_RESOURCE:
359 case DEPEVT_TRANSFER_BUS_EXPIRY:
361 * SW issues START TRANSFER command to
362 * isochronous ep with future frame interval. If
363 * future interval time has already passed when
364 * core receives the command, it will respond
365 * with an error status of 'Bus Expiry'.
367 * Instead of always returning -EINVAL, let's
368 * give a hint to the gadget driver that this is
369 * the case by returning -EAGAIN.
374 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
383 cmd_status = -ETIMEDOUT;
386 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
389 switch (DWC3_DEPCMD_CMD(cmd)) {
390 case DWC3_DEPCMD_STARTTRANSFER:
391 dep->flags |= DWC3_EP_TRANSFER_STARTED;
392 dwc3_gadget_ep_get_transfer_index(dep);
394 case DWC3_DEPCMD_ENDTRANSFER:
395 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
404 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
406 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
412 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
414 struct dwc3 *dwc = dep->dwc;
415 struct dwc3_gadget_ep_cmd_params params;
416 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
419 * As of core revision 2.60a the recommended programming model
420 * is to set the ClearPendIN bit when issuing a Clear Stall EP
421 * command for IN endpoints. This is to prevent an issue where
422 * some (non-compliant) hosts may not send ACK TPs for pending
423 * IN transfers due to a mishandled error condition. Synopsys
426 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
427 (dwc->gadget.speed >= USB_SPEED_SUPER))
428 cmd |= DWC3_DEPCMD_CLEARPENDIN;
430 memset(¶ms, 0, sizeof(params));
432 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
435 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
436 struct dwc3_trb *trb)
438 u32 offset = (char *) trb - (char *) dep->trb_pool;
440 return dep->trb_pool_dma + offset;
443 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
445 struct dwc3 *dwc = dep->dwc;
450 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
451 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
452 &dep->trb_pool_dma, GFP_KERNEL);
453 if (!dep->trb_pool) {
454 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
462 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
464 struct dwc3 *dwc = dep->dwc;
466 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
467 dep->trb_pool, dep->trb_pool_dma);
469 dep->trb_pool = NULL;
470 dep->trb_pool_dma = 0;
473 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
475 struct dwc3_gadget_ep_cmd_params params;
477 memset(¶ms, 0x00, sizeof(params));
479 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
481 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
486 * dwc3_gadget_start_config - configure ep resources
487 * @dep: endpoint that is being enabled
489 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
490 * completion, it will set Transfer Resource for all available endpoints.
492 * The assignment of transfer resources cannot perfectly follow the data book
493 * due to the fact that the controller driver does not have all knowledge of the
494 * configuration in advance. It is given this information piecemeal by the
495 * composite gadget framework after every SET_CONFIGURATION and
496 * SET_INTERFACE. Trying to follow the databook programming model in this
497 * scenario can cause errors. For two reasons:
499 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
500 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
501 * incorrect in the scenario of multiple interfaces.
503 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
504 * endpoint on alt setting (8.1.6).
506 * The following simplified method is used instead:
508 * All hardware endpoints can be assigned a transfer resource and this setting
509 * will stay persistent until either a core reset or hibernation. So whenever we
510 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
511 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
512 * guaranteed that there are as many transfer resources as endpoints.
514 * This function is called for each endpoint when it is being enabled but is
515 * triggered only when called for EP0-out, which always happens first, and which
516 * should only happen in one of the above conditions.
518 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
520 struct dwc3_gadget_ep_cmd_params params;
529 memset(¶ms, 0x00, sizeof(params));
530 cmd = DWC3_DEPCMD_DEPSTARTCFG;
533 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
537 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
538 struct dwc3_ep *dep = dwc->eps[i];
543 ret = dwc3_gadget_set_xfer_resource(dep);
551 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
553 const struct usb_ss_ep_comp_descriptor *comp_desc;
554 const struct usb_endpoint_descriptor *desc;
555 struct dwc3_gadget_ep_cmd_params params;
556 struct dwc3 *dwc = dep->dwc;
558 comp_desc = dep->endpoint.comp_desc;
559 desc = dep->endpoint.desc;
561 memset(¶ms, 0x00, sizeof(params));
563 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
564 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
566 /* Burst size is only needed in SuperSpeed mode */
567 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
568 u32 burst = dep->endpoint.maxburst;
569 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
572 params.param0 |= action;
573 if (action == DWC3_DEPCFG_ACTION_RESTORE)
574 params.param2 |= dep->saved_state;
576 if (usb_endpoint_xfer_control(desc))
577 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
579 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
580 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
582 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
583 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
584 | DWC3_DEPCFG_STREAM_EVENT_EN;
585 dep->stream_capable = true;
588 if (!usb_endpoint_xfer_control(desc))
589 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
592 * We are doing 1:1 mapping for endpoints, meaning
593 * Physical Endpoints 2 maps to Logical Endpoint 2 and
594 * so on. We consider the direction bit as part of the physical
595 * endpoint number. So USB endpoint 0x81 is 0x03.
597 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
600 * We must use the lower 16 TX FIFOs even though
604 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
606 if (desc->bInterval) {
607 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
608 dep->interval = 1 << (desc->bInterval - 1);
611 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
615 * __dwc3_gadget_ep_enable - initializes a hw endpoint
616 * @dep: endpoint to be initialized
617 * @action: one of INIT, MODIFY or RESTORE
619 * Caller should take care of locking. Execute all necessary commands to
620 * initialize a HW endpoint so it can be used by a gadget driver.
622 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
624 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
625 struct dwc3 *dwc = dep->dwc;
630 if (!(dep->flags & DWC3_EP_ENABLED)) {
631 ret = dwc3_gadget_start_config(dep);
636 ret = dwc3_gadget_set_ep_config(dep, action);
640 if (!(dep->flags & DWC3_EP_ENABLED)) {
641 struct dwc3_trb *trb_st_hw;
642 struct dwc3_trb *trb_link;
644 dep->type = usb_endpoint_type(desc);
645 dep->flags |= DWC3_EP_ENABLED;
646 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
648 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
649 reg |= DWC3_DALEPENA_EP(dep->number);
650 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
652 if (usb_endpoint_xfer_control(desc))
655 /* Initialize the TRB ring */
656 dep->trb_dequeue = 0;
657 dep->trb_enqueue = 0;
658 memset(dep->trb_pool, 0,
659 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
661 /* Link TRB. The HWO bit is never reset */
662 trb_st_hw = &dep->trb_pool[0];
664 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
665 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
667 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
668 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
672 * Issue StartTransfer here with no-op TRB so we can always rely on No
673 * Response Update Transfer command.
675 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
676 usb_endpoint_xfer_int(desc)) {
677 struct dwc3_gadget_ep_cmd_params params;
678 struct dwc3_trb *trb;
682 memset(¶ms, 0, sizeof(params));
683 trb = &dep->trb_pool[0];
684 trb_dma = dwc3_trb_dma_offset(dep, trb);
686 params.param0 = upper_32_bits(trb_dma);
687 params.param1 = lower_32_bits(trb_dma);
689 cmd = DWC3_DEPCMD_STARTTRANSFER;
691 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
697 trace_dwc3_gadget_ep_enable(dep);
702 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
703 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
705 struct dwc3_request *req;
707 dwc3_stop_active_transfer(dep, true);
709 /* - giveback all requests to gadget driver */
710 while (!list_empty(&dep->started_list)) {
711 req = next_request(&dep->started_list);
713 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
716 while (!list_empty(&dep->pending_list)) {
717 req = next_request(&dep->pending_list);
719 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
724 * __dwc3_gadget_ep_disable - disables a hw endpoint
725 * @dep: the endpoint to disable
727 * This function undoes what __dwc3_gadget_ep_enable did and also removes
728 * requests which are currently being processed by the hardware and those which
729 * are not yet scheduled.
731 * Caller should take care of locking.
733 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
735 struct dwc3 *dwc = dep->dwc;
738 trace_dwc3_gadget_ep_disable(dep);
740 dwc3_remove_requests(dwc, dep);
742 /* make sure HW endpoint isn't stalled */
743 if (dep->flags & DWC3_EP_STALL)
744 __dwc3_gadget_ep_set_halt(dep, 0, false);
746 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
747 reg &= ~DWC3_DALEPENA_EP(dep->number);
748 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
750 dep->stream_capable = false;
752 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
754 /* Clear out the ep descriptors for non-ep0 */
755 if (dep->number > 1) {
756 dep->endpoint.comp_desc = NULL;
757 dep->endpoint.desc = NULL;
763 /* -------------------------------------------------------------------------- */
765 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
766 const struct usb_endpoint_descriptor *desc)
771 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
776 /* -------------------------------------------------------------------------- */
778 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
779 const struct usb_endpoint_descriptor *desc)
786 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
787 pr_debug("dwc3: invalid parameters\n");
791 if (!desc->wMaxPacketSize) {
792 pr_debug("dwc3: missing wMaxPacketSize\n");
796 dep = to_dwc3_ep(ep);
799 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
800 "%s is already enabled\n",
804 spin_lock_irqsave(&dwc->lock, flags);
805 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
806 spin_unlock_irqrestore(&dwc->lock, flags);
811 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
819 pr_debug("dwc3: invalid parameters\n");
823 dep = to_dwc3_ep(ep);
826 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
827 "%s is already disabled\n",
831 spin_lock_irqsave(&dwc->lock, flags);
832 ret = __dwc3_gadget_ep_disable(dep);
833 spin_unlock_irqrestore(&dwc->lock, flags);
838 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
841 struct dwc3_request *req;
842 struct dwc3_ep *dep = to_dwc3_ep(ep);
844 req = kzalloc(sizeof(*req), gfp_flags);
848 req->direction = dep->direction;
849 req->epnum = dep->number;
851 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
853 trace_dwc3_alloc_request(req);
855 return &req->request;
858 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
859 struct usb_request *request)
861 struct dwc3_request *req = to_dwc3_request(request);
863 trace_dwc3_free_request(req);
868 * dwc3_ep_prev_trb - returns the previous TRB in the ring
869 * @dep: The endpoint with the TRB ring
870 * @index: The index of the current TRB in the ring
872 * Returns the TRB prior to the one pointed to by the index. If the
873 * index is 0, we will wrap backwards, skip the link TRB, and return
874 * the one just before that.
876 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
881 tmp = DWC3_TRB_NUM - 1;
883 return &dep->trb_pool[tmp - 1];
886 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
888 struct dwc3_trb *tmp;
892 * If enqueue & dequeue are equal than it is either full or empty.
894 * One way to know for sure is if the TRB right before us has HWO bit
895 * set or not. If it has, then we're definitely full and can't fit any
896 * more transfers in our ring.
898 if (dep->trb_enqueue == dep->trb_dequeue) {
899 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
900 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
903 return DWC3_TRB_NUM - 1;
906 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
907 trbs_left &= (DWC3_TRB_NUM - 1);
909 if (dep->trb_dequeue < dep->trb_enqueue)
915 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
916 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
917 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
919 struct dwc3 *dwc = dep->dwc;
920 struct usb_gadget *gadget = &dwc->gadget;
921 enum usb_device_speed speed = gadget->speed;
923 trb->size = DWC3_TRB_SIZE_LENGTH(length);
924 trb->bpl = lower_32_bits(dma);
925 trb->bph = upper_32_bits(dma);
927 switch (usb_endpoint_type(dep->endpoint.desc)) {
928 case USB_ENDPOINT_XFER_CONTROL:
929 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
932 case USB_ENDPOINT_XFER_ISOC:
934 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
937 * USB Specification 2.0 Section 5.9.2 states that: "If
938 * there is only a single transaction in the microframe,
939 * only a DATA0 data packet PID is used. If there are
940 * two transactions per microframe, DATA1 is used for
941 * the first transaction data packet and DATA0 is used
942 * for the second transaction data packet. If there are
943 * three transactions per microframe, DATA2 is used for
944 * the first transaction data packet, DATA1 is used for
945 * the second, and DATA0 is used for the third."
947 * IOW, we should satisfy the following cases:
949 * 1) length <= maxpacket
952 * 2) maxpacket < length <= (2 * maxpacket)
955 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
956 * - DATA2, DATA1, DATA0
958 if (speed == USB_SPEED_HIGH) {
959 struct usb_ep *ep = &dep->endpoint;
960 unsigned int mult = 2;
961 unsigned int maxp = usb_endpoint_maxp(ep->desc);
963 if (length <= (2 * maxp))
969 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
972 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
975 /* always enable Interrupt on Missed ISOC */
976 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
979 case USB_ENDPOINT_XFER_BULK:
980 case USB_ENDPOINT_XFER_INT:
981 trb->ctrl = DWC3_TRBCTL_NORMAL;
985 * This is only possible with faulty memory because we
986 * checked it already :)
988 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
989 usb_endpoint_type(dep->endpoint.desc));
993 * Enable Continue on Short Packet
994 * when endpoint is not a stream capable
996 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
997 if (!dep->stream_capable)
998 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1001 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1004 if ((!no_interrupt && !chain) ||
1005 (dwc3_calc_trbs_left(dep) == 1))
1006 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1009 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1011 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1012 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1014 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1016 dwc3_ep_inc_enq(dep);
1018 trace_dwc3_prepare_trb(dep, trb);
1022 * dwc3_prepare_one_trb - setup one TRB from one request
1023 * @dep: endpoint for which this request is prepared
1024 * @req: dwc3_request pointer
1025 * @chain: should this TRB be chained to the next?
1026 * @node: only for isochronous endpoints. First TRB needs different type.
1028 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1029 struct dwc3_request *req, unsigned chain, unsigned node)
1031 struct dwc3_trb *trb;
1032 unsigned int length;
1034 unsigned stream_id = req->request.stream_id;
1035 unsigned short_not_ok = req->request.short_not_ok;
1036 unsigned no_interrupt = req->request.no_interrupt;
1038 if (req->request.num_sgs > 0) {
1039 length = sg_dma_len(req->start_sg);
1040 dma = sg_dma_address(req->start_sg);
1042 length = req->request.length;
1043 dma = req->request.dma;
1046 trb = &dep->trb_pool[dep->trb_enqueue];
1049 dwc3_gadget_move_started_request(req);
1051 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1056 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1057 stream_id, short_not_ok, no_interrupt);
1060 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1061 struct dwc3_request *req)
1063 struct scatterlist *sg = req->start_sg;
1064 struct scatterlist *s;
1067 unsigned int remaining = req->request.num_mapped_sgs
1068 - req->num_queued_sgs;
1070 for_each_sg(sg, s, remaining, i) {
1071 unsigned int length = req->request.length;
1072 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1073 unsigned int rem = length % maxp;
1074 unsigned chain = true;
1079 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1080 struct dwc3 *dwc = dep->dwc;
1081 struct dwc3_trb *trb;
1083 req->needs_extra_trb = true;
1085 /* prepare normal TRB */
1086 dwc3_prepare_one_trb(dep, req, true, i);
1088 /* Now prepare one extra TRB to align transfer size */
1089 trb = &dep->trb_pool[dep->trb_enqueue];
1091 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1092 maxp - rem, false, 1,
1093 req->request.stream_id,
1094 req->request.short_not_ok,
1095 req->request.no_interrupt);
1097 dwc3_prepare_one_trb(dep, req, chain, i);
1101 * There can be a situation where all sgs in sglist are not
1102 * queued because of insufficient trb number. To handle this
1103 * case, update start_sg to next sg to be queued, so that
1104 * we have free trbs we can continue queuing from where we
1105 * previously stopped
1108 req->start_sg = sg_next(s);
1110 req->num_queued_sgs++;
1112 if (!dwc3_calc_trbs_left(dep))
1117 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1118 struct dwc3_request *req)
1120 unsigned int length = req->request.length;
1121 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1122 unsigned int rem = length % maxp;
1124 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1125 struct dwc3 *dwc = dep->dwc;
1126 struct dwc3_trb *trb;
1128 req->needs_extra_trb = true;
1130 /* prepare normal TRB */
1131 dwc3_prepare_one_trb(dep, req, true, 0);
1133 /* Now prepare one extra TRB to align transfer size */
1134 trb = &dep->trb_pool[dep->trb_enqueue];
1136 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1137 false, 1, req->request.stream_id,
1138 req->request.short_not_ok,
1139 req->request.no_interrupt);
1140 } else if (req->request.zero && req->request.length &&
1141 (IS_ALIGNED(req->request.length, maxp))) {
1142 struct dwc3 *dwc = dep->dwc;
1143 struct dwc3_trb *trb;
1145 req->needs_extra_trb = true;
1147 /* prepare normal TRB */
1148 dwc3_prepare_one_trb(dep, req, true, 0);
1150 /* Now prepare one extra TRB to handle ZLP */
1151 trb = &dep->trb_pool[dep->trb_enqueue];
1153 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1154 false, 1, req->request.stream_id,
1155 req->request.short_not_ok,
1156 req->request.no_interrupt);
1158 dwc3_prepare_one_trb(dep, req, false, 0);
1163 * dwc3_prepare_trbs - setup TRBs from requests
1164 * @dep: endpoint for which requests are being prepared
1166 * The function goes through the requests list and sets up TRBs for the
1167 * transfers. The function returns once there are no more TRBs available or
1168 * it runs out of requests.
1170 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1172 struct dwc3_request *req, *n;
1174 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1177 * We can get in a situation where there's a request in the started list
1178 * but there weren't enough TRBs to fully kick it in the first time
1179 * around, so it has been waiting for more TRBs to be freed up.
1181 * In that case, we should check if we have a request with pending_sgs
1182 * in the started list and prepare TRBs for that request first,
1183 * otherwise we will prepare TRBs completely out of order and that will
1186 list_for_each_entry(req, &dep->started_list, list) {
1187 if (req->num_pending_sgs > 0)
1188 dwc3_prepare_one_trb_sg(dep, req);
1190 if (!dwc3_calc_trbs_left(dep))
1194 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1195 struct dwc3 *dwc = dep->dwc;
1198 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1203 req->sg = req->request.sg;
1204 req->start_sg = req->sg;
1205 req->num_queued_sgs = 0;
1206 req->num_pending_sgs = req->request.num_mapped_sgs;
1208 if (req->num_pending_sgs > 0)
1209 dwc3_prepare_one_trb_sg(dep, req);
1211 dwc3_prepare_one_trb_linear(dep, req);
1213 if (!dwc3_calc_trbs_left(dep))
1218 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1220 struct dwc3_gadget_ep_cmd_params params;
1221 struct dwc3_request *req;
1226 if (!dwc3_calc_trbs_left(dep))
1229 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1231 dwc3_prepare_trbs(dep);
1232 req = next_request(&dep->started_list);
1234 dep->flags |= DWC3_EP_PENDING_REQUEST;
1238 memset(¶ms, 0, sizeof(params));
1241 params.param0 = upper_32_bits(req->trb_dma);
1242 params.param1 = lower_32_bits(req->trb_dma);
1243 cmd = DWC3_DEPCMD_STARTTRANSFER;
1245 if (dep->stream_capable)
1246 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1249 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1251 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1252 DWC3_DEPCMD_PARAM(dep->resource_index);
1255 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1258 * FIXME we need to iterate over the list of requests
1259 * here and stop, unmap, free and del each of the linked
1260 * requests instead of what we do now.
1263 memset(req->trb, 0, sizeof(struct dwc3_trb));
1264 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1271 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1275 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1276 return DWC3_DSTS_SOFFN(reg);
1280 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1281 * @dep: isoc endpoint
1283 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1284 * microframe number reported by the XferNotReady event for the future frame
1285 * number to start the isoc transfer.
1287 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1288 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1289 * XferNotReady event are invalid. The driver uses this number to schedule the
1290 * isochronous transfer and passes it to the START TRANSFER command. Because
1291 * this number is invalid, the command may fail. If BIT[15:14] matches the
1292 * internal 16-bit microframe, the START TRANSFER command will pass and the
1293 * transfer will start at the scheduled time, if it is off by 1, the command
1294 * will still pass, but the transfer will start 2 seconds in the future. For all
1295 * other conditions, the START TRANSFER command will fail with bus-expiry.
1297 * In order to workaround this issue, we can test for the correct combination of
1298 * BIT[15:14] by sending START TRANSFER commands with different values of
1299 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1300 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1301 * As the result, within the 4 possible combinations for BIT[15:14], there will
1302 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1303 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1304 * value is the correct combination.
1306 * Since there are only 4 outcomes and the results are ordered, we can simply
1307 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1308 * deduce the smaller successful combination.
1310 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1311 * of BIT[15:14]. The correct combination is as follow:
1313 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1314 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1315 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1316 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1318 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1321 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1327 while (dep->combo_num < 2) {
1328 struct dwc3_gadget_ep_cmd_params params;
1329 u32 test_frame_number;
1333 * Check if we can start isoc transfer on the next interval or
1334 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1336 test_frame_number = dep->frame_number & 0x3fff;
1337 test_frame_number |= dep->combo_num << 14;
1338 test_frame_number += max_t(u32, 4, dep->interval);
1340 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1341 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1343 cmd = DWC3_DEPCMD_STARTTRANSFER;
1344 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1345 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1347 /* Redo if some other failure beside bus-expiry is received */
1348 if (cmd_status && cmd_status != -EAGAIN) {
1349 dep->start_cmd_status = 0;
1354 /* Store the first test status */
1355 if (dep->combo_num == 0)
1356 dep->start_cmd_status = cmd_status;
1361 * End the transfer if the START_TRANSFER command is successful
1362 * to wait for the next XferNotReady to test the command again
1364 if (cmd_status == 0) {
1365 dwc3_stop_active_transfer(dep, true);
1370 /* test0 and test1 are both completed at this point */
1371 test0 = (dep->start_cmd_status == 0);
1372 test1 = (cmd_status == 0);
1374 if (!test0 && test1)
1376 else if (!test0 && !test1)
1378 else if (test0 && !test1)
1380 else if (test0 && test1)
1383 dep->frame_number &= 0x3fff;
1384 dep->frame_number |= dep->combo_num << 14;
1385 dep->frame_number += max_t(u32, 4, dep->interval);
1387 /* Reinitialize test variables */
1388 dep->start_cmd_status = 0;
1391 return __dwc3_gadget_kick_transfer(dep);
1394 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1396 struct dwc3 *dwc = dep->dwc;
1400 if (list_empty(&dep->pending_list)) {
1401 dep->flags |= DWC3_EP_PENDING_REQUEST;
1405 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1406 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1407 (dwc->revision == DWC3_USB31_REVISION_170A &&
1408 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1409 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1411 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1412 return dwc3_gadget_start_isoc_quirk(dep);
1415 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1416 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1418 ret = __dwc3_gadget_kick_transfer(dep);
1426 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1428 struct dwc3 *dwc = dep->dwc;
1430 if (!dep->endpoint.desc) {
1431 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1436 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1437 &req->request, req->dep->name))
1440 pm_runtime_get(dwc->dev);
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1445 trace_dwc3_ep_queue(req);
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1470 return __dwc3_gadget_kick_transfer(dep);
1473 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1480 unsigned long flags;
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1491 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1514 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1516 struct dwc3_request *req;
1517 struct dwc3_request *tmp;
1519 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1520 dwc3_gadget_ep_skip_trbs(dep, req);
1521 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1525 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1526 struct usb_request *request)
1528 struct dwc3_request *req = to_dwc3_request(request);
1529 struct dwc3_request *r = NULL;
1531 struct dwc3_ep *dep = to_dwc3_ep(ep);
1532 struct dwc3 *dwc = dep->dwc;
1534 unsigned long flags;
1537 trace_dwc3_ep_dequeue(req);
1539 spin_lock_irqsave(&dwc->lock, flags);
1541 list_for_each_entry(r, &dep->pending_list, list) {
1547 list_for_each_entry(r, &dep->started_list, list) {
1552 /* wait until it is processed */
1553 dwc3_stop_active_transfer(dep, true);
1558 dwc3_gadget_move_cancelled_request(req);
1561 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1570 spin_unlock_irqrestore(&dwc->lock, flags);
1575 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1577 struct dwc3_gadget_ep_cmd_params params;
1578 struct dwc3 *dwc = dep->dwc;
1581 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1582 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1586 memset(¶ms, 0x00, sizeof(params));
1589 struct dwc3_trb *trb;
1591 unsigned transfer_in_flight;
1594 if (dep->number > 1)
1595 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1597 trb = &dwc->ep0_trb[dep->trb_enqueue];
1599 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1600 started = !list_empty(&dep->started_list);
1602 if (!protocol && ((dep->direction && transfer_in_flight) ||
1603 (!dep->direction && started))) {
1607 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1610 dev_err(dwc->dev, "failed to set STALL on %s\n",
1613 dep->flags |= DWC3_EP_STALL;
1616 ret = dwc3_send_clear_stall_ep_cmd(dep);
1618 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1621 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1627 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1629 struct dwc3_ep *dep = to_dwc3_ep(ep);
1630 struct dwc3 *dwc = dep->dwc;
1632 unsigned long flags;
1636 spin_lock_irqsave(&dwc->lock, flags);
1637 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1638 spin_unlock_irqrestore(&dwc->lock, flags);
1643 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1645 struct dwc3_ep *dep = to_dwc3_ep(ep);
1646 struct dwc3 *dwc = dep->dwc;
1647 unsigned long flags;
1650 spin_lock_irqsave(&dwc->lock, flags);
1651 dep->flags |= DWC3_EP_WEDGE;
1653 if (dep->number == 0 || dep->number == 1)
1654 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1656 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1657 spin_unlock_irqrestore(&dwc->lock, flags);
1662 /* -------------------------------------------------------------------------- */
1664 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1665 .bLength = USB_DT_ENDPOINT_SIZE,
1666 .bDescriptorType = USB_DT_ENDPOINT,
1667 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1670 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1671 .enable = dwc3_gadget_ep0_enable,
1672 .disable = dwc3_gadget_ep0_disable,
1673 .alloc_request = dwc3_gadget_ep_alloc_request,
1674 .free_request = dwc3_gadget_ep_free_request,
1675 .queue = dwc3_gadget_ep0_queue,
1676 .dequeue = dwc3_gadget_ep_dequeue,
1677 .set_halt = dwc3_gadget_ep0_set_halt,
1678 .set_wedge = dwc3_gadget_ep_set_wedge,
1681 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1682 .enable = dwc3_gadget_ep_enable,
1683 .disable = dwc3_gadget_ep_disable,
1684 .alloc_request = dwc3_gadget_ep_alloc_request,
1685 .free_request = dwc3_gadget_ep_free_request,
1686 .queue = dwc3_gadget_ep_queue,
1687 .dequeue = dwc3_gadget_ep_dequeue,
1688 .set_halt = dwc3_gadget_ep_set_halt,
1689 .set_wedge = dwc3_gadget_ep_set_wedge,
1692 /* -------------------------------------------------------------------------- */
1694 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1696 struct dwc3 *dwc = gadget_to_dwc(g);
1698 return __dwc3_gadget_get_frame(dwc);
1701 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1712 * According to the Databook Remote wakeup request should
1713 * be issued only when the device is in early suspend state.
1715 * We can check that via USB Link State bits in DSTS register.
1717 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1719 speed = reg & DWC3_DSTS_CONNECTSPD;
1720 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1721 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1724 link_state = DWC3_DSTS_USBLNKST(reg);
1726 switch (link_state) {
1727 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1728 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1734 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1736 dev_err(dwc->dev, "failed to put link in Recovery\n");
1740 /* Recent versions do this automatically */
1741 if (dwc->revision < DWC3_REVISION_194A) {
1742 /* write zeroes to Link Change Request */
1743 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1744 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1745 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1748 /* poll until Link State changes to ON */
1752 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1754 /* in HS, means ON */
1755 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1759 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1760 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1769 struct dwc3 *dwc = gadget_to_dwc(g);
1770 unsigned long flags;
1773 spin_lock_irqsave(&dwc->lock, flags);
1774 ret = __dwc3_gadget_wakeup(dwc);
1775 spin_unlock_irqrestore(&dwc->lock, flags);
1780 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1783 struct dwc3 *dwc = gadget_to_dwc(g);
1784 unsigned long flags;
1786 spin_lock_irqsave(&dwc->lock, flags);
1787 g->is_selfpowered = !!is_selfpowered;
1788 spin_unlock_irqrestore(&dwc->lock, flags);
1793 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1798 if (pm_runtime_suspended(dwc->dev))
1801 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1803 if (dwc->revision <= DWC3_REVISION_187A) {
1804 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1805 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1808 if (dwc->revision >= DWC3_REVISION_194A)
1809 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1810 reg |= DWC3_DCTL_RUN_STOP;
1812 if (dwc->has_hibernation)
1813 reg |= DWC3_DCTL_KEEP_CONNECT;
1815 dwc->pullups_connected = true;
1817 reg &= ~DWC3_DCTL_RUN_STOP;
1819 if (dwc->has_hibernation && !suspend)
1820 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1822 dwc->pullups_connected = false;
1825 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1828 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1829 reg &= DWC3_DSTS_DEVCTRLHLT;
1830 } while (--timeout && !(!is_on ^ !reg));
1838 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1840 struct dwc3 *dwc = gadget_to_dwc(g);
1841 unsigned long flags;
1847 * Per databook, when we want to stop the gadget, if a control transfer
1848 * is still in process, complete it and get the core into setup phase.
1850 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1851 reinit_completion(&dwc->ep0_in_setup);
1853 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1854 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1856 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1861 spin_lock_irqsave(&dwc->lock, flags);
1862 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1863 spin_unlock_irqrestore(&dwc->lock, flags);
1868 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1872 /* Enable all but Start and End of Frame IRQs */
1873 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1874 DWC3_DEVTEN_EVNTOVERFLOWEN |
1875 DWC3_DEVTEN_CMDCMPLTEN |
1876 DWC3_DEVTEN_ERRTICERREN |
1877 DWC3_DEVTEN_WKUPEVTEN |
1878 DWC3_DEVTEN_CONNECTDONEEN |
1879 DWC3_DEVTEN_USBRSTEN |
1880 DWC3_DEVTEN_DISCONNEVTEN);
1882 if (dwc->revision < DWC3_REVISION_250A)
1883 reg |= DWC3_DEVTEN_ULSTCNGEN;
1885 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1888 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1890 /* mask all interrupts */
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1894 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1895 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1898 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1899 * @dwc: pointer to our context structure
1901 * The following looks like complex but it's actually very simple. In order to
1902 * calculate the number of packets we can burst at once on OUT transfers, we're
1903 * gonna use RxFIFO size.
1905 * To calculate RxFIFO size we need two numbers:
1906 * MDWIDTH = size, in bits, of the internal memory bus
1907 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1909 * Given these two numbers, the formula is simple:
1911 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1913 * 24 bytes is for 3x SETUP packets
1914 * 16 bytes is a clock domain crossing tolerance
1916 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1918 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1926 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1928 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1929 nump = min_t(u32, nump, 16);
1932 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1933 reg &= ~DWC3_DCFG_NUMP_MASK;
1934 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1935 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1938 static int __dwc3_gadget_start(struct dwc3 *dwc)
1940 struct dwc3_ep *dep;
1945 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1946 * the core supports IMOD, disable it.
1948 if (dwc->imod_interval) {
1949 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1950 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1951 } else if (dwc3_has_imod(dwc)) {
1952 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1956 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1957 * field instead of letting dwc3 itself calculate that automatically.
1959 * This way, we maximize the chances that we'll be able to get several
1960 * bursts of data without going through any sort of endpoint throttling.
1962 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1963 if (dwc3_is_usb31(dwc))
1964 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1966 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1968 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1970 dwc3_gadget_setup_nump(dwc);
1972 /* Start with SuperSpeed Default */
1973 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1976 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1978 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1983 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1985 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1989 /* begin to receive SETUP packets */
1990 dwc->ep0state = EP0_SETUP_PHASE;
1991 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1992 dwc3_ep0_out_start(dwc);
1994 dwc3_gadget_enable_irq(dwc);
1999 __dwc3_gadget_ep_disable(dwc->eps[0]);
2005 static int dwc3_gadget_start(struct usb_gadget *g,
2006 struct usb_gadget_driver *driver)
2008 struct dwc3 *dwc = gadget_to_dwc(g);
2009 unsigned long flags;
2013 irq = dwc->irq_gadget;
2014 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2015 IRQF_SHARED, "dwc3", dwc->ev_buf);
2017 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2022 spin_lock_irqsave(&dwc->lock, flags);
2023 if (dwc->gadget_driver) {
2024 dev_err(dwc->dev, "%s is already bound to %s\n",
2026 dwc->gadget_driver->driver.name);
2031 dwc->gadget_driver = driver;
2033 if (pm_runtime_active(dwc->dev))
2034 __dwc3_gadget_start(dwc);
2036 spin_unlock_irqrestore(&dwc->lock, flags);
2041 spin_unlock_irqrestore(&dwc->lock, flags);
2048 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2050 dwc3_gadget_disable_irq(dwc);
2051 __dwc3_gadget_ep_disable(dwc->eps[0]);
2052 __dwc3_gadget_ep_disable(dwc->eps[1]);
2055 static int dwc3_gadget_stop(struct usb_gadget *g)
2057 struct dwc3 *dwc = gadget_to_dwc(g);
2058 unsigned long flags;
2060 spin_lock_irqsave(&dwc->lock, flags);
2062 if (pm_runtime_suspended(dwc->dev))
2065 __dwc3_gadget_stop(dwc);
2068 dwc->gadget_driver = NULL;
2069 spin_unlock_irqrestore(&dwc->lock, flags);
2071 free_irq(dwc->irq_gadget, dwc->ev_buf);
2076 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2077 enum usb_device_speed speed)
2079 struct dwc3 *dwc = gadget_to_dwc(g);
2080 unsigned long flags;
2083 spin_lock_irqsave(&dwc->lock, flags);
2084 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2085 reg &= ~(DWC3_DCFG_SPEED_MASK);
2088 * WORKAROUND: DWC3 revision < 2.20a have an issue
2089 * which would cause metastability state on Run/Stop
2090 * bit if we try to force the IP to USB2-only mode.
2092 * Because of that, we cannot configure the IP to any
2093 * speed other than the SuperSpeed
2097 * STAR#9000525659: Clock Domain Crossing on DCTL in
2100 if (dwc->revision < DWC3_REVISION_220A &&
2101 !dwc->dis_metastability_quirk) {
2102 reg |= DWC3_DCFG_SUPERSPEED;
2106 reg |= DWC3_DCFG_LOWSPEED;
2108 case USB_SPEED_FULL:
2109 reg |= DWC3_DCFG_FULLSPEED;
2111 case USB_SPEED_HIGH:
2112 reg |= DWC3_DCFG_HIGHSPEED;
2114 case USB_SPEED_SUPER:
2115 reg |= DWC3_DCFG_SUPERSPEED;
2117 case USB_SPEED_SUPER_PLUS:
2118 if (dwc3_is_usb31(dwc))
2119 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2121 reg |= DWC3_DCFG_SUPERSPEED;
2124 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2126 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2127 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2129 reg |= DWC3_DCFG_SUPERSPEED;
2132 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2134 spin_unlock_irqrestore(&dwc->lock, flags);
2137 static const struct usb_gadget_ops dwc3_gadget_ops = {
2138 .get_frame = dwc3_gadget_get_frame,
2139 .wakeup = dwc3_gadget_wakeup,
2140 .set_selfpowered = dwc3_gadget_set_selfpowered,
2141 .pullup = dwc3_gadget_pullup,
2142 .udc_start = dwc3_gadget_start,
2143 .udc_stop = dwc3_gadget_stop,
2144 .udc_set_speed = dwc3_gadget_set_speed,
2147 /* -------------------------------------------------------------------------- */
2149 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2151 struct dwc3 *dwc = dep->dwc;
2153 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2154 dep->endpoint.maxburst = 1;
2155 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2156 if (!dep->direction)
2157 dwc->gadget.ep0 = &dep->endpoint;
2159 dep->endpoint.caps.type_control = true;
2164 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2166 struct dwc3 *dwc = dep->dwc;
2171 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2172 /* MDWIDTH is represented in bits, we need it in bytes */
2175 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2176 if (dwc3_is_usb31(dwc))
2177 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2179 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2181 /* FIFO Depth is in MDWDITH bytes. Multiply */
2184 kbytes = size / 1024;
2189 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2190 * internal overhead. We don't really know how these are used,
2191 * but documentation say it exists.
2193 size -= mdwidth * (kbytes + 1);
2196 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2198 dep->endpoint.max_streams = 15;
2199 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2200 list_add_tail(&dep->endpoint.ep_list,
2201 &dwc->gadget.ep_list);
2202 dep->endpoint.caps.type_iso = true;
2203 dep->endpoint.caps.type_bulk = true;
2204 dep->endpoint.caps.type_int = true;
2206 return dwc3_alloc_trb_pool(dep);
2209 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2211 struct dwc3 *dwc = dep->dwc;
2213 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2214 dep->endpoint.max_streams = 15;
2215 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2216 list_add_tail(&dep->endpoint.ep_list,
2217 &dwc->gadget.ep_list);
2218 dep->endpoint.caps.type_iso = true;
2219 dep->endpoint.caps.type_bulk = true;
2220 dep->endpoint.caps.type_int = true;
2222 return dwc3_alloc_trb_pool(dep);
2225 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2227 struct dwc3_ep *dep;
2228 bool direction = epnum & 1;
2230 u8 num = epnum >> 1;
2232 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2237 dep->number = epnum;
2238 dep->direction = direction;
2239 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2240 dwc->eps[epnum] = dep;
2242 dep->start_cmd_status = 0;
2244 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2245 direction ? "in" : "out");
2247 dep->endpoint.name = dep->name;
2249 if (!(dep->number > 1)) {
2250 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2251 dep->endpoint.comp_desc = NULL;
2254 spin_lock_init(&dep->lock);
2257 ret = dwc3_gadget_init_control_endpoint(dep);
2259 ret = dwc3_gadget_init_in_endpoint(dep);
2261 ret = dwc3_gadget_init_out_endpoint(dep);
2266 dep->endpoint.caps.dir_in = direction;
2267 dep->endpoint.caps.dir_out = !direction;
2269 INIT_LIST_HEAD(&dep->pending_list);
2270 INIT_LIST_HEAD(&dep->started_list);
2271 INIT_LIST_HEAD(&dep->cancelled_list);
2276 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2280 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2282 for (epnum = 0; epnum < total; epnum++) {
2285 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2293 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2295 struct dwc3_ep *dep;
2298 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2299 dep = dwc->eps[epnum];
2303 * Physical endpoints 0 and 1 are special; they form the
2304 * bi-directional USB endpoint 0.
2306 * For those two physical endpoints, we don't allocate a TRB
2307 * pool nor do we add them the endpoints list. Due to that, we
2308 * shouldn't do these two operations otherwise we would end up
2309 * with all sorts of bugs when removing dwc3.ko.
2311 if (epnum != 0 && epnum != 1) {
2312 dwc3_free_trb_pool(dep);
2313 list_del(&dep->endpoint.ep_list);
2320 /* -------------------------------------------------------------------------- */
2322 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2323 struct dwc3_request *req, struct dwc3_trb *trb,
2324 const struct dwc3_event_depevt *event, int status, int chain)
2328 dwc3_ep_inc_deq(dep);
2330 trace_dwc3_complete_trb(dep, trb);
2334 * If we're in the middle of series of chained TRBs and we
2335 * receive a short transfer along the way, DWC3 will skip
2336 * through all TRBs including the last TRB in the chain (the
2337 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2338 * bit and SW has to do it manually.
2340 * We're going to do that here to avoid problems of HW trying
2341 * to use bogus TRBs for transfers.
2343 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2344 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2347 * For isochronous transfers, the first TRB in a service interval must
2348 * have the Isoc-First type. Track and report its interval frame number.
2350 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2351 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2352 unsigned int frame_number;
2354 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2355 frame_number &= ~(dep->interval - 1);
2356 req->request.frame_number = frame_number;
2360 * If we're dealing with unaligned size OUT transfer, we will be left
2361 * with one TRB pending in the ring. We need to manually clear HWO bit
2365 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2366 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2370 count = trb->size & DWC3_TRB_SIZE_MASK;
2371 req->remaining += count;
2373 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2376 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2379 if (event->status & DEPEVT_STATUS_IOC)
2385 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2386 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2389 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2390 struct scatterlist *sg = req->sg;
2391 struct scatterlist *s;
2392 unsigned int pending = req->num_pending_sgs;
2396 for_each_sg(sg, s, pending, i) {
2397 trb = &dep->trb_pool[dep->trb_dequeue];
2399 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2402 req->sg = sg_next(s);
2403 req->num_pending_sgs--;
2405 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2406 trb, event, status, true);
2414 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2415 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2418 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2420 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2421 event, status, false);
2424 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2426 return req->request.actual == req->request.length;
2429 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2430 const struct dwc3_event_depevt *event,
2431 struct dwc3_request *req, int status)
2435 if (req->num_pending_sgs)
2436 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2439 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2442 if (req->needs_extra_trb) {
2443 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2445 req->needs_extra_trb = false;
2448 req->request.actual = req->request.length - req->remaining;
2450 if (!dwc3_gadget_ep_request_completed(req) &&
2451 req->num_pending_sgs) {
2452 __dwc3_gadget_kick_transfer(dep);
2456 dwc3_gadget_giveback(dep, req, status);
2462 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2463 const struct dwc3_event_depevt *event, int status)
2465 struct dwc3_request *req;
2466 struct dwc3_request *tmp;
2468 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2471 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2478 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2479 const struct dwc3_event_depevt *event)
2481 dep->frame_number = event->parameters;
2484 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2485 const struct dwc3_event_depevt *event)
2487 struct dwc3 *dwc = dep->dwc;
2488 unsigned status = 0;
2491 dwc3_gadget_endpoint_frame_from_event(dep, event);
2493 if (event->status & DEPEVT_STATUS_BUSERR)
2494 status = -ECONNRESET;
2496 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2499 if (list_empty(&dep->started_list))
2503 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2506 dwc3_stop_active_transfer(dep, true);
2507 dep->flags = DWC3_EP_ENABLED;
2511 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2512 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2514 if (dwc->revision < DWC3_REVISION_183A) {
2518 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2521 if (!(dep->flags & DWC3_EP_ENABLED))
2524 if (!list_empty(&dep->started_list))
2528 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2530 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2536 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2537 const struct dwc3_event_depevt *event)
2539 dwc3_gadget_endpoint_frame_from_event(dep, event);
2540 (void) __dwc3_gadget_start_isoc(dep);
2543 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2544 const struct dwc3_event_depevt *event)
2546 struct dwc3_ep *dep;
2547 u8 epnum = event->endpoint_number;
2550 dep = dwc->eps[epnum];
2552 if (!(dep->flags & DWC3_EP_ENABLED)) {
2553 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2556 /* Handle only EPCMDCMPLT when EP disabled */
2557 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2561 if (epnum == 0 || epnum == 1) {
2562 dwc3_ep0_interrupt(dwc, event);
2566 switch (event->endpoint_event) {
2567 case DWC3_DEPEVT_XFERINPROGRESS:
2568 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2570 case DWC3_DEPEVT_XFERNOTREADY:
2571 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2573 case DWC3_DEPEVT_EPCMDCMPLT:
2574 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2576 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2577 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2578 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2581 case DWC3_DEPEVT_STREAMEVT:
2582 case DWC3_DEPEVT_XFERCOMPLETE:
2583 case DWC3_DEPEVT_RXTXFIFOEVT:
2588 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2590 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2591 spin_unlock(&dwc->lock);
2592 dwc->gadget_driver->disconnect(&dwc->gadget);
2593 spin_lock(&dwc->lock);
2597 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2599 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2600 spin_unlock(&dwc->lock);
2601 dwc->gadget_driver->suspend(&dwc->gadget);
2602 spin_lock(&dwc->lock);
2606 static void dwc3_resume_gadget(struct dwc3 *dwc)
2608 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2609 spin_unlock(&dwc->lock);
2610 dwc->gadget_driver->resume(&dwc->gadget);
2611 spin_lock(&dwc->lock);
2615 static void dwc3_reset_gadget(struct dwc3 *dwc)
2617 if (!dwc->gadget_driver)
2620 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2621 spin_unlock(&dwc->lock);
2622 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2623 spin_lock(&dwc->lock);
2627 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2629 struct dwc3 *dwc = dep->dwc;
2630 struct dwc3_gadget_ep_cmd_params params;
2634 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2635 !dep->resource_index)
2639 * NOTICE: We are violating what the Databook says about the
2640 * EndTransfer command. Ideally we would _always_ wait for the
2641 * EndTransfer Command Completion IRQ, but that's causing too
2642 * much trouble synchronizing between us and gadget driver.
2644 * We have discussed this with the IP Provider and it was
2645 * suggested to giveback all requests here, but give HW some
2646 * extra time to synchronize with the interconnect. We're using
2647 * an arbitrary 100us delay for that.
2649 * Note also that a similar handling was tested by Synopsys
2650 * (thanks a lot Paul) and nothing bad has come out of it.
2651 * In short, what we're doing is:
2653 * - Issue EndTransfer WITH CMDIOC bit set
2656 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2657 * supports a mode to work around the above limitation. The
2658 * software can poll the CMDACT bit in the DEPCMD register
2659 * after issuing a EndTransfer command. This mode is enabled
2660 * by writing GUCTL2[14]. This polling is already done in the
2661 * dwc3_send_gadget_ep_cmd() function so if the mode is
2662 * enabled, the EndTransfer command will have completed upon
2663 * returning from this function and we don't need to delay for
2666 * This mode is NOT available on the DWC_usb31 IP.
2669 cmd = DWC3_DEPCMD_ENDTRANSFER;
2670 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2671 cmd |= DWC3_DEPCMD_CMDIOC;
2672 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2673 memset(¶ms, 0, sizeof(params));
2674 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2676 dep->resource_index = 0;
2678 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2679 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2684 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2688 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2689 struct dwc3_ep *dep;
2692 dep = dwc->eps[epnum];
2696 if (!(dep->flags & DWC3_EP_STALL))
2699 dep->flags &= ~DWC3_EP_STALL;
2701 ret = dwc3_send_clear_stall_ep_cmd(dep);
2706 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2710 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2711 reg &= ~DWC3_DCTL_INITU1ENA;
2712 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2714 reg &= ~DWC3_DCTL_INITU2ENA;
2715 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2717 dwc3_disconnect_gadget(dwc);
2719 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2720 dwc->setup_packet_pending = false;
2721 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2723 dwc->connected = false;
2726 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2730 dwc->connected = true;
2733 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2734 * would cause a missing Disconnect Event if there's a
2735 * pending Setup Packet in the FIFO.
2737 * There's no suggested workaround on the official Bug
2738 * report, which states that "unless the driver/application
2739 * is doing any special handling of a disconnect event,
2740 * there is no functional issue".
2742 * Unfortunately, it turns out that we _do_ some special
2743 * handling of a disconnect event, namely complete all
2744 * pending transfers, notify gadget driver of the
2745 * disconnection, and so on.
2747 * Our suggested workaround is to follow the Disconnect
2748 * Event steps here, instead, based on a setup_packet_pending
2749 * flag. Such flag gets set whenever we have a SETUP_PENDING
2750 * status for EP0 TRBs and gets cleared on XferComplete for the
2755 * STAR#9000466709: RTL: Device : Disconnect event not
2756 * generated if setup packet pending in FIFO
2758 if (dwc->revision < DWC3_REVISION_188A) {
2759 if (dwc->setup_packet_pending)
2760 dwc3_gadget_disconnect_interrupt(dwc);
2763 dwc3_reset_gadget(dwc);
2765 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2766 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2767 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2768 dwc->test_mode = false;
2769 dwc3_clear_stall_all_ep(dwc);
2771 /* Reset device address to zero */
2772 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2773 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2774 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2777 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2779 struct dwc3_ep *dep;
2784 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2785 speed = reg & DWC3_DSTS_CONNECTSPD;
2789 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2790 * each time on Connect Done.
2792 * Currently we always use the reset value. If any platform
2793 * wants to set this to a different value, we need to add a
2794 * setting and update GCTL.RAMCLKSEL here.
2798 case DWC3_DSTS_SUPERSPEED_PLUS:
2799 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2800 dwc->gadget.ep0->maxpacket = 512;
2801 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2803 case DWC3_DSTS_SUPERSPEED:
2805 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2806 * would cause a missing USB3 Reset event.
2808 * In such situations, we should force a USB3 Reset
2809 * event by calling our dwc3_gadget_reset_interrupt()
2814 * STAR#9000483510: RTL: SS : USB3 reset event may
2815 * not be generated always when the link enters poll
2817 if (dwc->revision < DWC3_REVISION_190A)
2818 dwc3_gadget_reset_interrupt(dwc);
2820 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2821 dwc->gadget.ep0->maxpacket = 512;
2822 dwc->gadget.speed = USB_SPEED_SUPER;
2824 case DWC3_DSTS_HIGHSPEED:
2825 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2826 dwc->gadget.ep0->maxpacket = 64;
2827 dwc->gadget.speed = USB_SPEED_HIGH;
2829 case DWC3_DSTS_FULLSPEED:
2830 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2831 dwc->gadget.ep0->maxpacket = 64;
2832 dwc->gadget.speed = USB_SPEED_FULL;
2834 case DWC3_DSTS_LOWSPEED:
2835 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2836 dwc->gadget.ep0->maxpacket = 8;
2837 dwc->gadget.speed = USB_SPEED_LOW;
2841 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2843 /* Enable USB2 LPM Capability */
2845 if ((dwc->revision > DWC3_REVISION_194A) &&
2846 (speed != DWC3_DSTS_SUPERSPEED) &&
2847 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2848 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2849 reg |= DWC3_DCFG_LPM_CAP;
2850 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2852 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2853 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2855 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2858 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2859 * DCFG.LPMCap is set, core responses with an ACK and the
2860 * BESL value in the LPM token is less than or equal to LPM
2863 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2864 && dwc->has_lpm_erratum,
2865 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2867 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2868 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2870 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2872 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2873 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2874 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2878 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2880 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2885 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2887 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2892 * Configure PHY via GUSB3PIPECTLn if required.
2894 * Update GTXFIFOSIZn
2896 * In both cases reset values should be sufficient.
2900 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2903 * TODO take core out of low power mode when that's
2907 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2908 spin_unlock(&dwc->lock);
2909 dwc->gadget_driver->resume(&dwc->gadget);
2910 spin_lock(&dwc->lock);
2914 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2915 unsigned int evtinfo)
2917 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2918 unsigned int pwropt;
2921 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2922 * Hibernation mode enabled which would show up when device detects
2923 * host-initiated U3 exit.
2925 * In that case, device will generate a Link State Change Interrupt
2926 * from U3 to RESUME which is only necessary if Hibernation is
2929 * There are no functional changes due to such spurious event and we
2930 * just need to ignore it.
2934 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2937 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2938 if ((dwc->revision < DWC3_REVISION_250A) &&
2939 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2940 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2941 (next == DWC3_LINK_STATE_RESUME)) {
2947 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2948 * on the link partner, the USB session might do multiple entry/exit
2949 * of low power states before a transfer takes place.
2951 * Due to this problem, we might experience lower throughput. The
2952 * suggested workaround is to disable DCTL[12:9] bits if we're
2953 * transitioning from U1/U2 to U0 and enable those bits again
2954 * after a transfer completes and there are no pending transfers
2955 * on any of the enabled endpoints.
2957 * This is the first half of that workaround.
2961 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2962 * core send LGO_Ux entering U0
2964 if (dwc->revision < DWC3_REVISION_183A) {
2965 if (next == DWC3_LINK_STATE_U0) {
2969 switch (dwc->link_state) {
2970 case DWC3_LINK_STATE_U1:
2971 case DWC3_LINK_STATE_U2:
2972 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2973 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2974 | DWC3_DCTL_ACCEPTU2ENA
2975 | DWC3_DCTL_INITU1ENA
2976 | DWC3_DCTL_ACCEPTU1ENA);
2979 dwc->u1u2 = reg & u1u2;
2983 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2993 case DWC3_LINK_STATE_U1:
2994 if (dwc->speed == USB_SPEED_SUPER)
2995 dwc3_suspend_gadget(dwc);
2997 case DWC3_LINK_STATE_U2:
2998 case DWC3_LINK_STATE_U3:
2999 dwc3_suspend_gadget(dwc);
3001 case DWC3_LINK_STATE_RESUME:
3002 dwc3_resume_gadget(dwc);
3009 dwc->link_state = next;
3012 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3013 unsigned int evtinfo)
3015 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3017 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3018 dwc3_suspend_gadget(dwc);
3020 dwc->link_state = next;
3023 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3024 unsigned int evtinfo)
3026 unsigned int is_ss = evtinfo & BIT(4);
3029 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3030 * have a known issue which can cause USB CV TD.9.23 to fail
3033 * Because of this issue, core could generate bogus hibernation
3034 * events which SW needs to ignore.
3038 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3039 * Device Fallback from SuperSpeed
3041 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3044 /* enter hibernation here */
3047 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3048 const struct dwc3_event_devt *event)
3050 switch (event->type) {
3051 case DWC3_DEVICE_EVENT_DISCONNECT:
3052 dwc3_gadget_disconnect_interrupt(dwc);
3054 case DWC3_DEVICE_EVENT_RESET:
3055 dwc3_gadget_reset_interrupt(dwc);
3057 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3058 dwc3_gadget_conndone_interrupt(dwc);
3060 case DWC3_DEVICE_EVENT_WAKEUP:
3061 dwc3_gadget_wakeup_interrupt(dwc);
3063 case DWC3_DEVICE_EVENT_HIBER_REQ:
3064 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3065 "unexpected hibernation event\n"))
3068 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3070 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3071 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3073 case DWC3_DEVICE_EVENT_EOPF:
3074 /* It changed to be suspend event for version 2.30a and above */
3075 if (dwc->revision >= DWC3_REVISION_230A) {
3077 * Ignore suspend event until the gadget enters into
3078 * USB_STATE_CONFIGURED state.
3080 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3081 dwc3_gadget_suspend_interrupt(dwc,
3085 case DWC3_DEVICE_EVENT_SOF:
3086 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3087 case DWC3_DEVICE_EVENT_CMD_CMPL:
3088 case DWC3_DEVICE_EVENT_OVERFLOW:
3091 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3095 static void dwc3_process_event_entry(struct dwc3 *dwc,
3096 const union dwc3_event *event)
3098 trace_dwc3_event(event->raw, dwc);
3100 if (!event->type.is_devspec)
3101 dwc3_endpoint_interrupt(dwc, &event->depevt);
3102 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3103 dwc3_gadget_interrupt(dwc, &event->devt);
3105 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3108 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3110 struct dwc3 *dwc = evt->dwc;
3111 irqreturn_t ret = IRQ_NONE;
3117 if (!(evt->flags & DWC3_EVENT_PENDING))
3121 union dwc3_event event;
3123 event.raw = *(u32 *) (evt->cache + evt->lpos);
3125 dwc3_process_event_entry(dwc, &event);
3128 * FIXME we wrap around correctly to the next entry as
3129 * almost all entries are 4 bytes in size. There is one
3130 * entry which has 12 bytes which is a regular entry
3131 * followed by 8 bytes data. ATM I don't know how
3132 * things are organized if we get next to the a
3133 * boundary so I worry about that once we try to handle
3136 evt->lpos = (evt->lpos + 4) % evt->length;
3141 evt->flags &= ~DWC3_EVENT_PENDING;
3144 /* Unmask interrupt */
3145 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3146 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3147 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3149 if (dwc->imod_interval) {
3150 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3151 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3157 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3159 struct dwc3_event_buffer *evt = _evt;
3160 struct dwc3 *dwc = evt->dwc;
3161 unsigned long flags;
3162 irqreturn_t ret = IRQ_NONE;
3164 spin_lock_irqsave(&dwc->lock, flags);
3165 ret = dwc3_process_event_buf(evt);
3166 spin_unlock_irqrestore(&dwc->lock, flags);
3171 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3173 struct dwc3 *dwc = evt->dwc;
3178 if (pm_runtime_suspended(dwc->dev)) {
3179 pm_runtime_get(dwc->dev);
3180 disable_irq_nosync(dwc->irq_gadget);
3181 dwc->pending_events = true;
3186 * With PCIe legacy interrupt, test shows that top-half irq handler can
3187 * be called again after HW interrupt deassertion. Check if bottom-half
3188 * irq event handler completes before caching new event to prevent
3191 if (evt->flags & DWC3_EVENT_PENDING)
3194 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3195 count &= DWC3_GEVNTCOUNT_MASK;
3200 evt->flags |= DWC3_EVENT_PENDING;
3202 /* Mask interrupt */
3203 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3204 reg |= DWC3_GEVNTSIZ_INTMASK;
3205 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3207 amount = min(count, evt->length - evt->lpos);
3208 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3211 memcpy(evt->cache, evt->buf, count - amount);
3213 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3215 return IRQ_WAKE_THREAD;
3218 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3220 struct dwc3_event_buffer *evt = _evt;
3222 return dwc3_check_event_buf(evt);
3225 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3227 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3230 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3234 if (irq == -EPROBE_DEFER)
3237 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3241 if (irq == -EPROBE_DEFER)
3244 irq = platform_get_irq(dwc3_pdev, 0);
3248 if (irq != -EPROBE_DEFER)
3249 dev_err(dwc->dev, "missing peripheral IRQ\n");
3259 * dwc3_gadget_init - initializes gadget related registers
3260 * @dwc: pointer to our controller context structure
3262 * Returns 0 on success otherwise negative errno.
3264 int dwc3_gadget_init(struct dwc3 *dwc)
3269 irq = dwc3_gadget_get_irq(dwc);
3275 dwc->irq_gadget = irq;
3277 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3278 sizeof(*dwc->ep0_trb) * 2,
3279 &dwc->ep0_trb_addr, GFP_KERNEL);
3280 if (!dwc->ep0_trb) {
3281 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3286 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3287 if (!dwc->setup_buf) {
3292 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3293 &dwc->bounce_addr, GFP_KERNEL);
3299 init_completion(&dwc->ep0_in_setup);
3301 dwc->gadget.ops = &dwc3_gadget_ops;
3302 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3303 dwc->gadget.sg_supported = true;
3304 dwc->gadget.name = "dwc3-gadget";
3305 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3308 * FIXME We might be setting max_speed to <SUPER, however versions
3309 * <2.20a of dwc3 have an issue with metastability (documented
3310 * elsewhere in this driver) which tells us we can't set max speed to
3311 * anything lower than SUPER.
3313 * Because gadget.max_speed is only used by composite.c and function
3314 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3315 * to happen so we avoid sending SuperSpeed Capability descriptor
3316 * together with our BOS descriptor as that could confuse host into
3317 * thinking we can handle super speed.
3319 * Note that, in fact, we won't even support GetBOS requests when speed
3320 * is less than super speed because we don't have means, yet, to tell
3321 * composite.c that we are USB 2.0 + LPM ECN.
3323 if (dwc->revision < DWC3_REVISION_220A &&
3324 !dwc->dis_metastability_quirk)
3325 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3328 dwc->gadget.max_speed = dwc->maximum_speed;
3331 * REVISIT: Here we should clear all pending IRQs to be
3332 * sure we're starting from a well known location.
3335 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3339 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3341 dev_err(dwc->dev, "failed to register udc\n");
3345 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3350 dwc3_gadget_free_endpoints(dwc);
3353 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3357 kfree(dwc->setup_buf);
3360 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3361 dwc->ep0_trb, dwc->ep0_trb_addr);
3367 /* -------------------------------------------------------------------------- */
3369 void dwc3_gadget_exit(struct dwc3 *dwc)
3371 usb_del_gadget_udc(&dwc->gadget);
3372 dwc3_gadget_free_endpoints(dwc);
3373 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3375 kfree(dwc->setup_buf);
3376 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3377 dwc->ep0_trb, dwc->ep0_trb_addr);
3380 int dwc3_gadget_suspend(struct dwc3 *dwc)
3382 if (!dwc->gadget_driver)
3385 dwc3_gadget_run_stop(dwc, false, false);
3386 dwc3_disconnect_gadget(dwc);
3387 __dwc3_gadget_stop(dwc);
3389 synchronize_irq(dwc->irq_gadget);
3394 int dwc3_gadget_resume(struct dwc3 *dwc)
3398 if (!dwc->gadget_driver)
3401 ret = __dwc3_gadget_start(dwc);
3405 ret = dwc3_gadget_run_stop(dwc, true, false);
3412 __dwc3_gadget_stop(dwc);
3418 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3420 if (dwc->pending_events) {
3421 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3422 dwc->pending_events = false;
3423 enable_irq(dwc->irq_gadget);