1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d) (((d)->frame_number + (d)->interval) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
189 trace_dwc3_gadget_giveback(req);
192 pm_runtime_put(dwc->dev);
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
208 struct dwc3 *dwc = dep->dwc;
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
212 spin_unlock(&dwc->lock);
213 usb_gadget_giveback_request(&dep->endpoint, &req->request);
214 spin_lock(&dwc->lock);
218 * dwc3_send_gadget_generic_command - issue a generic command for the controller
219 * @dwc: pointer to the controller context
220 * @cmd: the command to be issued
221 * @param: command parameter
223 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
224 * and wait for its completion.
226 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
233 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
234 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
237 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
238 if (!(reg & DWC3_DGCMD_CMDACT)) {
239 status = DWC3_DGCMD_STATUS(reg);
251 trace_dwc3_gadget_generic_cmd(cmd, param, status);
256 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
259 * dwc3_send_gadget_ep_cmd - issue an endpoint command
260 * @dep: the endpoint to which the command is going to be issued
261 * @cmd: the command to be issued
262 * @params: parameters to the command
264 * Caller should handle locking. This function will issue @cmd with given
265 * @params to @dep and wait for its completion.
267 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
268 struct dwc3_gadget_ep_cmd_params *params)
270 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
271 struct dwc3 *dwc = dep->dwc;
273 u32 saved_config = 0;
280 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
281 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
284 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
285 * settings. Restore them after the command is completed.
287 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
290 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
291 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
292 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
293 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
296 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
297 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
298 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
302 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
305 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
308 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
309 dwc->link_state == DWC3_LINK_STATE_U2 ||
310 dwc->link_state == DWC3_LINK_STATE_U3);
312 if (unlikely(needs_wakeup)) {
313 ret = __dwc3_gadget_wakeup(dwc);
314 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
319 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
324 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
325 * not relying on XferNotReady, we can make use of a special "No
326 * Response Update Transfer" command where we should clear both CmdAct
329 * With this, we don't need to wait for command completion and can
330 * straight away issue further commands to the endpoint.
332 * NOTICE: We're making an assumption that control endpoints will never
333 * make use of Update Transfer command. This is a safe assumption
334 * because we can never have more than one request at a time with
335 * Control Endpoints. If anybody changes that assumption, this chunk
336 * needs to be updated accordingly.
338 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
339 !usb_endpoint_xfer_isoc(desc))
340 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 cmd |= DWC3_DEPCMD_CMDACT;
344 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
347 if (!(reg & DWC3_DEPCMD_CMDACT)) {
348 cmd_status = DWC3_DEPCMD_STATUS(reg);
350 switch (cmd_status) {
354 case DEPEVT_TRANSFER_NO_RESOURCE:
357 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 * SW issues START TRANSFER command to
360 * isochronous ep with future frame interval. If
361 * future interval time has already passed when
362 * core receives the command, it will respond
363 * with an error status of 'Bus Expiry'.
365 * Instead of always returning -EINVAL, let's
366 * give a hint to the gadget driver that this is
367 * the case by returning -EAGAIN.
372 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
381 cmd_status = -ETIMEDOUT;
384 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
387 switch (DWC3_DEPCMD_CMD(cmd)) {
388 case DWC3_DEPCMD_STARTTRANSFER:
389 dep->flags |= DWC3_EP_TRANSFER_STARTED;
390 dwc3_gadget_ep_get_transfer_index(dep);
392 case DWC3_DEPCMD_ENDTRANSFER:
393 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
402 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
404 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
410 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
412 struct dwc3 *dwc = dep->dwc;
413 struct dwc3_gadget_ep_cmd_params params;
414 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
417 * As of core revision 2.60a the recommended programming model
418 * is to set the ClearPendIN bit when issuing a Clear Stall EP
419 * command for IN endpoints. This is to prevent an issue where
420 * some (non-compliant) hosts may not send ACK TPs for pending
421 * IN transfers due to a mishandled error condition. Synopsys
424 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
425 (dwc->gadget.speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
428 memset(¶ms, 0, sizeof(params));
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
438 return dep->trb_pool_dma + offset;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
443 struct dwc3 *dwc = dep->dwc;
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
475 memset(¶ms, 0x00, sizeof(params));
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
541 ret = dwc3_gadget_set_xfer_resource(dep);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
559 memset(¶ms, 0x00, sizeof(params));
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
567 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
570 params.param0 |= action;
571 if (action == DWC3_DEPCFG_ACTION_RESTORE)
572 params.param2 |= dep->saved_state;
574 if (usb_endpoint_xfer_control(desc))
575 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
577 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
580 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
581 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
582 | DWC3_DEPCFG_STREAM_EVENT_EN;
583 dep->stream_capable = true;
586 if (!usb_endpoint_xfer_control(desc))
587 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
590 * We are doing 1:1 mapping for endpoints, meaning
591 * Physical Endpoints 2 maps to Logical Endpoint 2 and
592 * so on. We consider the direction bit as part of the physical
593 * endpoint number. So USB endpoint 0x81 is 0x03.
595 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
598 * We must use the lower 16 TX FIFOs even though
602 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
604 if (desc->bInterval) {
605 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
606 dep->interval = 1 << (desc->bInterval - 1);
609 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
613 * __dwc3_gadget_ep_enable - initializes a hw endpoint
614 * @dep: endpoint to be initialized
615 * @action: one of INIT, MODIFY or RESTORE
617 * Caller should take care of locking. Execute all necessary commands to
618 * initialize a HW endpoint so it can be used by a gadget driver.
620 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
622 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
623 struct dwc3 *dwc = dep->dwc;
628 if (!(dep->flags & DWC3_EP_ENABLED)) {
629 ret = dwc3_gadget_start_config(dep);
634 ret = dwc3_gadget_set_ep_config(dep, action);
638 if (!(dep->flags & DWC3_EP_ENABLED)) {
639 struct dwc3_trb *trb_st_hw;
640 struct dwc3_trb *trb_link;
642 dep->type = usb_endpoint_type(desc);
643 dep->flags |= DWC3_EP_ENABLED;
644 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
646 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
647 reg |= DWC3_DALEPENA_EP(dep->number);
648 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
650 init_waitqueue_head(&dep->wait_end_transfer);
652 if (usb_endpoint_xfer_control(desc))
655 /* Initialize the TRB ring */
656 dep->trb_dequeue = 0;
657 dep->trb_enqueue = 0;
658 memset(dep->trb_pool, 0,
659 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
661 /* Link TRB. The HWO bit is never reset */
662 trb_st_hw = &dep->trb_pool[0];
664 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
665 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
667 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
668 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
672 * Issue StartTransfer here with no-op TRB so we can always rely on No
673 * Response Update Transfer command.
675 if (usb_endpoint_xfer_bulk(desc) ||
676 usb_endpoint_xfer_int(desc)) {
677 struct dwc3_gadget_ep_cmd_params params;
678 struct dwc3_trb *trb;
682 memset(¶ms, 0, sizeof(params));
683 trb = &dep->trb_pool[0];
684 trb_dma = dwc3_trb_dma_offset(dep, trb);
686 params.param0 = upper_32_bits(trb_dma);
687 params.param1 = lower_32_bits(trb_dma);
689 cmd = DWC3_DEPCMD_STARTTRANSFER;
691 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
697 trace_dwc3_gadget_ep_enable(dep);
702 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
703 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
705 struct dwc3_request *req;
707 dwc3_stop_active_transfer(dep, true);
709 /* - giveback all requests to gadget driver */
710 while (!list_empty(&dep->started_list)) {
711 req = next_request(&dep->started_list);
713 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
716 while (!list_empty(&dep->pending_list)) {
717 req = next_request(&dep->pending_list);
719 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
724 * __dwc3_gadget_ep_disable - disables a hw endpoint
725 * @dep: the endpoint to disable
727 * This function undoes what __dwc3_gadget_ep_enable did and also removes
728 * requests which are currently being processed by the hardware and those which
729 * are not yet scheduled.
731 * Caller should take care of locking.
733 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
735 struct dwc3 *dwc = dep->dwc;
738 trace_dwc3_gadget_ep_disable(dep);
740 dwc3_remove_requests(dwc, dep);
742 /* make sure HW endpoint isn't stalled */
743 if (dep->flags & DWC3_EP_STALL)
744 __dwc3_gadget_ep_set_halt(dep, 0, false);
746 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
747 reg &= ~DWC3_DALEPENA_EP(dep->number);
748 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
750 dep->stream_capable = false;
752 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
754 /* Clear out the ep descriptors for non-ep0 */
755 if (dep->number > 1) {
756 dep->endpoint.comp_desc = NULL;
757 dep->endpoint.desc = NULL;
763 /* -------------------------------------------------------------------------- */
765 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
766 const struct usb_endpoint_descriptor *desc)
771 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
776 /* -------------------------------------------------------------------------- */
778 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
779 const struct usb_endpoint_descriptor *desc)
786 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
787 pr_debug("dwc3: invalid parameters\n");
791 if (!desc->wMaxPacketSize) {
792 pr_debug("dwc3: missing wMaxPacketSize\n");
796 dep = to_dwc3_ep(ep);
799 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
800 "%s is already enabled\n",
804 spin_lock_irqsave(&dwc->lock, flags);
805 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
806 spin_unlock_irqrestore(&dwc->lock, flags);
811 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
819 pr_debug("dwc3: invalid parameters\n");
823 dep = to_dwc3_ep(ep);
826 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
827 "%s is already disabled\n",
831 spin_lock_irqsave(&dwc->lock, flags);
832 ret = __dwc3_gadget_ep_disable(dep);
833 spin_unlock_irqrestore(&dwc->lock, flags);
838 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
841 struct dwc3_request *req;
842 struct dwc3_ep *dep = to_dwc3_ep(ep);
844 req = kzalloc(sizeof(*req), gfp_flags);
848 req->direction = dep->direction;
849 req->epnum = dep->number;
852 trace_dwc3_alloc_request(req);
854 return &req->request;
857 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
858 struct usb_request *request)
860 struct dwc3_request *req = to_dwc3_request(request);
862 trace_dwc3_free_request(req);
867 * dwc3_ep_prev_trb - returns the previous TRB in the ring
868 * @dep: The endpoint with the TRB ring
869 * @index: The index of the current TRB in the ring
871 * Returns the TRB prior to the one pointed to by the index. If the
872 * index is 0, we will wrap backwards, skip the link TRB, and return
873 * the one just before that.
875 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
880 tmp = DWC3_TRB_NUM - 1;
882 return &dep->trb_pool[tmp - 1];
885 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
887 struct dwc3_trb *tmp;
891 * If enqueue & dequeue are equal than it is either full or empty.
893 * One way to know for sure is if the TRB right before us has HWO bit
894 * set or not. If it has, then we're definitely full and can't fit any
895 * more transfers in our ring.
897 if (dep->trb_enqueue == dep->trb_dequeue) {
898 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
899 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
902 return DWC3_TRB_NUM - 1;
905 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
906 trbs_left &= (DWC3_TRB_NUM - 1);
908 if (dep->trb_dequeue < dep->trb_enqueue)
914 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
915 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
916 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
918 struct dwc3 *dwc = dep->dwc;
919 struct usb_gadget *gadget = &dwc->gadget;
920 enum usb_device_speed speed = gadget->speed;
922 dwc3_ep_inc_enq(dep);
924 trb->size = DWC3_TRB_SIZE_LENGTH(length);
925 trb->bpl = lower_32_bits(dma);
926 trb->bph = upper_32_bits(dma);
928 switch (usb_endpoint_type(dep->endpoint.desc)) {
929 case USB_ENDPOINT_XFER_CONTROL:
930 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
933 case USB_ENDPOINT_XFER_ISOC:
935 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
938 * USB Specification 2.0 Section 5.9.2 states that: "If
939 * there is only a single transaction in the microframe,
940 * only a DATA0 data packet PID is used. If there are
941 * two transactions per microframe, DATA1 is used for
942 * the first transaction data packet and DATA0 is used
943 * for the second transaction data packet. If there are
944 * three transactions per microframe, DATA2 is used for
945 * the first transaction data packet, DATA1 is used for
946 * the second, and DATA0 is used for the third."
948 * IOW, we should satisfy the following cases:
950 * 1) length <= maxpacket
953 * 2) maxpacket < length <= (2 * maxpacket)
956 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
957 * - DATA2, DATA1, DATA0
959 if (speed == USB_SPEED_HIGH) {
960 struct usb_ep *ep = &dep->endpoint;
961 unsigned int mult = 2;
962 unsigned int maxp = usb_endpoint_maxp(ep->desc);
964 if (length <= (2 * maxp))
970 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
973 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
976 /* always enable Interrupt on Missed ISOC */
977 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
980 case USB_ENDPOINT_XFER_BULK:
981 case USB_ENDPOINT_XFER_INT:
982 trb->ctrl = DWC3_TRBCTL_NORMAL;
986 * This is only possible with faulty memory because we
987 * checked it already :)
989 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
990 usb_endpoint_type(dep->endpoint.desc));
993 /* always enable Continue on Short Packet */
994 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
995 trb->ctrl |= DWC3_TRB_CTRL_CSP;
998 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1001 if ((!no_interrupt && !chain) ||
1002 (dwc3_calc_trbs_left(dep) == 0))
1003 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1006 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1008 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1009 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1011 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1013 trace_dwc3_prepare_trb(dep, trb);
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1023 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1037 length = req->request.length;
1038 dma = req->request.dma;
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1044 dwc3_gadget_move_started_request(req);
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1055 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1078 req->needs_extra_trb = true;
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1103 req->start_sg = sg_next(s);
1105 req->num_queued_sgs++;
1107 if (!dwc3_calc_trbs_left(dep))
1112 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1119 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1123 req->needs_extra_trb = true;
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1140 req->needs_extra_trb = true;
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1165 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1167 struct dwc3_request *req, *n;
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1185 if (!dwc3_calc_trbs_left(dep))
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1206 dwc3_prepare_one_trb_linear(dep, req);
1208 if (!dwc3_calc_trbs_left(dep))
1213 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1221 if (!dwc3_calc_trbs_left(dep))
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1233 memset(¶ms, 0, sizeof(params));
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1240 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1241 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1243 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1244 DWC3_DEPCMD_PARAM(dep->resource_index);
1247 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1250 * FIXME we need to iterate over the list of requests
1251 * here and stop, unmap, free and del each of the linked
1252 * requests instead of what we do now.
1255 memset(req->trb, 0, sizeof(struct dwc3_trb));
1256 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1263 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1268 return DWC3_DSTS_SOFFN(reg);
1272 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1273 * @dep: isoc endpoint
1275 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1276 * microframe number reported by the XferNotReady event for the future frame
1277 * number to start the isoc transfer.
1279 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1280 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1281 * XferNotReady event are invalid. The driver uses this number to schedule the
1282 * isochronous transfer and passes it to the START TRANSFER command. Because
1283 * this number is invalid, the command may fail. If BIT[15:14] matches the
1284 * internal 16-bit microframe, the START TRANSFER command will pass and the
1285 * transfer will start at the scheduled time, if it is off by 1, the command
1286 * will still pass, but the transfer will start 2 seconds in the future. For all
1287 * other conditions, the START TRANSFER command will fail with bus-expiry.
1289 * In order to workaround this issue, we can test for the correct combination of
1290 * BIT[15:14] by sending START TRANSFER commands with different values of
1291 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1292 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1293 * As the result, within the 4 possible combinations for BIT[15:14], there will
1294 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1295 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1296 * value is the correct combination.
1298 * Since there are only 4 outcomes and the results are ordered, we can simply
1299 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1300 * deduce the smaller successful combination.
1302 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1303 * of BIT[15:14]. The correct combination is as follow:
1305 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1306 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1307 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1308 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1310 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1313 static void dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1319 while (dep->combo_num < 2) {
1320 struct dwc3_gadget_ep_cmd_params params;
1321 u32 test_frame_number;
1325 * Check if we can start isoc transfer on the next interval or
1326 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1328 test_frame_number = dep->frame_number & 0x3fff;
1329 test_frame_number |= dep->combo_num << 14;
1330 test_frame_number += max_t(u32, 4, dep->interval);
1332 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1333 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1335 cmd = DWC3_DEPCMD_STARTTRANSFER;
1336 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1337 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1339 /* Redo if some other failure beside bus-expiry is received */
1340 if (cmd_status && cmd_status != -EAGAIN) {
1341 dep->start_cmd_status = 0;
1346 /* Store the first test status */
1347 if (dep->combo_num == 0)
1348 dep->start_cmd_status = cmd_status;
1353 * End the transfer if the START_TRANSFER command is successful
1354 * to wait for the next XferNotReady to test the command again
1356 if (cmd_status == 0) {
1357 dwc3_stop_active_transfer(dep, true);
1362 /* test0 and test1 are both completed at this point */
1363 test0 = (dep->start_cmd_status == 0);
1364 test1 = (cmd_status == 0);
1366 if (!test0 && test1)
1368 else if (!test0 && !test1)
1370 else if (test0 && !test1)
1372 else if (test0 && test1)
1375 dep->frame_number &= 0x3fff;
1376 dep->frame_number |= dep->combo_num << 14;
1377 dep->frame_number += max_t(u32, 4, dep->interval);
1379 /* Reinitialize test variables */
1380 dep->start_cmd_status = 0;
1383 __dwc3_gadget_kick_transfer(dep);
1386 static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1388 struct dwc3 *dwc = dep->dwc;
1390 if (list_empty(&dep->pending_list)) {
1391 dev_info(dep->dwc->dev, "%s: ran out of requests\n",
1393 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1398 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1399 (dwc->revision == DWC3_USB31_REVISION_170A &&
1400 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1401 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1403 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) {
1404 dwc3_gadget_start_isoc_quirk(dep);
1409 dep->frame_number = DWC3_ALIGN_FRAME(dep);
1410 __dwc3_gadget_kick_transfer(dep);
1413 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1415 struct dwc3 *dwc = dep->dwc;
1417 if (!dep->endpoint.desc) {
1418 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1423 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1424 &req->request, req->dep->name))
1427 pm_runtime_get(dwc->dev);
1429 req->request.actual = 0;
1430 req->request.status = -EINPROGRESS;
1432 trace_dwc3_ep_queue(req);
1434 list_add_tail(&req->list, &dep->pending_list);
1437 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1438 * wait for a XferNotReady event so we will know what's the current
1439 * (micro-)frame number.
1441 * Without this trick, we are very, very likely gonna get Bus Expiry
1442 * errors which will force us issue EndTransfer command.
1444 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1445 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1446 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1449 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1450 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1451 __dwc3_gadget_start_isoc(dep);
1457 return __dwc3_gadget_kick_transfer(dep);
1460 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1463 struct dwc3_request *req = to_dwc3_request(request);
1464 struct dwc3_ep *dep = to_dwc3_ep(ep);
1465 struct dwc3 *dwc = dep->dwc;
1467 unsigned long flags;
1471 spin_lock_irqsave(&dwc->lock, flags);
1472 ret = __dwc3_gadget_ep_queue(dep, req);
1473 spin_unlock_irqrestore(&dwc->lock, flags);
1478 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1479 struct usb_request *request)
1481 struct dwc3_request *req = to_dwc3_request(request);
1482 struct dwc3_request *r = NULL;
1484 struct dwc3_ep *dep = to_dwc3_ep(ep);
1485 struct dwc3 *dwc = dep->dwc;
1487 unsigned long flags;
1490 trace_dwc3_ep_dequeue(req);
1492 spin_lock_irqsave(&dwc->lock, flags);
1494 list_for_each_entry(r, &dep->pending_list, list) {
1500 list_for_each_entry(r, &dep->started_list, list) {
1505 /* wait until it is processed */
1506 dwc3_stop_active_transfer(dep, true);
1509 * If request was already started, this means we had to
1510 * stop the transfer. With that we also need to ignore
1511 * all TRBs used by the request, however TRBs can only
1512 * be modified after completion of END_TRANSFER
1513 * command. So what we do here is that we wait for
1514 * END_TRANSFER completion and only after that, we jump
1515 * over TRBs by clearing HWO and incrementing dequeue
1518 * Note that we have 2 possible types of transfers here:
1520 * i) Linear buffer request
1521 * ii) SG-list based request
1523 * SG-list based requests will have r->num_pending_sgs
1524 * set to a valid number (> 0). Linear requests,
1525 * normally use a single TRB.
1527 * For each of these two cases, if r->unaligned flag is
1528 * set, one extra TRB has been used to align transfer
1529 * size to wMaxPacketSize.
1531 * All of these cases need to be taken into
1532 * consideration so we don't mess up our TRB ring
1535 wait_event_lock_irq(dep->wait_end_transfer,
1536 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1542 if (r->num_pending_sgs) {
1543 struct dwc3_trb *trb;
1546 for (i = 0; i < r->num_pending_sgs; i++) {
1548 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1549 dwc3_ep_inc_deq(dep);
1552 if (r->needs_extra_trb) {
1553 trb = r->trb + r->num_pending_sgs + 1;
1554 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1555 dwc3_ep_inc_deq(dep);
1558 struct dwc3_trb *trb = r->trb;
1560 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1561 dwc3_ep_inc_deq(dep);
1563 if (r->needs_extra_trb) {
1565 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1566 dwc3_ep_inc_deq(dep);
1571 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1578 /* giveback the request */
1580 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1583 spin_unlock_irqrestore(&dwc->lock, flags);
1588 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1590 struct dwc3_gadget_ep_cmd_params params;
1591 struct dwc3 *dwc = dep->dwc;
1594 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1595 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1599 memset(¶ms, 0x00, sizeof(params));
1602 struct dwc3_trb *trb;
1604 unsigned transfer_in_flight;
1607 if (dep->flags & DWC3_EP_STALL)
1610 if (dep->number > 1)
1611 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1613 trb = &dwc->ep0_trb[dep->trb_enqueue];
1615 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1616 started = !list_empty(&dep->started_list);
1618 if (!protocol && ((dep->direction && transfer_in_flight) ||
1619 (!dep->direction && started))) {
1623 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1626 dev_err(dwc->dev, "failed to set STALL on %s\n",
1629 dep->flags |= DWC3_EP_STALL;
1631 if (!(dep->flags & DWC3_EP_STALL))
1634 ret = dwc3_send_clear_stall_ep_cmd(dep);
1636 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1639 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1645 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1647 struct dwc3_ep *dep = to_dwc3_ep(ep);
1648 struct dwc3 *dwc = dep->dwc;
1650 unsigned long flags;
1654 spin_lock_irqsave(&dwc->lock, flags);
1655 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1656 spin_unlock_irqrestore(&dwc->lock, flags);
1661 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1663 struct dwc3_ep *dep = to_dwc3_ep(ep);
1664 struct dwc3 *dwc = dep->dwc;
1665 unsigned long flags;
1668 spin_lock_irqsave(&dwc->lock, flags);
1669 dep->flags |= DWC3_EP_WEDGE;
1671 if (dep->number == 0 || dep->number == 1)
1672 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1674 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1675 spin_unlock_irqrestore(&dwc->lock, flags);
1680 /* -------------------------------------------------------------------------- */
1682 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1683 .bLength = USB_DT_ENDPOINT_SIZE,
1684 .bDescriptorType = USB_DT_ENDPOINT,
1685 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1688 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1689 .enable = dwc3_gadget_ep0_enable,
1690 .disable = dwc3_gadget_ep0_disable,
1691 .alloc_request = dwc3_gadget_ep_alloc_request,
1692 .free_request = dwc3_gadget_ep_free_request,
1693 .queue = dwc3_gadget_ep0_queue,
1694 .dequeue = dwc3_gadget_ep_dequeue,
1695 .set_halt = dwc3_gadget_ep0_set_halt,
1696 .set_wedge = dwc3_gadget_ep_set_wedge,
1699 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1700 .enable = dwc3_gadget_ep_enable,
1701 .disable = dwc3_gadget_ep_disable,
1702 .alloc_request = dwc3_gadget_ep_alloc_request,
1703 .free_request = dwc3_gadget_ep_free_request,
1704 .queue = dwc3_gadget_ep_queue,
1705 .dequeue = dwc3_gadget_ep_dequeue,
1706 .set_halt = dwc3_gadget_ep_set_halt,
1707 .set_wedge = dwc3_gadget_ep_set_wedge,
1710 /* -------------------------------------------------------------------------- */
1712 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1714 struct dwc3 *dwc = gadget_to_dwc(g);
1716 return __dwc3_gadget_get_frame(dwc);
1719 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1730 * According to the Databook Remote wakeup request should
1731 * be issued only when the device is in early suspend state.
1733 * We can check that via USB Link State bits in DSTS register.
1735 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1737 speed = reg & DWC3_DSTS_CONNECTSPD;
1738 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1739 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1742 link_state = DWC3_DSTS_USBLNKST(reg);
1744 switch (link_state) {
1745 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1746 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1752 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1754 dev_err(dwc->dev, "failed to put link in Recovery\n");
1758 /* Recent versions do this automatically */
1759 if (dwc->revision < DWC3_REVISION_194A) {
1760 /* write zeroes to Link Change Request */
1761 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1762 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1763 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1766 /* poll until Link State changes to ON */
1770 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1772 /* in HS, means ON */
1773 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1777 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1778 dev_err(dwc->dev, "failed to send remote wakeup\n");
1785 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1787 struct dwc3 *dwc = gadget_to_dwc(g);
1788 unsigned long flags;
1791 spin_lock_irqsave(&dwc->lock, flags);
1792 ret = __dwc3_gadget_wakeup(dwc);
1793 spin_unlock_irqrestore(&dwc->lock, flags);
1798 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1801 struct dwc3 *dwc = gadget_to_dwc(g);
1802 unsigned long flags;
1804 spin_lock_irqsave(&dwc->lock, flags);
1805 g->is_selfpowered = !!is_selfpowered;
1806 spin_unlock_irqrestore(&dwc->lock, flags);
1811 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1816 if (pm_runtime_suspended(dwc->dev))
1819 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1821 if (dwc->revision <= DWC3_REVISION_187A) {
1822 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1823 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1826 if (dwc->revision >= DWC3_REVISION_194A)
1827 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1828 reg |= DWC3_DCTL_RUN_STOP;
1830 if (dwc->has_hibernation)
1831 reg |= DWC3_DCTL_KEEP_CONNECT;
1833 dwc->pullups_connected = true;
1835 reg &= ~DWC3_DCTL_RUN_STOP;
1837 if (dwc->has_hibernation && !suspend)
1838 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1840 dwc->pullups_connected = false;
1843 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1846 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1847 reg &= DWC3_DSTS_DEVCTRLHLT;
1848 } while (--timeout && !(!is_on ^ !reg));
1856 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1858 struct dwc3 *dwc = gadget_to_dwc(g);
1859 unsigned long flags;
1865 * Per databook, when we want to stop the gadget, if a control transfer
1866 * is still in process, complete it and get the core into setup phase.
1868 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1869 reinit_completion(&dwc->ep0_in_setup);
1871 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1872 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1874 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1879 spin_lock_irqsave(&dwc->lock, flags);
1880 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1881 spin_unlock_irqrestore(&dwc->lock, flags);
1886 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1890 /* Enable all but Start and End of Frame IRQs */
1891 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1892 DWC3_DEVTEN_EVNTOVERFLOWEN |
1893 DWC3_DEVTEN_CMDCMPLTEN |
1894 DWC3_DEVTEN_ERRTICERREN |
1895 DWC3_DEVTEN_WKUPEVTEN |
1896 DWC3_DEVTEN_CONNECTDONEEN |
1897 DWC3_DEVTEN_USBRSTEN |
1898 DWC3_DEVTEN_DISCONNEVTEN);
1900 if (dwc->revision < DWC3_REVISION_250A)
1901 reg |= DWC3_DEVTEN_ULSTCNGEN;
1903 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1906 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1908 /* mask all interrupts */
1909 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1912 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1913 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1916 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1917 * @dwc: pointer to our context structure
1919 * The following looks like complex but it's actually very simple. In order to
1920 * calculate the number of packets we can burst at once on OUT transfers, we're
1921 * gonna use RxFIFO size.
1923 * To calculate RxFIFO size we need two numbers:
1924 * MDWIDTH = size, in bits, of the internal memory bus
1925 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1927 * Given these two numbers, the formula is simple:
1929 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1931 * 24 bytes is for 3x SETUP packets
1932 * 16 bytes is a clock domain crossing tolerance
1934 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1936 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1943 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1944 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1946 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1947 nump = min_t(u32, nump, 16);
1950 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1951 reg &= ~DWC3_DCFG_NUMP_MASK;
1952 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1953 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1956 static int __dwc3_gadget_start(struct dwc3 *dwc)
1958 struct dwc3_ep *dep;
1963 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1964 * the core supports IMOD, disable it.
1966 if (dwc->imod_interval) {
1967 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1968 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1969 } else if (dwc3_has_imod(dwc)) {
1970 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1974 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1975 * field instead of letting dwc3 itself calculate that automatically.
1977 * This way, we maximize the chances that we'll be able to get several
1978 * bursts of data without going through any sort of endpoint throttling.
1980 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1981 if (dwc3_is_usb31(dwc))
1982 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1984 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1986 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1988 dwc3_gadget_setup_nump(dwc);
1990 /* Start with SuperSpeed Default */
1991 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1994 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1996 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2001 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2003 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2007 /* begin to receive SETUP packets */
2008 dwc->ep0state = EP0_SETUP_PHASE;
2009 dwc3_ep0_out_start(dwc);
2011 dwc3_gadget_enable_irq(dwc);
2016 __dwc3_gadget_ep_disable(dwc->eps[0]);
2022 static int dwc3_gadget_start(struct usb_gadget *g,
2023 struct usb_gadget_driver *driver)
2025 struct dwc3 *dwc = gadget_to_dwc(g);
2026 unsigned long flags;
2030 irq = dwc->irq_gadget;
2031 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2032 IRQF_SHARED, "dwc3", dwc->ev_buf);
2034 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2039 spin_lock_irqsave(&dwc->lock, flags);
2040 if (dwc->gadget_driver) {
2041 dev_err(dwc->dev, "%s is already bound to %s\n",
2043 dwc->gadget_driver->driver.name);
2048 dwc->gadget_driver = driver;
2050 if (pm_runtime_active(dwc->dev))
2051 __dwc3_gadget_start(dwc);
2053 spin_unlock_irqrestore(&dwc->lock, flags);
2058 spin_unlock_irqrestore(&dwc->lock, flags);
2065 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2067 dwc3_gadget_disable_irq(dwc);
2068 __dwc3_gadget_ep_disable(dwc->eps[0]);
2069 __dwc3_gadget_ep_disable(dwc->eps[1]);
2072 static int dwc3_gadget_stop(struct usb_gadget *g)
2074 struct dwc3 *dwc = gadget_to_dwc(g);
2075 unsigned long flags;
2079 spin_lock_irqsave(&dwc->lock, flags);
2081 if (pm_runtime_suspended(dwc->dev))
2084 __dwc3_gadget_stop(dwc);
2086 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2087 struct dwc3_ep *dep = dwc->eps[epnum];
2093 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2096 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
2097 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
2098 dwc->lock, msecs_to_jiffies(5));
2101 /* Timed out or interrupted! There's nothing much
2102 * we can do so we just log here and print which
2103 * endpoints timed out at the end.
2105 tmo_eps |= 1 << epnum;
2106 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
2112 "end transfer timed out on endpoints 0x%x [bitmap]\n",
2117 dwc->gadget_driver = NULL;
2118 spin_unlock_irqrestore(&dwc->lock, flags);
2120 free_irq(dwc->irq_gadget, dwc->ev_buf);
2125 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2126 enum usb_device_speed speed)
2128 struct dwc3 *dwc = gadget_to_dwc(g);
2129 unsigned long flags;
2132 spin_lock_irqsave(&dwc->lock, flags);
2133 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2134 reg &= ~(DWC3_DCFG_SPEED_MASK);
2137 * WORKAROUND: DWC3 revision < 2.20a have an issue
2138 * which would cause metastability state on Run/Stop
2139 * bit if we try to force the IP to USB2-only mode.
2141 * Because of that, we cannot configure the IP to any
2142 * speed other than the SuperSpeed
2146 * STAR#9000525659: Clock Domain Crossing on DCTL in
2149 if (dwc->revision < DWC3_REVISION_220A &&
2150 !dwc->dis_metastability_quirk) {
2151 reg |= DWC3_DCFG_SUPERSPEED;
2155 reg |= DWC3_DCFG_LOWSPEED;
2157 case USB_SPEED_FULL:
2158 reg |= DWC3_DCFG_FULLSPEED;
2160 case USB_SPEED_HIGH:
2161 reg |= DWC3_DCFG_HIGHSPEED;
2163 case USB_SPEED_SUPER:
2164 reg |= DWC3_DCFG_SUPERSPEED;
2166 case USB_SPEED_SUPER_PLUS:
2167 if (dwc3_is_usb31(dwc))
2168 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2170 reg |= DWC3_DCFG_SUPERSPEED;
2173 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2175 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2176 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2178 reg |= DWC3_DCFG_SUPERSPEED;
2181 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2183 spin_unlock_irqrestore(&dwc->lock, flags);
2186 static const struct usb_gadget_ops dwc3_gadget_ops = {
2187 .get_frame = dwc3_gadget_get_frame,
2188 .wakeup = dwc3_gadget_wakeup,
2189 .set_selfpowered = dwc3_gadget_set_selfpowered,
2190 .pullup = dwc3_gadget_pullup,
2191 .udc_start = dwc3_gadget_start,
2192 .udc_stop = dwc3_gadget_stop,
2193 .udc_set_speed = dwc3_gadget_set_speed,
2196 /* -------------------------------------------------------------------------- */
2198 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2200 struct dwc3 *dwc = dep->dwc;
2202 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2203 dep->endpoint.maxburst = 1;
2204 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2205 if (!dep->direction)
2206 dwc->gadget.ep0 = &dep->endpoint;
2208 dep->endpoint.caps.type_control = true;
2213 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2215 struct dwc3 *dwc = dep->dwc;
2220 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2221 /* MDWIDTH is represented in bits, we need it in bytes */
2224 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2225 if (dwc3_is_usb31(dwc))
2226 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2228 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2230 /* FIFO Depth is in MDWDITH bytes. Multiply */
2233 kbytes = size / 1024;
2238 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2239 * internal overhead. We don't really know how these are used,
2240 * but documentation say it exists.
2242 size -= mdwidth * (kbytes + 1);
2245 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2247 dep->endpoint.max_streams = 15;
2248 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2249 list_add_tail(&dep->endpoint.ep_list,
2250 &dwc->gadget.ep_list);
2251 dep->endpoint.caps.type_iso = true;
2252 dep->endpoint.caps.type_bulk = true;
2253 dep->endpoint.caps.type_int = true;
2255 return dwc3_alloc_trb_pool(dep);
2258 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2260 struct dwc3 *dwc = dep->dwc;
2262 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2263 dep->endpoint.max_streams = 15;
2264 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2265 list_add_tail(&dep->endpoint.ep_list,
2266 &dwc->gadget.ep_list);
2267 dep->endpoint.caps.type_iso = true;
2268 dep->endpoint.caps.type_bulk = true;
2269 dep->endpoint.caps.type_int = true;
2271 return dwc3_alloc_trb_pool(dep);
2274 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2276 struct dwc3_ep *dep;
2277 bool direction = epnum & 1;
2279 u8 num = epnum >> 1;
2281 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2286 dep->number = epnum;
2287 dep->direction = direction;
2288 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2289 dwc->eps[epnum] = dep;
2291 dep->start_cmd_status = 0;
2293 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2294 direction ? "in" : "out");
2296 dep->endpoint.name = dep->name;
2298 if (!(dep->number > 1)) {
2299 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2300 dep->endpoint.comp_desc = NULL;
2303 spin_lock_init(&dep->lock);
2306 ret = dwc3_gadget_init_control_endpoint(dep);
2308 ret = dwc3_gadget_init_in_endpoint(dep);
2310 ret = dwc3_gadget_init_out_endpoint(dep);
2315 dep->endpoint.caps.dir_in = direction;
2316 dep->endpoint.caps.dir_out = !direction;
2318 INIT_LIST_HEAD(&dep->pending_list);
2319 INIT_LIST_HEAD(&dep->started_list);
2324 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2328 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2330 for (epnum = 0; epnum < total; epnum++) {
2333 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2341 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2343 struct dwc3_ep *dep;
2346 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2347 dep = dwc->eps[epnum];
2351 * Physical endpoints 0 and 1 are special; they form the
2352 * bi-directional USB endpoint 0.
2354 * For those two physical endpoints, we don't allocate a TRB
2355 * pool nor do we add them the endpoints list. Due to that, we
2356 * shouldn't do these two operations otherwise we would end up
2357 * with all sorts of bugs when removing dwc3.ko.
2359 if (epnum != 0 && epnum != 1) {
2360 dwc3_free_trb_pool(dep);
2361 list_del(&dep->endpoint.ep_list);
2368 /* -------------------------------------------------------------------------- */
2370 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2371 struct dwc3_request *req, struct dwc3_trb *trb,
2372 const struct dwc3_event_depevt *event, int status, int chain)
2376 dwc3_ep_inc_deq(dep);
2378 trace_dwc3_complete_trb(dep, trb);
2382 * If we're in the middle of series of chained TRBs and we
2383 * receive a short transfer along the way, DWC3 will skip
2384 * through all TRBs including the last TRB in the chain (the
2385 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2386 * bit and SW has to do it manually.
2388 * We're going to do that here to avoid problems of HW trying
2389 * to use bogus TRBs for transfers.
2391 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2392 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2395 * If we're dealing with unaligned size OUT transfer, we will be left
2396 * with one TRB pending in the ring. We need to manually clear HWO bit
2400 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2401 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2405 count = trb->size & DWC3_TRB_SIZE_MASK;
2406 req->remaining += count;
2408 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2411 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2414 if (event->status & DEPEVT_STATUS_IOC)
2420 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2421 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2424 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2425 struct scatterlist *sg = req->sg;
2426 struct scatterlist *s;
2427 unsigned int pending = req->num_pending_sgs;
2431 for_each_sg(sg, s, pending, i) {
2432 trb = &dep->trb_pool[dep->trb_dequeue];
2434 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2437 req->sg = sg_next(s);
2438 req->num_pending_sgs--;
2440 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2441 trb, event, status, true);
2449 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2450 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2453 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2455 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2456 event, status, false);
2459 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2461 return req->request.actual == req->request.length;
2464 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2465 const struct dwc3_event_depevt *event,
2466 struct dwc3_request *req, int status)
2470 if (req->num_pending_sgs)
2471 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2474 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2477 if (req->needs_extra_trb) {
2478 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2480 req->needs_extra_trb = false;
2483 req->request.actual = req->request.length - req->remaining;
2485 if (!dwc3_gadget_ep_request_completed(req) &&
2486 req->num_pending_sgs) {
2487 __dwc3_gadget_kick_transfer(dep);
2491 dwc3_gadget_giveback(dep, req, status);
2497 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2498 const struct dwc3_event_depevt *event, int status)
2500 struct dwc3_request *req;
2501 struct dwc3_request *tmp;
2503 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2506 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2513 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2514 const struct dwc3_event_depevt *event)
2516 dep->frame_number = event->parameters;
2519 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2520 const struct dwc3_event_depevt *event)
2522 struct dwc3 *dwc = dep->dwc;
2523 unsigned status = 0;
2526 dwc3_gadget_endpoint_frame_from_event(dep, event);
2528 if (event->status & DEPEVT_STATUS_BUSERR)
2529 status = -ECONNRESET;
2531 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2534 if (list_empty(&dep->started_list))
2538 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2541 dwc3_stop_active_transfer(dep, true);
2542 dep->flags = DWC3_EP_ENABLED;
2546 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2547 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2549 if (dwc->revision < DWC3_REVISION_183A) {
2553 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2556 if (!(dep->flags & DWC3_EP_ENABLED))
2559 if (!list_empty(&dep->started_list))
2563 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2565 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2571 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2572 const struct dwc3_event_depevt *event)
2574 dwc3_gadget_endpoint_frame_from_event(dep, event);
2575 __dwc3_gadget_start_isoc(dep);
2578 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2579 const struct dwc3_event_depevt *event)
2581 struct dwc3_ep *dep;
2582 u8 epnum = event->endpoint_number;
2585 dep = dwc->eps[epnum];
2587 if (!(dep->flags & DWC3_EP_ENABLED)) {
2588 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2591 /* Handle only EPCMDCMPLT when EP disabled */
2592 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2596 if (epnum == 0 || epnum == 1) {
2597 dwc3_ep0_interrupt(dwc, event);
2601 switch (event->endpoint_event) {
2602 case DWC3_DEPEVT_XFERINPROGRESS:
2603 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2605 case DWC3_DEPEVT_XFERNOTREADY:
2606 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2608 case DWC3_DEPEVT_EPCMDCMPLT:
2609 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2611 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2612 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2613 wake_up(&dep->wait_end_transfer);
2616 case DWC3_DEPEVT_STREAMEVT:
2617 case DWC3_DEPEVT_XFERCOMPLETE:
2618 case DWC3_DEPEVT_RXTXFIFOEVT:
2623 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2625 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2626 spin_unlock(&dwc->lock);
2627 dwc->gadget_driver->disconnect(&dwc->gadget);
2628 spin_lock(&dwc->lock);
2632 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2634 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->suspend(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2641 static void dwc3_resume_gadget(struct dwc3 *dwc)
2643 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->resume(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2650 static void dwc3_reset_gadget(struct dwc3 *dwc)
2652 if (!dwc->gadget_driver)
2655 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2656 spin_unlock(&dwc->lock);
2657 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2658 spin_lock(&dwc->lock);
2662 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2664 struct dwc3 *dwc = dep->dwc;
2665 struct dwc3_gadget_ep_cmd_params params;
2669 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2670 !dep->resource_index)
2674 * NOTICE: We are violating what the Databook says about the
2675 * EndTransfer command. Ideally we would _always_ wait for the
2676 * EndTransfer Command Completion IRQ, but that's causing too
2677 * much trouble synchronizing between us and gadget driver.
2679 * We have discussed this with the IP Provider and it was
2680 * suggested to giveback all requests here, but give HW some
2681 * extra time to synchronize with the interconnect. We're using
2682 * an arbitrary 100us delay for that.
2684 * Note also that a similar handling was tested by Synopsys
2685 * (thanks a lot Paul) and nothing bad has come out of it.
2686 * In short, what we're doing is:
2688 * - Issue EndTransfer WITH CMDIOC bit set
2691 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2692 * supports a mode to work around the above limitation. The
2693 * software can poll the CMDACT bit in the DEPCMD register
2694 * after issuing a EndTransfer command. This mode is enabled
2695 * by writing GUCTL2[14]. This polling is already done in the
2696 * dwc3_send_gadget_ep_cmd() function so if the mode is
2697 * enabled, the EndTransfer command will have completed upon
2698 * returning from this function and we don't need to delay for
2701 * This mode is NOT available on the DWC_usb31 IP.
2704 cmd = DWC3_DEPCMD_ENDTRANSFER;
2705 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2706 cmd |= DWC3_DEPCMD_CMDIOC;
2707 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2708 memset(¶ms, 0, sizeof(params));
2709 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2711 dep->resource_index = 0;
2713 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2714 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2719 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2723 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2724 struct dwc3_ep *dep;
2727 dep = dwc->eps[epnum];
2731 if (!(dep->flags & DWC3_EP_STALL))
2734 dep->flags &= ~DWC3_EP_STALL;
2736 ret = dwc3_send_clear_stall_ep_cmd(dep);
2741 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2745 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2746 reg &= ~DWC3_DCTL_INITU1ENA;
2747 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2749 reg &= ~DWC3_DCTL_INITU2ENA;
2750 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2752 dwc3_disconnect_gadget(dwc);
2754 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2755 dwc->setup_packet_pending = false;
2756 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2758 dwc->connected = false;
2761 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2765 dwc->connected = true;
2768 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2769 * would cause a missing Disconnect Event if there's a
2770 * pending Setup Packet in the FIFO.
2772 * There's no suggested workaround on the official Bug
2773 * report, which states that "unless the driver/application
2774 * is doing any special handling of a disconnect event,
2775 * there is no functional issue".
2777 * Unfortunately, it turns out that we _do_ some special
2778 * handling of a disconnect event, namely complete all
2779 * pending transfers, notify gadget driver of the
2780 * disconnection, and so on.
2782 * Our suggested workaround is to follow the Disconnect
2783 * Event steps here, instead, based on a setup_packet_pending
2784 * flag. Such flag gets set whenever we have a SETUP_PENDING
2785 * status for EP0 TRBs and gets cleared on XferComplete for the
2790 * STAR#9000466709: RTL: Device : Disconnect event not
2791 * generated if setup packet pending in FIFO
2793 if (dwc->revision < DWC3_REVISION_188A) {
2794 if (dwc->setup_packet_pending)
2795 dwc3_gadget_disconnect_interrupt(dwc);
2798 dwc3_reset_gadget(dwc);
2800 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2801 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2802 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2803 dwc->test_mode = false;
2804 dwc3_clear_stall_all_ep(dwc);
2806 /* Reset device address to zero */
2807 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2808 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2809 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2812 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2814 struct dwc3_ep *dep;
2819 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2820 speed = reg & DWC3_DSTS_CONNECTSPD;
2824 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2825 * each time on Connect Done.
2827 * Currently we always use the reset value. If any platform
2828 * wants to set this to a different value, we need to add a
2829 * setting and update GCTL.RAMCLKSEL here.
2833 case DWC3_DSTS_SUPERSPEED_PLUS:
2834 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2835 dwc->gadget.ep0->maxpacket = 512;
2836 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2838 case DWC3_DSTS_SUPERSPEED:
2840 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2841 * would cause a missing USB3 Reset event.
2843 * In such situations, we should force a USB3 Reset
2844 * event by calling our dwc3_gadget_reset_interrupt()
2849 * STAR#9000483510: RTL: SS : USB3 reset event may
2850 * not be generated always when the link enters poll
2852 if (dwc->revision < DWC3_REVISION_190A)
2853 dwc3_gadget_reset_interrupt(dwc);
2855 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2856 dwc->gadget.ep0->maxpacket = 512;
2857 dwc->gadget.speed = USB_SPEED_SUPER;
2859 case DWC3_DSTS_HIGHSPEED:
2860 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2861 dwc->gadget.ep0->maxpacket = 64;
2862 dwc->gadget.speed = USB_SPEED_HIGH;
2864 case DWC3_DSTS_FULLSPEED:
2865 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2866 dwc->gadget.ep0->maxpacket = 64;
2867 dwc->gadget.speed = USB_SPEED_FULL;
2869 case DWC3_DSTS_LOWSPEED:
2870 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2871 dwc->gadget.ep0->maxpacket = 8;
2872 dwc->gadget.speed = USB_SPEED_LOW;
2876 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2878 /* Enable USB2 LPM Capability */
2880 if ((dwc->revision > DWC3_REVISION_194A) &&
2881 (speed != DWC3_DSTS_SUPERSPEED) &&
2882 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2883 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2884 reg |= DWC3_DCFG_LPM_CAP;
2885 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2887 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2888 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2890 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2893 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2894 * DCFG.LPMCap is set, core responses with an ACK and the
2895 * BESL value in the LPM token is less than or equal to LPM
2898 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2899 && dwc->has_lpm_erratum,
2900 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2902 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2903 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2905 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2907 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2908 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2909 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2913 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2915 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2920 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2927 * Configure PHY via GUSB3PIPECTLn if required.
2929 * Update GTXFIFOSIZn
2931 * In both cases reset values should be sufficient.
2935 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2938 * TODO take core out of low power mode when that's
2942 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2943 spin_unlock(&dwc->lock);
2944 dwc->gadget_driver->resume(&dwc->gadget);
2945 spin_lock(&dwc->lock);
2949 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2950 unsigned int evtinfo)
2952 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2953 unsigned int pwropt;
2956 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2957 * Hibernation mode enabled which would show up when device detects
2958 * host-initiated U3 exit.
2960 * In that case, device will generate a Link State Change Interrupt
2961 * from U3 to RESUME which is only necessary if Hibernation is
2964 * There are no functional changes due to such spurious event and we
2965 * just need to ignore it.
2969 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2972 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2973 if ((dwc->revision < DWC3_REVISION_250A) &&
2974 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2975 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2976 (next == DWC3_LINK_STATE_RESUME)) {
2982 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2983 * on the link partner, the USB session might do multiple entry/exit
2984 * of low power states before a transfer takes place.
2986 * Due to this problem, we might experience lower throughput. The
2987 * suggested workaround is to disable DCTL[12:9] bits if we're
2988 * transitioning from U1/U2 to U0 and enable those bits again
2989 * after a transfer completes and there are no pending transfers
2990 * on any of the enabled endpoints.
2992 * This is the first half of that workaround.
2996 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2997 * core send LGO_Ux entering U0
2999 if (dwc->revision < DWC3_REVISION_183A) {
3000 if (next == DWC3_LINK_STATE_U0) {
3004 switch (dwc->link_state) {
3005 case DWC3_LINK_STATE_U1:
3006 case DWC3_LINK_STATE_U2:
3007 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3008 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3009 | DWC3_DCTL_ACCEPTU2ENA
3010 | DWC3_DCTL_INITU1ENA
3011 | DWC3_DCTL_ACCEPTU1ENA);
3014 dwc->u1u2 = reg & u1u2;
3018 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3028 case DWC3_LINK_STATE_U1:
3029 if (dwc->speed == USB_SPEED_SUPER)
3030 dwc3_suspend_gadget(dwc);
3032 case DWC3_LINK_STATE_U2:
3033 case DWC3_LINK_STATE_U3:
3034 dwc3_suspend_gadget(dwc);
3036 case DWC3_LINK_STATE_RESUME:
3037 dwc3_resume_gadget(dwc);
3044 dwc->link_state = next;
3047 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3048 unsigned int evtinfo)
3050 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3052 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3053 dwc3_suspend_gadget(dwc);
3055 dwc->link_state = next;
3058 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3059 unsigned int evtinfo)
3061 unsigned int is_ss = evtinfo & BIT(4);
3064 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3065 * have a known issue which can cause USB CV TD.9.23 to fail
3068 * Because of this issue, core could generate bogus hibernation
3069 * events which SW needs to ignore.
3073 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3074 * Device Fallback from SuperSpeed
3076 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3079 /* enter hibernation here */
3082 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3083 const struct dwc3_event_devt *event)
3085 switch (event->type) {
3086 case DWC3_DEVICE_EVENT_DISCONNECT:
3087 dwc3_gadget_disconnect_interrupt(dwc);
3089 case DWC3_DEVICE_EVENT_RESET:
3090 dwc3_gadget_reset_interrupt(dwc);
3092 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3093 dwc3_gadget_conndone_interrupt(dwc);
3095 case DWC3_DEVICE_EVENT_WAKEUP:
3096 dwc3_gadget_wakeup_interrupt(dwc);
3098 case DWC3_DEVICE_EVENT_HIBER_REQ:
3099 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3100 "unexpected hibernation event\n"))
3103 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3105 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3106 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3108 case DWC3_DEVICE_EVENT_EOPF:
3109 /* It changed to be suspend event for version 2.30a and above */
3110 if (dwc->revision >= DWC3_REVISION_230A) {
3112 * Ignore suspend event until the gadget enters into
3113 * USB_STATE_CONFIGURED state.
3115 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3116 dwc3_gadget_suspend_interrupt(dwc,
3120 case DWC3_DEVICE_EVENT_SOF:
3121 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3122 case DWC3_DEVICE_EVENT_CMD_CMPL:
3123 case DWC3_DEVICE_EVENT_OVERFLOW:
3126 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3130 static void dwc3_process_event_entry(struct dwc3 *dwc,
3131 const union dwc3_event *event)
3133 trace_dwc3_event(event->raw, dwc);
3135 if (!event->type.is_devspec)
3136 dwc3_endpoint_interrupt(dwc, &event->depevt);
3137 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3138 dwc3_gadget_interrupt(dwc, &event->devt);
3140 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3143 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3145 struct dwc3 *dwc = evt->dwc;
3146 irqreturn_t ret = IRQ_NONE;
3152 if (!(evt->flags & DWC3_EVENT_PENDING))
3156 union dwc3_event event;
3158 event.raw = *(u32 *) (evt->cache + evt->lpos);
3160 dwc3_process_event_entry(dwc, &event);
3163 * FIXME we wrap around correctly to the next entry as
3164 * almost all entries are 4 bytes in size. There is one
3165 * entry which has 12 bytes which is a regular entry
3166 * followed by 8 bytes data. ATM I don't know how
3167 * things are organized if we get next to the a
3168 * boundary so I worry about that once we try to handle
3171 evt->lpos = (evt->lpos + 4) % evt->length;
3176 evt->flags &= ~DWC3_EVENT_PENDING;
3179 /* Unmask interrupt */
3180 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3181 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3182 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3184 if (dwc->imod_interval) {
3185 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3186 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3192 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3194 struct dwc3_event_buffer *evt = _evt;
3195 struct dwc3 *dwc = evt->dwc;
3196 unsigned long flags;
3197 irqreturn_t ret = IRQ_NONE;
3199 spin_lock_irqsave(&dwc->lock, flags);
3200 ret = dwc3_process_event_buf(evt);
3201 spin_unlock_irqrestore(&dwc->lock, flags);
3206 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3208 struct dwc3 *dwc = evt->dwc;
3213 if (pm_runtime_suspended(dwc->dev)) {
3214 pm_runtime_get(dwc->dev);
3215 disable_irq_nosync(dwc->irq_gadget);
3216 dwc->pending_events = true;
3221 * With PCIe legacy interrupt, test shows that top-half irq handler can
3222 * be called again after HW interrupt deassertion. Check if bottom-half
3223 * irq event handler completes before caching new event to prevent
3226 if (evt->flags & DWC3_EVENT_PENDING)
3229 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3230 count &= DWC3_GEVNTCOUNT_MASK;
3235 evt->flags |= DWC3_EVENT_PENDING;
3237 /* Mask interrupt */
3238 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3239 reg |= DWC3_GEVNTSIZ_INTMASK;
3240 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3242 amount = min(count, evt->length - evt->lpos);
3243 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3246 memcpy(evt->cache, evt->buf, count - amount);
3248 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3250 return IRQ_WAKE_THREAD;
3253 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3255 struct dwc3_event_buffer *evt = _evt;
3257 return dwc3_check_event_buf(evt);
3260 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3262 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3265 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3269 if (irq == -EPROBE_DEFER)
3272 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3276 if (irq == -EPROBE_DEFER)
3279 irq = platform_get_irq(dwc3_pdev, 0);
3283 if (irq != -EPROBE_DEFER)
3284 dev_err(dwc->dev, "missing peripheral IRQ\n");
3294 * dwc3_gadget_init - initializes gadget related registers
3295 * @dwc: pointer to our controller context structure
3297 * Returns 0 on success otherwise negative errno.
3299 int dwc3_gadget_init(struct dwc3 *dwc)
3304 irq = dwc3_gadget_get_irq(dwc);
3310 dwc->irq_gadget = irq;
3312 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3313 sizeof(*dwc->ep0_trb) * 2,
3314 &dwc->ep0_trb_addr, GFP_KERNEL);
3315 if (!dwc->ep0_trb) {
3316 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3321 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3322 if (!dwc->setup_buf) {
3327 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3328 &dwc->bounce_addr, GFP_KERNEL);
3334 init_completion(&dwc->ep0_in_setup);
3336 dwc->gadget.ops = &dwc3_gadget_ops;
3337 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3338 dwc->gadget.sg_supported = true;
3339 dwc->gadget.name = "dwc3-gadget";
3340 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3343 * FIXME We might be setting max_speed to <SUPER, however versions
3344 * <2.20a of dwc3 have an issue with metastability (documented
3345 * elsewhere in this driver) which tells us we can't set max speed to
3346 * anything lower than SUPER.
3348 * Because gadget.max_speed is only used by composite.c and function
3349 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3350 * to happen so we avoid sending SuperSpeed Capability descriptor
3351 * together with our BOS descriptor as that could confuse host into
3352 * thinking we can handle super speed.
3354 * Note that, in fact, we won't even support GetBOS requests when speed
3355 * is less than super speed because we don't have means, yet, to tell
3356 * composite.c that we are USB 2.0 + LPM ECN.
3358 if (dwc->revision < DWC3_REVISION_220A &&
3359 !dwc->dis_metastability_quirk)
3360 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3363 dwc->gadget.max_speed = dwc->maximum_speed;
3366 * REVISIT: Here we should clear all pending IRQs to be
3367 * sure we're starting from a well known location.
3370 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3374 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3376 dev_err(dwc->dev, "failed to register udc\n");
3383 dwc3_gadget_free_endpoints(dwc);
3386 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3390 kfree(dwc->setup_buf);
3393 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3394 dwc->ep0_trb, dwc->ep0_trb_addr);
3400 /* -------------------------------------------------------------------------- */
3402 void dwc3_gadget_exit(struct dwc3 *dwc)
3404 usb_del_gadget_udc(&dwc->gadget);
3405 dwc3_gadget_free_endpoints(dwc);
3406 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3408 kfree(dwc->setup_buf);
3409 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3410 dwc->ep0_trb, dwc->ep0_trb_addr);
3413 int dwc3_gadget_suspend(struct dwc3 *dwc)
3415 if (!dwc->gadget_driver)
3418 dwc3_gadget_run_stop(dwc, false, false);
3419 dwc3_disconnect_gadget(dwc);
3420 __dwc3_gadget_stop(dwc);
3425 int dwc3_gadget_resume(struct dwc3 *dwc)
3429 if (!dwc->gadget_driver)
3432 ret = __dwc3_gadget_start(dwc);
3436 ret = dwc3_gadget_run_stop(dwc, true, false);
3443 __dwc3_gadget_stop(dwc);
3449 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3451 if (dwc->pending_events) {
3452 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3453 dwc->pending_events = false;
3454 enable_irq(dwc->irq_gadget);