2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
43 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
49 trb = &dwc->ep0_trb[dep->trb_enqueue];
54 trb->bpl = lower_32_bits(buf_dma);
55 trb->bph = upper_32_bits(buf_dma);
59 trb->ctrl |= (DWC3_TRB_CTRL_HWO
60 | DWC3_TRB_CTRL_ISP_IMI);
63 trb->ctrl |= DWC3_TRB_CTRL_CHN;
65 trb->ctrl |= (DWC3_TRB_CTRL_IOC
68 trace_dwc3_prepare_trb(dep, trb);
71 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
73 struct dwc3_gadget_ep_cmd_params params;
77 if (dep->flags & DWC3_EP_BUSY)
82 memset(¶ms, 0, sizeof(params));
83 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
84 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
86 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
90 dep->flags |= DWC3_EP_BUSY;
91 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
92 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
97 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
98 struct dwc3_request *req)
100 struct dwc3 *dwc = dep->dwc;
102 req->request.actual = 0;
103 req->request.status = -EINPROGRESS;
104 req->epnum = dep->number;
106 list_add_tail(&req->list, &dep->pending_list);
109 * Gadget driver might not be quick enough to queue a request
110 * before we get a Transfer Not Ready event on this endpoint.
112 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
113 * flag is set, it's telling us that as soon as Gadget queues the
114 * required request, we should kick the transfer here because the
115 * IRQ we were waiting for is long gone.
117 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
120 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
122 if (dwc->ep0state != EP0_DATA_PHASE) {
123 dev_WARN(dwc->dev, "Unexpected pending request\n");
127 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
129 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
136 * In case gadget driver asked us to delay the STATUS phase,
139 if (dwc->delayed_status) {
142 direction = !dwc->ep0_expect_in;
143 dwc->delayed_status = false;
144 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
146 if (dwc->ep0state == EP0_STATUS_PHASE)
147 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
153 * Unfortunately we have uncovered a limitation wrt the Data Phase.
155 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
156 * come before issueing Start Transfer command, but if we do, we will
157 * miss situations where the host starts another SETUP phase instead of
158 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
159 * Layer Compliance Suite.
161 * The problem surfaces due to the fact that in case of back-to-back
162 * SETUP packets there will be no XferNotReady(DATA) generated and we
163 * will be stuck waiting for XferNotReady(DATA) forever.
165 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
166 * it tells us to start Data Phase right away. It also mentions that if
167 * we receive a SETUP phase instead of the DATA phase, core will issue
168 * XferComplete for the DATA phase, before actually initiating it in
169 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
170 * can only be used to print some debugging logs, as the core expects
171 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
172 * just so it completes right away, without transferring anything and,
173 * only then, we can go back to the SETUP phase.
175 * Because of this scenario, SNPS decided to change the programming
176 * model of control transfers and support on-demand transfers only for
177 * the STATUS phase. To fix the issue we have now, we will always wait
178 * for gadget driver to queue the DATA phase's struct usb_request, then
179 * start it right away.
181 * If we're actually in a 2-stage transfer, we will wait for
182 * XferNotReady(STATUS).
184 if (dwc->three_stage_setup) {
187 direction = dwc->ep0_expect_in;
188 dwc->ep0state = EP0_DATA_PHASE;
190 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
192 dep->flags &= ~DWC3_EP0_DIR_IN;
198 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
201 struct dwc3_request *req = to_dwc3_request(request);
202 struct dwc3_ep *dep = to_dwc3_ep(ep);
203 struct dwc3 *dwc = dep->dwc;
209 spin_lock_irqsave(&dwc->lock, flags);
210 if (!dep->endpoint.desc) {
211 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
217 /* we share one TRB for ep0/1 */
218 if (!list_empty(&dep->pending_list)) {
223 ret = __dwc3_gadget_ep0_queue(dep, req);
226 spin_unlock_irqrestore(&dwc->lock, flags);
231 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
235 /* reinitialize physical ep1 */
237 dep->flags = DWC3_EP_ENABLED;
239 /* stall is always issued on EP0 */
241 __dwc3_gadget_ep_set_halt(dep, 1, false);
242 dep->flags = DWC3_EP_ENABLED;
243 dwc->delayed_status = false;
245 if (!list_empty(&dep->pending_list)) {
246 struct dwc3_request *req;
248 req = next_request(&dep->pending_list);
249 dwc3_gadget_giveback(dep, req, -ECONNRESET);
252 dwc->ep0state = EP0_SETUP_PHASE;
253 dwc3_ep0_out_start(dwc);
256 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
258 struct dwc3_ep *dep = to_dwc3_ep(ep);
259 struct dwc3 *dwc = dep->dwc;
261 dwc3_ep0_stall_and_restart(dwc);
266 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
268 struct dwc3_ep *dep = to_dwc3_ep(ep);
269 struct dwc3 *dwc = dep->dwc;
273 spin_lock_irqsave(&dwc->lock, flags);
274 ret = __dwc3_gadget_ep0_set_halt(ep, value);
275 spin_unlock_irqrestore(&dwc->lock, flags);
280 void dwc3_ep0_out_start(struct dwc3 *dwc)
285 complete(&dwc->ep0_in_setup);
288 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
289 DWC3_TRBCTL_CONTROL_SETUP, false);
290 ret = dwc3_ep0_start_trans(dep);
294 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
297 u32 windex = le16_to_cpu(wIndex_le);
300 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
301 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
304 dep = dwc->eps[epnum];
305 if (dep->flags & DWC3_EP_ENABLED)
311 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
317 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
318 struct usb_ctrlrequest *ctrl)
325 __le16 *response_pkt;
327 /* We don't support PTM_STATUS */
328 value = le16_to_cpu(ctrl->wValue);
332 recip = ctrl->bRequestType & USB_RECIP_MASK;
334 case USB_RECIP_DEVICE:
336 * LTM will be set once we know how to set this in HW.
338 usb_status |= dwc->gadget.is_selfpowered;
340 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
341 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
342 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
343 if (reg & DWC3_DCTL_INITU1ENA)
344 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
345 if (reg & DWC3_DCTL_INITU2ENA)
346 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
351 case USB_RECIP_INTERFACE:
353 * Function Remote Wake Capable D0
354 * Function Remote Wakeup D1
358 case USB_RECIP_ENDPOINT:
359 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
363 if (dep->flags & DWC3_EP_STALL)
364 usb_status = 1 << USB_ENDPOINT_HALT;
370 response_pkt = (__le16 *) dwc->setup_buf;
371 *response_pkt = cpu_to_le16(usb_status);
374 dwc->ep0_usb_req.dep = dep;
375 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
376 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
377 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
379 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
382 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
387 if (state != USB_STATE_CONFIGURED)
389 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
390 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
393 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
395 reg |= DWC3_DCTL_INITU1ENA;
397 reg &= ~DWC3_DCTL_INITU1ENA;
398 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
403 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
409 if (state != USB_STATE_CONFIGURED)
411 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
412 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
417 reg |= DWC3_DCTL_INITU2ENA;
419 reg &= ~DWC3_DCTL_INITU2ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
425 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
428 if ((wIndex & 0xff) != 0)
433 switch (wIndex >> 8) {
439 dwc->test_mode_nr = wIndex >> 8;
440 dwc->test_mode = true;
449 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
450 struct usb_ctrlrequest *ctrl, int set)
452 enum usb_device_state state;
457 wValue = le16_to_cpu(ctrl->wValue);
458 wIndex = le16_to_cpu(ctrl->wIndex);
459 state = dwc->gadget.state;
462 case USB_DEVICE_REMOTE_WAKEUP:
465 * 9.4.1 says only only for SS, in AddressState only for
466 * default control pipe
468 case USB_DEVICE_U1_ENABLE:
469 ret = dwc3_ep0_handle_u1(dwc, state, set);
471 case USB_DEVICE_U2_ENABLE:
472 ret = dwc3_ep0_handle_u2(dwc, state, set);
474 case USB_DEVICE_LTM_ENABLE:
477 case USB_DEVICE_TEST_MODE:
478 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
487 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
488 struct usb_ctrlrequest *ctrl, int set)
490 enum usb_device_state state;
495 wValue = le16_to_cpu(ctrl->wValue);
496 wIndex = le16_to_cpu(ctrl->wIndex);
497 state = dwc->gadget.state;
500 case USB_INTRF_FUNC_SUSPEND:
502 * REVISIT: Ideally we would enable some low power mode here,
503 * however it's unclear what we should be doing here.
505 * For now, we're not doing anything, just making sure we return
506 * 0 so USB Command Verifier tests pass without any errors.
516 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
517 struct usb_ctrlrequest *ctrl, int set)
520 enum usb_device_state state;
525 wValue = le16_to_cpu(ctrl->wValue);
526 wIndex = le16_to_cpu(ctrl->wIndex);
527 state = dwc->gadget.state;
530 case USB_ENDPOINT_HALT:
531 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
535 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
538 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
549 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
550 struct usb_ctrlrequest *ctrl, int set)
554 enum usb_device_state state;
556 recip = ctrl->bRequestType & USB_RECIP_MASK;
557 state = dwc->gadget.state;
560 case USB_RECIP_DEVICE:
561 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
563 case USB_RECIP_INTERFACE:
564 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
566 case USB_RECIP_ENDPOINT:
567 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
576 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
578 enum usb_device_state state = dwc->gadget.state;
582 addr = le16_to_cpu(ctrl->wValue);
584 dev_err(dwc->dev, "invalid device address %d\n", addr);
588 if (state == USB_STATE_CONFIGURED) {
589 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
593 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
594 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
595 reg |= DWC3_DCFG_DEVADDR(addr);
596 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
599 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
601 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
606 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
610 spin_unlock(&dwc->lock);
611 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
612 spin_lock(&dwc->lock);
616 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
618 enum usb_device_state state = dwc->gadget.state;
623 cfg = le16_to_cpu(ctrl->wValue);
626 case USB_STATE_DEFAULT:
629 case USB_STATE_ADDRESS:
630 ret = dwc3_ep0_delegate_req(dwc, ctrl);
631 /* if the cfg matches and the cfg is non zero */
632 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
635 * only change state if set_config has already
636 * been processed. If gadget driver returns
637 * USB_GADGET_DELAYED_STATUS, we will wait
638 * to change the state on the next usb_ep_queue()
641 usb_gadget_set_state(&dwc->gadget,
642 USB_STATE_CONFIGURED);
645 * Enable transition to U1/U2 state when
646 * nothing is pending from application.
648 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
649 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
650 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
654 case USB_STATE_CONFIGURED:
655 ret = dwc3_ep0_delegate_req(dwc, ctrl);
657 usb_gadget_set_state(&dwc->gadget,
666 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
668 struct dwc3_ep *dep = to_dwc3_ep(ep);
669 struct dwc3 *dwc = dep->dwc;
683 memcpy(&timing, req->buf, sizeof(timing));
685 dwc->u1sel = timing.u1sel;
686 dwc->u1pel = timing.u1pel;
687 dwc->u2sel = le16_to_cpu(timing.u2sel);
688 dwc->u2pel = le16_to_cpu(timing.u2pel);
690 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
691 if (reg & DWC3_DCTL_INITU2ENA)
693 if (reg & DWC3_DCTL_INITU1ENA)
697 * According to Synopsys Databook, if parameter is
698 * greater than 125, a value of zero should be
699 * programmed in the register.
704 /* now that we have the time, issue DGCMD Set Sel */
705 ret = dwc3_send_gadget_generic_command(dwc,
706 DWC3_DGCMD_SET_PERIODIC_PAR, param);
710 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
713 enum usb_device_state state = dwc->gadget.state;
717 if (state == USB_STATE_DEFAULT)
720 wValue = le16_to_cpu(ctrl->wValue);
721 wLength = le16_to_cpu(ctrl->wLength);
724 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
730 * To handle Set SEL we need to receive 6 bytes from Host. So let's
731 * queue a usb_request for 6 bytes.
733 * Remember, though, this controller can't handle non-wMaxPacketSize
734 * aligned transfers on the OUT direction, so we queue a request for
735 * wMaxPacketSize instead.
738 dwc->ep0_usb_req.dep = dep;
739 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
740 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
741 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
743 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
746 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
752 wValue = le16_to_cpu(ctrl->wValue);
753 wLength = le16_to_cpu(ctrl->wLength);
754 wIndex = le16_to_cpu(ctrl->wIndex);
756 if (wIndex || wLength)
760 * REVISIT It's unclear from Databook what to do with this
761 * value. For now, just cache it.
763 dwc->isoch_delay = wValue;
768 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
772 switch (ctrl->bRequest) {
773 case USB_REQ_GET_STATUS:
774 ret = dwc3_ep0_handle_status(dwc, ctrl);
776 case USB_REQ_CLEAR_FEATURE:
777 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
779 case USB_REQ_SET_FEATURE:
780 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
782 case USB_REQ_SET_ADDRESS:
783 ret = dwc3_ep0_set_address(dwc, ctrl);
785 case USB_REQ_SET_CONFIGURATION:
786 ret = dwc3_ep0_set_config(dwc, ctrl);
788 case USB_REQ_SET_SEL:
789 ret = dwc3_ep0_set_sel(dwc, ctrl);
791 case USB_REQ_SET_ISOCH_DELAY:
792 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
795 ret = dwc3_ep0_delegate_req(dwc, ctrl);
802 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
803 const struct dwc3_event_depevt *event)
805 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
809 if (!dwc->gadget_driver)
812 trace_dwc3_ctrl_req(ctrl);
814 len = le16_to_cpu(ctrl->wLength);
816 dwc->three_stage_setup = false;
817 dwc->ep0_expect_in = false;
818 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
820 dwc->three_stage_setup = true;
821 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
822 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
825 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
826 ret = dwc3_ep0_std_request(dwc, ctrl);
828 ret = dwc3_ep0_delegate_req(dwc, ctrl);
830 if (ret == USB_GADGET_DELAYED_STATUS)
831 dwc->delayed_status = true;
835 dwc3_ep0_stall_and_restart(dwc);
838 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
839 const struct dwc3_event_depevt *event)
841 struct dwc3_request *r = NULL;
842 struct usb_request *ur;
843 struct dwc3_trb *trb;
846 unsigned remaining_ur_length;
853 epnum = event->endpoint_number;
856 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
858 trace_dwc3_complete_trb(ep0, trb);
860 r = next_request(&ep0->pending_list);
864 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
865 if (status == DWC3_TRBSTS_SETUP_PENDING) {
866 dwc->setup_packet_pending = true;
868 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
875 remaining_ur_length = ur->length;
877 length = trb->size & DWC3_TRB_SIZE_MASK;
878 maxp = ep0->endpoint.maxpacket;
879 transferred = ur->length - length;
880 ur->actual += transferred;
882 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
883 ur->length && ur->zero) || dwc->ep0_bounced) {
885 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
886 trace_dwc3_complete_trb(ep0, trb);
887 ep0->trb_enqueue = 0;
888 dwc->ep0_bounced = false;
891 if ((epnum & 1) && ur->actual < ur->length)
892 dwc3_ep0_stall_and_restart(dwc);
894 dwc3_gadget_giveback(ep0, r, 0);
897 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
898 const struct dwc3_event_depevt *event)
900 struct dwc3_request *r;
902 struct dwc3_trb *trb;
908 trace_dwc3_complete_trb(dep, trb);
910 if (!list_empty(&dep->pending_list)) {
911 r = next_request(&dep->pending_list);
913 dwc3_gadget_giveback(dep, r, 0);
916 if (dwc->test_mode) {
919 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
921 dev_err(dwc->dev, "invalid test #%d\n",
923 dwc3_ep0_stall_and_restart(dwc);
928 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
929 if (status == DWC3_TRBSTS_SETUP_PENDING)
930 dwc->setup_packet_pending = true;
932 dwc->ep0state = EP0_SETUP_PHASE;
933 dwc3_ep0_out_start(dwc);
936 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
937 const struct dwc3_event_depevt *event)
939 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
941 dep->flags &= ~DWC3_EP_BUSY;
942 dep->resource_index = 0;
943 dwc->setup_packet_pending = false;
945 switch (dwc->ep0state) {
946 case EP0_SETUP_PHASE:
947 dwc3_ep0_inspect_setup(dwc, event);
951 dwc3_ep0_complete_data(dwc, event);
954 case EP0_STATUS_PHASE:
955 dwc3_ep0_complete_status(dwc, event);
958 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
962 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
963 struct dwc3_ep *dep, struct dwc3_request *req)
967 req->direction = !!dep->number;
969 if (req->request.length == 0) {
970 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
971 DWC3_TRBCTL_CONTROL_DATA, false);
972 ret = dwc3_ep0_start_trans(dep);
973 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
974 && (dep->number == 0)) {
978 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
979 &req->request, dep->number);
983 maxpacket = dep->endpoint.maxpacket;
984 rem = req->request.length % maxpacket;
985 dwc->ep0_bounced = true;
987 /* prepare normal TRB */
988 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
990 DWC3_TRBCTL_CONTROL_DATA,
993 /* Now prepare one extra TRB to align transfer size */
994 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
996 DWC3_TRBCTL_CONTROL_DATA,
998 ret = dwc3_ep0_start_trans(dep);
999 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1000 req->request.length && req->request.zero) {
1004 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1005 &req->request, dep->number);
1009 maxpacket = dep->endpoint.maxpacket;
1010 rem = req->request.length % maxpacket;
1012 /* prepare normal TRB */
1013 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1014 req->request.length,
1015 DWC3_TRBCTL_CONTROL_DATA,
1018 /* Now prepare one extra TRB to align transfer size */
1019 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1020 0, DWC3_TRBCTL_CONTROL_DATA,
1022 ret = dwc3_ep0_start_trans(dep);
1024 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1025 &req->request, dep->number);
1029 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1030 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1032 ret = dwc3_ep0_start_trans(dep);
1038 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1040 struct dwc3 *dwc = dep->dwc;
1043 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1044 : DWC3_TRBCTL_CONTROL_STATUS2;
1046 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1047 return dwc3_ep0_start_trans(dep);
1050 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1052 WARN_ON(dwc3_ep0_start_control_status(dep));
1055 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1056 const struct dwc3_event_depevt *event)
1058 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1060 __dwc3_ep0_do_control_status(dwc, dep);
1063 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1065 struct dwc3_gadget_ep_cmd_params params;
1069 if (!dep->resource_index)
1072 cmd = DWC3_DEPCMD_ENDTRANSFER;
1073 cmd |= DWC3_DEPCMD_CMDIOC;
1074 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1075 memset(¶ms, 0, sizeof(params));
1076 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1078 dep->resource_index = 0;
1081 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1082 const struct dwc3_event_depevt *event)
1084 switch (event->status) {
1085 case DEPEVT_STATUS_CONTROL_DATA:
1087 * We already have a DATA transfer in the controller's cache,
1088 * if we receive a XferNotReady(DATA) we will ignore it, unless
1089 * it's for the wrong direction.
1091 * In that case, we must issue END_TRANSFER command to the Data
1092 * Phase we already have started and issue SetStall on the
1095 if (dwc->ep0_expect_in != event->endpoint_number) {
1096 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1098 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1099 dwc3_ep0_end_control_data(dwc, dep);
1100 dwc3_ep0_stall_and_restart(dwc);
1106 case DEPEVT_STATUS_CONTROL_STATUS:
1107 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1110 dwc->ep0state = EP0_STATUS_PHASE;
1112 if (dwc->delayed_status) {
1113 struct dwc3_ep *dep = dwc->eps[0];
1115 WARN_ON_ONCE(event->endpoint_number != 1);
1117 * We should handle the delay STATUS phase here if the
1118 * request for handling delay STATUS has been queued
1121 if (!list_empty(&dep->pending_list)) {
1122 dwc->delayed_status = false;
1123 usb_gadget_set_state(&dwc->gadget,
1124 USB_STATE_CONFIGURED);
1125 dwc3_ep0_do_control_status(dwc, event);
1131 dwc3_ep0_do_control_status(dwc, event);
1135 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1136 const struct dwc3_event_depevt *event)
1138 switch (event->endpoint_event) {
1139 case DWC3_DEPEVT_XFERCOMPLETE:
1140 dwc3_ep0_xfer_complete(dwc, event);
1143 case DWC3_DEPEVT_XFERNOTREADY:
1144 dwc3_ep0_xfernotready(dwc, event);
1147 case DWC3_DEPEVT_XFERINPROGRESS:
1148 case DWC3_DEPEVT_RXTXFIFOEVT:
1149 case DWC3_DEPEVT_STREAMEVT:
1150 case DWC3_DEPEVT_EPCMDCMPLT: