drivers/usb/dwc3/dwc3-xilinx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
   4  *
   5  * Authors: Manish Narani <manish.narani@xilinx.com>
   6  *          Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/reset.h>
  19 #include <linux/of_address.h>
  20 #include <linux/delay.h>
  21 #include <linux/firmware/xlnx-zynqmp.h>
  22 #include <linux/io.h>
  23
  24 #include <linux/phy/phy.h>
  25
  26 /* USB phy reset mask register */
  27 #define XLNX_USB_PHY_RST_EN                     0x001C
  28 #define XLNX_PHY_RST_MASK                       0x1
  29
  30 /* Xilinx USB 3.0 IP Register */
  31 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG           0x005C
  32 #define XLNX_USB_TRAFFIC_ROUTE_FPD              0x1
  33
  34 /* Versal USB Reset ID */
  35 #define VERSAL_USB_RESET_ID                     0xC104036
  36
  37 #define XLNX_USB_FPD_PIPE_CLK                   0x7c
  38 #define PIPE_CLK_DESELECT                       1
  39 #define PIPE_CLK_SELECT                         0
  40 #define XLNX_USB_FPD_POWER_PRSNT                0x80
  41 #define FPD_POWER_PRSNT_OPTION                  BIT(0)
  42
  43 struct dwc3_xlnx {
  44         int                             num_clocks;
  45         struct clk_bulk_data            *clks;
  46         struct device                   *dev;
  47         void __iomem                    *regs;
  48         int                             (*pltfm_init)(struct dwc3_xlnx *data);
  49 };
  50
  51 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
  52 {
  53         u32 reg;
  54
  55         /*
  56          * Enable or disable ULPI PHY reset from USB Controller.
  57          * This does not actually reset the phy, but just controls
  58          * whether USB controller can or cannot reset ULPI PHY.
  59          */
  60         reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
  61
  62         if (mask)
  63                 reg &= ~XLNX_PHY_RST_MASK;
  64         else
  65                 reg |= XLNX_PHY_RST_MASK;
  66
  67         writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
  68 }
  69
  70 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
  71 {
  72         struct device           *dev = priv_data->dev;
  73         int                     ret;
  74
  75         dwc3_xlnx_mask_phy_rst(priv_data, false);
  76
  77         /* Assert and De-assert reset */
  78         ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
  79                                      PM_RESET_ACTION_ASSERT);
  80         if (ret < 0) {
  81                 dev_err_probe(dev, ret, "failed to assert Reset\n");
  82                 return ret;
  83         }
  84
  85         ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
  86                                      PM_RESET_ACTION_RELEASE);
  87         if (ret < 0) {
  88                 dev_err_probe(dev, ret, "failed to De-assert Reset\n");
  89                 return ret;
  90         }
  91
  92         dwc3_xlnx_mask_phy_rst(priv_data, true);
  93
  94         return 0;
  95 }
  96
  97 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
  98 {
  99         struct device           *dev = priv_data->dev;
 100         struct reset_control    *crst, *hibrst, *apbrst;
 101         struct phy              *usb3_phy;
 102         int                     ret = 0;
 103         u32                     reg;
 104
 105         usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
 106         if (IS_ERR(usb3_phy)) {
 107                 ret = PTR_ERR(usb3_phy);
 108                 dev_err_probe(dev, ret,
 109                               "failed to get USB3 PHY\n");
 110                 goto err;
 111         }
 112
 113         /*
 114          * The following core resets are not required unless a USB3 PHY
 115          * is used, and the subsequent register settings are not required
 116          * unless a core reset is performed (they should be set properly
 117          * by the first-stage boot loader, but may be reverted by a core
 118          * reset). They may also break the configuration if USB3 is actually
 119          * in use but the usb3-phy entry is missing from the device tree.
 120          * Therefore, skip these operations in this case.
 121          */
 122         if (!usb3_phy)
 123                 goto skip_usb3_phy;
 124
 125         crst = devm_reset_control_get_exclusive(dev, "usb_crst");
 126         if (IS_ERR(crst)) {
 127                 ret = PTR_ERR(crst);
 128                 dev_err_probe(dev, ret,
 129                               "failed to get core reset signal\n");
 130                 goto err;
 131         }
 132
 133         hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
 134         if (IS_ERR(hibrst)) {
 135                 ret = PTR_ERR(hibrst);
 136                 dev_err_probe(dev, ret,
 137                               "failed to get hibernation reset signal\n");
 138                 goto err;
 139         }
 140
 141         apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
 142         if (IS_ERR(apbrst)) {
 143                 ret = PTR_ERR(apbrst);
 144                 dev_err_probe(dev, ret,
 145                               "failed to get APB reset signal\n");
 146                 goto err;
 147         }
 148
 149         ret = reset_control_assert(crst);
 150         if (ret < 0) {
 151                 dev_err(dev, "Failed to assert core reset\n");
 152                 goto err;
 153         }
 154
 155         ret = reset_control_assert(hibrst);
 156         if (ret < 0) {
 157                 dev_err(dev, "Failed to assert hibernation reset\n");
 158                 goto err;
 159         }
 160
 161         ret = reset_control_assert(apbrst);
 162         if (ret < 0) {
 163                 dev_err(dev, "Failed to assert APB reset\n");
 164                 goto err;
 165         }
 166
 167         ret = phy_init(usb3_phy);
 168         if (ret < 0) {
 169                 phy_exit(usb3_phy);
 170                 goto err;
 171         }
 172
 173         ret = reset_control_deassert(apbrst);
 174         if (ret < 0) {
 175                 dev_err(dev, "Failed to release APB reset\n");
 176                 goto err;
 177         }
 178
 179         /* Set PIPE Power Present signal in FPD Power Present Register*/
 180         writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
 181
 182         /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
 183         writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
 184
 185         ret = reset_control_deassert(crst);
 186         if (ret < 0) {
 187                 dev_err(dev, "Failed to release core reset\n");
 188                 goto err;
 189         }
 190
 191         ret = reset_control_deassert(hibrst);
 192         if (ret < 0) {
 193                 dev_err(dev, "Failed to release hibernation reset\n");
 194                 goto err;
 195         }
 196
 197         ret = phy_power_on(usb3_phy);
 198         if (ret < 0) {
 199                 phy_exit(usb3_phy);
 200                 goto err;
 201         }
 202
 203 skip_usb3_phy:
 204         /*
 205          * This routes the USB DMA traffic to go through FPD path instead
 206          * of reaching DDR directly. This traffic routing is needed to
 207          * make SMMU and CCI work with USB DMA.
 208          */
 209         if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
 210                 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
 211                 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
 212                 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
 213         }
 214
 215 err:
 216         return ret;
 217 }
 218
 219 static const struct of_device_id dwc3_xlnx_of_match[] = {
 220         {
 221                 .compatible = "xlnx,zynqmp-dwc3",
 222                 .data = &dwc3_xlnx_init_zynqmp,
 223         },
 224         {
 225                 .compatible = "xlnx,versal-dwc3",
 226                 .data = &dwc3_xlnx_init_versal,
 227         },
 228         { /* Sentinel */ }
 229 };
 230 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
 231
 232 static int dwc3_xlnx_probe(struct platform_device *pdev)
 233 {
 234         struct dwc3_xlnx                *priv_data;
 235         struct device                   *dev = &pdev->dev;
 236         struct device_node              *np = dev->of_node;
 237         const struct of_device_id       *match;
 238         void __iomem                    *regs;
 239         int                             ret;
 240
 241         priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
 242         if (!priv_data)
 243                 return -ENOMEM;
 244
 245         regs = devm_platform_ioremap_resource(pdev, 0);
 246         if (IS_ERR(regs)) {
 247                 ret = PTR_ERR(regs);
 248                 dev_err_probe(dev, ret, "failed to map registers\n");
 249                 return ret;
 250         }
 251
 252         match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
 253
 254         priv_data->pltfm_init = match->data;
 255         priv_data->regs = regs;
 256         priv_data->dev = dev;
 257
 258         platform_set_drvdata(pdev, priv_data);
 259
 260         ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
 261         if (ret < 0)
 262                 return ret;
 263
 264         priv_data->num_clocks = ret;
 265
 266         ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
 267         if (ret)
 268                 return ret;
 269
 270         ret = priv_data->pltfm_init(priv_data);
 271         if (ret)
 272                 goto err_clk_put;
 273
 274         ret = of_platform_populate(np, NULL, NULL, dev);
 275         if (ret)
 276                 goto err_clk_put;
 277
 278         pm_runtime_set_active(dev);
 279         pm_runtime_enable(dev);
 280         pm_suspend_ignore_children(dev, false);
 281         pm_runtime_get_sync(dev);
 282
 283         return 0;
 284
 285 err_clk_put:
 286         clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
 287
 288         return ret;
 289 }
 290
 291 static int dwc3_xlnx_remove(struct platform_device *pdev)
 292 {
 293         struct dwc3_xlnx        *priv_data = platform_get_drvdata(pdev);
 294         struct device           *dev = &pdev->dev;
 295
 296         of_platform_depopulate(dev);
 297
 298         clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
 299         priv_data->num_clocks = 0;
 300
 301         pm_runtime_disable(dev);
 302         pm_runtime_put_noidle(dev);
 303         pm_runtime_set_suspended(dev);
 304
 305         return 0;
 306 }
 307
 308 static int __maybe_unused dwc3_xlnx_suspend_common(struct device *dev)
 309 {
 310         struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
 311
 312         clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
 313
 314         return 0;
 315 }
 316
 317 static int __maybe_unused dwc3_xlnx_resume_common(struct device *dev)
 318 {
 319         struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
 320
 321         return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
 322 }
 323
 324 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
 325 {
 326         pm_runtime_mark_last_busy(dev);
 327         pm_runtime_autosuspend(dev);
 328
 329         return 0;
 330 }
 331
 332 static UNIVERSAL_DEV_PM_OPS(dwc3_xlnx_dev_pm_ops, dwc3_xlnx_suspend_common,
 333                             dwc3_xlnx_resume_common, dwc3_xlnx_runtime_idle);
 334
 335 static struct platform_driver dwc3_xlnx_driver = {
 336         .probe          = dwc3_xlnx_probe,
 337         .remove         = dwc3_xlnx_remove,
 338         .driver         = {
 339                 .name           = "dwc3-xilinx",
 340                 .of_match_table = dwc3_xlnx_of_match,
 341                 .pm             = &dwc3_xlnx_dev_pm_ops,
 342         },
 343 };
 344
 345 module_platform_driver(dwc3_xlnx_driver);
 346
 347 MODULE_LICENSE("GPL v2");
 348 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
 349 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
 350 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");