1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Inspired by dwc3-of-simple.c
7 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb.h>
27 /* USB QSCRATCH Hardware registers */
28 #define QSCRATCH_HS_PHY_CTRL 0x10
29 #define UTMI_OTG_VBUS_VALID BIT(20)
30 #define SW_SESSVLD_SEL BIT(28)
32 #define QSCRATCH_SS_PHY_CTRL 0x30
33 #define LANE0_PWR_PRESENT BIT(24)
35 #define QSCRATCH_GENERAL_CFG 0x08
36 #define PIPE_UTMI_CLK_SEL BIT(0)
37 #define PIPE3_PHYSTATUS_SW BIT(3)
38 #define PIPE_UTMI_CLK_DIS BIT(8)
40 #define PWR_EVNT_IRQ_STAT_REG 0x58
41 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
42 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45 #define SDM845_QSCRATCH_SIZE 0x400
46 #define SDM845_DWC3_CORE_SIZE 0xcd00
48 /* Interconnect path bandwidths in MBps */
49 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
50 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
51 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
52 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
53 #define APPS_USB_AVG_BW 0
54 #define APPS_USB_PEAK_BW MBps_to_icc(40)
56 struct dwc3_acpi_pdata {
57 u32 qscratch_base_offset;
58 u32 qscratch_base_size;
59 u32 dwc3_core_base_size;
61 int dp_hs_phy_irq_index;
62 int dm_hs_phy_irq_index;
69 void __iomem *qscratch_base;
70 struct platform_device *dwc3;
71 struct platform_device *urs_usb;
74 struct reset_control *resets;
80 enum usb_device_speed usb2_speed;
82 struct extcon_dev *edev;
83 struct extcon_dev *host_edev;
84 struct notifier_block vbus_nb;
85 struct notifier_block host_nb;
87 const struct dwc3_acpi_pdata *acpi_pdata;
89 enum usb_dr_mode mode;
92 struct icc_path *icc_path_ddr;
93 struct icc_path *icc_path_apps;
96 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
100 reg = readl(base + offset);
102 writel(reg, base + offset);
104 /* ensure that above write is through */
105 readl(base + offset);
108 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
112 reg = readl(base + offset);
114 writel(reg, base + offset);
116 /* ensure that above write is through */
117 readl(base + offset);
120 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
135 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
136 unsigned long event, void *ptr)
138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
140 /* enable vbus override for device mode */
141 dwc3_qcom_vbus_override_enable(qcom, event);
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
147 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
148 unsigned long event, void *ptr)
150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
152 /* disable vbus override in host mode */
153 dwc3_qcom_vbus_override_enable(qcom, !event);
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
159 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
161 struct device *dev = qcom->dev;
162 struct extcon_dev *host_edev;
165 if (!of_property_read_bool(dev->of_node, "extcon"))
168 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
169 if (IS_ERR(qcom->edev))
170 return dev_err_probe(dev, PTR_ERR(qcom->edev),
171 "Failed to get extcon\n");
173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
176 if (IS_ERR(qcom->host_edev))
177 qcom->host_edev = NULL;
179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
182 dev_err(dev, "VBUS notifier register failed\n");
187 host_edev = qcom->host_edev;
189 host_edev = qcom->edev;
191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
195 dev_err(dev, "Host notifier register failed\n");
199 /* Update initial VBUS override based on extcon state */
200 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
201 !extcon_get_state(host_edev, EXTCON_USB_HOST))
202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
209 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
213 ret = icc_enable(qcom->icc_path_ddr);
217 ret = icc_enable(qcom->icc_path_apps);
219 icc_disable(qcom->icc_path_ddr);
224 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
228 ret = icc_disable(qcom->icc_path_ddr);
232 ret = icc_disable(qcom->icc_path_apps);
234 icc_enable(qcom->icc_path_ddr);
240 * dwc3_qcom_interconnect_init() - Get interconnect path handles
242 * @qcom: Pointer to the concerned usb core.
245 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
247 enum usb_device_speed max_speed;
248 struct device *dev = qcom->dev;
251 if (has_acpi_companion(dev))
254 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
255 if (IS_ERR(qcom->icc_path_ddr)) {
256 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr),
257 "failed to get usb-ddr path\n");
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps),
263 "failed to get apps-usb path\n");
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
272 ret = icc_set_bw(qcom->icc_path_ddr,
273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
289 icc_put(qcom->icc_path_apps);
291 icc_put(qcom->icc_path_ddr);
296 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
297 * @qcom: Pointer to the concerned usb core.
299 * This function is used to release interconnect path handle.
301 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
303 icc_put(qcom->icc_path_ddr);
304 icc_put(qcom->icc_path_apps);
307 /* Only usable in contexts where the role can not change. */
308 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
313 * FIXME: Fix this layering violation.
315 dwc = platform_get_drvdata(qcom->dwc3);
317 /* Core driver may not have probed yet. */
324 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
327 struct usb_device *udev;
328 struct usb_hcd __maybe_unused *hcd;
331 * FIXME: Fix this layering violation.
333 hcd = platform_get_drvdata(dwc->xhci);
336 * It is possible to query the speed of all children of
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
338 * currently supports only 1 port per controller. So
339 * this is sufficient.
342 udev = usb_hub_find_child(hcd->self.root_hub, 1);
347 return USB_SPEED_UNKNOWN;
352 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
358 irq_set_irq_type(irq, polarity);
361 enable_irq_wake(irq);
364 static void dwc3_qcom_disable_wakeup_irq(int irq)
369 disable_irq_wake(irq);
370 disable_irq_nosync(irq);
373 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
375 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
377 if (qcom->usb2_speed == USB_SPEED_LOW) {
378 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
379 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
380 (qcom->usb2_speed == USB_SPEED_FULL)) {
381 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
383 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
384 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
387 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
390 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
392 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
395 * Configure DP/DM line interrupts based on the USB2 device attached to
396 * the root hub port. When HS/FS device is connected, configure the DP line
397 * as falling edge to detect both disconnect and remote wakeup scenarios. When
398 * LS device is connected, configure DM line as falling edge to detect both
399 * disconnect and remote wakeup. When no device is connected, configure both
400 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
403 if (qcom->usb2_speed == USB_SPEED_LOW) {
404 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
405 IRQ_TYPE_EDGE_FALLING);
406 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
407 (qcom->usb2_speed == USB_SPEED_FULL)) {
408 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
409 IRQ_TYPE_EDGE_FALLING);
411 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
412 IRQ_TYPE_EDGE_RISING);
413 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
414 IRQ_TYPE_EDGE_RISING);
417 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
420 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
425 if (qcom->is_suspended)
428 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
429 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
430 dev_err(qcom->dev, "HS-PHY not in L2\n");
432 for (i = qcom->num_clocks - 1; i >= 0; i--)
433 clk_disable_unprepare(qcom->clks[i]);
435 ret = dwc3_qcom_interconnect_disable(qcom);
437 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
440 * The role is stable during suspend as role switching is done from a
441 * freezable workqueue.
443 if (dwc3_qcom_is_host(qcom) && wakeup) {
444 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
445 dwc3_qcom_enable_interrupts(qcom);
448 qcom->is_suspended = true;
453 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
458 if (!qcom->is_suspended)
461 if (dwc3_qcom_is_host(qcom) && wakeup)
462 dwc3_qcom_disable_interrupts(qcom);
464 for (i = 0; i < qcom->num_clocks; i++) {
465 ret = clk_prepare_enable(qcom->clks[i]);
468 clk_disable_unprepare(qcom->clks[i]);
473 ret = dwc3_qcom_interconnect_enable(qcom);
475 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
477 /* Clear existing events from PHY related to L2 in/out */
478 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
479 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
481 qcom->is_suspended = false;
486 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
488 struct dwc3_qcom *qcom = data;
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
491 /* If pm_suspended then let pm_resume take care of resuming h/w */
492 if (qcom->pm_suspended)
496 * This is safe as role switching is done from a freezable workqueue
497 * and the wakeup interrupts are disabled as part of resume.
499 if (dwc3_qcom_is_host(qcom))
500 pm_runtime_resume(&dwc->xhci->dev);
505 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
508 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
511 usleep_range(100, 1000);
513 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
514 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
516 usleep_range(100, 1000);
518 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
522 static int dwc3_qcom_get_irq(struct platform_device *pdev,
523 const char *name, int num)
525 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
526 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
527 struct device_node *np = pdev->dev.of_node;
531 ret = platform_get_irq_byname_optional(pdev_irq, name);
533 ret = platform_get_irq_optional(pdev_irq, num);
538 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
540 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
541 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
545 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
546 pdata ? pdata->hs_phy_irq_index : -1);
548 /* Keep wakeup interrupts disabled until suspend */
549 irq_set_status_flags(irq, IRQ_NOAUTOEN);
550 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
551 qcom_dwc3_resume_irq,
552 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
553 "qcom_dwc3 HS", qcom);
555 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
558 qcom->hs_phy_irq = irq;
561 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
562 pdata ? pdata->dp_hs_phy_irq_index : -1);
564 irq_set_status_flags(irq, IRQ_NOAUTOEN);
565 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
566 qcom_dwc3_resume_irq,
567 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
568 "qcom_dwc3 DP_HS", qcom);
570 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
573 qcom->dp_hs_phy_irq = irq;
576 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
577 pdata ? pdata->dm_hs_phy_irq_index : -1);
579 irq_set_status_flags(irq, IRQ_NOAUTOEN);
580 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
581 qcom_dwc3_resume_irq,
582 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
583 "qcom_dwc3 DM_HS", qcom);
585 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
588 qcom->dm_hs_phy_irq = irq;
591 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
592 pdata ? pdata->ss_phy_irq_index : -1);
594 irq_set_status_flags(irq, IRQ_NOAUTOEN);
595 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
596 qcom_dwc3_resume_irq,
597 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
598 "qcom_dwc3 SS", qcom);
600 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
603 qcom->ss_phy_irq = irq;
609 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
611 struct device *dev = qcom->dev;
612 struct device_node *np = dev->of_node;
621 qcom->num_clocks = count;
623 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
624 sizeof(struct clk *), GFP_KERNEL);
628 for (i = 0; i < qcom->num_clocks; i++) {
632 clk = of_clk_get(np, i);
635 clk_put(qcom->clks[i]);
639 ret = clk_prepare_enable(clk);
642 clk_disable_unprepare(qcom->clks[i]);
643 clk_put(qcom->clks[i]);
656 static const struct property_entry dwc3_qcom_acpi_properties[] = {
657 PROPERTY_ENTRY_STRING("dr_mode", "host"),
661 static const struct software_node dwc3_qcom_swnode = {
662 .properties = dwc3_qcom_acpi_properties,
665 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
667 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
668 struct device *dev = &pdev->dev;
669 struct resource *res, *child_res = NULL;
670 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
675 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
679 qcom->dwc3->dev.parent = dev;
680 qcom->dwc3->dev.type = dev->type;
681 qcom->dwc3->dev.dma_mask = dev->dma_mask;
682 qcom->dwc3->dev.dma_parms = dev->dma_parms;
683 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
685 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
687 platform_device_put(qcom->dwc3);
691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 dev_err(&pdev->dev, "failed to get memory resource\n");
698 child_res[0].flags = res->flags;
699 child_res[0].start = res->start;
700 child_res[0].end = child_res[0].start +
701 qcom->acpi_pdata->dwc3_core_base_size;
703 irq = platform_get_irq(pdev_irq, 0);
708 child_res[1].flags = IORESOURCE_IRQ;
709 child_res[1].start = child_res[1].end = irq;
711 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
713 dev_err(&pdev->dev, "failed to add resources\n");
717 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
719 dev_err(&pdev->dev, "failed to add properties\n");
723 ret = platform_device_add(qcom->dwc3);
725 dev_err(&pdev->dev, "failed to add device\n");
726 device_remove_software_node(&qcom->dwc3->dev);
733 platform_device_put(qcom->dwc3);
738 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
740 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
741 struct device_node *np = pdev->dev.of_node, *dwc3_np;
742 struct device *dev = &pdev->dev;
745 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
747 dev_err(dev, "failed to find dwc3 core child\n");
751 ret = of_platform_populate(np, NULL, NULL, dev);
753 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
757 qcom->dwc3 = of_find_device_by_node(dwc3_np);
760 dev_err(dev, "failed to get dwc3 platform device\n");
764 of_node_put(dwc3_np);
769 static struct platform_device *
770 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
772 struct fwnode_handle *fwh;
773 struct acpi_device *adev;
778 /* Figure out device id */
779 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
783 /* Find the child using name */
784 snprintf(name, sizeof(name), "USB%d", id);
785 fwh = fwnode_get_named_child_node(dev->fwnode, name);
789 adev = to_acpi_device_node(fwh);
793 return acpi_create_platform_device(adev, NULL);
796 static int dwc3_qcom_probe(struct platform_device *pdev)
798 struct device_node *np = pdev->dev.of_node;
799 struct device *dev = &pdev->dev;
800 struct dwc3_qcom *qcom;
801 struct resource *res, *parent_res = NULL;
802 struct resource local_res;
804 bool ignore_pipe_clk;
807 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
811 platform_set_drvdata(pdev, qcom);
812 qcom->dev = &pdev->dev;
814 if (has_acpi_companion(dev)) {
815 qcom->acpi_pdata = acpi_device_get_match_data(dev);
816 if (!qcom->acpi_pdata) {
817 dev_err(&pdev->dev, "no supporting ACPI device data\n");
822 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
823 if (IS_ERR(qcom->resets)) {
824 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
825 "failed to get resets\n");
828 ret = reset_control_assert(qcom->resets);
830 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
834 usleep_range(10, 1000);
836 ret = reset_control_deassert(qcom->resets);
838 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
842 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
844 dev_err_probe(dev, ret, "failed to get clocks\n");
848 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
853 memcpy(&local_res, res, sizeof(struct resource));
854 parent_res = &local_res;
856 parent_res->start = res->start +
857 qcom->acpi_pdata->qscratch_base_offset;
858 parent_res->end = parent_res->start +
859 qcom->acpi_pdata->qscratch_base_size;
861 if (qcom->acpi_pdata->is_urs) {
862 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
863 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
864 dev_err(dev, "failed to create URS USB platdev\n");
868 ret = PTR_ERR(qcom->urs_usb);
874 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
875 if (IS_ERR(qcom->qscratch_base)) {
876 ret = PTR_ERR(qcom->qscratch_base);
880 ret = dwc3_qcom_setup_irq(pdev);
882 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
887 * Disable pipe_clk requirement if specified. Used when dwc3
888 * operates without SSPHY and only HS/FS/LS modes are supported.
890 ignore_pipe_clk = device_property_read_bool(dev,
891 "qcom,select-utmi-as-pipe-clk");
893 dwc3_qcom_select_utmi_clk(qcom);
896 ret = dwc3_qcom_of_register_core(pdev);
898 ret = dwc3_qcom_acpi_register_core(pdev);
901 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
905 ret = dwc3_qcom_interconnect_init(qcom);
909 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
911 /* enable vbus override for device mode */
912 if (qcom->mode != USB_DR_MODE_HOST)
913 dwc3_qcom_vbus_override_enable(qcom, true);
915 /* register extcon to override sw_vbus on Vbus change later */
916 ret = dwc3_qcom_register_extcon(qcom);
918 goto interconnect_exit;
920 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
921 device_init_wakeup(&pdev->dev, wakeup_source);
922 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
924 qcom->is_suspended = false;
925 pm_runtime_set_active(dev);
926 pm_runtime_enable(dev);
927 pm_runtime_forbid(dev);
932 dwc3_qcom_interconnect_exit(qcom);
935 of_platform_depopulate(&pdev->dev);
937 platform_device_put(pdev);
939 for (i = qcom->num_clocks - 1; i >= 0; i--) {
940 clk_disable_unprepare(qcom->clks[i]);
941 clk_put(qcom->clks[i]);
944 reset_control_assert(qcom->resets);
949 static void dwc3_qcom_remove(struct platform_device *pdev)
951 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
952 struct device_node *np = pdev->dev.of_node;
953 struct device *dev = &pdev->dev;
956 device_remove_software_node(&qcom->dwc3->dev);
958 of_platform_depopulate(&pdev->dev);
960 platform_device_put(pdev);
962 for (i = qcom->num_clocks - 1; i >= 0; i--) {
963 clk_disable_unprepare(qcom->clks[i]);
964 clk_put(qcom->clks[i]);
966 qcom->num_clocks = 0;
968 dwc3_qcom_interconnect_exit(qcom);
969 reset_control_assert(qcom->resets);
971 pm_runtime_allow(dev);
972 pm_runtime_disable(dev);
975 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
977 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
978 bool wakeup = device_may_wakeup(dev);
981 ret = dwc3_qcom_suspend(qcom, wakeup);
985 qcom->pm_suspended = true;
990 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
992 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
993 bool wakeup = device_may_wakeup(dev);
996 ret = dwc3_qcom_resume(qcom, wakeup);
1000 qcom->pm_suspended = false;
1005 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
1007 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1009 return dwc3_qcom_suspend(qcom, true);
1012 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
1014 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1016 return dwc3_qcom_resume(qcom, true);
1019 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
1020 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
1021 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
1025 static const struct of_device_id dwc3_qcom_of_match[] = {
1026 { .compatible = "qcom,dwc3" },
1029 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
1032 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1033 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1034 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1035 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1036 .hs_phy_irq_index = 1,
1037 .dp_hs_phy_irq_index = 4,
1038 .dm_hs_phy_irq_index = 3,
1039 .ss_phy_irq_index = 2
1042 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1043 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1044 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1045 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1046 .hs_phy_irq_index = 1,
1047 .dp_hs_phy_irq_index = 4,
1048 .dm_hs_phy_irq_index = 3,
1049 .ss_phy_irq_index = 2,
1053 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1054 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1055 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1056 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1057 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1060 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1063 static struct platform_driver dwc3_qcom_driver = {
1064 .probe = dwc3_qcom_probe,
1065 .remove_new = dwc3_qcom_remove,
1067 .name = "dwc3-qcom",
1068 .pm = &dwc3_qcom_dev_pm_ops,
1069 .of_match_table = dwc3_qcom_of_match,
1070 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1074 module_platform_driver(dwc3_qcom_driver);
1076 MODULE_LICENSE("GPL v2");
1077 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");