1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Inspired by dwc3-of-simple.c
7 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
26 /* USB QSCRATCH Hardware registers */
27 #define QSCRATCH_HS_PHY_CTRL 0x10
28 #define UTMI_OTG_VBUS_VALID BIT(20)
29 #define SW_SESSVLD_SEL BIT(28)
31 #define QSCRATCH_SS_PHY_CTRL 0x30
32 #define LANE0_PWR_PRESENT BIT(24)
34 #define QSCRATCH_GENERAL_CFG 0x08
35 #define PIPE_UTMI_CLK_SEL BIT(0)
36 #define PIPE3_PHYSTATUS_SW BIT(3)
37 #define PIPE_UTMI_CLK_DIS BIT(8)
39 #define PWR_EVNT_IRQ_STAT_REG 0x58
40 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
41 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44 #define SDM845_QSCRATCH_SIZE 0x400
45 #define SDM845_DWC3_CORE_SIZE 0xcd00
47 /* Interconnect path bandwidths in MBps */
48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52 #define APPS_USB_AVG_BW 0
53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
55 struct dwc3_acpi_pdata {
56 u32 qscratch_base_offset;
57 u32 qscratch_base_size;
58 u32 dwc3_core_base_size;
60 int dp_hs_phy_irq_index;
61 int dm_hs_phy_irq_index;
68 void __iomem *qscratch_base;
69 struct platform_device *dwc3;
70 struct platform_device *urs_usb;
73 struct reset_control *resets;
80 struct extcon_dev *edev;
81 struct extcon_dev *host_edev;
82 struct notifier_block vbus_nb;
83 struct notifier_block host_nb;
85 const struct dwc3_acpi_pdata *acpi_pdata;
87 enum usb_dr_mode mode;
90 struct icc_path *icc_path_ddr;
91 struct icc_path *icc_path_apps;
94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
98 reg = readl(base + offset);
100 writel(reg, base + offset);
102 /* ensure that above write is through */
103 readl(base + offset);
106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
110 reg = readl(base + offset);
112 writel(reg, base + offset);
114 /* ensure that above write is through */
115 readl(base + offset);
118 static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable)
121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
134 unsigned long event, void *ptr)
136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
138 /* enable vbus override for device mode */
139 dwc3_qcom_vbus_overrride_enable(qcom, event);
140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
146 unsigned long event, void *ptr)
148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
150 /* disable vbus override in host mode */
151 dwc3_qcom_vbus_overrride_enable(qcom, !event);
152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
159 struct device *dev = qcom->dev;
160 struct extcon_dev *host_edev;
163 if (!of_property_read_bool(dev->of_node, "extcon"))
166 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
167 if (IS_ERR(qcom->edev))
168 return PTR_ERR(qcom->edev);
170 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
172 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
173 if (IS_ERR(qcom->host_edev))
174 qcom->host_edev = NULL;
176 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
179 dev_err(dev, "VBUS notifier register failed\n");
184 host_edev = qcom->host_edev;
186 host_edev = qcom->edev;
188 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
189 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
192 dev_err(dev, "Host notifier register failed\n");
196 /* Update initial VBUS override based on extcon state */
197 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
198 !extcon_get_state(host_edev, EXTCON_USB_HOST))
199 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
210 ret = icc_enable(qcom->icc_path_ddr);
214 ret = icc_enable(qcom->icc_path_apps);
216 icc_disable(qcom->icc_path_ddr);
221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
225 ret = icc_disable(qcom->icc_path_ddr);
229 ret = icc_disable(qcom->icc_path_apps);
231 icc_enable(qcom->icc_path_ddr);
237 * dwc3_qcom_interconnect_init() - Get interconnect path handles
239 * @qcom: Pointer to the concerned usb core.
242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
244 struct device *dev = qcom->dev;
247 if (has_acpi_companion(dev))
250 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
251 if (IS_ERR(qcom->icc_path_ddr)) {
252 dev_err(dev, "failed to get usb-ddr path: %ld\n",
253 PTR_ERR(qcom->icc_path_ddr));
254 return PTR_ERR(qcom->icc_path_ddr);
257 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
258 if (IS_ERR(qcom->icc_path_apps)) {
259 dev_err(dev, "failed to get apps-usb path: %ld\n",
260 PTR_ERR(qcom->icc_path_apps));
261 return PTR_ERR(qcom->icc_path_apps);
264 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
265 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
266 ret = icc_set_bw(qcom->icc_path_ddr,
267 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
273 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
277 ret = icc_set_bw(qcom->icc_path_apps,
278 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
280 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
288 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
289 * @qcom: Pointer to the concerned usb core.
291 * This function is used to release interconnect path handle.
293 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
295 icc_put(qcom->icc_path_ddr);
296 icc_put(qcom->icc_path_apps);
299 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
301 if (qcom->hs_phy_irq) {
302 disable_irq_wake(qcom->hs_phy_irq);
303 disable_irq_nosync(qcom->hs_phy_irq);
306 if (qcom->dp_hs_phy_irq) {
307 disable_irq_wake(qcom->dp_hs_phy_irq);
308 disable_irq_nosync(qcom->dp_hs_phy_irq);
311 if (qcom->dm_hs_phy_irq) {
312 disable_irq_wake(qcom->dm_hs_phy_irq);
313 disable_irq_nosync(qcom->dm_hs_phy_irq);
316 if (qcom->ss_phy_irq) {
317 disable_irq_wake(qcom->ss_phy_irq);
318 disable_irq_nosync(qcom->ss_phy_irq);
322 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
324 if (qcom->hs_phy_irq) {
325 enable_irq(qcom->hs_phy_irq);
326 enable_irq_wake(qcom->hs_phy_irq);
329 if (qcom->dp_hs_phy_irq) {
330 enable_irq(qcom->dp_hs_phy_irq);
331 enable_irq_wake(qcom->dp_hs_phy_irq);
334 if (qcom->dm_hs_phy_irq) {
335 enable_irq(qcom->dm_hs_phy_irq);
336 enable_irq_wake(qcom->dm_hs_phy_irq);
339 if (qcom->ss_phy_irq) {
340 enable_irq(qcom->ss_phy_irq);
341 enable_irq_wake(qcom->ss_phy_irq);
345 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
350 if (qcom->is_suspended)
353 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
354 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
355 dev_err(qcom->dev, "HS-PHY not in L2\n");
357 for (i = qcom->num_clocks - 1; i >= 0; i--)
358 clk_disable_unprepare(qcom->clks[i]);
360 ret = dwc3_qcom_interconnect_disable(qcom);
362 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
364 if (device_may_wakeup(qcom->dev))
365 dwc3_qcom_enable_interrupts(qcom);
367 qcom->is_suspended = true;
372 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
377 if (!qcom->is_suspended)
380 if (device_may_wakeup(qcom->dev))
381 dwc3_qcom_disable_interrupts(qcom);
383 for (i = 0; i < qcom->num_clocks; i++) {
384 ret = clk_prepare_enable(qcom->clks[i]);
387 clk_disable_unprepare(qcom->clks[i]);
392 ret = dwc3_qcom_interconnect_enable(qcom);
394 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
396 /* Clear existing events from PHY related to L2 in/out */
397 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
398 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
400 qcom->is_suspended = false;
405 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
407 struct dwc3_qcom *qcom = data;
408 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
410 /* If pm_suspended then let pm_resume take care of resuming h/w */
411 if (qcom->pm_suspended)
415 pm_runtime_resume(&dwc->xhci->dev);
420 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
422 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
423 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
426 usleep_range(100, 1000);
428 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
429 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
431 usleep_range(100, 1000);
433 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
437 static int dwc3_qcom_get_irq(struct platform_device *pdev,
438 const char *name, int num)
440 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
441 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
442 struct device_node *np = pdev->dev.of_node;
446 ret = platform_get_irq_byname(pdev_irq, name);
448 ret = platform_get_irq(pdev_irq, num);
453 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
455 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
456 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
460 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
461 pdata ? pdata->hs_phy_irq_index : -1);
463 /* Keep wakeup interrupts disabled until suspend */
464 irq_set_status_flags(irq, IRQ_NOAUTOEN);
465 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
466 qcom_dwc3_resume_irq,
467 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
468 "qcom_dwc3 HS", qcom);
470 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
473 qcom->hs_phy_irq = irq;
476 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
477 pdata ? pdata->dp_hs_phy_irq_index : -1);
479 irq_set_status_flags(irq, IRQ_NOAUTOEN);
480 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
481 qcom_dwc3_resume_irq,
482 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
483 "qcom_dwc3 DP_HS", qcom);
485 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
488 qcom->dp_hs_phy_irq = irq;
491 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
492 pdata ? pdata->dm_hs_phy_irq_index : -1);
494 irq_set_status_flags(irq, IRQ_NOAUTOEN);
495 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
496 qcom_dwc3_resume_irq,
497 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
498 "qcom_dwc3 DM_HS", qcom);
500 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
503 qcom->dm_hs_phy_irq = irq;
506 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
507 pdata ? pdata->ss_phy_irq_index : -1);
509 irq_set_status_flags(irq, IRQ_NOAUTOEN);
510 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
511 qcom_dwc3_resume_irq,
512 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
513 "qcom_dwc3 SS", qcom);
515 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
518 qcom->ss_phy_irq = irq;
524 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
526 struct device *dev = qcom->dev;
527 struct device_node *np = dev->of_node;
536 qcom->num_clocks = count;
538 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
539 sizeof(struct clk *), GFP_KERNEL);
543 for (i = 0; i < qcom->num_clocks; i++) {
547 clk = of_clk_get(np, i);
550 clk_put(qcom->clks[i]);
554 ret = clk_prepare_enable(clk);
557 clk_disable_unprepare(qcom->clks[i]);
558 clk_put(qcom->clks[i]);
571 static const struct property_entry dwc3_qcom_acpi_properties[] = {
572 PROPERTY_ENTRY_STRING("dr_mode", "host"),
576 static const struct software_node dwc3_qcom_swnode = {
577 .properties = dwc3_qcom_acpi_properties,
580 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
582 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
583 struct device *dev = &pdev->dev;
584 struct resource *res, *child_res = NULL;
585 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
590 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
594 qcom->dwc3->dev.parent = dev;
595 qcom->dwc3->dev.type = dev->type;
596 qcom->dwc3->dev.dma_mask = dev->dma_mask;
597 qcom->dwc3->dev.dma_parms = dev->dma_parms;
598 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
600 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
604 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
606 dev_err(&pdev->dev, "failed to get memory resource\n");
611 child_res[0].flags = res->flags;
612 child_res[0].start = res->start;
613 child_res[0].end = child_res[0].start +
614 qcom->acpi_pdata->dwc3_core_base_size;
616 irq = platform_get_irq(pdev_irq, 0);
617 child_res[1].flags = IORESOURCE_IRQ;
618 child_res[1].start = child_res[1].end = irq;
620 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
622 dev_err(&pdev->dev, "failed to add resources\n");
626 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
628 dev_err(&pdev->dev, "failed to add properties\n");
632 ret = platform_device_add(qcom->dwc3);
634 dev_err(&pdev->dev, "failed to add device\n");
635 device_remove_software_node(&qcom->dwc3->dev);
643 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
645 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
646 struct device_node *np = pdev->dev.of_node, *dwc3_np;
647 struct device *dev = &pdev->dev;
650 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
652 dev_err(dev, "failed to find dwc3 core child\n");
656 ret = of_platform_populate(np, NULL, NULL, dev);
658 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
662 qcom->dwc3 = of_find_device_by_node(dwc3_np);
665 dev_err(dev, "failed to get dwc3 platform device\n");
669 of_node_put(dwc3_np);
674 static struct platform_device *
675 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
677 struct fwnode_handle *fwh;
678 struct acpi_device *adev;
683 /* Figure out device id */
684 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
688 /* Find the child using name */
689 snprintf(name, sizeof(name), "USB%d", id);
690 fwh = fwnode_get_named_child_node(dev->fwnode, name);
694 adev = to_acpi_device_node(fwh);
698 return acpi_create_platform_device(adev, NULL);
701 static int dwc3_qcom_probe(struct platform_device *pdev)
703 struct device_node *np = pdev->dev.of_node;
704 struct device *dev = &pdev->dev;
705 struct dwc3_qcom *qcom;
706 struct resource *res, *parent_res = NULL;
708 bool ignore_pipe_clk;
710 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
714 platform_set_drvdata(pdev, qcom);
715 qcom->dev = &pdev->dev;
717 if (has_acpi_companion(dev)) {
718 qcom->acpi_pdata = acpi_device_get_match_data(dev);
719 if (!qcom->acpi_pdata) {
720 dev_err(&pdev->dev, "no supporting ACPI device data\n");
725 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
726 if (IS_ERR(qcom->resets)) {
727 ret = PTR_ERR(qcom->resets);
728 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
732 ret = reset_control_assert(qcom->resets);
734 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
738 usleep_range(10, 1000);
740 ret = reset_control_deassert(qcom->resets);
742 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
746 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
748 dev_err(dev, "failed to get clocks\n");
752 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
757 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
761 parent_res->start = res->start +
762 qcom->acpi_pdata->qscratch_base_offset;
763 parent_res->end = parent_res->start +
764 qcom->acpi_pdata->qscratch_base_size;
766 if (qcom->acpi_pdata->is_urs) {
767 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
768 if (!qcom->urs_usb) {
769 dev_err(dev, "failed to create URS USB platdev\n");
775 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
776 if (IS_ERR(qcom->qscratch_base)) {
777 ret = PTR_ERR(qcom->qscratch_base);
781 ret = dwc3_qcom_setup_irq(pdev);
783 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
788 * Disable pipe_clk requirement if specified. Used when dwc3
789 * operates without SSPHY and only HS/FS/LS modes are supported.
791 ignore_pipe_clk = device_property_read_bool(dev,
792 "qcom,select-utmi-as-pipe-clk");
794 dwc3_qcom_select_utmi_clk(qcom);
797 ret = dwc3_qcom_of_register_core(pdev);
799 ret = dwc3_qcom_acpi_register_core(pdev);
802 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
806 ret = dwc3_qcom_interconnect_init(qcom);
810 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
812 /* enable vbus override for device mode */
813 if (qcom->mode == USB_DR_MODE_PERIPHERAL)
814 dwc3_qcom_vbus_overrride_enable(qcom, true);
816 /* register extcon to override sw_vbus on Vbus change later */
817 ret = dwc3_qcom_register_extcon(qcom);
819 goto interconnect_exit;
821 device_init_wakeup(&pdev->dev, 1);
822 qcom->is_suspended = false;
823 pm_runtime_set_active(dev);
824 pm_runtime_enable(dev);
825 pm_runtime_forbid(dev);
830 dwc3_qcom_interconnect_exit(qcom);
833 of_platform_depopulate(&pdev->dev);
835 platform_device_put(pdev);
837 for (i = qcom->num_clocks - 1; i >= 0; i--) {
838 clk_disable_unprepare(qcom->clks[i]);
839 clk_put(qcom->clks[i]);
842 reset_control_assert(qcom->resets);
847 static int dwc3_qcom_remove(struct platform_device *pdev)
849 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
850 struct device *dev = &pdev->dev;
853 device_remove_software_node(&qcom->dwc3->dev);
854 of_platform_depopulate(dev);
856 for (i = qcom->num_clocks - 1; i >= 0; i--) {
857 clk_disable_unprepare(qcom->clks[i]);
858 clk_put(qcom->clks[i]);
860 qcom->num_clocks = 0;
862 dwc3_qcom_interconnect_exit(qcom);
863 reset_control_assert(qcom->resets);
865 pm_runtime_allow(dev);
866 pm_runtime_disable(dev);
871 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
873 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
876 ret = dwc3_qcom_suspend(qcom);
878 qcom->pm_suspended = true;
883 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
885 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
888 ret = dwc3_qcom_resume(qcom);
890 qcom->pm_suspended = false;
895 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
897 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
899 return dwc3_qcom_suspend(qcom);
902 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
904 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
906 return dwc3_qcom_resume(qcom);
909 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
910 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
911 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
915 static const struct of_device_id dwc3_qcom_of_match[] = {
916 { .compatible = "qcom,dwc3" },
917 { .compatible = "qcom,msm8996-dwc3" },
918 { .compatible = "qcom,msm8998-dwc3" },
919 { .compatible = "qcom,sdm845-dwc3" },
922 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
925 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
926 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
927 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
928 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
929 .hs_phy_irq_index = 1,
930 .dp_hs_phy_irq_index = 4,
931 .dm_hs_phy_irq_index = 3,
932 .ss_phy_irq_index = 2
935 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
936 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
937 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
938 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
939 .hs_phy_irq_index = 1,
940 .dp_hs_phy_irq_index = 4,
941 .dm_hs_phy_irq_index = 3,
942 .ss_phy_irq_index = 2,
946 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
947 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
948 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
949 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
950 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
953 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
956 static struct platform_driver dwc3_qcom_driver = {
957 .probe = dwc3_qcom_probe,
958 .remove = dwc3_qcom_remove,
961 .pm = &dwc3_qcom_dev_pm_ops,
962 .of_match_table = dwc3_qcom_of_match,
963 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
967 module_platform_driver(dwc3_qcom_driver);
969 MODULE_LICENSE("GPL v2");
970 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");