1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Inspired by dwc3-of-simple.c
7 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb.h>
27 /* USB QSCRATCH Hardware registers */
28 #define QSCRATCH_HS_PHY_CTRL 0x10
29 #define UTMI_OTG_VBUS_VALID BIT(20)
30 #define SW_SESSVLD_SEL BIT(28)
32 #define QSCRATCH_SS_PHY_CTRL 0x30
33 #define LANE0_PWR_PRESENT BIT(24)
35 #define QSCRATCH_GENERAL_CFG 0x08
36 #define PIPE_UTMI_CLK_SEL BIT(0)
37 #define PIPE3_PHYSTATUS_SW BIT(3)
38 #define PIPE_UTMI_CLK_DIS BIT(8)
40 #define PWR_EVNT_IRQ_STAT_REG 0x58
41 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
42 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45 #define SDM845_QSCRATCH_SIZE 0x400
46 #define SDM845_DWC3_CORE_SIZE 0xcd00
48 /* Interconnect path bandwidths in MBps */
49 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
50 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
51 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
52 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
53 #define APPS_USB_AVG_BW 0
54 #define APPS_USB_PEAK_BW MBps_to_icc(40)
56 struct dwc3_acpi_pdata {
57 u32 qscratch_base_offset;
58 u32 qscratch_base_size;
59 u32 dwc3_core_base_size;
61 int dp_hs_phy_irq_index;
62 int dm_hs_phy_irq_index;
69 void __iomem *qscratch_base;
70 struct platform_device *dwc3;
71 struct platform_device *urs_usb;
74 struct reset_control *resets;
80 enum usb_device_speed usb2_speed;
82 struct extcon_dev *edev;
83 struct extcon_dev *host_edev;
84 struct notifier_block vbus_nb;
85 struct notifier_block host_nb;
87 const struct dwc3_acpi_pdata *acpi_pdata;
89 enum usb_dr_mode mode;
92 struct icc_path *icc_path_ddr;
93 struct icc_path *icc_path_apps;
96 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
100 reg = readl(base + offset);
102 writel(reg, base + offset);
104 /* ensure that above write is through */
105 readl(base + offset);
108 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
112 reg = readl(base + offset);
114 writel(reg, base + offset);
116 /* ensure that above write is through */
117 readl(base + offset);
120 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
135 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
136 unsigned long event, void *ptr)
138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
140 /* enable vbus override for device mode */
141 dwc3_qcom_vbus_override_enable(qcom, event);
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
147 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
148 unsigned long event, void *ptr)
150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
152 /* disable vbus override in host mode */
153 dwc3_qcom_vbus_override_enable(qcom, !event);
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
159 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
161 struct device *dev = qcom->dev;
162 struct extcon_dev *host_edev;
165 if (!of_property_read_bool(dev->of_node, "extcon"))
168 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
169 if (IS_ERR(qcom->edev))
170 return PTR_ERR(qcom->edev);
172 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
174 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
175 if (IS_ERR(qcom->host_edev))
176 qcom->host_edev = NULL;
178 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
181 dev_err(dev, "VBUS notifier register failed\n");
186 host_edev = qcom->host_edev;
188 host_edev = qcom->edev;
190 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
191 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
194 dev_err(dev, "Host notifier register failed\n");
198 /* Update initial VBUS override based on extcon state */
199 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
200 !extcon_get_state(host_edev, EXTCON_USB_HOST))
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
203 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
208 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
212 ret = icc_enable(qcom->icc_path_ddr);
216 ret = icc_enable(qcom->icc_path_apps);
218 icc_disable(qcom->icc_path_ddr);
223 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
227 ret = icc_disable(qcom->icc_path_ddr);
231 ret = icc_disable(qcom->icc_path_apps);
233 icc_enable(qcom->icc_path_ddr);
239 * dwc3_qcom_interconnect_init() - Get interconnect path handles
241 * @qcom: Pointer to the concerned usb core.
244 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
246 enum usb_device_speed max_speed;
247 struct device *dev = qcom->dev;
250 if (has_acpi_companion(dev))
253 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
254 if (IS_ERR(qcom->icc_path_ddr)) {
255 dev_err(dev, "failed to get usb-ddr path: %ld\n",
256 PTR_ERR(qcom->icc_path_ddr));
257 return PTR_ERR(qcom->icc_path_ddr);
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 dev_err(dev, "failed to get apps-usb path: %ld\n",
263 PTR_ERR(qcom->icc_path_apps));
264 ret = PTR_ERR(qcom->icc_path_apps);
268 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
269 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
270 ret = icc_set_bw(qcom->icc_path_ddr,
271 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
273 ret = icc_set_bw(qcom->icc_path_ddr,
274 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
277 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
281 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
283 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
290 icc_put(qcom->icc_path_apps);
292 icc_put(qcom->icc_path_ddr);
297 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
298 * @qcom: Pointer to the concerned usb core.
300 * This function is used to release interconnect path handle.
302 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
304 icc_put(qcom->icc_path_ddr);
305 icc_put(qcom->icc_path_apps);
308 /* Only usable in contexts where the role can not change. */
309 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
314 * FIXME: Fix this layering violation.
316 dwc = platform_get_drvdata(qcom->dwc3);
318 /* Core driver may not have probed yet. */
325 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
327 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
328 struct usb_device *udev;
329 struct usb_hcd __maybe_unused *hcd;
332 * FIXME: Fix this layering violation.
334 hcd = platform_get_drvdata(dwc->xhci);
337 * It is possible to query the speed of all children of
338 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
339 * currently supports only 1 port per controller. So
340 * this is sufficient.
343 udev = usb_hub_find_child(hcd->self.root_hub, 1);
348 return USB_SPEED_UNKNOWN;
353 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
359 irq_set_irq_type(irq, polarity);
362 enable_irq_wake(irq);
365 static void dwc3_qcom_disable_wakeup_irq(int irq)
370 disable_irq_wake(irq);
371 disable_irq_nosync(irq);
374 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
376 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
378 if (qcom->usb2_speed == USB_SPEED_LOW) {
379 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
380 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
381 (qcom->usb2_speed == USB_SPEED_FULL)) {
382 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
384 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
385 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
388 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
391 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
393 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
396 * Configure DP/DM line interrupts based on the USB2 device attached to
397 * the root hub port. When HS/FS device is connected, configure the DP line
398 * as falling edge to detect both disconnect and remote wakeup scenarios. When
399 * LS device is connected, configure DM line as falling edge to detect both
400 * disconnect and remote wakeup. When no device is connected, configure both
401 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
404 if (qcom->usb2_speed == USB_SPEED_LOW) {
405 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
406 IRQ_TYPE_EDGE_FALLING);
407 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
408 (qcom->usb2_speed == USB_SPEED_FULL)) {
409 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
410 IRQ_TYPE_EDGE_FALLING);
412 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
413 IRQ_TYPE_EDGE_RISING);
414 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
415 IRQ_TYPE_EDGE_RISING);
418 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
421 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
426 if (qcom->is_suspended)
429 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
430 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
431 dev_err(qcom->dev, "HS-PHY not in L2\n");
433 for (i = qcom->num_clocks - 1; i >= 0; i--)
434 clk_disable_unprepare(qcom->clks[i]);
436 ret = dwc3_qcom_interconnect_disable(qcom);
438 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
441 * The role is stable during suspend as role switching is done from a
442 * freezable workqueue.
444 if (dwc3_qcom_is_host(qcom) && wakeup) {
445 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
446 dwc3_qcom_enable_interrupts(qcom);
449 qcom->is_suspended = true;
454 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
459 if (!qcom->is_suspended)
462 if (dwc3_qcom_is_host(qcom) && wakeup)
463 dwc3_qcom_disable_interrupts(qcom);
465 for (i = 0; i < qcom->num_clocks; i++) {
466 ret = clk_prepare_enable(qcom->clks[i]);
469 clk_disable_unprepare(qcom->clks[i]);
474 ret = dwc3_qcom_interconnect_enable(qcom);
476 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
478 /* Clear existing events from PHY related to L2 in/out */
479 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
480 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
482 qcom->is_suspended = false;
487 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
489 struct dwc3_qcom *qcom = data;
490 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
492 /* If pm_suspended then let pm_resume take care of resuming h/w */
493 if (qcom->pm_suspended)
497 * This is safe as role switching is done from a freezable workqueue
498 * and the wakeup interrupts are disabled as part of resume.
500 if (dwc3_qcom_is_host(qcom))
501 pm_runtime_resume(&dwc->xhci->dev);
506 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
508 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
509 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
512 usleep_range(100, 1000);
514 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
515 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
517 usleep_range(100, 1000);
519 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
523 static int dwc3_qcom_get_irq(struct platform_device *pdev,
524 const char *name, int num)
526 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
527 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
528 struct device_node *np = pdev->dev.of_node;
532 ret = platform_get_irq_byname_optional(pdev_irq, name);
534 ret = platform_get_irq_optional(pdev_irq, num);
539 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
541 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
542 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
546 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
547 pdata ? pdata->hs_phy_irq_index : -1);
549 /* Keep wakeup interrupts disabled until suspend */
550 irq_set_status_flags(irq, IRQ_NOAUTOEN);
551 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
552 qcom_dwc3_resume_irq,
553 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
554 "qcom_dwc3 HS", qcom);
556 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
559 qcom->hs_phy_irq = irq;
562 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
563 pdata ? pdata->dp_hs_phy_irq_index : -1);
565 irq_set_status_flags(irq, IRQ_NOAUTOEN);
566 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
567 qcom_dwc3_resume_irq,
568 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
569 "qcom_dwc3 DP_HS", qcom);
571 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
574 qcom->dp_hs_phy_irq = irq;
577 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
578 pdata ? pdata->dm_hs_phy_irq_index : -1);
580 irq_set_status_flags(irq, IRQ_NOAUTOEN);
581 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
582 qcom_dwc3_resume_irq,
583 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
584 "qcom_dwc3 DM_HS", qcom);
586 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
589 qcom->dm_hs_phy_irq = irq;
592 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
593 pdata ? pdata->ss_phy_irq_index : -1);
595 irq_set_status_flags(irq, IRQ_NOAUTOEN);
596 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
597 qcom_dwc3_resume_irq,
598 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
599 "qcom_dwc3 SS", qcom);
601 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
604 qcom->ss_phy_irq = irq;
610 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
612 struct device *dev = qcom->dev;
613 struct device_node *np = dev->of_node;
622 qcom->num_clocks = count;
624 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
625 sizeof(struct clk *), GFP_KERNEL);
629 for (i = 0; i < qcom->num_clocks; i++) {
633 clk = of_clk_get(np, i);
636 clk_put(qcom->clks[i]);
640 ret = clk_prepare_enable(clk);
643 clk_disable_unprepare(qcom->clks[i]);
644 clk_put(qcom->clks[i]);
657 static const struct property_entry dwc3_qcom_acpi_properties[] = {
658 PROPERTY_ENTRY_STRING("dr_mode", "host"),
662 static const struct software_node dwc3_qcom_swnode = {
663 .properties = dwc3_qcom_acpi_properties,
666 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
668 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
669 struct device *dev = &pdev->dev;
670 struct resource *res, *child_res = NULL;
671 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
676 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
680 qcom->dwc3->dev.parent = dev;
681 qcom->dwc3->dev.type = dev->type;
682 qcom->dwc3->dev.dma_mask = dev->dma_mask;
683 qcom->dwc3->dev.dma_parms = dev->dma_parms;
684 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
686 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
688 platform_device_put(qcom->dwc3);
692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
694 dev_err(&pdev->dev, "failed to get memory resource\n");
699 child_res[0].flags = res->flags;
700 child_res[0].start = res->start;
701 child_res[0].end = child_res[0].start +
702 qcom->acpi_pdata->dwc3_core_base_size;
704 irq = platform_get_irq(pdev_irq, 0);
709 child_res[1].flags = IORESOURCE_IRQ;
710 child_res[1].start = child_res[1].end = irq;
712 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
714 dev_err(&pdev->dev, "failed to add resources\n");
718 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
720 dev_err(&pdev->dev, "failed to add properties\n");
724 ret = platform_device_add(qcom->dwc3);
726 dev_err(&pdev->dev, "failed to add device\n");
727 device_remove_software_node(&qcom->dwc3->dev);
734 platform_device_put(qcom->dwc3);
739 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
741 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
742 struct device_node *np = pdev->dev.of_node, *dwc3_np;
743 struct device *dev = &pdev->dev;
746 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
748 dev_err(dev, "failed to find dwc3 core child\n");
752 ret = of_platform_populate(np, NULL, NULL, dev);
754 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
758 qcom->dwc3 = of_find_device_by_node(dwc3_np);
761 dev_err(dev, "failed to get dwc3 platform device\n");
765 of_node_put(dwc3_np);
770 static struct platform_device *
771 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
773 struct fwnode_handle *fwh;
774 struct acpi_device *adev;
779 /* Figure out device id */
780 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
784 /* Find the child using name */
785 snprintf(name, sizeof(name), "USB%d", id);
786 fwh = fwnode_get_named_child_node(dev->fwnode, name);
790 adev = to_acpi_device_node(fwh);
794 return acpi_create_platform_device(adev, NULL);
797 static int dwc3_qcom_probe(struct platform_device *pdev)
799 struct device_node *np = pdev->dev.of_node;
800 struct device *dev = &pdev->dev;
801 struct dwc3_qcom *qcom;
802 struct resource *res, *parent_res = NULL;
804 bool ignore_pipe_clk;
807 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
811 platform_set_drvdata(pdev, qcom);
812 qcom->dev = &pdev->dev;
814 if (has_acpi_companion(dev)) {
815 qcom->acpi_pdata = acpi_device_get_match_data(dev);
816 if (!qcom->acpi_pdata) {
817 dev_err(&pdev->dev, "no supporting ACPI device data\n");
822 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
823 if (IS_ERR(qcom->resets)) {
824 ret = PTR_ERR(qcom->resets);
825 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
829 ret = reset_control_assert(qcom->resets);
831 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
835 usleep_range(10, 1000);
837 ret = reset_control_deassert(qcom->resets);
839 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
843 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
845 dev_err(dev, "failed to get clocks\n");
849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
854 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
858 parent_res->start = res->start +
859 qcom->acpi_pdata->qscratch_base_offset;
860 parent_res->end = parent_res->start +
861 qcom->acpi_pdata->qscratch_base_size;
863 if (qcom->acpi_pdata->is_urs) {
864 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
865 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
866 dev_err(dev, "failed to create URS USB platdev\n");
870 return PTR_ERR(qcom->urs_usb);
875 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
876 if (IS_ERR(qcom->qscratch_base)) {
877 ret = PTR_ERR(qcom->qscratch_base);
881 ret = dwc3_qcom_setup_irq(pdev);
883 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
888 * Disable pipe_clk requirement if specified. Used when dwc3
889 * operates without SSPHY and only HS/FS/LS modes are supported.
891 ignore_pipe_clk = device_property_read_bool(dev,
892 "qcom,select-utmi-as-pipe-clk");
894 dwc3_qcom_select_utmi_clk(qcom);
897 ret = dwc3_qcom_of_register_core(pdev);
899 ret = dwc3_qcom_acpi_register_core(pdev);
902 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
906 ret = dwc3_qcom_interconnect_init(qcom);
910 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
912 /* enable vbus override for device mode */
913 if (qcom->mode != USB_DR_MODE_HOST)
914 dwc3_qcom_vbus_override_enable(qcom, true);
916 /* register extcon to override sw_vbus on Vbus change later */
917 ret = dwc3_qcom_register_extcon(qcom);
919 goto interconnect_exit;
921 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
922 device_init_wakeup(&pdev->dev, wakeup_source);
923 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
925 qcom->is_suspended = false;
926 pm_runtime_set_active(dev);
927 pm_runtime_enable(dev);
928 pm_runtime_forbid(dev);
933 dwc3_qcom_interconnect_exit(qcom);
936 of_platform_depopulate(&pdev->dev);
938 platform_device_put(pdev);
940 for (i = qcom->num_clocks - 1; i >= 0; i--) {
941 clk_disable_unprepare(qcom->clks[i]);
942 clk_put(qcom->clks[i]);
945 reset_control_assert(qcom->resets);
950 static int dwc3_qcom_remove(struct platform_device *pdev)
952 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
953 struct device *dev = &pdev->dev;
956 device_remove_software_node(&qcom->dwc3->dev);
957 of_platform_depopulate(dev);
959 for (i = qcom->num_clocks - 1; i >= 0; i--) {
960 clk_disable_unprepare(qcom->clks[i]);
961 clk_put(qcom->clks[i]);
963 qcom->num_clocks = 0;
965 dwc3_qcom_interconnect_exit(qcom);
966 reset_control_assert(qcom->resets);
968 pm_runtime_allow(dev);
969 pm_runtime_disable(dev);
974 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
976 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
977 bool wakeup = device_may_wakeup(dev);
980 ret = dwc3_qcom_suspend(qcom, wakeup);
984 qcom->pm_suspended = true;
989 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
991 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
992 bool wakeup = device_may_wakeup(dev);
995 ret = dwc3_qcom_resume(qcom, wakeup);
999 qcom->pm_suspended = false;
1004 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
1006 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1008 return dwc3_qcom_suspend(qcom, true);
1011 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
1013 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1015 return dwc3_qcom_resume(qcom, true);
1018 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
1019 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
1020 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
1024 static const struct of_device_id dwc3_qcom_of_match[] = {
1025 { .compatible = "qcom,dwc3" },
1028 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
1031 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1032 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1033 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1034 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1035 .hs_phy_irq_index = 1,
1036 .dp_hs_phy_irq_index = 4,
1037 .dm_hs_phy_irq_index = 3,
1038 .ss_phy_irq_index = 2
1041 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1042 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1043 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1044 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1045 .hs_phy_irq_index = 1,
1046 .dp_hs_phy_irq_index = 4,
1047 .dm_hs_phy_irq_index = 3,
1048 .ss_phy_irq_index = 2,
1052 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1053 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1054 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1055 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1056 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1059 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1062 static struct platform_driver dwc3_qcom_driver = {
1063 .probe = dwc3_qcom_probe,
1064 .remove = dwc3_qcom_remove,
1066 .name = "dwc3-qcom",
1067 .pm = &dwc3_qcom_dev_pm_ops,
1068 .of_match_table = dwc3_qcom_of_match,
1069 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1073 module_platform_driver(dwc3_qcom_driver);
1075 MODULE_LICENSE("GPL v2");
1076 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");