drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39 #define PCI_DEVICE_ID_INTEL_EHL                 0x4b7e
  40 #define PCI_DEVICE_ID_INTEL_TGPLP               0xa0ee
  41 #define PCI_DEVICE_ID_INTEL_TGPH                0x43ee
  42 #define PCI_DEVICE_ID_INTEL_JSP                 0x4dee
  43 #define PCI_DEVICE_ID_INTEL_ADLP                0x51ee
  44 #define PCI_DEVICE_ID_INTEL_ADLM                0x54ee
  45 #define PCI_DEVICE_ID_INTEL_ADLS                0x7ae1
  46 #define PCI_DEVICE_ID_INTEL_TGL                 0x9a15
  47 #define PCI_DEVICE_ID_AMD_MR                    0x163a
  48
  49 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  50 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  51 #define PCI_INTEL_BXT_STATE_D0          0
  52 #define PCI_INTEL_BXT_STATE_D3          3
  53
  54 #define GP_RWBAR                        1
  55 #define GP_RWREG1                       0xa0
  56 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  57
  58 /**
  59  * struct dwc3_pci - Driver private structure
  60  * @dwc3: child dwc3 platform_device
  61  * @pci: our link to PCI bus
  62  * @guid: _DSM GUID
  63  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  64  * @wakeup_work: work for asynchronous resume
  65  */
  66 struct dwc3_pci {
  67         struct platform_device *dwc3;
  68         struct pci_dev *pci;
  69
  70         guid_t guid;
  71
  72         unsigned int has_dsm_for_pm:1;
  73         struct work_struct wakeup_work;
  74 };
  75
  76 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  77 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  78
  79 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  80         { "reset-gpios", &reset_gpios, 1 },
  81         { "cs-gpios", &cs_gpios, 1 },
  82         { },
  83 };
  84
  85 static struct gpiod_lookup_table platform_bytcr_gpios = {
  86         .dev_id         = "0000:00:16.0",
  87         .table          = {
  88                 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
  89                 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
  90                 {}
  91         },
  92 };
  93
  94 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  95 {
  96         void __iomem    *reg;
  97         u32             value;
  98
  99         reg = pcim_iomap(pci, GP_RWBAR, 0);
 100         if (!reg)
 101                 return -ENOMEM;
 102
 103         value = readl(reg + GP_RWREG1);
 104         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
 105                 goto unmap; /* ULPI refclk already enabled */
 106
 107         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
 108         writel(value, reg + GP_RWREG1);
 109         /* This comes from the Intel Android x86 tree w/o any explanation */
 110         msleep(100);
 111 unmap:
 112         pcim_iounmap(pci, reg);
 113         return 0;
 114 }
 115
 116 static const struct property_entry dwc3_pci_intel_properties[] = {
 117         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 118         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 119         {}
 120 };
 121
 122 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 123         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 124         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 125         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 126         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 127         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 128         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 129         {}
 130 };
 131
 132 static const struct property_entry dwc3_pci_amd_properties[] = {
 133         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 134         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 135         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 136         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 137         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 138         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 139         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 140         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 141         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 142         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 143         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 144         /* FIXME these quirks should be removed when AMD NL tapes out */
 145         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 146         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 147         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 148         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 149         {}
 150 };
 151
 152 static const struct property_entry dwc3_pci_mr_properties[] = {
 153         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 154         PROPERTY_ENTRY_BOOL("usb-role-switch"),
 155         PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
 156         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 157         {}
 158 };
 159
 160 static const struct software_node dwc3_pci_intel_swnode = {
 161         .properties = dwc3_pci_intel_properties,
 162 };
 163
 164 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
 165         .properties = dwc3_pci_mrfld_properties,
 166 };
 167
 168 static const struct software_node dwc3_pci_amd_swnode = {
 169         .properties = dwc3_pci_amd_properties,
 170 };
 171
 172 static const struct software_node dwc3_pci_amd_mr_swnode = {
 173         .properties = dwc3_pci_mr_properties,
 174 };
 175
 176 static int dwc3_pci_quirks(struct dwc3_pci *dwc)
 177 {
 178         struct pci_dev                  *pdev = dwc->pci;
 179
 180         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 181                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 182                     pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
 183                     pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
 184                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 185                         dwc->has_dsm_for_pm = true;
 186                 }
 187
 188                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 189                         struct gpio_desc *gpio;
 190                         int ret;
 191
 192                         /* On BYT the FW does not always enable the refclock */
 193                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 194                         if (ret)
 195                                 return ret;
 196
 197                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 198                                         acpi_dwc3_byt_gpios);
 199                         if (ret)
 200                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 201
 202                         /*
 203                          * A lot of BYT devices lack ACPI resource entries for
 204                          * the GPIOs, add a fallback mapping to the reference
 205                          * design GPIOs which all boards seem to use.
 206                          */
 207                         gpiod_add_lookup_table(&platform_bytcr_gpios);
 208
 209                         /*
 210                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 211                          * put the gpio descriptors again here because the phy driver
 212                          * might want to grab them, too.
 213                          */
 214                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 215                         if (IS_ERR(gpio))
 216                                 return PTR_ERR(gpio);
 217
 218                         gpiod_set_value_cansleep(gpio, 1);
 219                         gpiod_put(gpio);
 220
 221                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 222                         if (IS_ERR(gpio))
 223                                 return PTR_ERR(gpio);
 224
 225                         if (gpio) {
 226                                 gpiod_set_value_cansleep(gpio, 1);
 227                                 gpiod_put(gpio);
 228                                 usleep_range(10000, 11000);
 229                         }
 230                 }
 231         }
 232
 233         return 0;
 234 }
 235
 236 #ifdef CONFIG_PM
 237 static void dwc3_pci_resume_work(struct work_struct *work)
 238 {
 239         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 240         struct platform_device *dwc3 = dwc->dwc3;
 241         int ret;
 242
 243         ret = pm_runtime_get_sync(&dwc3->dev);
 244         if (ret) {
 245                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 246                 return;
 247         }
 248
 249         pm_runtime_mark_last_busy(&dwc3->dev);
 250         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 251 }
 252 #endif
 253
 254 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 255 {
 256         struct dwc3_pci         *dwc;
 257         struct resource         res[2];
 258         int                     ret;
 259         struct device           *dev = &pci->dev;
 260
 261         ret = pcim_enable_device(pci);
 262         if (ret) {
 263                 dev_err(dev, "failed to enable pci device\n");
 264                 return -ENODEV;
 265         }
 266
 267         pci_set_master(pci);
 268
 269         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 270         if (!dwc)
 271                 return -ENOMEM;
 272
 273         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 274         if (!dwc->dwc3)
 275                 return -ENOMEM;
 276
 277         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 278
 279         res[0].start    = pci_resource_start(pci, 0);
 280         res[0].end      = pci_resource_end(pci, 0);
 281         res[0].name     = "dwc_usb3";
 282         res[0].flags    = IORESOURCE_MEM;
 283
 284         res[1].start    = pci->irq;
 285         res[1].name     = "dwc_usb3";
 286         res[1].flags    = IORESOURCE_IRQ;
 287
 288         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 289         if (ret) {
 290                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 291                 goto err;
 292         }
 293
 294         dwc->pci = pci;
 295         dwc->dwc3->dev.parent = dev;
 296         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 297
 298         ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data);
 299         if (ret < 0)
 300                 goto err;
 301
 302         ret = dwc3_pci_quirks(dwc);
 303         if (ret)
 304                 goto err;
 305
 306         ret = platform_device_add(dwc->dwc3);
 307         if (ret) {
 308                 dev_err(dev, "failed to register dwc3 device\n");
 309                 goto err;
 310         }
 311
 312         device_init_wakeup(dev, true);
 313         pci_set_drvdata(pci, dwc);
 314         pm_runtime_put(dev);
 315 #ifdef CONFIG_PM
 316         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 317 #endif
 318
 319         return 0;
 320 err:
 321         device_remove_software_node(&dwc->dwc3->dev);
 322         platform_device_put(dwc->dwc3);
 323         return ret;
 324 }
 325
 326 static void dwc3_pci_remove(struct pci_dev *pci)
 327 {
 328         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 329         struct pci_dev          *pdev = dwc->pci;
 330
 331         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 332                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 333 #ifdef CONFIG_PM
 334         cancel_work_sync(&dwc->wakeup_work);
 335 #endif
 336         device_init_wakeup(&pci->dev, false);
 337         pm_runtime_get(&pci->dev);
 338         device_remove_software_node(&dwc->dwc3->dev);
 339         platform_device_unregister(dwc->dwc3);
 340 }
 341
 342 static const struct pci_device_id dwc3_pci_id_table[] = {
 343         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
 344           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 345
 346         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
 347           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 348
 349         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
 350           (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
 351
 352         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
 353           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 354
 355         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
 356           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 357
 358         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
 359           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 360
 361         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
 362           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 363
 364         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
 365           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 366
 367         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
 368           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 369
 370         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
 371           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 372
 373         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
 374           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 375
 376         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
 377           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 378
 379         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
 380           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 381
 382         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
 383           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 384
 385         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
 386           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 387
 388         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
 389           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 390
 391         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
 392           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 393
 394         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
 395           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 396
 397         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
 398           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 399
 400         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
 401           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 402
 403         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
 404           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 405
 406         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
 407           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 408
 409         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
 410           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 411
 412         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
 413           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 414
 415         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 416           (kernel_ulong_t) &dwc3_pci_amd_swnode, },
 417
 418         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
 419           (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
 420
 421         {  }    /* Terminating Entry */
 422 };
 423 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 424
 425 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 426 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 427 {
 428         union acpi_object *obj;
 429         union acpi_object tmp;
 430         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 431
 432         if (!dwc->has_dsm_for_pm)
 433                 return 0;
 434
 435         tmp.type = ACPI_TYPE_INTEGER;
 436         tmp.integer.value = param;
 437
 438         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 439                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 440         if (!obj) {
 441                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 442                 return -EIO;
 443         }
 444
 445         ACPI_FREE(obj);
 446
 447         return 0;
 448 }
 449 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 450
 451 #ifdef CONFIG_PM
 452 static int dwc3_pci_runtime_suspend(struct device *dev)
 453 {
 454         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 455
 456         if (device_can_wakeup(dev))
 457                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 458
 459         return -EBUSY;
 460 }
 461
 462 static int dwc3_pci_runtime_resume(struct device *dev)
 463 {
 464         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 465         int                     ret;
 466
 467         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 468         if (ret)
 469                 return ret;
 470
 471         queue_work(pm_wq, &dwc->wakeup_work);
 472
 473         return 0;
 474 }
 475 #endif /* CONFIG_PM */
 476
 477 #ifdef CONFIG_PM_SLEEP
 478 static int dwc3_pci_suspend(struct device *dev)
 479 {
 480         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 481
 482         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 483 }
 484
 485 static int dwc3_pci_resume(struct device *dev)
 486 {
 487         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 488
 489         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 490 }
 491 #endif /* CONFIG_PM_SLEEP */
 492
 493 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 494         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 495         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 496                 NULL)
 497 };
 498
 499 static struct pci_driver dwc3_pci_driver = {
 500         .name           = "dwc3-pci",
 501         .id_table       = dwc3_pci_id_table,
 502         .probe          = dwc3_pci_probe,
 503         .remove         = dwc3_pci_remove,
 504         .driver         = {
 505                 .pm     = &dwc3_pci_dev_pm_ops,
 506         }
 507 };
 508
 509 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 510 MODULE_LICENSE("GPL v2");
 511 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 512
 513 module_pci_driver(dwc3_pci_driver);