1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/ioport.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/wait.h>
23 #include <linux/workqueue.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 #include <linux/usb/otg.h>
28 #include <linux/usb/role.h>
29 #include <linux/ulpi/interface.h>
31 #include <linux/phy/phy.h>
33 #define DWC3_MSG_MAX 500
35 /* Global constants */
36 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
37 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
38 #define DWC3_EP0_SETUP_SIZE 512
39 #define DWC3_ENDPOINTS_NUM 32
40 #define DWC3_XHCI_RESOURCES_NUM 2
41 #define DWC3_ISOC_MAX_RETRIES 5
43 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
44 #define DWC3_EVENT_BUFFERS_SIZE 4096
45 #define DWC3_EVENT_TYPE_MASK 0xfe
47 #define DWC3_EVENT_TYPE_DEV 0
48 #define DWC3_EVENT_TYPE_CARKIT 3
49 #define DWC3_EVENT_TYPE_I2C 4
51 #define DWC3_DEVICE_EVENT_DISCONNECT 0
52 #define DWC3_DEVICE_EVENT_RESET 1
53 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
54 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
55 #define DWC3_DEVICE_EVENT_WAKEUP 4
56 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
57 #define DWC3_DEVICE_EVENT_EOPF 6
58 #define DWC3_DEVICE_EVENT_SOF 7
59 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
60 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
61 #define DWC3_DEVICE_EVENT_OVERFLOW 11
63 /* Controller's role while using the OTG block */
64 #define DWC3_OTG_ROLE_IDLE 0
65 #define DWC3_OTG_ROLE_HOST 1
66 #define DWC3_OTG_ROLE_DEVICE 2
68 #define DWC3_GEVNTCOUNT_MASK 0xfffc
69 #define DWC3_GEVNTCOUNT_EHB BIT(31)
70 #define DWC3_GSNPSID_MASK 0xffff0000
71 #define DWC3_GSNPSREV_MASK 0xffff
72 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
74 /* DWC3 registers memory space boundries */
75 #define DWC3_XHCI_REGS_START 0x0
76 #define DWC3_XHCI_REGS_END 0x7fff
77 #define DWC3_GLOBALS_REGS_START 0xc100
78 #define DWC3_GLOBALS_REGS_END 0xc6ff
79 #define DWC3_DEVICE_REGS_START 0xc700
80 #define DWC3_DEVICE_REGS_END 0xcbff
81 #define DWC3_OTG_REGS_START 0xcc00
82 #define DWC3_OTG_REGS_END 0xccff
84 /* Global Registers */
85 #define DWC3_GSBUSCFG0 0xc100
86 #define DWC3_GSBUSCFG1 0xc104
87 #define DWC3_GTXTHRCFG 0xc108
88 #define DWC3_GRXTHRCFG 0xc10c
89 #define DWC3_GCTL 0xc110
90 #define DWC3_GEVTEN 0xc114
91 #define DWC3_GSTS 0xc118
92 #define DWC3_GUCTL1 0xc11c
93 #define DWC3_GSNPSID 0xc120
94 #define DWC3_GGPIO 0xc124
95 #define DWC3_GUID 0xc128
96 #define DWC3_GUCTL 0xc12c
97 #define DWC3_GBUSERRADDR0 0xc130
98 #define DWC3_GBUSERRADDR1 0xc134
99 #define DWC3_GPRTBIMAP0 0xc138
100 #define DWC3_GPRTBIMAP1 0xc13c
101 #define DWC3_GHWPARAMS0 0xc140
102 #define DWC3_GHWPARAMS1 0xc144
103 #define DWC3_GHWPARAMS2 0xc148
104 #define DWC3_GHWPARAMS3 0xc14c
105 #define DWC3_GHWPARAMS4 0xc150
106 #define DWC3_GHWPARAMS5 0xc154
107 #define DWC3_GHWPARAMS6 0xc158
108 #define DWC3_GHWPARAMS7 0xc15c
109 #define DWC3_GDBGFIFOSPACE 0xc160
110 #define DWC3_GDBGLTSSM 0xc164
111 #define DWC3_GDBGBMU 0xc16c
112 #define DWC3_GDBGLSPMUX 0xc170
113 #define DWC3_GDBGLSP 0xc174
114 #define DWC3_GDBGEPINFO0 0xc178
115 #define DWC3_GDBGEPINFO1 0xc17c
116 #define DWC3_GPRTBIMAP_HS0 0xc180
117 #define DWC3_GPRTBIMAP_HS1 0xc184
118 #define DWC3_GPRTBIMAP_FS0 0xc188
119 #define DWC3_GPRTBIMAP_FS1 0xc18c
120 #define DWC3_GUCTL2 0xc19c
122 #define DWC3_VER_NUMBER 0xc1a0
123 #define DWC3_VER_TYPE 0xc1a4
125 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
126 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
128 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
130 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
132 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
133 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
135 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
136 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
137 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
138 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
140 #define DWC3_GHWPARAMS8 0xc600
141 #define DWC3_GFLADJ 0xc630
143 /* Device Registers */
144 #define DWC3_DCFG 0xc700
145 #define DWC3_DCTL 0xc704
146 #define DWC3_DEVTEN 0xc708
147 #define DWC3_DSTS 0xc70c
148 #define DWC3_DGCMDPAR 0xc710
149 #define DWC3_DGCMD 0xc714
150 #define DWC3_DALEPENA 0xc720
152 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
153 #define DWC3_DEPCMDPAR2 0x00
154 #define DWC3_DEPCMDPAR1 0x04
155 #define DWC3_DEPCMDPAR0 0x08
156 #define DWC3_DEPCMD 0x0c
158 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
161 #define DWC3_OCFG 0xcc00
162 #define DWC3_OCTL 0xcc04
163 #define DWC3_OEVT 0xcc08
164 #define DWC3_OEVTEN 0xcc0C
165 #define DWC3_OSTS 0xcc10
169 /* Global SoC Bus Configuration INCRx Register 0 */
170 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
171 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
172 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
173 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
174 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
175 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
176 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
177 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
178 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
180 /* Global Debug LSP MUX Select */
181 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
182 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
183 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
184 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
186 /* Global Debug Queue/FIFO Space Available Register */
187 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
188 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
189 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
191 #define DWC3_TXFIFO 0
192 #define DWC3_RXFIFO 1
193 #define DWC3_TXREQQ 2
194 #define DWC3_RXREQQ 3
195 #define DWC3_RXINFOQ 4
196 #define DWC3_PSTATQ 5
197 #define DWC3_DESCFETCHQ 6
198 #define DWC3_EVENTQ 7
199 #define DWC3_AUXEVENTQ 8
201 /* Global RX Threshold Configuration Register */
202 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
203 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
204 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
206 /* Global RX Threshold Configuration Register for DWC_usb31 only */
207 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
208 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
209 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
210 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
211 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
212 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
213 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
214 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
216 /* Global TX Threshold Configuration Register for DWC_usb31 only */
217 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
218 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
219 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
220 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
221 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
222 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
223 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
224 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
226 /* Global Configuration Register */
227 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
228 #define DWC3_GCTL_U2RSTECN BIT(16)
229 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
230 #define DWC3_GCTL_CLK_BUS (0)
231 #define DWC3_GCTL_CLK_PIPE (1)
232 #define DWC3_GCTL_CLK_PIPEHALF (2)
233 #define DWC3_GCTL_CLK_MASK (3)
235 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
236 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
237 #define DWC3_GCTL_PRTCAP_HOST 1
238 #define DWC3_GCTL_PRTCAP_DEVICE 2
239 #define DWC3_GCTL_PRTCAP_OTG 3
241 #define DWC3_GCTL_CORESOFTRESET BIT(11)
242 #define DWC3_GCTL_SOFITPSYNC BIT(10)
243 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
244 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
245 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
246 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
247 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
248 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
250 /* Global User Control Register */
251 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
253 /* Global User Control 1 Register */
254 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
255 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
256 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
258 /* Global Status Register */
259 #define DWC3_GSTS_OTG_IP BIT(10)
260 #define DWC3_GSTS_BC_IP BIT(9)
261 #define DWC3_GSTS_ADP_IP BIT(8)
262 #define DWC3_GSTS_HOST_IP BIT(7)
263 #define DWC3_GSTS_DEVICE_IP BIT(6)
264 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
265 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
266 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
267 #define DWC3_GSTS_CURMOD_DEVICE 0
268 #define DWC3_GSTS_CURMOD_HOST 1
270 /* Global USB2 PHY Configuration Register */
271 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
272 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
273 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
274 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
275 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
276 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
277 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
278 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
279 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
280 #define USBTRDTIM_UTMI_8_BIT 9
281 #define USBTRDTIM_UTMI_16_BIT 5
282 #define UTMI_PHYIF_16_BIT 1
283 #define UTMI_PHYIF_8_BIT 0
285 /* Global USB2 PHY Vendor Control Register */
286 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
287 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
288 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
289 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
290 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
291 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
293 /* Global USB3 PIPE Control Register */
294 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
295 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
296 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
297 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
298 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
299 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
300 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
301 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
302 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
303 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
304 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
305 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
306 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
307 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
309 /* Global TX Fifo Size Register */
310 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
311 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
312 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
313 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
315 /* Global RX Fifo Size Register */
316 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
317 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
319 /* Global Event Size Registers */
320 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
321 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
323 /* Global HWPARAMS0 Register */
324 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
325 #define DWC3_GHWPARAMS0_MODE_GADGET 0
326 #define DWC3_GHWPARAMS0_MODE_HOST 1
327 #define DWC3_GHWPARAMS0_MODE_DRD 2
328 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
329 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
330 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
331 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
332 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
334 /* Global HWPARAMS1 Register */
335 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
336 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
337 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
338 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
339 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
340 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
341 #define DWC3_GHWPARAMS1_ENDBC BIT(31)
343 /* Global HWPARAMS3 Register */
344 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
345 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
346 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
347 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
348 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
349 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
350 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
351 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
352 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
353 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
354 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
355 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
357 /* Global HWPARAMS4 Register */
358 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
359 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
361 /* Global HWPARAMS6 Register */
362 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
363 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
364 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
365 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
366 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
367 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
370 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
372 /* Global HWPARAMS7 Register */
373 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
374 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
376 /* Global Frame Length Adjustment Register */
377 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
378 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
380 /* Global User Control Register 2 */
381 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
383 /* Device Configuration Register */
384 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
385 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
387 #define DWC3_DCFG_SPEED_MASK (7 << 0)
388 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
389 #define DWC3_DCFG_SUPERSPEED (4 << 0)
390 #define DWC3_DCFG_HIGHSPEED (0 << 0)
391 #define DWC3_DCFG_FULLSPEED BIT(0)
392 #define DWC3_DCFG_LOWSPEED (2 << 0)
394 #define DWC3_DCFG_NUMP_SHIFT 17
395 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
396 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
397 #define DWC3_DCFG_LPM_CAP BIT(22)
399 /* Device Control Register */
400 #define DWC3_DCTL_RUN_STOP BIT(31)
401 #define DWC3_DCTL_CSFTRST BIT(30)
402 #define DWC3_DCTL_LSFTRST BIT(29)
404 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
405 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
407 #define DWC3_DCTL_APPL1RES BIT(23)
409 /* These apply for core versions 1.87a and earlier */
410 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
411 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
412 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
413 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
414 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
415 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
416 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
418 /* These apply for core versions 1.94a and later */
419 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
421 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
422 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
423 #define DWC3_DCTL_CRS BIT(17)
424 #define DWC3_DCTL_CSS BIT(16)
426 #define DWC3_DCTL_INITU2ENA BIT(12)
427 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
428 #define DWC3_DCTL_INITU1ENA BIT(10)
429 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
430 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
432 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
433 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
435 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
436 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
437 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
438 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
439 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
440 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
441 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
443 /* Device Event Enable Register */
444 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
445 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
446 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
447 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
448 #define DWC3_DEVTEN_SOFEN BIT(7)
449 #define DWC3_DEVTEN_EOPFEN BIT(6)
450 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
451 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
452 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
453 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
454 #define DWC3_DEVTEN_USBRSTEN BIT(1)
455 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
457 /* Device Status Register */
458 #define DWC3_DSTS_DCNRD BIT(29)
460 /* This applies for core versions 1.87a and earlier */
461 #define DWC3_DSTS_PWRUPREQ BIT(24)
463 /* These apply for core versions 1.94a and later */
464 #define DWC3_DSTS_RSS BIT(25)
465 #define DWC3_DSTS_SSS BIT(24)
467 #define DWC3_DSTS_COREIDLE BIT(23)
468 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
470 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
471 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
473 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
475 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
476 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
478 #define DWC3_DSTS_CONNECTSPD (7 << 0)
480 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
481 #define DWC3_DSTS_SUPERSPEED (4 << 0)
482 #define DWC3_DSTS_HIGHSPEED (0 << 0)
483 #define DWC3_DSTS_FULLSPEED BIT(0)
484 #define DWC3_DSTS_LOWSPEED (2 << 0)
486 /* Device Generic Command Register */
487 #define DWC3_DGCMD_SET_LMP 0x01
488 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
489 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
491 /* These apply for core versions 1.94a and later */
492 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
493 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
495 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
496 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
497 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
498 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
499 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
501 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
502 #define DWC3_DGCMD_CMDACT BIT(10)
503 #define DWC3_DGCMD_CMDIOC BIT(8)
505 /* Device Generic Command Parameter Register */
506 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
507 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
508 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
509 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
510 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
511 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
513 /* Device Endpoint Command Register */
514 #define DWC3_DEPCMD_PARAM_SHIFT 16
515 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
516 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
517 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
518 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
519 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
520 #define DWC3_DEPCMD_CMDACT BIT(10)
521 #define DWC3_DEPCMD_CMDIOC BIT(8)
523 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
524 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
525 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
526 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
527 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
528 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
529 /* This applies for core versions 1.90a and earlier */
530 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
531 /* This applies for core versions 1.94a and later */
532 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
533 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
534 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
536 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
538 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
539 #define DWC3_DALEPENA_EP(n) BIT(n)
541 #define DWC3_DEPCMD_TYPE_CONTROL 0
542 #define DWC3_DEPCMD_TYPE_ISOC 1
543 #define DWC3_DEPCMD_TYPE_BULK 2
544 #define DWC3_DEPCMD_TYPE_INTR 3
546 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
547 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
548 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
549 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
551 /* OTG Configuration Register */
552 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
553 #define DWC3_OCFG_HIBDISMASK BIT(4)
554 #define DWC3_OCFG_SFTRSTMASK BIT(3)
555 #define DWC3_OCFG_OTGVERSION BIT(2)
556 #define DWC3_OCFG_HNPCAP BIT(1)
557 #define DWC3_OCFG_SRPCAP BIT(0)
559 /* OTG CTL Register */
560 #define DWC3_OCTL_OTG3GOERR BIT(7)
561 #define DWC3_OCTL_PERIMODE BIT(6)
562 #define DWC3_OCTL_PRTPWRCTL BIT(5)
563 #define DWC3_OCTL_HNPREQ BIT(4)
564 #define DWC3_OCTL_SESREQ BIT(3)
565 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
566 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
567 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
569 /* OTG Event Register */
570 #define DWC3_OEVT_DEVICEMODE BIT(31)
571 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
572 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
573 #define DWC3_OEVT_HIBENTRY BIT(25)
574 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
575 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
576 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
577 #define DWC3_OEVT_ADEVIDLE BIT(21)
578 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
579 #define DWC3_OEVT_ADEVHOST BIT(19)
580 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
581 #define DWC3_OEVT_ADEVSRPDET BIT(17)
582 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
583 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
584 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
585 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
586 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
587 #define DWC3_OEVT_BSESSVLD BIT(3)
588 #define DWC3_OEVT_HSTNEGSTS BIT(2)
589 #define DWC3_OEVT_SESREQSTS BIT(1)
590 #define DWC3_OEVT_ERROR BIT(0)
592 /* OTG Event Enable Register */
593 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
594 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
595 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
596 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
597 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
598 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
599 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
600 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
601 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
602 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
603 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
604 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
605 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
606 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
607 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
608 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
610 /* OTG Status Register */
611 #define DWC3_OSTS_DEVRUNSTP BIT(13)
612 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
613 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
614 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
615 #define DWC3_OSTS_BSESVLD BIT(2)
616 #define DWC3_OSTS_VBUSVLD BIT(1)
617 #define DWC3_OSTS_CONIDSTS BIT(0)
624 * struct dwc3_event_buffer - Software event buffer representation
626 * @cache: The buffer cache used in the threaded interrupt
627 * @length: size of this buffer
628 * @lpos: event offset
629 * @count: cache of last read event count register
630 * @flags: flags related to this event buffer
632 * @dwc: pointer to DWC controller
634 struct dwc3_event_buffer {
642 #define DWC3_EVENT_PENDING BIT(0)
649 #define DWC3_EP_FLAG_STALLED BIT(0)
650 #define DWC3_EP_FLAG_WEDGED BIT(1)
652 #define DWC3_EP_DIRECTION_TX true
653 #define DWC3_EP_DIRECTION_RX false
655 #define DWC3_TRB_NUM 256
658 * struct dwc3_ep - device side endpoint representation
659 * @endpoint: usb endpoint
660 * @cancelled_list: list of cancelled requests for this endpoint
661 * @pending_list: list of pending requests for this endpoint
662 * @started_list: list of started requests on this endpoint
663 * @regs: pointer to first endpoint register
664 * @trb_pool: array of transaction buffers
665 * @trb_pool_dma: dma address of @trb_pool
666 * @trb_enqueue: enqueue 'pointer' into TRB array
667 * @trb_dequeue: dequeue 'pointer' into TRB array
668 * @dwc: pointer to DWC controller
669 * @saved_state: ep state saved during hibernation
670 * @flags: endpoint flags (wedged, stalled, ...)
671 * @number: endpoint number (1 - 15)
672 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
673 * @resource_index: Resource transfer index
674 * @frame_number: set to the frame number we want this transfer to start (ISOC)
675 * @interval: the interval on which the ISOC transfer is started
676 * @name: a human readable name e.g. ep1out-bulk
677 * @direction: true for TX, false for RX
678 * @stream_capable: true when streams are enabled
679 * @combo_num: the test combination BIT[15:14] of the frame number to test
680 * isochronous START TRANSFER command failure workaround
681 * @start_cmd_status: the status of testing START TRANSFER command with
685 struct usb_ep endpoint;
686 struct list_head cancelled_list;
687 struct list_head pending_list;
688 struct list_head started_list;
692 struct dwc3_trb *trb_pool;
693 dma_addr_t trb_pool_dma;
698 #define DWC3_EP_ENABLED BIT(0)
699 #define DWC3_EP_STALL BIT(1)
700 #define DWC3_EP_WEDGE BIT(2)
701 #define DWC3_EP_TRANSFER_STARTED BIT(3)
702 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
703 #define DWC3_EP_PENDING_REQUEST BIT(5)
704 #define DWC3_EP_DELAY_START BIT(6)
705 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
706 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
707 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
708 #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
710 /* This last one is specific to EP0 */
711 #define DWC3_EP0_DIR_IN BIT(31)
714 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
715 * use a u8 type here. If anybody decides to increase number of TRBs to
716 * anything larger than 256 - I can't see why people would want to do
717 * this though - then this type needs to be changed.
719 * By using u8 types we ensure that our % operator when incrementing
720 * enqueue and dequeue get optimized away by the compiler.
733 unsigned direction:1;
734 unsigned stream_capable:1;
736 /* For isochronous START TRANSFER workaround only */
738 int start_cmd_status;
742 DWC3_PHY_UNKNOWN = 0,
748 DWC3_EP0_UNKNOWN = 0,
751 DWC3_EP0_NRDY_STATUS,
754 enum dwc3_ep0_state {
761 enum dwc3_link_state {
763 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
764 DWC3_LINK_STATE_U1 = 0x01,
765 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
766 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
767 DWC3_LINK_STATE_SS_DIS = 0x04,
768 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
769 DWC3_LINK_STATE_SS_INACT = 0x06,
770 DWC3_LINK_STATE_POLL = 0x07,
771 DWC3_LINK_STATE_RECOV = 0x08,
772 DWC3_LINK_STATE_HRESET = 0x09,
773 DWC3_LINK_STATE_CMPLY = 0x0a,
774 DWC3_LINK_STATE_LPBK = 0x0b,
775 DWC3_LINK_STATE_RESET = 0x0e,
776 DWC3_LINK_STATE_RESUME = 0x0f,
777 DWC3_LINK_STATE_MASK = 0x0f,
780 /* TRB Length, PCM and Status */
781 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
782 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
783 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
784 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
786 #define DWC3_TRBSTS_OK 0
787 #define DWC3_TRBSTS_MISSED_ISOC 1
788 #define DWC3_TRBSTS_SETUP_PENDING 2
789 #define DWC3_TRB_STS_XFER_IN_PROG 4
792 #define DWC3_TRB_CTRL_HWO BIT(0)
793 #define DWC3_TRB_CTRL_LST BIT(1)
794 #define DWC3_TRB_CTRL_CHN BIT(2)
795 #define DWC3_TRB_CTRL_CSP BIT(3)
796 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
797 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
798 #define DWC3_TRB_CTRL_IOC BIT(11)
799 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
800 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
802 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
803 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
804 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
805 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
806 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
807 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
808 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
809 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
810 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
813 * struct dwc3_trb - transfer request block (hw format)
827 * struct dwc3_hwparams - copy of HWPARAMS registers
828 * @hwparams0: GHWPARAMS0
829 * @hwparams1: GHWPARAMS1
830 * @hwparams2: GHWPARAMS2
831 * @hwparams3: GHWPARAMS3
832 * @hwparams4: GHWPARAMS4
833 * @hwparams5: GHWPARAMS5
834 * @hwparams6: GHWPARAMS6
835 * @hwparams7: GHWPARAMS7
836 * @hwparams8: GHWPARAMS8
838 struct dwc3_hwparams {
851 #define DWC3_MODE(n) ((n) & 0x7)
853 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
856 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
859 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
860 #define DWC3_NUM_EPS_MASK (0x3f << 12)
861 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
862 (DWC3_NUM_EPS_MASK)) >> 12)
863 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
864 (DWC3_NUM_IN_EPS_MASK)) >> 18)
867 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
870 * struct dwc3_request - representation of a transfer request
871 * @request: struct usb_request to be transferred
872 * @list: a list_head used for request queueing
873 * @dep: struct dwc3_ep owning this request
874 * @sg: pointer to first incomplete sg
875 * @start_sg: pointer to the sg which should be queued next
876 * @num_pending_sgs: counter to pending sgs
877 * @num_queued_sgs: counter to the number of sgs which already got queued
878 * @remaining: amount of data remaining
879 * @status: internal dwc3 request status tracking
880 * @epnum: endpoint number to which this request refers
881 * @trb: pointer to struct dwc3_trb
882 * @trb_dma: DMA address of @trb
883 * @num_trbs: number of TRBs used by this request
884 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
886 * @direction: IN or OUT direction flag
887 * @mapped: true when request has been dma-mapped
889 struct dwc3_request {
890 struct usb_request request;
891 struct list_head list;
893 struct scatterlist *sg;
894 struct scatterlist *start_sg;
896 unsigned num_pending_sgs;
897 unsigned int num_queued_sgs;
901 #define DWC3_REQUEST_STATUS_QUEUED 0
902 #define DWC3_REQUEST_STATUS_STARTED 1
903 #define DWC3_REQUEST_STATUS_CANCELLED 2
904 #define DWC3_REQUEST_STATUS_COMPLETED 3
905 #define DWC3_REQUEST_STATUS_UNKNOWN -1
908 struct dwc3_trb *trb;
913 unsigned needs_extra_trb:1;
914 unsigned direction:1;
919 * struct dwc3_scratchpad_array - hibernation scratchpad array
920 * (format defined by hw)
922 struct dwc3_scratchpad_array {
923 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
927 * struct dwc3 - representation of our controller
928 * @drd_work: workqueue used for role swapping
929 * @ep0_trb: trb which is used for the ctrl_req
930 * @bounce: address of bounce buffer
931 * @scratchbuf: address of scratch buffer
932 * @setup_buf: used while precessing STD USB requests
933 * @ep0_trb_addr: dma address of @ep0_trb
934 * @bounce_addr: dma address of @bounce
935 * @ep0_usb_req: dummy req used while handling STD USB requests
936 * @scratch_addr: dma address of scratchbuf
937 * @ep0_in_setup: one control transfer is completed and enter setup phase
938 * @lock: for synchronizing
939 * @dev: pointer to our struct device
940 * @sysdev: pointer to the DMA-capable device
941 * @xhci: pointer to our xHCI child
942 * @xhci_resources: struct resources for our @xhci child
943 * @ev_buf: struct dwc3_event_buffer pointer
944 * @eps: endpoint array
945 * @gadget: device side representation of the peripheral controller
946 * @gadget_driver: pointer to the gadget driver
947 * @clks: array of clocks
948 * @num_clks: number of clocks
949 * @reset: reset control
950 * @regs: base address for our registers
951 * @regs_size: address space size
952 * @fladj: frame length adjustment
953 * @irq_gadget: peripheral controller's IRQ number
954 * @otg_irq: IRQ number for OTG IRQs
955 * @current_otg_role: current role of operation while using the OTG block
956 * @desired_otg_role: desired role of operation while using the OTG block
957 * @otg_restart_host: flag that OTG controller needs to restart host
958 * @nr_scratch: number of scratch buffers
959 * @u1u2: only used on revisions <1.83a for workaround
960 * @maximum_speed: maximum speed requested (mainly for testing purposes)
961 * @ip: controller's ID
962 * @revision: controller's version of an IP
963 * @version_type: VERSIONTYPE register contents, a sub release of a revision
964 * @dr_mode: requested mode of operation
965 * @current_dr_role: current role of operation when in dual-role mode
966 * @desired_dr_role: desired role of operation when in dual-role mode
967 * @edev: extcon handle
968 * @edev_nb: extcon notifier
969 * @hsphy_mode: UTMI phy mode, one of following:
970 * - USBPHY_INTERFACE_MODE_UTMI
971 * - USBPHY_INTERFACE_MODE_UTMIW
972 * @role_sw: usb_role_switch handle
973 * @role_switch_default_mode: default operation mode of controller while
974 * usb role is USB_ROLE_NONE.
975 * @usb2_phy: pointer to USB2 PHY
976 * @usb3_phy: pointer to USB3 PHY
977 * @usb2_generic_phy: pointer to USB2 PHY
978 * @usb3_generic_phy: pointer to USB3 PHY
979 * @phys_ready: flag to indicate that PHYs are ready
980 * @ulpi: pointer to ulpi interface
981 * @ulpi_ready: flag to indicate that ULPI is initialized
982 * @u2sel: parameter from Set SEL request.
983 * @u2pel: parameter from Set SEL request.
984 * @u1sel: parameter from Set SEL request.
985 * @u1pel: parameter from Set SEL request.
986 * @num_eps: number of endpoints
987 * @ep0_next_event: hold the next expected event
988 * @ep0state: state of endpoint zero
989 * @link_state: link state
990 * @speed: device speed (super, high, full, low)
991 * @hwparams: copy of hwparams registers
992 * @root: debugfs root folder pointer
993 * @regset: debugfs pointer to regdump file
994 * @dbg_lsp_select: current debug lsp mux register selection
995 * @test_mode: true when we're entering a USB test mode
996 * @test_mode_nr: test feature selector
997 * @lpm_nyet_threshold: LPM NYET response threshold
998 * @hird_threshold: HIRD threshold
999 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1000 * @rx_max_burst_prd: max periodic ESS receive burst size
1001 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1002 * @tx_max_burst_prd: max periodic ESS transmit burst size
1003 * @hsphy_interface: "utmi" or "ulpi"
1004 * @connected: true when we're connected to a host, false otherwise
1005 * @delayed_status: true when gadget driver asks for delayed status
1006 * @ep0_bounced: true when we used bounce buffer
1007 * @ep0_expect_in: true when we expect a DATA IN transfer
1008 * @has_hibernation: true when dwc3 was configured with Hibernation
1009 * @sysdev_is_parent: true when dwc3 device has a parent driver
1010 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1011 * there's now way for software to detect this in runtime.
1012 * @is_utmi_l1_suspend: the core asserts output signal
1014 * 1 - utmi_l1_suspend_n
1015 * @is_fpga: true when we are using the FPGA board
1016 * @pending_events: true when we have pending IRQs to be handled
1017 * @pullups_connected: true when Run/Stop bit is set
1018 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1019 * @three_stage_setup: set if we perform a three phase setup
1020 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1021 * not needed for DWC_usb31 version 1.70a-ea06 and below
1022 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1023 * @usb2_lpm_disable: set to disable usb2 lpm
1024 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1025 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1026 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1027 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1028 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1029 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1030 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1031 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1032 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1033 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1034 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1035 * disabling the suspend signal to the PHY.
1036 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1037 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1038 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1039 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1040 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1041 * provide a free-running PHY clock.
1042 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1044 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1045 * check during HS transmit.
1046 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1047 * instances in park mode.
1048 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1049 * @tx_de_emphasis: Tx de-emphasis value
1050 * 0 - -6dB de-emphasis
1051 * 1 - -3.5dB de-emphasis
1052 * 2 - No de-emphasis
1054 * @dis_metastability_quirk: set to disable metastability quirk.
1055 * @imod_interval: set the interrupt moderation interval in 250ns
1056 * increments or 0 to disable.
1059 struct work_struct drd_work;
1060 struct dwc3_trb *ep0_trb;
1064 dma_addr_t ep0_trb_addr;
1065 dma_addr_t bounce_addr;
1066 dma_addr_t scratch_addr;
1067 struct dwc3_request ep0_usb_req;
1068 struct completion ep0_in_setup;
1074 struct device *sysdev;
1076 struct platform_device *xhci;
1077 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1079 struct dwc3_event_buffer *ev_buf;
1080 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1082 struct usb_gadget gadget;
1083 struct usb_gadget_driver *gadget_driver;
1085 struct clk_bulk_data *clks;
1088 struct reset_control *reset;
1090 struct usb_phy *usb2_phy;
1091 struct usb_phy *usb3_phy;
1093 struct phy *usb2_generic_phy;
1094 struct phy *usb3_generic_phy;
1104 enum usb_dr_mode dr_mode;
1105 u32 current_dr_role;
1106 u32 desired_dr_role;
1107 struct extcon_dev *edev;
1108 struct notifier_block edev_nb;
1109 enum usb_phy_interface hsphy_mode;
1110 struct usb_role_switch *role_sw;
1111 enum usb_dr_mode role_switch_default_mode;
1116 u32 current_otg_role;
1117 u32 desired_otg_role;
1118 bool otg_restart_host;
1125 #define DWC3_IP 0x5533
1126 #define DWC31_IP 0x3331
1127 #define DWC32_IP 0x3332
1131 #define DWC3_REVISION_ANY 0x0
1132 #define DWC3_REVISION_173A 0x5533173a
1133 #define DWC3_REVISION_175A 0x5533175a
1134 #define DWC3_REVISION_180A 0x5533180a
1135 #define DWC3_REVISION_183A 0x5533183a
1136 #define DWC3_REVISION_185A 0x5533185a
1137 #define DWC3_REVISION_187A 0x5533187a
1138 #define DWC3_REVISION_188A 0x5533188a
1139 #define DWC3_REVISION_190A 0x5533190a
1140 #define DWC3_REVISION_194A 0x5533194a
1141 #define DWC3_REVISION_200A 0x5533200a
1142 #define DWC3_REVISION_202A 0x5533202a
1143 #define DWC3_REVISION_210A 0x5533210a
1144 #define DWC3_REVISION_220A 0x5533220a
1145 #define DWC3_REVISION_230A 0x5533230a
1146 #define DWC3_REVISION_240A 0x5533240a
1147 #define DWC3_REVISION_250A 0x5533250a
1148 #define DWC3_REVISION_260A 0x5533260a
1149 #define DWC3_REVISION_270A 0x5533270a
1150 #define DWC3_REVISION_280A 0x5533280a
1151 #define DWC3_REVISION_290A 0x5533290a
1152 #define DWC3_REVISION_300A 0x5533300a
1153 #define DWC3_REVISION_310A 0x5533310a
1154 #define DWC3_REVISION_330A 0x5533330a
1156 #define DWC31_REVISION_ANY 0x0
1157 #define DWC31_REVISION_110A 0x3131302a
1158 #define DWC31_REVISION_120A 0x3132302a
1159 #define DWC31_REVISION_160A 0x3136302a
1160 #define DWC31_REVISION_170A 0x3137302a
1161 #define DWC31_REVISION_180A 0x3138302a
1162 #define DWC31_REVISION_190A 0x3139302a
1164 #define DWC32_REVISION_ANY 0x0
1165 #define DWC32_REVISION_100A 0x3130302a
1169 #define DWC31_VERSIONTYPE_ANY 0x0
1170 #define DWC31_VERSIONTYPE_EA01 0x65613031
1171 #define DWC31_VERSIONTYPE_EA02 0x65613032
1172 #define DWC31_VERSIONTYPE_EA03 0x65613033
1173 #define DWC31_VERSIONTYPE_EA04 0x65613034
1174 #define DWC31_VERSIONTYPE_EA05 0x65613035
1175 #define DWC31_VERSIONTYPE_EA06 0x65613036
1177 enum dwc3_ep0_next ep0_next_event;
1178 enum dwc3_ep0_state ep0state;
1179 enum dwc3_link_state link_state;
1190 struct dwc3_hwparams hwparams;
1191 struct dentry *root;
1192 struct debugfs_regset32 *regset;
1198 u8 lpm_nyet_threshold;
1200 u8 rx_thr_num_pkt_prd;
1201 u8 rx_max_burst_prd;
1202 u8 tx_thr_num_pkt_prd;
1203 u8 tx_max_burst_prd;
1205 const char *hsphy_interface;
1207 unsigned connected:1;
1208 unsigned delayed_status:1;
1209 unsigned ep0_bounced:1;
1210 unsigned ep0_expect_in:1;
1211 unsigned has_hibernation:1;
1212 unsigned sysdev_is_parent:1;
1213 unsigned has_lpm_erratum:1;
1214 unsigned is_utmi_l1_suspend:1;
1216 unsigned pending_events:1;
1217 unsigned pullups_connected:1;
1218 unsigned setup_packet_pending:1;
1219 unsigned three_stage_setup:1;
1220 unsigned dis_start_transfer_quirk:1;
1221 unsigned usb3_lpm_capable:1;
1222 unsigned usb2_lpm_disable:1;
1224 unsigned disable_scramble_quirk:1;
1225 unsigned u2exit_lfps_quirk:1;
1226 unsigned u2ss_inp3_quirk:1;
1227 unsigned req_p1p2p3_quirk:1;
1228 unsigned del_p1p2p3_quirk:1;
1229 unsigned del_phy_power_chg_quirk:1;
1230 unsigned lfps_filter_quirk:1;
1231 unsigned rx_detect_poll_quirk:1;
1232 unsigned dis_u3_susphy_quirk:1;
1233 unsigned dis_u2_susphy_quirk:1;
1234 unsigned dis_enblslpm_quirk:1;
1235 unsigned dis_u1_entry_quirk:1;
1236 unsigned dis_u2_entry_quirk:1;
1237 unsigned dis_rxdet_inp3_quirk:1;
1238 unsigned dis_u2_freeclk_exists_quirk:1;
1239 unsigned dis_del_phy_power_chg_quirk:1;
1240 unsigned dis_tx_ipgap_linecheck_quirk:1;
1241 unsigned parkmode_disable_ss_quirk:1;
1243 unsigned tx_de_emphasis_quirk:1;
1244 unsigned tx_de_emphasis:2;
1246 unsigned dis_metastability_quirk:1;
1251 #define INCRX_BURST_MODE 0
1252 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1254 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1256 /* -------------------------------------------------------------------------- */
1258 struct dwc3_event_type {
1261 u32 reserved8_31:24;
1264 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1265 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1266 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1267 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1268 #define DWC3_DEPEVT_STREAMEVT 0x06
1269 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1272 * struct dwc3_event_depvt - Device Endpoint Events
1273 * @one_bit: indicates this is an endpoint event (not used)
1274 * @endpoint_number: number of the endpoint
1275 * @endpoint_event: The event we have:
1277 * 0x01 - XferComplete
1278 * 0x02 - XferInProgress
1279 * 0x03 - XferNotReady
1280 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1284 * @reserved11_10: Reserved, don't use.
1285 * @status: Indicates the status of the event. Refer to databook for
1287 * @parameters: Parameters of the current event. Refer to databook for
1290 struct dwc3_event_depevt {
1292 u32 endpoint_number:5;
1293 u32 endpoint_event:4;
1294 u32 reserved11_10:2;
1297 /* Within XferNotReady */
1298 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1300 /* Within XferComplete or XferInProgress */
1301 #define DEPEVT_STATUS_BUSERR BIT(0)
1302 #define DEPEVT_STATUS_SHORT BIT(1)
1303 #define DEPEVT_STATUS_IOC BIT(2)
1304 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1305 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1307 /* Stream event only */
1308 #define DEPEVT_STREAMEVT_FOUND 1
1309 #define DEPEVT_STREAMEVT_NOTFOUND 2
1311 /* Stream event parameter */
1312 #define DEPEVT_STREAM_PRIME 0xfffe
1313 #define DEPEVT_STREAM_NOSTREAM 0x0
1315 /* Control-only Status */
1316 #define DEPEVT_STATUS_CONTROL_DATA 1
1317 #define DEPEVT_STATUS_CONTROL_STATUS 2
1318 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1320 /* In response to Start Transfer */
1321 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1322 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1326 /* For Command Complete Events */
1327 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1331 * struct dwc3_event_devt - Device Events
1332 * @one_bit: indicates this is a non-endpoint event (not used)
1333 * @device_event: indicates it's a device event. Should read as 0x00
1334 * @type: indicates the type of device event.
1347 * 12 - VndrDevTstRcved
1348 * @reserved15_12: Reserved, not used
1349 * @event_info: Information about this event
1350 * @reserved31_25: Reserved, not used
1352 struct dwc3_event_devt {
1356 u32 reserved15_12:4;
1358 u32 reserved31_25:7;
1362 * struct dwc3_event_gevt - Other Core Events
1363 * @one_bit: indicates this is a non-endpoint event (not used)
1364 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1365 * @phy_port_number: self-explanatory
1366 * @reserved31_12: Reserved, not used.
1368 struct dwc3_event_gevt {
1371 u32 phy_port_number:4;
1372 u32 reserved31_12:20;
1376 * union dwc3_event - representation of Event Buffer contents
1377 * @raw: raw 32-bit event
1378 * @type: the type of the event
1379 * @depevt: Device Endpoint Event
1380 * @devt: Device Event
1381 * @gevt: Global Event
1385 struct dwc3_event_type type;
1386 struct dwc3_event_depevt depevt;
1387 struct dwc3_event_devt devt;
1388 struct dwc3_event_gevt gevt;
1392 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1394 * @param2: third parameter
1395 * @param1: second parameter
1396 * @param0: first parameter
1398 struct dwc3_gadget_ep_cmd_params {
1405 * DWC3 Features to be used as Driver Data
1408 #define DWC3_HAS_PERIPHERAL BIT(0)
1409 #define DWC3_HAS_XHCI BIT(1)
1410 #define DWC3_HAS_OTG BIT(3)
1413 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1414 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1415 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1417 #define DWC3_IP_IS(_ip) \
1418 (dwc->ip == _ip##_IP)
1420 #define DWC3_VER_IS(_ip, _ver) \
1421 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1423 #define DWC3_VER_IS_PRIOR(_ip, _ver) \
1424 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1426 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1427 (DWC3_IP_IS(_ip) && \
1428 dwc->revision >= _ip##_REVISION_##_from && \
1429 (!(_ip##_REVISION_##_to) || \
1430 dwc->revision <= _ip##_REVISION_##_to))
1432 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1433 (DWC3_VER_IS(_ip, _ver) && \
1434 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1435 (!(_ip##_VERSIONTYPE_##_to) || \
1436 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1438 bool dwc3_has_imod(struct dwc3 *dwc);
1440 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1441 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1443 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1444 int dwc3_host_init(struct dwc3 *dwc);
1445 void dwc3_host_exit(struct dwc3 *dwc);
1447 static inline int dwc3_host_init(struct dwc3 *dwc)
1449 static inline void dwc3_host_exit(struct dwc3 *dwc)
1453 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1454 int dwc3_gadget_init(struct dwc3 *dwc);
1455 void dwc3_gadget_exit(struct dwc3 *dwc);
1456 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1457 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1458 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1459 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1460 struct dwc3_gadget_ep_cmd_params *params);
1461 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1463 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1465 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1467 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1469 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1471 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1472 enum dwc3_link_state state)
1475 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1476 struct dwc3_gadget_ep_cmd_params *params)
1478 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1483 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1484 int dwc3_drd_init(struct dwc3 *dwc);
1485 void dwc3_drd_exit(struct dwc3 *dwc);
1486 void dwc3_otg_init(struct dwc3 *dwc);
1487 void dwc3_otg_exit(struct dwc3 *dwc);
1488 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1489 void dwc3_otg_host_init(struct dwc3 *dwc);
1491 static inline int dwc3_drd_init(struct dwc3 *dwc)
1493 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1495 static inline void dwc3_otg_init(struct dwc3 *dwc)
1497 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1499 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1501 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1505 /* power management interface */
1506 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1507 int dwc3_gadget_suspend(struct dwc3 *dwc);
1508 int dwc3_gadget_resume(struct dwc3 *dwc);
1509 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1511 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1516 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1521 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1524 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1526 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1527 int dwc3_ulpi_init(struct dwc3 *dwc);
1528 void dwc3_ulpi_exit(struct dwc3 *dwc);
1530 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1532 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1536 #endif /* __DRIVERS_USB_DWC3_CORE_H */