drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29 #include <linux/bitfield.h>
  30
  31 #include <linux/usb/ch9.h>
  32 #include <linux/usb/gadget.h>
  33 #include <linux/usb/of.h>
  34 #include <linux/usb/otg.h>
  35
  36 #include "core.h"
  37 #include "gadget.h"
  38 #include "io.h"
  39
  40 #include "debug.h"
  41
  42 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  43
  44 /**
  45  * dwc3_get_dr_mode - Validates and sets dr_mode
  46  * @dwc: pointer to our context structure
  47  */
  48 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  49 {
  50         enum usb_dr_mode mode;
  51         struct device *dev = dwc->dev;
  52         unsigned int hw_mode;
  53
  54         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  55                 dwc->dr_mode = USB_DR_MODE_OTG;
  56
  57         mode = dwc->dr_mode;
  58         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  59
  60         switch (hw_mode) {
  61         case DWC3_GHWPARAMS0_MODE_GADGET:
  62                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  63                         dev_err(dev,
  64                                 "Controller does not support host mode.\n");
  65                         return -EINVAL;
  66                 }
  67                 mode = USB_DR_MODE_PERIPHERAL;
  68                 break;
  69         case DWC3_GHWPARAMS0_MODE_HOST:
  70                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  71                         dev_err(dev,
  72                                 "Controller does not support device mode.\n");
  73                         return -EINVAL;
  74                 }
  75                 mode = USB_DR_MODE_HOST;
  76                 break;
  77         default:
  78                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  79                         mode = USB_DR_MODE_HOST;
  80                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  81                         mode = USB_DR_MODE_PERIPHERAL;
  82
  83                 /*
  84                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  85                  * mode. If the controller supports DRD but the dr_mode is not
  86                  * specified or set to OTG, then set the mode to peripheral.
  87                  */
  88                 if (mode == USB_DR_MODE_OTG &&
  89                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  90                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  91                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  92                         mode = USB_DR_MODE_PERIPHERAL;
  93         }
  94
  95         if (mode != dwc->dr_mode) {
  96                 dev_warn(dev,
  97                          "Configuration mismatch. dr_mode forced to %s\n",
  98                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  99
 100                 dwc->dr_mode = mode;
 101         }
 102
 103         return 0;
 104 }
 105
 106 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 107 {
 108         u32 reg;
 109
 110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 111         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 112         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 113         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 114
 115         dwc->current_dr_role = mode;
 116 }
 117
 118 static int dwc3_core_soft_reset(struct dwc3 *dwc);
 119
 120 static void __dwc3_set_mode(struct work_struct *work)
 121 {
 122         struct dwc3 *dwc = work_to_dwc(work);
 123         unsigned long flags;
 124         int ret;
 125         u32 reg;
 126
 127         mutex_lock(&dwc->mutex);
 128
 129         pm_runtime_get_sync(dwc->dev);
 130
 131         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 132                 dwc3_otg_update(dwc, 0);
 133
 134         if (!dwc->desired_dr_role)
 135                 goto out;
 136
 137         if (dwc->desired_dr_role == dwc->current_dr_role)
 138                 goto out;
 139
 140         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 141                 goto out;
 142
 143         switch (dwc->current_dr_role) {
 144         case DWC3_GCTL_PRTCAP_HOST:
 145                 dwc3_host_exit(dwc);
 146                 break;
 147         case DWC3_GCTL_PRTCAP_DEVICE:
 148                 dwc3_gadget_exit(dwc);
 149                 dwc3_event_buffers_cleanup(dwc);
 150                 break;
 151         case DWC3_GCTL_PRTCAP_OTG:
 152                 dwc3_otg_exit(dwc);
 153                 spin_lock_irqsave(&dwc->lock, flags);
 154                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 155                 spin_unlock_irqrestore(&dwc->lock, flags);
 156                 dwc3_otg_update(dwc, 1);
 157                 break;
 158         default:
 159                 break;
 160         }
 161
 162         /* For DRD host or device mode only */
 163         if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
 164                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 165                 reg |= DWC3_GCTL_CORESOFTRESET;
 166                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 167
 168                 /*
 169                  * Wait for internal clocks to synchronized. DWC_usb31 and
 170                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 171                  * keep it consistent across different IPs, let's wait up to
 172                  * 100ms before clearing GCTL.CORESOFTRESET.
 173                  */
 174                 msleep(100);
 175
 176                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 177                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 178                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 179         }
 180
 181         spin_lock_irqsave(&dwc->lock, flags);
 182
 183         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 184
 185         spin_unlock_irqrestore(&dwc->lock, flags);
 186
 187         switch (dwc->desired_dr_role) {
 188         case DWC3_GCTL_PRTCAP_HOST:
 189                 ret = dwc3_host_init(dwc);
 190                 if (ret) {
 191                         dev_err(dwc->dev, "failed to initialize host\n");
 192                 } else {
 193                         if (dwc->usb2_phy)
 194                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 195                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 196                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 197                         if (dwc->dis_split_quirk) {
 198                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 199                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 200                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 201                         }
 202                 }
 203                 break;
 204         case DWC3_GCTL_PRTCAP_DEVICE:
 205                 dwc3_core_soft_reset(dwc);
 206
 207                 dwc3_event_buffers_setup(dwc);
 208
 209                 if (dwc->usb2_phy)
 210                         otg_set_vbus(dwc->usb2_phy->otg, false);
 211                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 212                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 213
 214                 ret = dwc3_gadget_init(dwc);
 215                 if (ret)
 216                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 217                 break;
 218         case DWC3_GCTL_PRTCAP_OTG:
 219                 dwc3_otg_init(dwc);
 220                 dwc3_otg_update(dwc, 0);
 221                 break;
 222         default:
 223                 break;
 224         }
 225
 226 out:
 227         pm_runtime_mark_last_busy(dwc->dev);
 228         pm_runtime_put_autosuspend(dwc->dev);
 229         mutex_unlock(&dwc->mutex);
 230 }
 231
 232 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 233 {
 234         unsigned long flags;
 235
 236         if (dwc->dr_mode != USB_DR_MODE_OTG)
 237                 return;
 238
 239         spin_lock_irqsave(&dwc->lock, flags);
 240         dwc->desired_dr_role = mode;
 241         spin_unlock_irqrestore(&dwc->lock, flags);
 242
 243         queue_work(system_freezable_wq, &dwc->drd_work);
 244 }
 245
 246 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 247 {
 248         struct dwc3             *dwc = dep->dwc;
 249         u32                     reg;
 250
 251         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 252                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 253                         DWC3_GDBGFIFOSPACE_TYPE(type));
 254
 255         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 256
 257         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 258 }
 259
 260 /**
 261  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 262  * @dwc: pointer to our context structure
 263  */
 264 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 265 {
 266         u32             reg;
 267         int             retries = 1000;
 268
 269         /*
 270          * We're resetting only the device side because, if we're in host mode,
 271          * XHCI driver will reset the host block. If dwc3 was configured for
 272          * host-only mode, then we can return early.
 273          */
 274         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 275                 return 0;
 276
 277         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 278         reg |= DWC3_DCTL_CSFTRST;
 279         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 280
 281         /*
 282          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 283          * is cleared only after all the clocks are synchronized. This can
 284          * take a little more than 50ms. Set the polling rate at 20ms
 285          * for 10 times instead.
 286          */
 287         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 288                 retries = 10;
 289
 290         do {
 291                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 292                 if (!(reg & DWC3_DCTL_CSFTRST))
 293                         goto done;
 294
 295                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 296                         msleep(20);
 297                 else
 298                         udelay(1);
 299         } while (--retries);
 300
 301         return -ETIMEDOUT;
 302
 303 done:
 304         /*
 305          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 306          * is cleared, we must wait at least 50ms before accessing the PHY
 307          * domain (synchronization delay).
 308          */
 309         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 310                 msleep(50);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * dwc3_frame_length_adjustment - Adjusts frame length if required
 317  * @dwc3: Pointer to our controller context structure
 318  */
 319 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 320 {
 321         u32 reg;
 322         u32 dft;
 323
 324         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 325                 return;
 326
 327         if (dwc->fladj == 0)
 328                 return;
 329
 330         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 331         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 332         if (dft != dwc->fladj) {
 333                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 334                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 335                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 336         }
 337 }
 338
 339 /**
 340  * dwc3_ref_clk_period - Reference clock period configuration
 341  *              Default reference clock period depends on hardware
 342  *              configuration. For systems with reference clock that differs
 343  *              from the default, this will set clock period in DWC3_GUCTL
 344  *              register.
 345  * @dwc: Pointer to our controller context structure
 346  * @ref_clk_per: reference clock period in ns
 347  */
 348 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 349 {
 350         u32 reg;
 351
 352         if (dwc->ref_clk_per == 0)
 353                 return;
 354
 355         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 356         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 357         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per);
 358         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 359 }
 360
 361
 362 /**
 363  * dwc3_free_one_event_buffer - Frees one event buffer
 364  * @dwc: Pointer to our controller context structure
 365  * @evt: Pointer to event buffer to be freed
 366  */
 367 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 368                 struct dwc3_event_buffer *evt)
 369 {
 370         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 371 }
 372
 373 /**
 374  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 375  * @dwc: Pointer to our controller context structure
 376  * @length: size of the event buffer
 377  *
 378  * Returns a pointer to the allocated event buffer structure on success
 379  * otherwise ERR_PTR(errno).
 380  */
 381 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 382                 unsigned length)
 383 {
 384         struct dwc3_event_buffer        *evt;
 385
 386         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 387         if (!evt)
 388                 return ERR_PTR(-ENOMEM);
 389
 390         evt->dwc        = dwc;
 391         evt->length     = length;
 392         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 393         if (!evt->cache)
 394                 return ERR_PTR(-ENOMEM);
 395
 396         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 397                         &evt->dma, GFP_KERNEL);
 398         if (!evt->buf)
 399                 return ERR_PTR(-ENOMEM);
 400
 401         return evt;
 402 }
 403
 404 /**
 405  * dwc3_free_event_buffers - frees all allocated event buffers
 406  * @dwc: Pointer to our controller context structure
 407  */
 408 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 409 {
 410         struct dwc3_event_buffer        *evt;
 411
 412         evt = dwc->ev_buf;
 413         if (evt)
 414                 dwc3_free_one_event_buffer(dwc, evt);
 415 }
 416
 417 /**
 418  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 419  * @dwc: pointer to our controller context structure
 420  * @length: size of event buffer
 421  *
 422  * Returns 0 on success otherwise negative errno. In the error case, dwc
 423  * may contain some buffers allocated but not all which were requested.
 424  */
 425 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 426 {
 427         struct dwc3_event_buffer *evt;
 428
 429         evt = dwc3_alloc_one_event_buffer(dwc, length);
 430         if (IS_ERR(evt)) {
 431                 dev_err(dwc->dev, "can't allocate event buffer\n");
 432                 return PTR_ERR(evt);
 433         }
 434         dwc->ev_buf = evt;
 435
 436         return 0;
 437 }
 438
 439 /**
 440  * dwc3_event_buffers_setup - setup our allocated event buffers
 441  * @dwc: pointer to our controller context structure
 442  *
 443  * Returns 0 on success otherwise negative errno.
 444  */
 445 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 446 {
 447         struct dwc3_event_buffer        *evt;
 448
 449         evt = dwc->ev_buf;
 450         evt->lpos = 0;
 451         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 452                         lower_32_bits(evt->dma));
 453         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 454                         upper_32_bits(evt->dma));
 455         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 456                         DWC3_GEVNTSIZ_SIZE(evt->length));
 457         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 458
 459         return 0;
 460 }
 461
 462 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 463 {
 464         struct dwc3_event_buffer        *evt;
 465
 466         evt = dwc->ev_buf;
 467
 468         evt->lpos = 0;
 469
 470         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 471         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 472         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 473                         | DWC3_GEVNTSIZ_SIZE(0));
 474         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 475 }
 476
 477 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 478 {
 479         if (!dwc->has_hibernation)
 480                 return 0;
 481
 482         if (!dwc->nr_scratch)
 483                 return 0;
 484
 485         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 486                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 487         if (!dwc->scratchbuf)
 488                 return -ENOMEM;
 489
 490         return 0;
 491 }
 492
 493 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 494 {
 495         dma_addr_t scratch_addr;
 496         u32 param;
 497         int ret;
 498
 499         if (!dwc->has_hibernation)
 500                 return 0;
 501
 502         if (!dwc->nr_scratch)
 503                 return 0;
 504
 505          /* should never fall here */
 506         if (!WARN_ON(dwc->scratchbuf))
 507                 return 0;
 508
 509         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 510                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 511                         DMA_BIDIRECTIONAL);
 512         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 513                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 514                 ret = -EFAULT;
 515                 goto err0;
 516         }
 517
 518         dwc->scratch_addr = scratch_addr;
 519
 520         param = lower_32_bits(scratch_addr);
 521
 522         ret = dwc3_send_gadget_generic_command(dwc,
 523                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 524         if (ret < 0)
 525                 goto err1;
 526
 527         param = upper_32_bits(scratch_addr);
 528
 529         ret = dwc3_send_gadget_generic_command(dwc,
 530                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 531         if (ret < 0)
 532                 goto err1;
 533
 534         return 0;
 535
 536 err1:
 537         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 538                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 539
 540 err0:
 541         return ret;
 542 }
 543
 544 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 545 {
 546         if (!dwc->has_hibernation)
 547                 return;
 548
 549         if (!dwc->nr_scratch)
 550                 return;
 551
 552          /* should never fall here */
 553         if (!WARN_ON(dwc->scratchbuf))
 554                 return;
 555
 556         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 557                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 558         kfree(dwc->scratchbuf);
 559 }
 560
 561 static void dwc3_core_num_eps(struct dwc3 *dwc)
 562 {
 563         struct dwc3_hwparams    *parms = &dwc->hwparams;
 564
 565         dwc->num_eps = DWC3_NUM_EPS(parms);
 566 }
 567
 568 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 569 {
 570         struct dwc3_hwparams    *parms = &dwc->hwparams;
 571
 572         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 573         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 574         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 575         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 576         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 577         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 578         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 579         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 580         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 581
 582         if (DWC3_IP_IS(DWC32))
 583                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 584 }
 585
 586 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 587 {
 588         int intf;
 589         int ret = 0;
 590
 591         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 592
 593         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 594             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 595              dwc->hsphy_interface &&
 596              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 597                 ret = dwc3_ulpi_init(dwc);
 598
 599         return ret;
 600 }
 601
 602 /**
 603  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 604  * @dwc: Pointer to our controller context structure
 605  *
 606  * Returns 0 on success. The USB PHY interfaces are configured but not
 607  * initialized. The PHY interfaces and the PHYs get initialized together with
 608  * the core in dwc3_core_init.
 609  */
 610 static int dwc3_phy_setup(struct dwc3 *dwc)
 611 {
 612         unsigned int hw_mode;
 613         u32 reg;
 614
 615         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 616
 617         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 618
 619         /*
 620          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 621          * PHYs. Also, this bit is not supposed to be used in normal operation.
 622          */
 623         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 624
 625         /*
 626          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 627          * to '0' during coreConsultant configuration. So default value
 628          * will be '0' when the core is reset. Application needs to set it
 629          * to '1' after the core initialization is completed.
 630          */
 631         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 632                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 633
 634         /*
 635          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 636          * power-on reset, and it can be set after core initialization, which is
 637          * after device soft-reset during initialization.
 638          */
 639         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 640                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 641
 642         if (dwc->u2ss_inp3_quirk)
 643                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 644
 645         if (dwc->dis_rxdet_inp3_quirk)
 646                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 647
 648         if (dwc->req_p1p2p3_quirk)
 649                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 650
 651         if (dwc->del_p1p2p3_quirk)
 652                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 653
 654         if (dwc->del_phy_power_chg_quirk)
 655                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 656
 657         if (dwc->lfps_filter_quirk)
 658                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 659
 660         if (dwc->rx_detect_poll_quirk)
 661                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 662
 663         if (dwc->tx_de_emphasis_quirk)
 664                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 665
 666         if (dwc->dis_u3_susphy_quirk)
 667                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 668
 669         if (dwc->dis_del_phy_power_chg_quirk)
 670                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 671
 672         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 673
 674         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 675
 676         /* Select the HS PHY interface */
 677         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 678         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 679                 if (dwc->hsphy_interface &&
 680                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 681                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 682                         break;
 683                 } else if (dwc->hsphy_interface &&
 684                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 685                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 686                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 687                 } else {
 688                         /* Relying on default value. */
 689                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 690                                 break;
 691                 }
 692                 fallthrough;
 693         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 694         default:
 695                 break;
 696         }
 697
 698         switch (dwc->hsphy_mode) {
 699         case USBPHY_INTERFACE_MODE_UTMI:
 700                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 701                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 702                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 703                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 704                 break;
 705         case USBPHY_INTERFACE_MODE_UTMIW:
 706                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 707                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 708                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 709                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 710                 break;
 711         default:
 712                 break;
 713         }
 714
 715         /*
 716          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 717          * '0' during coreConsultant configuration. So default value will
 718          * be '0' when the core is reset. Application needs to set it to
 719          * '1' after the core initialization is completed.
 720          */
 721         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 722                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 723
 724         /*
 725          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 726          * power-on reset, and it can be set after core initialization, which is
 727          * after device soft-reset during initialization.
 728          */
 729         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 730                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 731
 732         if (dwc->dis_u2_susphy_quirk)
 733                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 734
 735         if (dwc->dis_enblslpm_quirk)
 736                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 737         else
 738                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 739
 740         if (dwc->dis_u2_freeclk_exists_quirk)
 741                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 742
 743         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 744
 745         return 0;
 746 }
 747
 748 static void dwc3_core_exit(struct dwc3 *dwc)
 749 {
 750         dwc3_event_buffers_cleanup(dwc);
 751
 752         usb_phy_shutdown(dwc->usb2_phy);
 753         usb_phy_shutdown(dwc->usb3_phy);
 754         phy_exit(dwc->usb2_generic_phy);
 755         phy_exit(dwc->usb3_generic_phy);
 756
 757         usb_phy_set_suspend(dwc->usb2_phy, 1);
 758         usb_phy_set_suspend(dwc->usb3_phy, 1);
 759         phy_power_off(dwc->usb2_generic_phy);
 760         phy_power_off(dwc->usb3_generic_phy);
 761         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 762         reset_control_assert(dwc->reset);
 763 }
 764
 765 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 766 {
 767         u32 reg;
 768
 769         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 770         dwc->ip = DWC3_GSNPS_ID(reg);
 771
 772         /* This should read as U3 followed by revision number */
 773         if (DWC3_IP_IS(DWC3)) {
 774                 dwc->revision = reg;
 775         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 776                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 777                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 778         } else {
 779                 return false;
 780         }
 781
 782         return true;
 783 }
 784
 785 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 786 {
 787         u32 hwparams4 = dwc->hwparams.hwparams4;
 788         u32 reg;
 789
 790         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 791         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 792
 793         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 794         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 795                 /**
 796                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 797                  * issue which would cause xHCI compliance tests to fail.
 798                  *
 799                  * Because of that we cannot enable clock gating on such
 800                  * configurations.
 801                  *
 802                  * Refers to:
 803                  *
 804                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 805                  * SOF/ITP Mode Used
 806                  */
 807                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 808                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 809                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 810                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 811                 else
 812                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 813                 break;
 814         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 815                 /* enable hibernation here */
 816                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 817
 818                 /*
 819                  * REVISIT Enabling this bit so that host-mode hibernation
 820                  * will work. Device-mode hibernation is not yet implemented.
 821                  */
 822                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 823                 break;
 824         default:
 825                 /* nothing */
 826                 break;
 827         }
 828
 829         /* check if current dwc3 is on simulation board */
 830         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 831                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 832                 dwc->is_fpga = true;
 833         }
 834
 835         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 836                         "disable_scramble cannot be used on non-FPGA builds\n");
 837
 838         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 839                 reg |= DWC3_GCTL_DISSCRAMBLE;
 840         else
 841                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 842
 843         if (dwc->u2exit_lfps_quirk)
 844                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 845
 846         /*
 847          * WORKAROUND: DWC3 revisions <1.90a have a bug
 848          * where the device can fail to connect at SuperSpeed
 849          * and falls back to high-speed mode which causes
 850          * the device to enter a Connect/Disconnect loop
 851          */
 852         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 853                 reg |= DWC3_GCTL_U2RSTECN;
 854
 855         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 856 }
 857
 858 static int dwc3_core_get_phy(struct dwc3 *dwc);
 859 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 860
 861 /* set global incr burst type configuration registers */
 862 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 863 {
 864         struct device *dev = dwc->dev;
 865         /* incrx_mode : for INCR burst type. */
 866         bool incrx_mode;
 867         /* incrx_size : for size of INCRX burst. */
 868         u32 incrx_size;
 869         u32 *vals;
 870         u32 cfg;
 871         int ntype;
 872         int ret;
 873         int i;
 874
 875         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 876
 877         /*
 878          * Handle property "snps,incr-burst-type-adjustment".
 879          * Get the number of value from this property:
 880          * result <= 0, means this property is not supported.
 881          * result = 1, means INCRx burst mode supported.
 882          * result > 1, means undefined length burst mode supported.
 883          */
 884         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 885         if (ntype <= 0)
 886                 return;
 887
 888         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 889         if (!vals) {
 890                 dev_err(dev, "Error to get memory\n");
 891                 return;
 892         }
 893
 894         /* Get INCR burst type, and parse it */
 895         ret = device_property_read_u32_array(dev,
 896                         "snps,incr-burst-type-adjustment", vals, ntype);
 897         if (ret) {
 898                 kfree(vals);
 899                 dev_err(dev, "Error to get property\n");
 900                 return;
 901         }
 902
 903         incrx_size = *vals;
 904
 905         if (ntype > 1) {
 906                 /* INCRX (undefined length) burst mode */
 907                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 908                 for (i = 1; i < ntype; i++) {
 909                         if (vals[i] > incrx_size)
 910                                 incrx_size = vals[i];
 911                 }
 912         } else {
 913                 /* INCRX burst mode */
 914                 incrx_mode = INCRX_BURST_MODE;
 915         }
 916
 917         kfree(vals);
 918
 919         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 920         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 921         if (incrx_mode)
 922                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 923         switch (incrx_size) {
 924         case 256:
 925                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 926                 break;
 927         case 128:
 928                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 929                 break;
 930         case 64:
 931                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 932                 break;
 933         case 32:
 934                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 935                 break;
 936         case 16:
 937                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 938                 break;
 939         case 8:
 940                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 941                 break;
 942         case 4:
 943                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 944                 break;
 945         case 1:
 946                 break;
 947         default:
 948                 dev_err(dev, "Invalid property\n");
 949                 break;
 950         }
 951
 952         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 953 }
 954
 955 /**
 956  * dwc3_core_init - Low-level initialization of DWC3 Core
 957  * @dwc: Pointer to our controller context structure
 958  *
 959  * Returns 0 on success otherwise negative errno.
 960  */
 961 static int dwc3_core_init(struct dwc3 *dwc)
 962 {
 963         unsigned int            hw_mode;
 964         u32                     reg;
 965         int                     ret;
 966
 967         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 968
 969         /*
 970          * Write Linux Version Code to our GUID register so it's easy to figure
 971          * out which kernel version a bug was found.
 972          */
 973         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 974
 975         ret = dwc3_phy_setup(dwc);
 976         if (ret)
 977                 goto err0;
 978
 979         if (!dwc->ulpi_ready) {
 980                 ret = dwc3_core_ulpi_init(dwc);
 981                 if (ret)
 982                         goto err0;
 983                 dwc->ulpi_ready = true;
 984         }
 985
 986         if (!dwc->phys_ready) {
 987                 ret = dwc3_core_get_phy(dwc);
 988                 if (ret)
 989                         goto err0a;
 990                 dwc->phys_ready = true;
 991         }
 992
 993         usb_phy_init(dwc->usb2_phy);
 994         usb_phy_init(dwc->usb3_phy);
 995         ret = phy_init(dwc->usb2_generic_phy);
 996         if (ret < 0)
 997                 goto err0a;
 998
 999         ret = phy_init(dwc->usb3_generic_phy);
1000         if (ret < 0) {
1001                 phy_exit(dwc->usb2_generic_phy);
1002                 goto err0a;
1003         }
1004
1005         ret = dwc3_core_soft_reset(dwc);
1006         if (ret)
1007                 goto err1;
1008
1009         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1010             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1011                 if (!dwc->dis_u3_susphy_quirk) {
1012                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1013                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1014                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1015                 }
1016
1017                 if (!dwc->dis_u2_susphy_quirk) {
1018                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1019                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1020                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1021                 }
1022         }
1023
1024         dwc3_core_setup_global_control(dwc);
1025         dwc3_core_num_eps(dwc);
1026
1027         ret = dwc3_setup_scratch_buffers(dwc);
1028         if (ret)
1029                 goto err1;
1030
1031         /* Adjust Frame Length */
1032         dwc3_frame_length_adjustment(dwc);
1033
1034         /* Adjust Reference Clock Period */
1035         dwc3_ref_clk_period(dwc);
1036
1037         dwc3_set_incr_burst_type(dwc);
1038
1039         usb_phy_set_suspend(dwc->usb2_phy, 0);
1040         usb_phy_set_suspend(dwc->usb3_phy, 0);
1041         ret = phy_power_on(dwc->usb2_generic_phy);
1042         if (ret < 0)
1043                 goto err2;
1044
1045         ret = phy_power_on(dwc->usb3_generic_phy);
1046         if (ret < 0)
1047                 goto err3;
1048
1049         ret = dwc3_event_buffers_setup(dwc);
1050         if (ret) {
1051                 dev_err(dwc->dev, "failed to setup event buffers\n");
1052                 goto err4;
1053         }
1054
1055         /*
1056          * ENDXFER polling is available on version 3.10a and later of
1057          * the DWC_usb3 controller. It is NOT available in the
1058          * DWC_usb31 controller.
1059          */
1060         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1061                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1062                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1063                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1064         }
1065
1066         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1067                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1068
1069                 /*
1070                  * Enable hardware control of sending remote wakeup
1071                  * in HS when the device is in the L1 state.
1072                  */
1073                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1074                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1075
1076                 /*
1077                  * Decouple USB 2.0 L1 & L2 events which will allow for
1078                  * gadget driver to only receive U3/L2 suspend & wakeup
1079                  * events and prevent the more frequent L1 LPM transitions
1080                  * from interrupting the driver.
1081                  */
1082                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1083                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1084
1085                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1086                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1087
1088                 if (dwc->parkmode_disable_ss_quirk)
1089                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1090
1091                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1092         }
1093
1094         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1095             dwc->dr_mode == USB_DR_MODE_OTG) {
1096                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1097
1098                 /*
1099                  * Enable Auto retry Feature to make the controller operating in
1100                  * Host mode on seeing transaction errors(CRC errors or internal
1101                  * overrun scenerios) on IN transfers to reply to the device
1102                  * with a non-terminating retry ACK (i.e, an ACK transcation
1103                  * packet with Retry=1 & Nump != 0)
1104                  */
1105                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1106
1107                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1108         }
1109
1110         /*
1111          * Must config both number of packets and max burst settings to enable
1112          * RX and/or TX threshold.
1113          */
1114         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1115                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1116                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1117                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1118                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1119
1120                 if (rx_thr_num && rx_maxburst) {
1121                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1122                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1123
1124                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1125                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1126
1127                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1128                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1129
1130                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1131                 }
1132
1133                 if (tx_thr_num && tx_maxburst) {
1134                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1135                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1136
1137                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1138                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1139
1140                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1141                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1142
1143                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1144                 }
1145         }
1146
1147         return 0;
1148
1149 err4:
1150         phy_power_off(dwc->usb3_generic_phy);
1151
1152 err3:
1153         phy_power_off(dwc->usb2_generic_phy);
1154
1155 err2:
1156         usb_phy_set_suspend(dwc->usb2_phy, 1);
1157         usb_phy_set_suspend(dwc->usb3_phy, 1);
1158
1159 err1:
1160         usb_phy_shutdown(dwc->usb2_phy);
1161         usb_phy_shutdown(dwc->usb3_phy);
1162         phy_exit(dwc->usb2_generic_phy);
1163         phy_exit(dwc->usb3_generic_phy);
1164
1165 err0a:
1166         dwc3_ulpi_exit(dwc);
1167
1168 err0:
1169         return ret;
1170 }
1171
1172 static int dwc3_core_get_phy(struct dwc3 *dwc)
1173 {
1174         struct device           *dev = dwc->dev;
1175         struct device_node      *node = dev->of_node;
1176         int ret;
1177
1178         if (node) {
1179                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1180                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1181         } else {
1182                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1183                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1184         }
1185
1186         if (IS_ERR(dwc->usb2_phy)) {
1187                 ret = PTR_ERR(dwc->usb2_phy);
1188                 if (ret == -ENXIO || ret == -ENODEV) {
1189                         dwc->usb2_phy = NULL;
1190                 } else {
1191                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1192                 }
1193         }
1194
1195         if (IS_ERR(dwc->usb3_phy)) {
1196                 ret = PTR_ERR(dwc->usb3_phy);
1197                 if (ret == -ENXIO || ret == -ENODEV) {
1198                         dwc->usb3_phy = NULL;
1199                 } else {
1200                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1201                 }
1202         }
1203
1204         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1205         if (IS_ERR(dwc->usb2_generic_phy)) {
1206                 ret = PTR_ERR(dwc->usb2_generic_phy);
1207                 if (ret == -ENOSYS || ret == -ENODEV) {
1208                         dwc->usb2_generic_phy = NULL;
1209                 } else {
1210                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1211                 }
1212         }
1213
1214         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1215         if (IS_ERR(dwc->usb3_generic_phy)) {
1216                 ret = PTR_ERR(dwc->usb3_generic_phy);
1217                 if (ret == -ENOSYS || ret == -ENODEV) {
1218                         dwc->usb3_generic_phy = NULL;
1219                 } else {
1220                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1221                 }
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int dwc3_core_init_mode(struct dwc3 *dwc)
1228 {
1229         struct device *dev = dwc->dev;
1230         int ret;
1231
1232         switch (dwc->dr_mode) {
1233         case USB_DR_MODE_PERIPHERAL:
1234                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1235
1236                 if (dwc->usb2_phy)
1237                         otg_set_vbus(dwc->usb2_phy->otg, false);
1238                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1239                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1240
1241                 ret = dwc3_gadget_init(dwc);
1242                 if (ret)
1243                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1244                 break;
1245         case USB_DR_MODE_HOST:
1246                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1247
1248                 if (dwc->usb2_phy)
1249                         otg_set_vbus(dwc->usb2_phy->otg, true);
1250                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1251                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1252
1253                 ret = dwc3_host_init(dwc);
1254                 if (ret)
1255                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1256                 break;
1257         case USB_DR_MODE_OTG:
1258                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1259                 ret = dwc3_drd_init(dwc);
1260                 if (ret)
1261                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1262                 break;
1263         default:
1264                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1265                 return -EINVAL;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1272 {
1273         switch (dwc->dr_mode) {
1274         case USB_DR_MODE_PERIPHERAL:
1275                 dwc3_gadget_exit(dwc);
1276                 break;
1277         case USB_DR_MODE_HOST:
1278                 dwc3_host_exit(dwc);
1279                 break;
1280         case USB_DR_MODE_OTG:
1281                 dwc3_drd_exit(dwc);
1282                 break;
1283         default:
1284                 /* do nothing */
1285                 break;
1286         }
1287
1288         /* de-assert DRVVBUS for HOST and OTG mode */
1289         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1290 }
1291
1292 static void dwc3_get_properties(struct dwc3 *dwc)
1293 {
1294         struct device           *dev = dwc->dev;
1295         u8                      lpm_nyet_threshold;
1296         u8                      tx_de_emphasis;
1297         u8                      hird_threshold;
1298         u8                      rx_thr_num_pkt_prd;
1299         u8                      rx_max_burst_prd;
1300         u8                      tx_thr_num_pkt_prd;
1301         u8                      tx_max_burst_prd;
1302         u8                      tx_fifo_resize_max_num;
1303         const char              *usb_psy_name;
1304         int                     ret;
1305
1306         /* default to highest possible threshold */
1307         lpm_nyet_threshold = 0xf;
1308
1309         /* default to -3.5dB de-emphasis */
1310         tx_de_emphasis = 1;
1311
1312         /*
1313          * default to assert utmi_sleep_n and use maximum allowed HIRD
1314          * threshold value of 0b1100
1315          */
1316         hird_threshold = 12;
1317
1318         /*
1319          * default to a TXFIFO size large enough to fit 6 max packets.  This
1320          * allows for systems with larger bus latencies to have some headroom
1321          * for endpoints that have a large bMaxBurst value.
1322          */
1323         tx_fifo_resize_max_num = 6;
1324
1325         dwc->maximum_speed = usb_get_maximum_speed(dev);
1326         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1327         dwc->dr_mode = usb_get_dr_mode(dev);
1328         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1329
1330         dwc->sysdev_is_parent = device_property_read_bool(dev,
1331                                 "linux,sysdev_is_parent");
1332         if (dwc->sysdev_is_parent)
1333                 dwc->sysdev = dwc->dev->parent;
1334         else
1335                 dwc->sysdev = dwc->dev;
1336
1337         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1338         if (ret >= 0) {
1339                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1340                 if (!dwc->usb_psy)
1341                         dev_err(dev, "couldn't get usb power supply\n");
1342         }
1343
1344         dwc->has_lpm_erratum = device_property_read_bool(dev,
1345                                 "snps,has-lpm-erratum");
1346         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1347                                 &lpm_nyet_threshold);
1348         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1349                                 "snps,is-utmi-l1-suspend");
1350         device_property_read_u8(dev, "snps,hird-threshold",
1351                                 &hird_threshold);
1352         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1353                                 "snps,dis-start-transfer-quirk");
1354         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1355                                 "snps,usb3_lpm_capable");
1356         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1357                                 "snps,usb2-lpm-disable");
1358         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1359                                 "snps,usb2-gadget-lpm-disable");
1360         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1361                                 &rx_thr_num_pkt_prd);
1362         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1363                                 &rx_max_burst_prd);
1364         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1365                                 &tx_thr_num_pkt_prd);
1366         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1367                                 &tx_max_burst_prd);
1368         dwc->do_fifo_resize = device_property_read_bool(dev,
1369                                                         "tx-fifo-resize");
1370         if (dwc->do_fifo_resize)
1371                 device_property_read_u8(dev, "tx-fifo-max-num",
1372                                         &tx_fifo_resize_max_num);
1373
1374         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1375                                 "snps,disable_scramble_quirk");
1376         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1377                                 "snps,u2exit_lfps_quirk");
1378         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1379                                 "snps,u2ss_inp3_quirk");
1380         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1381                                 "snps,req_p1p2p3_quirk");
1382         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1383                                 "snps,del_p1p2p3_quirk");
1384         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1385                                 "snps,del_phy_power_chg_quirk");
1386         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1387                                 "snps,lfps_filter_quirk");
1388         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1389                                 "snps,rx_detect_poll_quirk");
1390         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1391                                 "snps,dis_u3_susphy_quirk");
1392         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1393                                 "snps,dis_u2_susphy_quirk");
1394         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1395                                 "snps,dis_enblslpm_quirk");
1396         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1397                                 "snps,dis-u1-entry-quirk");
1398         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1399                                 "snps,dis-u2-entry-quirk");
1400         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1401                                 "snps,dis_rxdet_inp3_quirk");
1402         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1403                                 "snps,dis-u2-freeclk-exists-quirk");
1404         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1405                                 "snps,dis-del-phy-power-chg-quirk");
1406         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1407                                 "snps,dis-tx-ipgap-linecheck-quirk");
1408         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1409                                 "snps,parkmode-disable-ss-quirk");
1410
1411         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1412                                 "snps,tx_de_emphasis_quirk");
1413         device_property_read_u8(dev, "snps,tx_de_emphasis",
1414                                 &tx_de_emphasis);
1415         device_property_read_string(dev, "snps,hsphy_interface",
1416                                     &dwc->hsphy_interface);
1417         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1418                                  &dwc->fladj);
1419         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1420                                  &dwc->ref_clk_per);
1421
1422         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1423                                 "snps,dis_metastability_quirk");
1424
1425         dwc->dis_split_quirk = device_property_read_bool(dev,
1426                                 "snps,dis-split-quirk");
1427
1428         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1429         dwc->tx_de_emphasis = tx_de_emphasis;
1430
1431         dwc->hird_threshold = hird_threshold;
1432
1433         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1434         dwc->rx_max_burst_prd = rx_max_burst_prd;
1435
1436         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1437         dwc->tx_max_burst_prd = tx_max_burst_prd;
1438
1439         dwc->imod_interval = 0;
1440
1441         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1442 }
1443
1444 /* check whether the core supports IMOD */
1445 bool dwc3_has_imod(struct dwc3 *dwc)
1446 {
1447         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1448                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1449                 DWC3_IP_IS(DWC32);
1450 }
1451
1452 static void dwc3_check_params(struct dwc3 *dwc)
1453 {
1454         struct device *dev = dwc->dev;
1455         unsigned int hwparam_gen =
1456                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1457
1458         /* Check for proper value of imod_interval */
1459         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1460                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1461                 dwc->imod_interval = 0;
1462         }
1463
1464         /*
1465          * Workaround for STAR 9000961433 which affects only version
1466          * 3.00a of the DWC_usb3 core. This prevents the controller
1467          * interrupt from being masked while handling events. IMOD
1468          * allows us to work around this issue. Enable it for the
1469          * affected version.
1470          */
1471         if (!dwc->imod_interval &&
1472             DWC3_VER_IS(DWC3, 300A))
1473                 dwc->imod_interval = 1;
1474
1475         /* Check the maximum_speed parameter */
1476         switch (dwc->maximum_speed) {
1477         case USB_SPEED_FULL:
1478         case USB_SPEED_HIGH:
1479                 break;
1480         case USB_SPEED_SUPER:
1481                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1482                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1483                 break;
1484         case USB_SPEED_SUPER_PLUS:
1485                 if ((DWC3_IP_IS(DWC32) &&
1486                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1487                     (!DWC3_IP_IS(DWC32) &&
1488                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1489                         dev_warn(dev, "UDC doesn't support SSP\n");
1490                 break;
1491         default:
1492                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1493                         dwc->maximum_speed);
1494                 fallthrough;
1495         case USB_SPEED_UNKNOWN:
1496                 switch (hwparam_gen) {
1497                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1498                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1499                         break;
1500                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1501                         if (DWC3_IP_IS(DWC32))
1502                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1503                         else
1504                                 dwc->maximum_speed = USB_SPEED_SUPER;
1505                         break;
1506                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1507                         dwc->maximum_speed = USB_SPEED_HIGH;
1508                         break;
1509                 default:
1510                         dwc->maximum_speed = USB_SPEED_SUPER;
1511                         break;
1512                 }
1513                 break;
1514         }
1515
1516         /*
1517          * Currently the controller does not have visibility into the HW
1518          * parameter to determine the maximum number of lanes the HW supports.
1519          * If the number of lanes is not specified in the device property, then
1520          * set the default to support dual-lane for DWC_usb32 and single-lane
1521          * for DWC_usb31 for super-speed-plus.
1522          */
1523         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1524                 switch (dwc->max_ssp_rate) {
1525                 case USB_SSP_GEN_2x1:
1526                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1527                                 dev_warn(dev, "UDC only supports Gen 1\n");
1528                         break;
1529                 case USB_SSP_GEN_1x2:
1530                 case USB_SSP_GEN_2x2:
1531                         if (DWC3_IP_IS(DWC31))
1532                                 dev_warn(dev, "UDC only supports single lane\n");
1533                         break;
1534                 case USB_SSP_GEN_UNKNOWN:
1535                 default:
1536                         switch (hwparam_gen) {
1537                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1538                                 if (DWC3_IP_IS(DWC32))
1539                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1540                                 else
1541                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1542                                 break;
1543                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1544                                 if (DWC3_IP_IS(DWC32))
1545                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1546                                 break;
1547                         }
1548                         break;
1549                 }
1550         }
1551 }
1552
1553 static int dwc3_probe(struct platform_device *pdev)
1554 {
1555         struct device           *dev = &pdev->dev;
1556         struct resource         *res, dwc_res;
1557         struct dwc3             *dwc;
1558
1559         int                     ret;
1560
1561         void __iomem            *regs;
1562
1563         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1564         if (!dwc)
1565                 return -ENOMEM;
1566
1567         dwc->dev = dev;
1568
1569         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1570         if (!res) {
1571                 dev_err(dev, "missing memory resource\n");
1572                 return -ENODEV;
1573         }
1574
1575         dwc->xhci_resources[0].start = res->start;
1576         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1577                                         DWC3_XHCI_REGS_END;
1578         dwc->xhci_resources[0].flags = res->flags;
1579         dwc->xhci_resources[0].name = res->name;
1580
1581         /*
1582          * Request memory region but exclude xHCI regs,
1583          * since it will be requested by the xhci-plat driver.
1584          */
1585         dwc_res = *res;
1586         dwc_res.start += DWC3_GLOBALS_REGS_START;
1587
1588         regs = devm_ioremap_resource(dev, &dwc_res);
1589         if (IS_ERR(regs))
1590                 return PTR_ERR(regs);
1591
1592         dwc->regs       = regs;
1593         dwc->regs_size  = resource_size(&dwc_res);
1594
1595         dwc3_get_properties(dwc);
1596
1597         if (!dwc->sysdev_is_parent) {
1598                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1599                 if (ret)
1600                         return ret;
1601         }
1602
1603         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1604         if (IS_ERR(dwc->reset))
1605                 return PTR_ERR(dwc->reset);
1606
1607         if (dev->of_node) {
1608                 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1609                 if (ret == -EPROBE_DEFER)
1610                         return ret;
1611                 /*
1612                  * Clocks are optional, but new DT platforms should support all
1613                  * clocks as required by the DT-binding.
1614                  */
1615                 if (ret < 0)
1616                         dwc->num_clks = 0;
1617                 else
1618                         dwc->num_clks = ret;
1619
1620         }
1621
1622         ret = reset_control_deassert(dwc->reset);
1623         if (ret)
1624                 return ret;
1625
1626         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1627         if (ret)
1628                 goto assert_reset;
1629
1630         if (!dwc3_core_is_valid(dwc)) {
1631                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1632                 ret = -ENODEV;
1633                 goto disable_clks;
1634         }
1635
1636         platform_set_drvdata(pdev, dwc);
1637         dwc3_cache_hwparams(dwc);
1638
1639         spin_lock_init(&dwc->lock);
1640         mutex_init(&dwc->mutex);
1641
1642         pm_runtime_set_active(dev);
1643         pm_runtime_use_autosuspend(dev);
1644         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1645         pm_runtime_enable(dev);
1646         ret = pm_runtime_get_sync(dev);
1647         if (ret < 0)
1648                 goto err1;
1649
1650         pm_runtime_forbid(dev);
1651
1652         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1653         if (ret) {
1654                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1655                 ret = -ENOMEM;
1656                 goto err2;
1657         }
1658
1659         ret = dwc3_get_dr_mode(dwc);
1660         if (ret)
1661                 goto err3;
1662
1663         ret = dwc3_alloc_scratch_buffers(dwc);
1664         if (ret)
1665                 goto err3;
1666
1667         ret = dwc3_core_init(dwc);
1668         if (ret) {
1669                 dev_err_probe(dev, ret, "failed to initialize core\n");
1670                 goto err4;
1671         }
1672
1673         dwc3_check_params(dwc);
1674         dwc3_debugfs_init(dwc);
1675
1676         ret = dwc3_core_init_mode(dwc);
1677         if (ret)
1678                 goto err5;
1679
1680         pm_runtime_put(dev);
1681
1682         return 0;
1683
1684 err5:
1685         dwc3_debugfs_exit(dwc);
1686         dwc3_event_buffers_cleanup(dwc);
1687
1688         usb_phy_shutdown(dwc->usb2_phy);
1689         usb_phy_shutdown(dwc->usb3_phy);
1690         phy_exit(dwc->usb2_generic_phy);
1691         phy_exit(dwc->usb3_generic_phy);
1692
1693         usb_phy_set_suspend(dwc->usb2_phy, 1);
1694         usb_phy_set_suspend(dwc->usb3_phy, 1);
1695         phy_power_off(dwc->usb2_generic_phy);
1696         phy_power_off(dwc->usb3_generic_phy);
1697
1698         dwc3_ulpi_exit(dwc);
1699
1700 err4:
1701         dwc3_free_scratch_buffers(dwc);
1702
1703 err3:
1704         dwc3_free_event_buffers(dwc);
1705
1706 err2:
1707         pm_runtime_allow(&pdev->dev);
1708
1709 err1:
1710         pm_runtime_put_sync(&pdev->dev);
1711         pm_runtime_disable(&pdev->dev);
1712
1713 disable_clks:
1714         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1715 assert_reset:
1716         reset_control_assert(dwc->reset);
1717
1718         if (dwc->usb_psy)
1719                 power_supply_put(dwc->usb_psy);
1720
1721         return ret;
1722 }
1723
1724 static int dwc3_remove(struct platform_device *pdev)
1725 {
1726         struct dwc3     *dwc = platform_get_drvdata(pdev);
1727
1728         pm_runtime_get_sync(&pdev->dev);
1729
1730         dwc3_core_exit_mode(dwc);
1731         dwc3_debugfs_exit(dwc);
1732
1733         dwc3_core_exit(dwc);
1734         dwc3_ulpi_exit(dwc);
1735
1736         pm_runtime_disable(&pdev->dev);
1737         pm_runtime_put_noidle(&pdev->dev);
1738         pm_runtime_set_suspended(&pdev->dev);
1739
1740         dwc3_free_event_buffers(dwc);
1741         dwc3_free_scratch_buffers(dwc);
1742
1743         if (dwc->usb_psy)
1744                 power_supply_put(dwc->usb_psy);
1745
1746         return 0;
1747 }
1748
1749 #ifdef CONFIG_PM
1750 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1751 {
1752         int ret;
1753
1754         ret = reset_control_deassert(dwc->reset);
1755         if (ret)
1756                 return ret;
1757
1758         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1759         if (ret)
1760                 goto assert_reset;
1761
1762         ret = dwc3_core_init(dwc);
1763         if (ret)
1764                 goto disable_clks;
1765
1766         return 0;
1767
1768 disable_clks:
1769         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1770 assert_reset:
1771         reset_control_assert(dwc->reset);
1772
1773         return ret;
1774 }
1775
1776 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1777 {
1778         unsigned long   flags;
1779         u32 reg;
1780
1781         switch (dwc->current_dr_role) {
1782         case DWC3_GCTL_PRTCAP_DEVICE:
1783                 if (pm_runtime_suspended(dwc->dev))
1784                         break;
1785                 spin_lock_irqsave(&dwc->lock, flags);
1786                 dwc3_gadget_suspend(dwc);
1787                 spin_unlock_irqrestore(&dwc->lock, flags);
1788                 synchronize_irq(dwc->irq_gadget);
1789                 dwc3_core_exit(dwc);
1790                 break;
1791         case DWC3_GCTL_PRTCAP_HOST:
1792                 if (!PMSG_IS_AUTO(msg)) {
1793                         dwc3_core_exit(dwc);
1794                         break;
1795                 }
1796
1797                 /* Let controller to suspend HSPHY before PHY driver suspends */
1798                 if (dwc->dis_u2_susphy_quirk ||
1799                     dwc->dis_enblslpm_quirk) {
1800                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1801                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1802                                 DWC3_GUSB2PHYCFG_SUSPHY;
1803                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1804
1805                         /* Give some time for USB2 PHY to suspend */
1806                         usleep_range(5000, 6000);
1807                 }
1808
1809                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1810                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1811                 break;
1812         case DWC3_GCTL_PRTCAP_OTG:
1813                 /* do nothing during runtime_suspend */
1814                 if (PMSG_IS_AUTO(msg))
1815                         break;
1816
1817                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1818                         spin_lock_irqsave(&dwc->lock, flags);
1819                         dwc3_gadget_suspend(dwc);
1820                         spin_unlock_irqrestore(&dwc->lock, flags);
1821                         synchronize_irq(dwc->irq_gadget);
1822                 }
1823
1824                 dwc3_otg_exit(dwc);
1825                 dwc3_core_exit(dwc);
1826                 break;
1827         default:
1828                 /* do nothing */
1829                 break;
1830         }
1831
1832         return 0;
1833 }
1834
1835 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1836 {
1837         unsigned long   flags;
1838         int             ret;
1839         u32             reg;
1840
1841         switch (dwc->current_dr_role) {
1842         case DWC3_GCTL_PRTCAP_DEVICE:
1843                 ret = dwc3_core_init_for_resume(dwc);
1844                 if (ret)
1845                         return ret;
1846
1847                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1848                 spin_lock_irqsave(&dwc->lock, flags);
1849                 dwc3_gadget_resume(dwc);
1850                 spin_unlock_irqrestore(&dwc->lock, flags);
1851                 break;
1852         case DWC3_GCTL_PRTCAP_HOST:
1853                 if (!PMSG_IS_AUTO(msg)) {
1854                         ret = dwc3_core_init_for_resume(dwc);
1855                         if (ret)
1856                                 return ret;
1857                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1858                         break;
1859                 }
1860                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1861                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1862                 if (dwc->dis_u2_susphy_quirk)
1863                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1864
1865                 if (dwc->dis_enblslpm_quirk)
1866                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1867
1868                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1869
1870                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1871                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1872                 break;
1873         case DWC3_GCTL_PRTCAP_OTG:
1874                 /* nothing to do on runtime_resume */
1875                 if (PMSG_IS_AUTO(msg))
1876                         break;
1877
1878                 ret = dwc3_core_init_for_resume(dwc);
1879                 if (ret)
1880                         return ret;
1881
1882                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1883
1884                 dwc3_otg_init(dwc);
1885                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1886                         dwc3_otg_host_init(dwc);
1887                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1888                         spin_lock_irqsave(&dwc->lock, flags);
1889                         dwc3_gadget_resume(dwc);
1890                         spin_unlock_irqrestore(&dwc->lock, flags);
1891                 }
1892
1893                 break;
1894         default:
1895                 /* do nothing */
1896                 break;
1897         }
1898
1899         return 0;
1900 }
1901
1902 static int dwc3_runtime_checks(struct dwc3 *dwc)
1903 {
1904         switch (dwc->current_dr_role) {
1905         case DWC3_GCTL_PRTCAP_DEVICE:
1906                 if (dwc->connected)
1907                         return -EBUSY;
1908                 break;
1909         case DWC3_GCTL_PRTCAP_HOST:
1910         default:
1911                 /* do nothing */
1912                 break;
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int dwc3_runtime_suspend(struct device *dev)
1919 {
1920         struct dwc3     *dwc = dev_get_drvdata(dev);
1921         int             ret;
1922
1923         if (dwc3_runtime_checks(dwc))
1924                 return -EBUSY;
1925
1926         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1927         if (ret)
1928                 return ret;
1929
1930         device_init_wakeup(dev, true);
1931
1932         return 0;
1933 }
1934
1935 static int dwc3_runtime_resume(struct device *dev)
1936 {
1937         struct dwc3     *dwc = dev_get_drvdata(dev);
1938         int             ret;
1939
1940         device_init_wakeup(dev, false);
1941
1942         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1943         if (ret)
1944                 return ret;
1945
1946         switch (dwc->current_dr_role) {
1947         case DWC3_GCTL_PRTCAP_DEVICE:
1948                 dwc3_gadget_process_pending_events(dwc);
1949                 break;
1950         case DWC3_GCTL_PRTCAP_HOST:
1951         default:
1952                 /* do nothing */
1953                 break;
1954         }
1955
1956         pm_runtime_mark_last_busy(dev);
1957
1958         return 0;
1959 }
1960
1961 static int dwc3_runtime_idle(struct device *dev)
1962 {
1963         struct dwc3     *dwc = dev_get_drvdata(dev);
1964
1965         switch (dwc->current_dr_role) {
1966         case DWC3_GCTL_PRTCAP_DEVICE:
1967                 if (dwc3_runtime_checks(dwc))
1968                         return -EBUSY;
1969                 break;
1970         case DWC3_GCTL_PRTCAP_HOST:
1971         default:
1972                 /* do nothing */
1973                 break;
1974         }
1975
1976         pm_runtime_mark_last_busy(dev);
1977         pm_runtime_autosuspend(dev);
1978
1979         return 0;
1980 }
1981 #endif /* CONFIG_PM */
1982
1983 #ifdef CONFIG_PM_SLEEP
1984 static int dwc3_suspend(struct device *dev)
1985 {
1986         struct dwc3     *dwc = dev_get_drvdata(dev);
1987         int             ret;
1988
1989         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1990         if (ret)
1991                 return ret;
1992
1993         pinctrl_pm_select_sleep_state(dev);
1994
1995         return 0;
1996 }
1997
1998 static int dwc3_resume(struct device *dev)
1999 {
2000         struct dwc3     *dwc = dev_get_drvdata(dev);
2001         int             ret;
2002
2003         pinctrl_pm_select_default_state(dev);
2004
2005         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2006         if (ret)
2007                 return ret;
2008
2009         pm_runtime_disable(dev);
2010         pm_runtime_set_active(dev);
2011         pm_runtime_enable(dev);
2012
2013         return 0;
2014 }
2015
2016 static void dwc3_complete(struct device *dev)
2017 {
2018         struct dwc3     *dwc = dev_get_drvdata(dev);
2019         u32             reg;
2020
2021         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2022                         dwc->dis_split_quirk) {
2023                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2024                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2025                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2026         }
2027 }
2028 #else
2029 #define dwc3_complete NULL
2030 #endif /* CONFIG_PM_SLEEP */
2031
2032 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2033         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2034         .complete = dwc3_complete,
2035         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2036                         dwc3_runtime_idle)
2037 };
2038
2039 #ifdef CONFIG_OF
2040 static const struct of_device_id of_dwc3_match[] = {
2041         {
2042                 .compatible = "snps,dwc3"
2043         },
2044         {
2045                 .compatible = "synopsys,dwc3"
2046         },
2047         { },
2048 };
2049 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2050 #endif
2051
2052 #ifdef CONFIG_ACPI
2053
2054 #define ACPI_ID_INTEL_BSW       "808622B7"
2055
2056 static const struct acpi_device_id dwc3_acpi_match[] = {
2057         { ACPI_ID_INTEL_BSW, 0 },
2058         { },
2059 };
2060 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2061 #endif
2062
2063 static struct platform_driver dwc3_driver = {
2064         .probe          = dwc3_probe,
2065         .remove         = dwc3_remove,
2066         .driver         = {
2067                 .name   = "dwc3",
2068                 .of_match_table = of_match_ptr(of_dwc3_match),
2069                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2070                 .pm     = &dwc3_dev_pm_ops,
2071         },
2072 };
2073
2074 module_platform_driver(dwc3_driver);
2075
2076 MODULE_ALIAS("platform:dwc3");
2077 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2078 MODULE_LICENSE("GPL v2");
2079 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");