1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
63 "Controller does not support host mode.\n");
66 mode = USB_DR_MODE_PERIPHERAL;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
71 "Controller does not support device mode.\n");
74 mode = USB_DR_MODE_HOST;
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
94 if (mode != dwc->dr_mode) {
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114 dwc->current_dr_role = mode;
117 static void __dwc3_set_mode(struct work_struct *work)
119 struct dwc3 *dwc = work_to_dwc(work);
124 pm_runtime_get_sync(dwc->dev);
126 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
127 dwc3_otg_update(dwc, 0);
129 if (!dwc->desired_dr_role)
132 if (dwc->desired_dr_role == dwc->current_dr_role)
135 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
138 switch (dwc->current_dr_role) {
139 case DWC3_GCTL_PRTCAP_HOST:
142 case DWC3_GCTL_PRTCAP_DEVICE:
143 dwc3_gadget_exit(dwc);
144 dwc3_event_buffers_cleanup(dwc);
146 case DWC3_GCTL_PRTCAP_OTG:
148 spin_lock_irqsave(&dwc->lock, flags);
149 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
150 spin_unlock_irqrestore(&dwc->lock, flags);
151 dwc3_otg_update(dwc, 1);
157 spin_lock_irqsave(&dwc->lock, flags);
159 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
161 spin_unlock_irqrestore(&dwc->lock, flags);
163 switch (dwc->desired_dr_role) {
164 case DWC3_GCTL_PRTCAP_HOST:
165 ret = dwc3_host_init(dwc);
167 dev_err(dwc->dev, "failed to initialize host\n");
170 otg_set_vbus(dwc->usb2_phy->otg, true);
171 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
172 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
173 if (dwc->dis_split_quirk) {
174 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
175 reg |= DWC3_GUCTL3_SPLITDISABLE;
176 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
180 case DWC3_GCTL_PRTCAP_DEVICE:
181 dwc3_event_buffers_setup(dwc);
184 otg_set_vbus(dwc->usb2_phy->otg, false);
185 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
186 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
188 ret = dwc3_gadget_init(dwc);
190 dev_err(dwc->dev, "failed to initialize peripheral\n");
192 case DWC3_GCTL_PRTCAP_OTG:
194 dwc3_otg_update(dwc, 0);
201 pm_runtime_mark_last_busy(dwc->dev);
202 pm_runtime_put_autosuspend(dwc->dev);
205 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
209 if (dwc->dr_mode != USB_DR_MODE_OTG)
212 spin_lock_irqsave(&dwc->lock, flags);
213 dwc->desired_dr_role = mode;
214 spin_unlock_irqrestore(&dwc->lock, flags);
216 queue_work(system_freezable_wq, &dwc->drd_work);
219 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
221 struct dwc3 *dwc = dep->dwc;
224 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
225 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
226 DWC3_GDBGFIFOSPACE_TYPE(type));
228 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
230 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
234 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
235 * @dwc: pointer to our context structure
237 static int dwc3_core_soft_reset(struct dwc3 *dwc)
243 usb_phy_init(dwc->usb2_phy);
244 usb_phy_init(dwc->usb3_phy);
245 ret = phy_init(dwc->usb2_generic_phy);
249 ret = phy_init(dwc->usb3_generic_phy);
251 phy_exit(dwc->usb2_generic_phy);
256 * We're resetting only the device side because, if we're in host mode,
257 * XHCI driver will reset the host block. If dwc3 was configured for
258 * host-only mode, then we can return early.
260 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
263 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
264 reg |= DWC3_DCTL_CSFTRST;
265 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
268 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
269 * is cleared only after all the clocks are synchronized. This can
270 * take a little more than 50ms. Set the polling rate at 20ms
271 * for 10 times instead.
273 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
277 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
278 if (!(reg & DWC3_DCTL_CSFTRST))
281 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
287 phy_exit(dwc->usb3_generic_phy);
288 phy_exit(dwc->usb2_generic_phy);
294 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
295 * is cleared, we must wait at least 50ms before accessing the PHY
296 * domain (synchronization delay).
298 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
305 * dwc3_frame_length_adjustment - Adjusts frame length if required
306 * @dwc3: Pointer to our controller context structure
308 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
313 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
319 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
320 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
321 if (dft != dwc->fladj) {
322 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
323 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
324 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
329 * dwc3_free_one_event_buffer - Frees one event buffer
330 * @dwc: Pointer to our controller context structure
331 * @evt: Pointer to event buffer to be freed
333 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
334 struct dwc3_event_buffer *evt)
336 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
340 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
341 * @dwc: Pointer to our controller context structure
342 * @length: size of the event buffer
344 * Returns a pointer to the allocated event buffer structure on success
345 * otherwise ERR_PTR(errno).
347 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
350 struct dwc3_event_buffer *evt;
352 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
354 return ERR_PTR(-ENOMEM);
357 evt->length = length;
358 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
360 return ERR_PTR(-ENOMEM);
362 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
363 &evt->dma, GFP_KERNEL);
365 return ERR_PTR(-ENOMEM);
371 * dwc3_free_event_buffers - frees all allocated event buffers
372 * @dwc: Pointer to our controller context structure
374 static void dwc3_free_event_buffers(struct dwc3 *dwc)
376 struct dwc3_event_buffer *evt;
380 dwc3_free_one_event_buffer(dwc, evt);
384 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
385 * @dwc: pointer to our controller context structure
386 * @length: size of event buffer
388 * Returns 0 on success otherwise negative errno. In the error case, dwc
389 * may contain some buffers allocated but not all which were requested.
391 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
393 struct dwc3_event_buffer *evt;
395 evt = dwc3_alloc_one_event_buffer(dwc, length);
397 dev_err(dwc->dev, "can't allocate event buffer\n");
406 * dwc3_event_buffers_setup - setup our allocated event buffers
407 * @dwc: pointer to our controller context structure
409 * Returns 0 on success otherwise negative errno.
411 int dwc3_event_buffers_setup(struct dwc3 *dwc)
413 struct dwc3_event_buffer *evt;
417 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
418 lower_32_bits(evt->dma));
419 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
420 upper_32_bits(evt->dma));
421 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
422 DWC3_GEVNTSIZ_SIZE(evt->length));
423 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
428 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
430 struct dwc3_event_buffer *evt;
436 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
437 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
438 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
439 | DWC3_GEVNTSIZ_SIZE(0));
440 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
443 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
445 if (!dwc->has_hibernation)
448 if (!dwc->nr_scratch)
451 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
452 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
453 if (!dwc->scratchbuf)
459 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
461 dma_addr_t scratch_addr;
465 if (!dwc->has_hibernation)
468 if (!dwc->nr_scratch)
471 /* should never fall here */
472 if (!WARN_ON(dwc->scratchbuf))
475 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
476 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
478 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
479 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
484 dwc->scratch_addr = scratch_addr;
486 param = lower_32_bits(scratch_addr);
488 ret = dwc3_send_gadget_generic_command(dwc,
489 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
493 param = upper_32_bits(scratch_addr);
495 ret = dwc3_send_gadget_generic_command(dwc,
496 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
503 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
504 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
510 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
512 if (!dwc->has_hibernation)
515 if (!dwc->nr_scratch)
518 /* should never fall here */
519 if (!WARN_ON(dwc->scratchbuf))
522 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
523 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
524 kfree(dwc->scratchbuf);
527 static void dwc3_core_num_eps(struct dwc3 *dwc)
529 struct dwc3_hwparams *parms = &dwc->hwparams;
531 dwc->num_eps = DWC3_NUM_EPS(parms);
534 static void dwc3_cache_hwparams(struct dwc3 *dwc)
536 struct dwc3_hwparams *parms = &dwc->hwparams;
538 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
539 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
540 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
541 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
542 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
543 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
544 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
545 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
546 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
549 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
554 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
556 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
557 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
558 dwc->hsphy_interface &&
559 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
560 ret = dwc3_ulpi_init(dwc);
566 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
567 * @dwc: Pointer to our controller context structure
569 * Returns 0 on success. The USB PHY interfaces are configured but not
570 * initialized. The PHY interfaces and the PHYs get initialized together with
571 * the core in dwc3_core_init.
573 static int dwc3_phy_setup(struct dwc3 *dwc)
575 unsigned int hw_mode;
578 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
580 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
583 * Make sure UX_EXIT_PX is cleared as that causes issues with some
584 * PHYs. Also, this bit is not supposed to be used in normal operation.
586 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
589 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
590 * to '0' during coreConsultant configuration. So default value
591 * will be '0' when the core is reset. Application needs to set it
592 * to '1' after the core initialization is completed.
594 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
595 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
598 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
599 * power-on reset, and it can be set after core initialization, which is
600 * after device soft-reset during initialization.
602 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
603 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
605 if (dwc->u2ss_inp3_quirk)
606 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
608 if (dwc->dis_rxdet_inp3_quirk)
609 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
611 if (dwc->req_p1p2p3_quirk)
612 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
614 if (dwc->del_p1p2p3_quirk)
615 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
617 if (dwc->del_phy_power_chg_quirk)
618 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
620 if (dwc->lfps_filter_quirk)
621 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
623 if (dwc->rx_detect_poll_quirk)
624 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
626 if (dwc->tx_de_emphasis_quirk)
627 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
629 if (dwc->dis_u3_susphy_quirk)
630 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
632 if (dwc->dis_del_phy_power_chg_quirk)
633 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
635 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
637 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
639 /* Select the HS PHY interface */
640 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
641 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
642 if (dwc->hsphy_interface &&
643 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
644 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
646 } else if (dwc->hsphy_interface &&
647 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
648 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
649 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
651 /* Relying on default value. */
652 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
656 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
661 switch (dwc->hsphy_mode) {
662 case USBPHY_INTERFACE_MODE_UTMI:
663 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
664 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
665 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
666 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
668 case USBPHY_INTERFACE_MODE_UTMIW:
669 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
670 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
671 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
672 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
679 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
680 * '0' during coreConsultant configuration. So default value will
681 * be '0' when the core is reset. Application needs to set it to
682 * '1' after the core initialization is completed.
684 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
685 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
688 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
689 * power-on reset, and it can be set after core initialization, which is
690 * after device soft-reset during initialization.
692 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
693 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
695 if (dwc->dis_u2_susphy_quirk)
696 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
698 if (dwc->dis_enblslpm_quirk)
699 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
701 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
703 if (dwc->dis_u2_freeclk_exists_quirk)
704 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
706 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
711 static void dwc3_core_exit(struct dwc3 *dwc)
713 dwc3_event_buffers_cleanup(dwc);
715 usb_phy_shutdown(dwc->usb2_phy);
716 usb_phy_shutdown(dwc->usb3_phy);
717 phy_exit(dwc->usb2_generic_phy);
718 phy_exit(dwc->usb3_generic_phy);
720 usb_phy_set_suspend(dwc->usb2_phy, 1);
721 usb_phy_set_suspend(dwc->usb3_phy, 1);
722 phy_power_off(dwc->usb2_generic_phy);
723 phy_power_off(dwc->usb3_generic_phy);
724 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
725 reset_control_assert(dwc->reset);
728 static bool dwc3_core_is_valid(struct dwc3 *dwc)
732 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
733 dwc->ip = DWC3_GSNPS_ID(reg);
735 /* This should read as U3 followed by revision number */
736 if (DWC3_IP_IS(DWC3)) {
738 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
739 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
740 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
748 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
750 u32 hwparams4 = dwc->hwparams.hwparams4;
753 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
754 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
756 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
757 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
759 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
760 * issue which would cause xHCI compliance tests to fail.
762 * Because of that we cannot enable clock gating on such
767 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
770 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
771 dwc->dr_mode == USB_DR_MODE_OTG) &&
772 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
773 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
775 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
777 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
778 /* enable hibernation here */
779 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
782 * REVISIT Enabling this bit so that host-mode hibernation
783 * will work. Device-mode hibernation is not yet implemented.
785 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
792 /* check if current dwc3 is on simulation board */
793 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
794 dev_info(dwc->dev, "Running with FPGA optimizations\n");
798 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
799 "disable_scramble cannot be used on non-FPGA builds\n");
801 if (dwc->disable_scramble_quirk && dwc->is_fpga)
802 reg |= DWC3_GCTL_DISSCRAMBLE;
804 reg &= ~DWC3_GCTL_DISSCRAMBLE;
806 if (dwc->u2exit_lfps_quirk)
807 reg |= DWC3_GCTL_U2EXIT_LFPS;
810 * WORKAROUND: DWC3 revisions <1.90a have a bug
811 * where the device can fail to connect at SuperSpeed
812 * and falls back to high-speed mode which causes
813 * the device to enter a Connect/Disconnect loop
815 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
816 reg |= DWC3_GCTL_U2RSTECN;
818 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
821 static int dwc3_core_get_phy(struct dwc3 *dwc);
822 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
824 /* set global incr burst type configuration registers */
825 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
827 struct device *dev = dwc->dev;
828 /* incrx_mode : for INCR burst type. */
830 /* incrx_size : for size of INCRX burst. */
838 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
841 * Handle property "snps,incr-burst-type-adjustment".
842 * Get the number of value from this property:
843 * result <= 0, means this property is not supported.
844 * result = 1, means INCRx burst mode supported.
845 * result > 1, means undefined length burst mode supported.
847 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
851 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
853 dev_err(dev, "Error to get memory\n");
857 /* Get INCR burst type, and parse it */
858 ret = device_property_read_u32_array(dev,
859 "snps,incr-burst-type-adjustment", vals, ntype);
862 dev_err(dev, "Error to get property\n");
869 /* INCRX (undefined length) burst mode */
870 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
871 for (i = 1; i < ntype; i++) {
872 if (vals[i] > incrx_size)
873 incrx_size = vals[i];
876 /* INCRX burst mode */
877 incrx_mode = INCRX_BURST_MODE;
882 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
883 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
885 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
886 switch (incrx_size) {
888 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
891 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
894 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
897 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
900 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
903 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
906 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
911 dev_err(dev, "Invalid property\n");
915 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
919 * dwc3_core_init - Low-level initialization of DWC3 Core
920 * @dwc: Pointer to our controller context structure
922 * Returns 0 on success otherwise negative errno.
924 static int dwc3_core_init(struct dwc3 *dwc)
926 unsigned int hw_mode;
930 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
933 * Write Linux Version Code to our GUID register so it's easy to figure
934 * out which kernel version a bug was found.
936 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
938 ret = dwc3_phy_setup(dwc);
942 if (!dwc->ulpi_ready) {
943 ret = dwc3_core_ulpi_init(dwc);
946 dwc->ulpi_ready = true;
949 if (!dwc->phys_ready) {
950 ret = dwc3_core_get_phy(dwc);
953 dwc->phys_ready = true;
956 ret = dwc3_core_soft_reset(dwc);
960 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
961 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
962 if (!dwc->dis_u3_susphy_quirk) {
963 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
964 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
965 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
968 if (!dwc->dis_u2_susphy_quirk) {
969 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
970 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
971 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
975 dwc3_core_setup_global_control(dwc);
976 dwc3_core_num_eps(dwc);
978 ret = dwc3_setup_scratch_buffers(dwc);
982 /* Adjust Frame Length */
983 dwc3_frame_length_adjustment(dwc);
985 dwc3_set_incr_burst_type(dwc);
987 usb_phy_set_suspend(dwc->usb2_phy, 0);
988 usb_phy_set_suspend(dwc->usb3_phy, 0);
989 ret = phy_power_on(dwc->usb2_generic_phy);
993 ret = phy_power_on(dwc->usb3_generic_phy);
997 ret = dwc3_event_buffers_setup(dwc);
999 dev_err(dwc->dev, "failed to setup event buffers\n");
1004 * ENDXFER polling is available on version 3.10a and later of
1005 * the DWC_usb3 controller. It is NOT available in the
1006 * DWC_usb31 controller.
1008 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1009 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1010 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1011 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1014 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1015 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1018 * Enable hardware control of sending remote wakeup
1019 * in HS when the device is in the L1 state.
1021 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1022 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1024 if (dwc->dis_tx_ipgap_linecheck_quirk)
1025 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1027 if (dwc->parkmode_disable_ss_quirk)
1028 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1030 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1033 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1034 dwc->dr_mode == USB_DR_MODE_OTG) {
1035 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1038 * Enable Auto retry Feature to make the controller operating in
1039 * Host mode on seeing transaction errors(CRC errors or internal
1040 * overrun scenerios) on IN transfers to reply to the device
1041 * with a non-terminating retry ACK (i.e, an ACK transcation
1042 * packet with Retry=1 & Nump != 0)
1044 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1046 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1050 * Must config both number of packets and max burst settings to enable
1051 * RX and/or TX threshold.
1053 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1054 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1055 u8 rx_maxburst = dwc->rx_max_burst_prd;
1056 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1057 u8 tx_maxburst = dwc->tx_max_burst_prd;
1059 if (rx_thr_num && rx_maxburst) {
1060 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1061 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1063 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1064 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1066 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1067 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1069 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1072 if (tx_thr_num && tx_maxburst) {
1073 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1074 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1076 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1077 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1079 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1080 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1082 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1089 phy_power_off(dwc->usb3_generic_phy);
1092 phy_power_off(dwc->usb2_generic_phy);
1095 usb_phy_set_suspend(dwc->usb2_phy, 1);
1096 usb_phy_set_suspend(dwc->usb3_phy, 1);
1099 usb_phy_shutdown(dwc->usb2_phy);
1100 usb_phy_shutdown(dwc->usb3_phy);
1101 phy_exit(dwc->usb2_generic_phy);
1102 phy_exit(dwc->usb3_generic_phy);
1105 dwc3_ulpi_exit(dwc);
1111 static int dwc3_core_get_phy(struct dwc3 *dwc)
1113 struct device *dev = dwc->dev;
1114 struct device_node *node = dev->of_node;
1118 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1119 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1121 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1122 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1125 if (IS_ERR(dwc->usb2_phy)) {
1126 ret = PTR_ERR(dwc->usb2_phy);
1127 if (ret == -ENXIO || ret == -ENODEV) {
1128 dwc->usb2_phy = NULL;
1130 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1134 if (IS_ERR(dwc->usb3_phy)) {
1135 ret = PTR_ERR(dwc->usb3_phy);
1136 if (ret == -ENXIO || ret == -ENODEV) {
1137 dwc->usb3_phy = NULL;
1139 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1143 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1144 if (IS_ERR(dwc->usb2_generic_phy)) {
1145 ret = PTR_ERR(dwc->usb2_generic_phy);
1146 if (ret == -ENOSYS || ret == -ENODEV) {
1147 dwc->usb2_generic_phy = NULL;
1149 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1153 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1154 if (IS_ERR(dwc->usb3_generic_phy)) {
1155 ret = PTR_ERR(dwc->usb3_generic_phy);
1156 if (ret == -ENOSYS || ret == -ENODEV) {
1157 dwc->usb3_generic_phy = NULL;
1159 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1166 static int dwc3_core_init_mode(struct dwc3 *dwc)
1168 struct device *dev = dwc->dev;
1171 switch (dwc->dr_mode) {
1172 case USB_DR_MODE_PERIPHERAL:
1173 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1176 otg_set_vbus(dwc->usb2_phy->otg, false);
1177 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1178 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1180 ret = dwc3_gadget_init(dwc);
1182 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1184 case USB_DR_MODE_HOST:
1185 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1188 otg_set_vbus(dwc->usb2_phy->otg, true);
1189 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1190 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1192 ret = dwc3_host_init(dwc);
1194 return dev_err_probe(dev, ret, "failed to initialize host\n");
1196 case USB_DR_MODE_OTG:
1197 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1198 ret = dwc3_drd_init(dwc);
1200 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1203 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1210 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1212 switch (dwc->dr_mode) {
1213 case USB_DR_MODE_PERIPHERAL:
1214 dwc3_gadget_exit(dwc);
1216 case USB_DR_MODE_HOST:
1217 dwc3_host_exit(dwc);
1219 case USB_DR_MODE_OTG:
1227 /* de-assert DRVVBUS for HOST and OTG mode */
1228 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1231 static void dwc3_get_properties(struct dwc3 *dwc)
1233 struct device *dev = dwc->dev;
1234 u8 lpm_nyet_threshold;
1237 u8 rx_thr_num_pkt_prd;
1238 u8 rx_max_burst_prd;
1239 u8 tx_thr_num_pkt_prd;
1240 u8 tx_max_burst_prd;
1242 /* default to highest possible threshold */
1243 lpm_nyet_threshold = 0xf;
1245 /* default to -3.5dB de-emphasis */
1249 * default to assert utmi_sleep_n and use maximum allowed HIRD
1250 * threshold value of 0b1100
1252 hird_threshold = 12;
1254 dwc->maximum_speed = usb_get_maximum_speed(dev);
1255 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1256 dwc->dr_mode = usb_get_dr_mode(dev);
1257 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1259 dwc->sysdev_is_parent = device_property_read_bool(dev,
1260 "linux,sysdev_is_parent");
1261 if (dwc->sysdev_is_parent)
1262 dwc->sysdev = dwc->dev->parent;
1264 dwc->sysdev = dwc->dev;
1266 dwc->has_lpm_erratum = device_property_read_bool(dev,
1267 "snps,has-lpm-erratum");
1268 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1269 &lpm_nyet_threshold);
1270 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1271 "snps,is-utmi-l1-suspend");
1272 device_property_read_u8(dev, "snps,hird-threshold",
1274 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1275 "snps,dis-start-transfer-quirk");
1276 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1277 "snps,usb3_lpm_capable");
1278 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1279 "snps,usb2-lpm-disable");
1280 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1281 &rx_thr_num_pkt_prd);
1282 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1284 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1285 &tx_thr_num_pkt_prd);
1286 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1289 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1290 "snps,disable_scramble_quirk");
1291 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1292 "snps,u2exit_lfps_quirk");
1293 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1294 "snps,u2ss_inp3_quirk");
1295 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1296 "snps,req_p1p2p3_quirk");
1297 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1298 "snps,del_p1p2p3_quirk");
1299 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1300 "snps,del_phy_power_chg_quirk");
1301 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1302 "snps,lfps_filter_quirk");
1303 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1304 "snps,rx_detect_poll_quirk");
1305 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1306 "snps,dis_u3_susphy_quirk");
1307 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1308 "snps,dis_u2_susphy_quirk");
1309 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1310 "snps,dis_enblslpm_quirk");
1311 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1312 "snps,dis-u1-entry-quirk");
1313 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1314 "snps,dis-u2-entry-quirk");
1315 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1316 "snps,dis_rxdet_inp3_quirk");
1317 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1318 "snps,dis-u2-freeclk-exists-quirk");
1319 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1320 "snps,dis-del-phy-power-chg-quirk");
1321 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1322 "snps,dis-tx-ipgap-linecheck-quirk");
1323 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1324 "snps,parkmode-disable-ss-quirk");
1326 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1327 "snps,tx_de_emphasis_quirk");
1328 device_property_read_u8(dev, "snps,tx_de_emphasis",
1330 device_property_read_string(dev, "snps,hsphy_interface",
1331 &dwc->hsphy_interface);
1332 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1335 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1336 "snps,dis_metastability_quirk");
1338 dwc->dis_split_quirk = device_property_read_bool(dev,
1339 "snps,dis-split-quirk");
1341 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1342 dwc->tx_de_emphasis = tx_de_emphasis;
1344 dwc->hird_threshold = hird_threshold;
1346 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1347 dwc->rx_max_burst_prd = rx_max_burst_prd;
1349 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1350 dwc->tx_max_burst_prd = tx_max_burst_prd;
1352 dwc->imod_interval = 0;
1355 /* check whether the core supports IMOD */
1356 bool dwc3_has_imod(struct dwc3 *dwc)
1358 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1359 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1363 static void dwc3_check_params(struct dwc3 *dwc)
1365 struct device *dev = dwc->dev;
1366 unsigned int hwparam_gen =
1367 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1369 /* Check for proper value of imod_interval */
1370 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1371 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1372 dwc->imod_interval = 0;
1376 * Workaround for STAR 9000961433 which affects only version
1377 * 3.00a of the DWC_usb3 core. This prevents the controller
1378 * interrupt from being masked while handling events. IMOD
1379 * allows us to work around this issue. Enable it for the
1382 if (!dwc->imod_interval &&
1383 DWC3_VER_IS(DWC3, 300A))
1384 dwc->imod_interval = 1;
1386 /* Check the maximum_speed parameter */
1387 switch (dwc->maximum_speed) {
1389 case USB_SPEED_FULL:
1390 case USB_SPEED_HIGH:
1392 case USB_SPEED_SUPER:
1393 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1394 dev_warn(dev, "UDC doesn't support Gen 1\n");
1396 case USB_SPEED_SUPER_PLUS:
1397 if ((DWC3_IP_IS(DWC32) &&
1398 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1399 (!DWC3_IP_IS(DWC32) &&
1400 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1401 dev_warn(dev, "UDC doesn't support SSP\n");
1404 dev_err(dev, "invalid maximum_speed parameter %d\n",
1405 dwc->maximum_speed);
1407 case USB_SPEED_UNKNOWN:
1408 switch (hwparam_gen) {
1409 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1410 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1412 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1413 if (DWC3_IP_IS(DWC32))
1414 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1416 dwc->maximum_speed = USB_SPEED_SUPER;
1418 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1419 dwc->maximum_speed = USB_SPEED_HIGH;
1422 dwc->maximum_speed = USB_SPEED_SUPER;
1429 * Currently the controller does not have visibility into the HW
1430 * parameter to determine the maximum number of lanes the HW supports.
1431 * If the number of lanes is not specified in the device property, then
1432 * set the default to support dual-lane for DWC_usb32 and single-lane
1433 * for DWC_usb31 for super-speed-plus.
1435 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1436 switch (dwc->max_ssp_rate) {
1437 case USB_SSP_GEN_2x1:
1438 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1439 dev_warn(dev, "UDC only supports Gen 1\n");
1441 case USB_SSP_GEN_1x2:
1442 case USB_SSP_GEN_2x2:
1443 if (DWC3_IP_IS(DWC31))
1444 dev_warn(dev, "UDC only supports single lane\n");
1446 case USB_SSP_GEN_UNKNOWN:
1448 switch (hwparam_gen) {
1449 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1450 if (DWC3_IP_IS(DWC32))
1451 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1453 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1455 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1456 if (DWC3_IP_IS(DWC32))
1457 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1465 static int dwc3_probe(struct platform_device *pdev)
1467 struct device *dev = &pdev->dev;
1468 struct resource *res, dwc_res;
1475 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1481 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1483 dev_err(dev, "missing memory resource\n");
1487 dwc->xhci_resources[0].start = res->start;
1488 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1490 dwc->xhci_resources[0].flags = res->flags;
1491 dwc->xhci_resources[0].name = res->name;
1494 * Request memory region but exclude xHCI regs,
1495 * since it will be requested by the xhci-plat driver.
1498 dwc_res.start += DWC3_GLOBALS_REGS_START;
1500 regs = devm_ioremap_resource(dev, &dwc_res);
1502 return PTR_ERR(regs);
1505 dwc->regs_size = resource_size(&dwc_res);
1507 dwc3_get_properties(dwc);
1509 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1510 if (IS_ERR(dwc->reset))
1511 return PTR_ERR(dwc->reset);
1514 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1515 if (ret == -EPROBE_DEFER)
1518 * Clocks are optional, but new DT platforms should support all
1519 * clocks as required by the DT-binding.
1524 dwc->num_clks = ret;
1528 ret = reset_control_deassert(dwc->reset);
1532 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1536 if (!dwc3_core_is_valid(dwc)) {
1537 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1542 platform_set_drvdata(pdev, dwc);
1543 dwc3_cache_hwparams(dwc);
1545 spin_lock_init(&dwc->lock);
1547 pm_runtime_set_active(dev);
1548 pm_runtime_use_autosuspend(dev);
1549 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1550 pm_runtime_enable(dev);
1551 ret = pm_runtime_get_sync(dev);
1555 pm_runtime_forbid(dev);
1557 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1559 dev_err(dwc->dev, "failed to allocate event buffers\n");
1564 ret = dwc3_get_dr_mode(dwc);
1568 ret = dwc3_alloc_scratch_buffers(dwc);
1572 ret = dwc3_core_init(dwc);
1574 dev_err_probe(dev, ret, "failed to initialize core\n");
1578 dwc3_check_params(dwc);
1580 ret = dwc3_core_init_mode(dwc);
1584 dwc3_debugfs_init(dwc);
1585 pm_runtime_put(dev);
1590 dwc3_event_buffers_cleanup(dwc);
1592 usb_phy_shutdown(dwc->usb2_phy);
1593 usb_phy_shutdown(dwc->usb3_phy);
1594 phy_exit(dwc->usb2_generic_phy);
1595 phy_exit(dwc->usb3_generic_phy);
1597 usb_phy_set_suspend(dwc->usb2_phy, 1);
1598 usb_phy_set_suspend(dwc->usb3_phy, 1);
1599 phy_power_off(dwc->usb2_generic_phy);
1600 phy_power_off(dwc->usb3_generic_phy);
1602 dwc3_ulpi_exit(dwc);
1605 dwc3_free_scratch_buffers(dwc);
1608 dwc3_free_event_buffers(dwc);
1611 pm_runtime_allow(&pdev->dev);
1614 pm_runtime_put_sync(&pdev->dev);
1615 pm_runtime_disable(&pdev->dev);
1618 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1620 reset_control_assert(dwc->reset);
1625 static int dwc3_remove(struct platform_device *pdev)
1627 struct dwc3 *dwc = platform_get_drvdata(pdev);
1629 pm_runtime_get_sync(&pdev->dev);
1631 dwc3_debugfs_exit(dwc);
1632 dwc3_core_exit_mode(dwc);
1634 dwc3_core_exit(dwc);
1635 dwc3_ulpi_exit(dwc);
1637 pm_runtime_disable(&pdev->dev);
1638 pm_runtime_put_noidle(&pdev->dev);
1639 pm_runtime_set_suspended(&pdev->dev);
1641 dwc3_free_event_buffers(dwc);
1642 dwc3_free_scratch_buffers(dwc);
1648 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1652 ret = reset_control_deassert(dwc->reset);
1656 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1660 ret = dwc3_core_init(dwc);
1667 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1669 reset_control_assert(dwc->reset);
1674 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1676 unsigned long flags;
1679 switch (dwc->current_dr_role) {
1680 case DWC3_GCTL_PRTCAP_DEVICE:
1681 if (pm_runtime_suspended(dwc->dev))
1683 spin_lock_irqsave(&dwc->lock, flags);
1684 dwc3_gadget_suspend(dwc);
1685 spin_unlock_irqrestore(&dwc->lock, flags);
1686 synchronize_irq(dwc->irq_gadget);
1687 dwc3_core_exit(dwc);
1689 case DWC3_GCTL_PRTCAP_HOST:
1690 if (!PMSG_IS_AUTO(msg)) {
1691 dwc3_core_exit(dwc);
1695 /* Let controller to suspend HSPHY before PHY driver suspends */
1696 if (dwc->dis_u2_susphy_quirk ||
1697 dwc->dis_enblslpm_quirk) {
1698 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1699 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1700 DWC3_GUSB2PHYCFG_SUSPHY;
1701 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1703 /* Give some time for USB2 PHY to suspend */
1704 usleep_range(5000, 6000);
1707 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1708 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1710 case DWC3_GCTL_PRTCAP_OTG:
1711 /* do nothing during runtime_suspend */
1712 if (PMSG_IS_AUTO(msg))
1715 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1716 spin_lock_irqsave(&dwc->lock, flags);
1717 dwc3_gadget_suspend(dwc);
1718 spin_unlock_irqrestore(&dwc->lock, flags);
1719 synchronize_irq(dwc->irq_gadget);
1723 dwc3_core_exit(dwc);
1733 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1735 unsigned long flags;
1739 switch (dwc->current_dr_role) {
1740 case DWC3_GCTL_PRTCAP_DEVICE:
1741 ret = dwc3_core_init_for_resume(dwc);
1745 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1746 spin_lock_irqsave(&dwc->lock, flags);
1747 dwc3_gadget_resume(dwc);
1748 spin_unlock_irqrestore(&dwc->lock, flags);
1750 case DWC3_GCTL_PRTCAP_HOST:
1751 if (!PMSG_IS_AUTO(msg)) {
1752 ret = dwc3_core_init_for_resume(dwc);
1755 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1758 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1759 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1760 if (dwc->dis_u2_susphy_quirk)
1761 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1763 if (dwc->dis_enblslpm_quirk)
1764 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1766 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1768 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1769 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1771 case DWC3_GCTL_PRTCAP_OTG:
1772 /* nothing to do on runtime_resume */
1773 if (PMSG_IS_AUTO(msg))
1776 ret = dwc3_core_init_for_resume(dwc);
1780 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1783 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1784 dwc3_otg_host_init(dwc);
1785 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1786 spin_lock_irqsave(&dwc->lock, flags);
1787 dwc3_gadget_resume(dwc);
1788 spin_unlock_irqrestore(&dwc->lock, flags);
1800 static int dwc3_runtime_checks(struct dwc3 *dwc)
1802 switch (dwc->current_dr_role) {
1803 case DWC3_GCTL_PRTCAP_DEVICE:
1807 case DWC3_GCTL_PRTCAP_HOST:
1816 static int dwc3_runtime_suspend(struct device *dev)
1818 struct dwc3 *dwc = dev_get_drvdata(dev);
1821 if (dwc3_runtime_checks(dwc))
1824 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1828 device_init_wakeup(dev, true);
1833 static int dwc3_runtime_resume(struct device *dev)
1835 struct dwc3 *dwc = dev_get_drvdata(dev);
1838 device_init_wakeup(dev, false);
1840 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1844 switch (dwc->current_dr_role) {
1845 case DWC3_GCTL_PRTCAP_DEVICE:
1846 dwc3_gadget_process_pending_events(dwc);
1848 case DWC3_GCTL_PRTCAP_HOST:
1854 pm_runtime_mark_last_busy(dev);
1859 static int dwc3_runtime_idle(struct device *dev)
1861 struct dwc3 *dwc = dev_get_drvdata(dev);
1863 switch (dwc->current_dr_role) {
1864 case DWC3_GCTL_PRTCAP_DEVICE:
1865 if (dwc3_runtime_checks(dwc))
1868 case DWC3_GCTL_PRTCAP_HOST:
1874 pm_runtime_mark_last_busy(dev);
1875 pm_runtime_autosuspend(dev);
1879 #endif /* CONFIG_PM */
1881 #ifdef CONFIG_PM_SLEEP
1882 static int dwc3_suspend(struct device *dev)
1884 struct dwc3 *dwc = dev_get_drvdata(dev);
1887 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1891 pinctrl_pm_select_sleep_state(dev);
1896 static int dwc3_resume(struct device *dev)
1898 struct dwc3 *dwc = dev_get_drvdata(dev);
1901 pinctrl_pm_select_default_state(dev);
1903 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1907 pm_runtime_disable(dev);
1908 pm_runtime_set_active(dev);
1909 pm_runtime_enable(dev);
1914 static void dwc3_complete(struct device *dev)
1916 struct dwc3 *dwc = dev_get_drvdata(dev);
1919 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1920 dwc->dis_split_quirk) {
1921 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1922 reg |= DWC3_GUCTL3_SPLITDISABLE;
1923 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1927 #define dwc3_complete NULL
1928 #endif /* CONFIG_PM_SLEEP */
1930 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1931 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1932 .complete = dwc3_complete,
1933 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1938 static const struct of_device_id of_dwc3_match[] = {
1940 .compatible = "snps,dwc3"
1943 .compatible = "synopsys,dwc3"
1947 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1952 #define ACPI_ID_INTEL_BSW "808622B7"
1954 static const struct acpi_device_id dwc3_acpi_match[] = {
1955 { ACPI_ID_INTEL_BSW, 0 },
1958 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1961 static struct platform_driver dwc3_driver = {
1962 .probe = dwc3_probe,
1963 .remove = dwc3_remove,
1966 .of_match_table = of_match_ptr(of_dwc3_match),
1967 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1968 .pm = &dwc3_dev_pm_ops,
1972 module_platform_driver(dwc3_driver);
1974 MODULE_ALIAS("platform:dwc3");
1975 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1976 MODULE_LICENSE("GPL v2");
1977 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");