drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  72 }
  73
  74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  79         p->phy_utmi_width = 8;
  80 }
  81
  82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  83 {
  84         struct dwc2_core_params *p = &hsotg->params;
  85
  86         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  87         p->host_rx_fifo_size = 525;
  88         p->host_nperio_tx_fifo_size = 128;
  89         p->host_perio_tx_fifo_size = 256;
  90         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  91                 GAHBCFG_HBSTLEN_SHIFT;
  92         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  93 }
  94
  95 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  96 {
  97         struct dwc2_core_params *p = &hsotg->params;
  98
  99         p->otg_cap = 2;
 100         p->host_rx_fifo_size = 288;
 101         p->host_nperio_tx_fifo_size = 128;
 102         p->host_perio_tx_fifo_size = 96;
 103         p->max_transfer_size = 65535;
 104         p->max_packet_count = 511;
 105         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 106                 GAHBCFG_HBSTLEN_SHIFT;
 107 }
 108
 109 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 110 {
 111         struct dwc2_core_params *p = &hsotg->params;
 112
 113         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 114         p->speed = DWC2_SPEED_PARAM_HIGH;
 115         p->host_rx_fifo_size = 512;
 116         p->host_nperio_tx_fifo_size = 500;
 117         p->host_perio_tx_fifo_size = 500;
 118         p->host_channels = 16;
 119         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 120         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 121                 GAHBCFG_HBSTLEN_SHIFT;
 122         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 123 }
 124
 125 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 126 {
 127         struct dwc2_core_params *p = &hsotg->params;
 128
 129         p->lpm = false;
 130         p->lpm_clock_gating = false;
 131         p->besl = false;
 132         p->hird_threshold_en = false;
 133 }
 134
 135 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 136 {
 137         struct dwc2_core_params *p = &hsotg->params;
 138
 139         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 140 }
 141
 142 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 143 {
 144         struct dwc2_core_params *p = &hsotg->params;
 145
 146         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 147         p->speed = DWC2_SPEED_PARAM_FULL;
 148         p->host_rx_fifo_size = 128;
 149         p->host_nperio_tx_fifo_size = 96;
 150         p->host_perio_tx_fifo_size = 96;
 151         p->max_packet_count = 256;
 152         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 153         p->i2c_enable = false;
 154         p->activate_stm_fs_transceiver = true;
 155 }
 156
 157 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 158 {
 159         struct dwc2_core_params *p = &hsotg->params;
 160
 161         p->host_rx_fifo_size = 622;
 162         p->host_nperio_tx_fifo_size = 128;
 163         p->host_perio_tx_fifo_size = 256;
 164 }
 165
 166 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
 167 {
 168         struct dwc2_core_params *p = &hsotg->params;
 169
 170         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 171         p->speed = DWC2_SPEED_PARAM_FULL;
 172         p->host_rx_fifo_size = 128;
 173         p->host_nperio_tx_fifo_size = 96;
 174         p->host_perio_tx_fifo_size = 96;
 175         p->max_packet_count = 256;
 176         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 177         p->i2c_enable = false;
 178         p->activate_stm_fs_transceiver = true;
 179         p->activate_stm_id_vb_detection = true;
 180         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 181         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 182         p->host_support_fs_ls_low_power = true;
 183         p->host_ls_low_power_phy_clk = true;
 184 }
 185
 186 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 187 {
 188         struct dwc2_core_params *p = &hsotg->params;
 189
 190         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 191         p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
 192         p->host_rx_fifo_size = 440;
 193         p->host_nperio_tx_fifo_size = 256;
 194         p->host_perio_tx_fifo_size = 256;
 195         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 196         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 197         p->lpm = false;
 198         p->lpm_clock_gating = false;
 199         p->besl = false;
 200         p->hird_threshold_en = false;
 201 }
 202
 203 const struct of_device_id dwc2_of_match_table[] = {
 204         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 205         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 206         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 207         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 208         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 209         { .compatible = "snps,dwc2" },
 210         { .compatible = "samsung,s3c6400-hsotg",
 211           .data = dwc2_set_s3c6400_params },
 212         { .compatible = "amlogic,meson8-usb",
 213           .data = dwc2_set_amlogic_params },
 214         { .compatible = "amlogic,meson8b-usb",
 215           .data = dwc2_set_amlogic_params },
 216         { .compatible = "amlogic,meson-gxbb-usb",
 217           .data = dwc2_set_amlogic_params },
 218         { .compatible = "amlogic,meson-g12a-usb",
 219           .data = dwc2_set_amlogic_g12a_params },
 220         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 221         { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
 222         { .compatible = "st,stm32f4x9-fsotg",
 223           .data = dwc2_set_stm32f4x9_fsotg_params },
 224         { .compatible = "st,stm32f4x9-hsotg" },
 225         { .compatible = "st,stm32f7-hsotg",
 226           .data = dwc2_set_stm32f7_hsotg_params },
 227         { .compatible = "st,stm32mp15-fsotg",
 228           .data = dwc2_set_stm32mp15_fsotg_params },
 229         { .compatible = "st,stm32mp15-hsotg",
 230           .data = dwc2_set_stm32mp15_hsotg_params },
 231         {},
 232 };
 233 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 234
 235 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 236 {
 237         u8 val;
 238
 239         switch (hsotg->hw_params.op_mode) {
 240         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 241                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 242                 break;
 243         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 244         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 245         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 246                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 247                 break;
 248         default:
 249                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 250                 break;
 251         }
 252
 253         hsotg->params.otg_cap = val;
 254 }
 255
 256 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 257 {
 258         int val;
 259         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 260
 261         val = DWC2_PHY_TYPE_PARAM_FS;
 262         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 263                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 264                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 265                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 266                 else
 267                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 268         }
 269
 270         if (dwc2_is_fs_iot(hsotg))
 271                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 272
 273         hsotg->params.phy_type = val;
 274 }
 275
 276 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 277 {
 278         int val;
 279
 280         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 281                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 282
 283         if (dwc2_is_fs_iot(hsotg))
 284                 val = DWC2_SPEED_PARAM_FULL;
 285
 286         if (dwc2_is_hs_iot(hsotg))
 287                 val = DWC2_SPEED_PARAM_HIGH;
 288
 289         hsotg->params.speed = val;
 290 }
 291
 292 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 293 {
 294         int val;
 295
 296         val = (hsotg->hw_params.utmi_phy_data_width ==
 297                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 298
 299         if (hsotg->phy) {
 300                 /*
 301                  * If using the generic PHY framework, check if the PHY bus
 302                  * width is 8-bit and set the phyif appropriately.
 303                  */
 304                 if (phy_get_bus_width(hsotg->phy) == 8)
 305                         val = 8;
 306         }
 307
 308         hsotg->params.phy_utmi_width = val;
 309 }
 310
 311 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 312 {
 313         struct dwc2_core_params *p = &hsotg->params;
 314         int depth_average;
 315         int fifo_count;
 316         int i;
 317
 318         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 319
 320         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 321         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 322         for (i = 1; i <= fifo_count; i++)
 323                 p->g_tx_fifo_size[i] = depth_average;
 324 }
 325
 326 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 327 {
 328         int val;
 329
 330         if (hsotg->hw_params.hibernation)
 331                 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
 332         else if (hsotg->hw_params.power_optimized)
 333                 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
 334         else
 335                 val = DWC2_POWER_DOWN_PARAM_NONE;
 336
 337         hsotg->params.power_down = val;
 338 }
 339
 340 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 341 {
 342         struct dwc2_core_params *p = &hsotg->params;
 343
 344         p->lpm = hsotg->hw_params.lpm_mode;
 345         if (p->lpm) {
 346                 p->lpm_clock_gating = true;
 347                 p->besl = true;
 348                 p->hird_threshold_en = true;
 349                 p->hird_threshold = 4;
 350         } else {
 351                 p->lpm_clock_gating = false;
 352                 p->besl = false;
 353                 p->hird_threshold_en = false;
 354         }
 355 }
 356
 357 /**
 358  * dwc2_set_default_params() - Set all core parameters to their
 359  * auto-detected default values.
 360  *
 361  * @hsotg: Programming view of the DWC_otg controller
 362  *
 363  */
 364 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 365 {
 366         struct dwc2_hw_params *hw = &hsotg->hw_params;
 367         struct dwc2_core_params *p = &hsotg->params;
 368         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 369
 370         dwc2_set_param_otg_cap(hsotg);
 371         dwc2_set_param_phy_type(hsotg);
 372         dwc2_set_param_speed(hsotg);
 373         dwc2_set_param_phy_utmi_width(hsotg);
 374         dwc2_set_param_power_down(hsotg);
 375         dwc2_set_param_lpm(hsotg);
 376         p->phy_ulpi_ddr = false;
 377         p->phy_ulpi_ext_vbus = false;
 378
 379         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 380         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 381         p->i2c_enable = hw->i2c_enable;
 382         p->acg_enable = hw->acg_enable;
 383         p->ulpi_fs_ls = false;
 384         p->ts_dline = false;
 385         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 386         p->uframe_sched = true;
 387         p->external_id_pin_ctl = false;
 388         p->ipg_isoc_en = false;
 389         p->service_interval = false;
 390         p->max_packet_count = hw->max_packet_count;
 391         p->max_transfer_size = hw->max_transfer_size;
 392         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 393         p->ref_clk_per = 33333;
 394         p->sof_cnt_wkup_alert = 100;
 395
 396         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 397             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 398                 p->host_dma = dma_capable;
 399                 p->dma_desc_enable = false;
 400                 p->dma_desc_fs_enable = false;
 401                 p->host_support_fs_ls_low_power = false;
 402                 p->host_ls_low_power_phy_clk = false;
 403                 p->host_channels = hw->host_channels;
 404                 p->host_rx_fifo_size = hw->rx_fifo_size;
 405                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 406                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 407         }
 408
 409         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 410             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 411                 p->g_dma = dma_capable;
 412                 p->g_dma_desc = hw->dma_desc_enable;
 413
 414                 /*
 415                  * The values for g_rx_fifo_size (2048) and
 416                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 417                  * gadget driver. These defaults have been hard-coded
 418                  * for some time so many platforms depend on these
 419                  * values. Leave them as defaults for now and only
 420                  * auto-detect if the hardware does not support the
 421                  * default.
 422                  */
 423                 p->g_rx_fifo_size = 2048;
 424                 p->g_np_tx_fifo_size = 1024;
 425                 dwc2_set_param_tx_fifo_sizes(hsotg);
 426         }
 427 }
 428
 429 /**
 430  * dwc2_get_device_properties() - Read in device properties.
 431  *
 432  * @hsotg: Programming view of the DWC_otg controller
 433  *
 434  * Read in the device properties and adjust core parameters if needed.
 435  */
 436 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 437 {
 438         struct dwc2_core_params *p = &hsotg->params;
 439         int num;
 440
 441         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 442             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 443                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 444                                          &p->g_rx_fifo_size);
 445
 446                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 447                                          &p->g_np_tx_fifo_size);
 448
 449                 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
 450                 if (num > 0) {
 451                         num = min(num, 15);
 452                         memset(p->g_tx_fifo_size, 0,
 453                                sizeof(p->g_tx_fifo_size));
 454                         device_property_read_u32_array(hsotg->dev,
 455                                                        "g-tx-fifo-size",
 456                                                        &p->g_tx_fifo_size[1],
 457                                                        num);
 458                 }
 459         }
 460
 461         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 462                 p->oc_disable = true;
 463 }
 464
 465 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 466 {
 467         int valid = 1;
 468
 469         switch (hsotg->params.otg_cap) {
 470         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 471                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 472                         valid = 0;
 473                 break;
 474         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 475                 switch (hsotg->hw_params.op_mode) {
 476                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 477                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 478                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 479                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 480                         break;
 481                 default:
 482                         valid = 0;
 483                         break;
 484                 }
 485                 break;
 486         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 487                 /* always valid */
 488                 break;
 489         default:
 490                 valid = 0;
 491                 break;
 492         }
 493
 494         if (!valid)
 495                 dwc2_set_param_otg_cap(hsotg);
 496 }
 497
 498 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 499 {
 500         int valid = 0;
 501         u32 hs_phy_type;
 502         u32 fs_phy_type;
 503
 504         hs_phy_type = hsotg->hw_params.hs_phy_type;
 505         fs_phy_type = hsotg->hw_params.fs_phy_type;
 506
 507         switch (hsotg->params.phy_type) {
 508         case DWC2_PHY_TYPE_PARAM_FS:
 509                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 510                         valid = 1;
 511                 break;
 512         case DWC2_PHY_TYPE_PARAM_UTMI:
 513                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 514                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 515                         valid = 1;
 516                 break;
 517         case DWC2_PHY_TYPE_PARAM_ULPI:
 518                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 519                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 520                         valid = 1;
 521                 break;
 522         default:
 523                 break;
 524         }
 525
 526         if (!valid)
 527                 dwc2_set_param_phy_type(hsotg);
 528 }
 529
 530 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 531 {
 532         int valid = 1;
 533         int phy_type = hsotg->params.phy_type;
 534         int speed = hsotg->params.speed;
 535
 536         switch (speed) {
 537         case DWC2_SPEED_PARAM_HIGH:
 538                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 539                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 540                         valid = 0;
 541                 break;
 542         case DWC2_SPEED_PARAM_FULL:
 543         case DWC2_SPEED_PARAM_LOW:
 544                 break;
 545         default:
 546                 valid = 0;
 547                 break;
 548         }
 549
 550         if (!valid)
 551                 dwc2_set_param_speed(hsotg);
 552 }
 553
 554 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 555 {
 556         int valid = 0;
 557         int param = hsotg->params.phy_utmi_width;
 558         int width = hsotg->hw_params.utmi_phy_data_width;
 559
 560         switch (width) {
 561         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 562                 valid = (param == 8);
 563                 break;
 564         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 565                 valid = (param == 16);
 566                 break;
 567         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 568                 valid = (param == 8 || param == 16);
 569                 break;
 570         }
 571
 572         if (!valid)
 573                 dwc2_set_param_phy_utmi_width(hsotg);
 574 }
 575
 576 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 577 {
 578         int param = hsotg->params.power_down;
 579
 580         switch (param) {
 581         case DWC2_POWER_DOWN_PARAM_NONE:
 582                 break;
 583         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 584                 if (hsotg->hw_params.power_optimized)
 585                         break;
 586                 dev_dbg(hsotg->dev,
 587                         "Partial power down isn't supported by HW\n");
 588                 param = DWC2_POWER_DOWN_PARAM_NONE;
 589                 break;
 590         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 591                 if (hsotg->hw_params.hibernation)
 592                         break;
 593                 dev_dbg(hsotg->dev,
 594                         "Hibernation isn't supported by HW\n");
 595                 param = DWC2_POWER_DOWN_PARAM_NONE;
 596                 break;
 597         default:
 598                 dev_err(hsotg->dev,
 599                         "%s: Invalid parameter power_down=%d\n",
 600                         __func__, param);
 601                 param = DWC2_POWER_DOWN_PARAM_NONE;
 602                 break;
 603         }
 604
 605         hsotg->params.power_down = param;
 606 }
 607
 608 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 609 {
 610         int fifo_count;
 611         int fifo;
 612         int min;
 613         u32 total = 0;
 614         u32 dptxfszn;
 615
 616         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 617         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 618
 619         for (fifo = 1; fifo <= fifo_count; fifo++)
 620                 total += hsotg->params.g_tx_fifo_size[fifo];
 621
 622         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 623                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 624                          __func__);
 625                 dwc2_set_param_tx_fifo_sizes(hsotg);
 626         }
 627
 628         for (fifo = 1; fifo <= fifo_count; fifo++) {
 629                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 630
 631                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 632                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 633                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 634                                  __func__, fifo,
 635                                  hsotg->params.g_tx_fifo_size[fifo]);
 636                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 637                 }
 638         }
 639 }
 640
 641 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 642                 if ((int)(hsotg->params._param) < (_min) ||             \
 643                     (hsotg->params._param) > (_max)) {                  \
 644                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 645                                  __func__, #_param, hsotg->params._param); \
 646                         hsotg->params._param = (_def);                  \
 647                 }                                                       \
 648         } while (0)
 649
 650 #define CHECK_BOOL(_param, _check) do {                                 \
 651                 if (hsotg->params._param && !(_check)) {                \
 652                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 653                                  __func__, #_param, hsotg->params._param); \
 654                         hsotg->params._param = false;                   \
 655                 }                                                       \
 656         } while (0)
 657
 658 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 659 {
 660         struct dwc2_hw_params *hw = &hsotg->hw_params;
 661         struct dwc2_core_params *p = &hsotg->params;
 662         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 663
 664         dwc2_check_param_otg_cap(hsotg);
 665         dwc2_check_param_phy_type(hsotg);
 666         dwc2_check_param_speed(hsotg);
 667         dwc2_check_param_phy_utmi_width(hsotg);
 668         dwc2_check_param_power_down(hsotg);
 669         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 670         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 671         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 672         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 673         CHECK_BOOL(acg_enable, hw->acg_enable);
 674         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 675         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 676         CHECK_BOOL(lpm, hw->lpm_mode);
 677         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 678         CHECK_BOOL(besl, hsotg->params.lpm);
 679         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 680         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 681         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 682         CHECK_BOOL(service_interval, hw->service_interval_mode);
 683         CHECK_RANGE(max_packet_count,
 684                     15, hw->max_packet_count,
 685                     hw->max_packet_count);
 686         CHECK_RANGE(max_transfer_size,
 687                     2047, hw->max_transfer_size,
 688                     hw->max_transfer_size);
 689
 690         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 691             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 692                 CHECK_BOOL(host_dma, dma_capable);
 693                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 694                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 695                 CHECK_BOOL(host_ls_low_power_phy_clk,
 696                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 697                 CHECK_RANGE(host_channels,
 698                             1, hw->host_channels,
 699                             hw->host_channels);
 700                 CHECK_RANGE(host_rx_fifo_size,
 701                             16, hw->rx_fifo_size,
 702                             hw->rx_fifo_size);
 703                 CHECK_RANGE(host_nperio_tx_fifo_size,
 704                             16, hw->host_nperio_tx_fifo_size,
 705                             hw->host_nperio_tx_fifo_size);
 706                 CHECK_RANGE(host_perio_tx_fifo_size,
 707                             16, hw->host_perio_tx_fifo_size,
 708                             hw->host_perio_tx_fifo_size);
 709         }
 710
 711         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 712             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 713                 CHECK_BOOL(g_dma, dma_capable);
 714                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 715                 CHECK_RANGE(g_rx_fifo_size,
 716                             16, hw->rx_fifo_size,
 717                             hw->rx_fifo_size);
 718                 CHECK_RANGE(g_np_tx_fifo_size,
 719                             16, hw->dev_nperio_tx_fifo_size,
 720                             hw->dev_nperio_tx_fifo_size);
 721                 dwc2_check_param_tx_fifo_sizes(hsotg);
 722         }
 723 }
 724
 725 /*
 726  * Gets host hardware parameters. Forces host mode if not currently in
 727  * host mode. Should be called immediately after a core soft reset in
 728  * order to get the reset values.
 729  */
 730 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 731 {
 732         struct dwc2_hw_params *hw = &hsotg->hw_params;
 733         u32 gnptxfsiz;
 734         u32 hptxfsiz;
 735
 736         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 737                 return;
 738
 739         dwc2_force_mode(hsotg, true);
 740
 741         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 742         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 743
 744         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 745                                        FIFOSIZE_DEPTH_SHIFT;
 746         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 747                                       FIFOSIZE_DEPTH_SHIFT;
 748 }
 749
 750 /*
 751  * Gets device hardware parameters. Forces device mode if not
 752  * currently in device mode. Should be called immediately after a core
 753  * soft reset in order to get the reset values.
 754  */
 755 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 756 {
 757         struct dwc2_hw_params *hw = &hsotg->hw_params;
 758         u32 gnptxfsiz;
 759         int fifo, fifo_count;
 760
 761         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 762                 return;
 763
 764         dwc2_force_mode(hsotg, false);
 765
 766         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 767
 768         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 769
 770         for (fifo = 1; fifo <= fifo_count; fifo++) {
 771                 hw->g_tx_fifo_size[fifo] =
 772                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 773                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 774         }
 775
 776         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 777                                        FIFOSIZE_DEPTH_SHIFT;
 778 }
 779
 780 /**
 781  * During device initialization, read various hardware configuration
 782  * registers and interpret the contents.
 783  *
 784  * @hsotg: Programming view of the DWC_otg controller
 785  *
 786  */
 787 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 788 {
 789         struct dwc2_hw_params *hw = &hsotg->hw_params;
 790         unsigned int width;
 791         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 792         u32 grxfsiz;
 793
 794         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 795         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 796         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 797         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 798         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 799
 800         /* hwcfg1 */
 801         hw->dev_ep_dirs = hwcfg1;
 802
 803         /* hwcfg2 */
 804         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 805                       GHWCFG2_OP_MODE_SHIFT;
 806         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 807                    GHWCFG2_ARCHITECTURE_SHIFT;
 808         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 809         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 810                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 811         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 812                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 813         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 814                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 815         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 816                          GHWCFG2_NUM_DEV_EP_SHIFT;
 817         hw->nperio_tx_q_depth =
 818                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 819                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 820         hw->host_perio_tx_q_depth =
 821                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 822                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 823         hw->dev_token_q_depth =
 824                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 825                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 826
 827         /* hwcfg3 */
 828         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 829                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 830         hw->max_transfer_size = (1 << (width + 11)) - 1;
 831         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 832                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 833         hw->max_packet_count = (1 << (width + 4)) - 1;
 834         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 835         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 836                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 837         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 838
 839         /* hwcfg4 */
 840         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 841         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 842                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 843         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 844                              GHWCFG4_NUM_IN_EPS_SHIFT;
 845         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 846         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 847         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 848         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 849                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 850         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 851         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 852         hw->service_interval_mode = !!(hwcfg4 &
 853                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 854
 855         /* fifo sizes */
 856         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 857                                 GRXFSIZ_DEPTH_SHIFT;
 858         /*
 859          * Host specific hardware parameters. Reading these parameters
 860          * requires the controller to be in host mode. The mode will
 861          * be forced, if necessary, to read these values.
 862          */
 863         dwc2_get_host_hwparams(hsotg);
 864         dwc2_get_dev_hwparams(hsotg);
 865
 866         return 0;
 867 }
 868
 869 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 870 {
 871         const struct of_device_id *match;
 872         void (*set_params)(struct dwc2_hsotg *data);
 873
 874         dwc2_set_default_params(hsotg);
 875         dwc2_get_device_properties(hsotg);
 876
 877         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 878         if (match && match->data) {
 879                 set_params = match->data;
 880                 set_params(hsotg);
 881         }
 882
 883         dwc2_check_params(hsotg);
 884
 885         return 0;
 886 }