2 * Copyright (C) 2004-2016 Synopsys, Inc.
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5 * modification, are permitted provided that the following conditions
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15 * specific prior written permission.
17 * ALTERNATIVELY, this software may be distributed under the terms of the
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19 * Foundation; either version 2 of the License, or (at your option) any
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32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/of_device.h>
41 static const struct dwc2_core_params params_hi6220 = {
42 .otg_cap = 2, /* No HNP/SRP capable */
43 .otg_ver = 0, /* 1.3 */
45 .dma_desc_fs_enable = 0,
46 .speed = 0, /* High Speed */
47 .enable_dynamic_fifo = 1,
48 .en_multiple_tx_fifo = 1,
49 .host_rx_fifo_size = 512,
50 .host_nperio_tx_fifo_size = 512,
51 .host_perio_tx_fifo_size = 512,
52 .max_transfer_size = 65535,
53 .max_packet_count = 511,
55 .phy_type = 1, /* UTMI */
57 .phy_ulpi_ddr = 0, /* Single */
58 .phy_ulpi_ext_vbus = 0,
61 .host_support_fs_ls_low_power = 0,
62 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
65 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
66 GAHBCFG_HBSTLEN_SHIFT,
68 .external_id_pin_ctl = -1,
72 static const struct dwc2_core_params params_bcm2835 = {
73 .otg_cap = 0, /* HNP/SRP capable */
74 .otg_ver = 0, /* 1.3 */
76 .dma_desc_fs_enable = 0,
77 .speed = 0, /* High Speed */
78 .enable_dynamic_fifo = 1,
79 .en_multiple_tx_fifo = 1,
80 .host_rx_fifo_size = 774, /* 774 DWORDs */
81 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
82 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
83 .max_transfer_size = 65535,
84 .max_packet_count = 511,
86 .phy_type = 1, /* UTMI */
87 .phy_utmi_width = 8, /* 8 bits */
88 .phy_ulpi_ddr = 0, /* Single */
89 .phy_ulpi_ext_vbus = 0,
92 .host_support_fs_ls_low_power = 0,
93 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
98 .external_id_pin_ctl = -1,
102 static const struct dwc2_core_params params_rk3066 = {
103 .otg_cap = 2, /* non-HNP/non-SRP */
105 .dma_desc_enable = 0,
106 .dma_desc_fs_enable = 0,
108 .enable_dynamic_fifo = 1,
109 .en_multiple_tx_fifo = -1,
110 .host_rx_fifo_size = 525, /* 525 DWORDs */
111 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
112 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
113 .max_transfer_size = -1,
114 .max_packet_count = -1,
117 .phy_utmi_width = -1,
119 .phy_ulpi_ext_vbus = -1,
122 .host_support_fs_ls_low_power = -1,
123 .host_ls_low_power_phy_clk = -1,
126 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
127 GAHBCFG_HBSTLEN_SHIFT,
129 .external_id_pin_ctl = -1,
133 static const struct dwc2_core_params params_ltq = {
134 .otg_cap = 2, /* non-HNP/non-SRP */
136 .dma_desc_enable = -1,
137 .dma_desc_fs_enable = -1,
139 .enable_dynamic_fifo = -1,
140 .en_multiple_tx_fifo = -1,
141 .host_rx_fifo_size = 288, /* 288 DWORDs */
142 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
143 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
144 .max_transfer_size = 65535,
145 .max_packet_count = 511,
148 .phy_utmi_width = -1,
150 .phy_ulpi_ext_vbus = -1,
153 .host_support_fs_ls_low_power = -1,
154 .host_ls_low_power_phy_clk = -1,
157 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
158 GAHBCFG_HBSTLEN_SHIFT,
160 .external_id_pin_ctl = -1,
164 static const struct dwc2_core_params params_amlogic = {
165 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
167 .dma_desc_enable = 0,
168 .dma_desc_fs_enable = 0,
169 .speed = DWC2_SPEED_PARAM_HIGH,
170 .enable_dynamic_fifo = 1,
171 .en_multiple_tx_fifo = -1,
172 .host_rx_fifo_size = 512,
173 .host_nperio_tx_fifo_size = 500,
174 .host_perio_tx_fifo_size = 500,
175 .max_transfer_size = -1,
176 .max_packet_count = -1,
178 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
179 .phy_utmi_width = -1,
181 .phy_ulpi_ext_vbus = -1,
184 .host_support_fs_ls_low_power = -1,
185 .host_ls_low_power_phy_clk = -1,
188 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
189 GAHBCFG_HBSTLEN_SHIFT,
191 .external_id_pin_ctl = -1,
195 static const struct dwc2_core_params params_default = {
200 * Disable descriptor dma mode by default as the HW can support
201 * it, but does not support it for SPLIT transactions.
202 * Disable it for FS devices as well.
204 .dma_desc_enable = 0,
205 .dma_desc_fs_enable = 0,
208 .enable_dynamic_fifo = -1,
209 .en_multiple_tx_fifo = -1,
210 .host_rx_fifo_size = -1,
211 .host_nperio_tx_fifo_size = -1,
212 .host_perio_tx_fifo_size = -1,
213 .max_transfer_size = -1,
214 .max_packet_count = -1,
217 .phy_utmi_width = -1,
219 .phy_ulpi_ext_vbus = -1,
222 .host_support_fs_ls_low_power = -1,
223 .host_ls_low_power_phy_clk = -1,
228 .external_id_pin_ctl = -1,
232 const struct of_device_id dwc2_of_match_table[] = {
233 { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
234 { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 },
235 { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
236 { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq },
237 { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq },
238 { .compatible = "snps,dwc2", .data = NULL },
239 { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
240 { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
241 { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
242 { .compatible = "amcc,dwc-otg", .data = NULL },
245 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
247 static void dwc2_get_device_property(struct dwc2_hsotg *hsotg,
248 char *property, u8 size, u64 *value)
256 *value = device_property_read_bool(hsotg->dev, property);
259 if (device_property_read_u8(hsotg->dev, property, &val8))
265 if (device_property_read_u16(hsotg->dev, property, &val16))
271 if (device_property_read_u32(hsotg->dev, property, &val32))
277 if (device_property_read_u64(hsotg->dev, property, value))
283 * The size is checked by the only function that calls
284 * this so this should never happen.
291 static void dwc2_set_core_param(void *param, u8 size, u64 value)
295 *((bool *)param) = !!value;
298 *((u8 *)param) = (u8)value;
301 *((u16 *)param) = (u16)value;
304 *((u32 *)param) = (u32)value;
307 *((u64 *)param) = (u64)value;
311 * The size is checked by the only function that calls
312 * this so this should never happen.
320 * dwc2_set_param() - Set a core parameter
322 * @hsotg: Programming view of the DWC_otg controller
323 * @param: Pointer to the parameter to set
324 * @lookup: True if the property should be looked up
325 * @property: The device property to read
326 * @legacy: The param value to set if @property is not available. This
327 * will typically be the legacy value set in the static
329 * @def: The default value
330 * @min: The minimum value
331 * @max: The maximum value
332 * @size: The size of the core parameter in bytes, or 0 for bool.
334 * This function looks up @property and sets the @param to that value.
335 * If the property doesn't exist it uses the passed-in @value. It will
336 * verify that the value falls between @min and @max. If it doesn't,
337 * it will output an error and set the parameter to either @def or,
338 * failing that, to @min.
340 * The @size is used to write to @param and to query the device
341 * properties so that this same function can be used with different
342 * types of parameters.
344 static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param,
345 bool lookup, char *property, u64 legacy,
346 u64 def, u64 min, u64 max, u8 size)
351 if (WARN_ON(!hsotg || !param || !property))
354 if (WARN((size > 8) || ((size & (size - 1)) != 0),
355 "Invalid size %d for %s\n", size, property))
358 dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n",
359 __func__, property, legacy, def, min, max, size);
361 sizemax = (1ULL << (size * 8)) - 1;
364 /* Override legacy settings. */
366 dwc2_get_device_property(hsotg, property, size, &value);
369 * While the value is not valid, try setting it to the default
370 * value, and failing that, set it to the minimum.
372 while ((value < min) || (value > max)) {
373 /* Print an error unless the value is set to auto. */
374 if (value != sizemax)
375 dev_err(hsotg->dev, "Invalid value %llu for param %s\n",
379 * If we are already the default, just set it to the
383 dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n",
389 /* Try the default value */
390 dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n",
395 dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value);
396 dwc2_set_core_param(param, size, value);
400 * dwc2_set_param_u16() - Set a u16 parameter
402 * See dwc2_set_param().
404 static void dwc2_set_param_u16(struct dwc2_hsotg *hsotg, u16 *param,
405 bool lookup, char *property, u16 legacy,
406 u16 def, u16 min, u16 max)
408 dwc2_set_param(hsotg, param, lookup, property,
409 legacy, def, min, max, 2);
413 * dwc2_set_param_bool() - Set a bool parameter
415 * See dwc2_set_param().
417 * Note: there is no 'legacy' argument here because there is no legacy
418 * source of bool params.
420 static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param,
421 bool lookup, char *property,
422 bool def, bool min, bool max)
424 dwc2_set_param(hsotg, param, lookup, property,
425 def, def, min, max, 0);
428 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
430 /* Parameter access functions */
431 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
436 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
437 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
440 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
441 switch (hsotg->hw_params.op_mode) {
442 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
443 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
444 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
445 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
452 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
463 "%d invalid for otg_cap parameter. Check HW configuration.\n",
465 switch (hsotg->hw_params.op_mode) {
466 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
467 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
469 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
470 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
471 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
472 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
475 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
478 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
481 hsotg->params.otg_cap = val;
484 static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
488 if (val > 0 && (hsotg->params.host_dma <= 0 ||
489 !hsotg->hw_params.dma_desc_enable))
497 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
499 val = (hsotg->params.host_dma > 0 &&
500 hsotg->hw_params.dma_desc_enable);
501 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
504 hsotg->params.dma_desc_enable = val;
507 static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
511 if (val > 0 && (hsotg->params.host_dma <= 0 ||
512 !hsotg->hw_params.dma_desc_enable))
520 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
522 val = (hsotg->params.host_dma > 0 &&
523 hsotg->hw_params.dma_desc_enable);
526 hsotg->params.dma_desc_fs_enable = val;
527 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
531 dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
534 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
537 "Wrong value for host_support_fs_low_power\n");
539 "host_support_fs_low_power must be 0 or 1\n");
543 "Setting host_support_fs_low_power to %d\n", val);
546 hsotg->params.host_support_fs_ls_low_power = val;
549 static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
554 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
562 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
564 val = hsotg->hw_params.enable_dynamic_fifo;
565 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
568 hsotg->params.enable_dynamic_fifo = val;
571 static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
575 if (val < 16 || val > hsotg->hw_params.rx_fifo_size)
581 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
583 val = hsotg->hw_params.rx_fifo_size;
584 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
587 hsotg->params.host_rx_fifo_size = val;
590 static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
595 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
601 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
603 val = hsotg->hw_params.host_nperio_tx_fifo_size;
604 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
608 hsotg->params.host_nperio_tx_fifo_size = val;
611 static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
616 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
622 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
624 val = hsotg->hw_params.host_perio_tx_fifo_size;
625 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
629 hsotg->params.host_perio_tx_fifo_size = val;
632 static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
636 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
642 "%d invalid for max_transfer_size. Check HW configuration.\n",
644 val = hsotg->hw_params.max_transfer_size;
645 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
648 hsotg->params.max_transfer_size = val;
651 static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
655 if (val < 15 || val > hsotg->hw_params.max_packet_count)
661 "%d invalid for max_packet_count. Check HW configuration.\n",
663 val = hsotg->hw_params.max_packet_count;
664 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
667 hsotg->params.max_packet_count = val;
670 static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
674 if (val < 1 || val > hsotg->hw_params.host_channels)
680 "%d invalid for host_channels. Check HW configuration.\n",
682 val = hsotg->hw_params.host_channels;
683 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
686 hsotg->params.host_channels = val;
689 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
692 u32 hs_phy_type, fs_phy_type;
694 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
695 DWC2_PHY_TYPE_PARAM_ULPI)) {
697 dev_err(hsotg->dev, "Wrong value for phy_type\n");
698 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
704 hs_phy_type = hsotg->hw_params.hs_phy_type;
705 fs_phy_type = hsotg->hw_params.fs_phy_type;
706 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
707 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
708 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
710 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
711 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
712 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
714 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
715 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
721 "%d invalid for phy_type. Check HW configuration.\n",
723 val = DWC2_PHY_TYPE_PARAM_FS;
724 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
725 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
726 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
727 val = DWC2_PHY_TYPE_PARAM_UTMI;
729 val = DWC2_PHY_TYPE_PARAM_ULPI;
731 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
734 hsotg->params.phy_type = val;
737 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
739 return hsotg->params.phy_type;
742 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
746 if (DWC2_OUT_OF_BOUNDS(val, 0, 2)) {
748 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
749 dev_err(hsotg->dev, "max_speed parameter must be 0, 1, or 2\n");
754 if (dwc2_is_hs_iot(hsotg) &&
755 val == DWC2_SPEED_PARAM_LOW)
758 if (val == DWC2_SPEED_PARAM_HIGH &&
759 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
765 "%d invalid for speed parameter. Check HW configuration.\n",
767 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
768 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
769 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
772 hsotg->params.speed = val;
775 static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
780 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
781 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
784 "Wrong value for host_ls_low_power_phy_clk parameter\n");
786 "host_ls_low_power_phy_clk must be 0 or 1\n");
791 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
792 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
798 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
800 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
801 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
802 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
803 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
807 hsotg->params.host_ls_low_power_phy_clk = val;
810 static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
812 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
814 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
815 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
818 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
821 hsotg->params.phy_ulpi_ddr = val;
824 static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
826 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
829 "Wrong value for phy_ulpi_ext_vbus\n");
831 "phy_ulpi_ext_vbus must be 0 or 1\n");
834 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
837 hsotg->params.phy_ulpi_ext_vbus = val;
840 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
844 switch (hsotg->hw_params.utmi_phy_data_width) {
845 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
848 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
851 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
852 valid = (val == 8 || val == 16);
859 "%d invalid for phy_utmi_width. Check HW configuration.\n",
862 val = (hsotg->hw_params.utmi_phy_data_width ==
863 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
864 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
867 hsotg->params.phy_utmi_width = val;
870 static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
872 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
874 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
875 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
878 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
881 hsotg->params.ulpi_fs_ls = val;
884 static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
886 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
888 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
889 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
892 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
895 hsotg->params.ts_dline = val;
898 static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
902 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
904 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
905 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
911 if (val == 1 && !(hsotg->hw_params.i2c_enable))
917 "%d invalid for i2c_enable. Check HW configuration.\n",
919 val = hsotg->hw_params.i2c_enable;
920 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
923 hsotg->params.i2c_enable = val;
926 static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
931 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
934 "Wrong value for en_multiple_tx_fifo,\n");
936 "en_multiple_tx_fifo must be 0 or 1\n");
941 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
947 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
949 val = hsotg->hw_params.en_multiple_tx_fifo;
950 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
953 hsotg->params.en_multiple_tx_fifo = val;
956 static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
960 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
963 "'%d' invalid for parameter reload_ctl\n", val);
964 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
969 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
975 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
977 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
978 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
981 hsotg->params.reload_ctl = val;
984 static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
987 hsotg->params.ahbcfg = val;
989 hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
990 GAHBCFG_HBSTLEN_SHIFT;
993 static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
995 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
998 "'%d' invalid for parameter otg_ver\n", val);
1000 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
1003 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
1006 hsotg->params.otg_ver = val;
1009 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
1011 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1014 "'%d' invalid for parameter uframe_sched\n",
1016 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1019 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1022 hsotg->params.uframe_sched = val;
1025 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
1028 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1031 "'%d' invalid for parameter external_id_pin_ctl\n",
1033 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1036 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1039 hsotg->params.external_id_pin_ctl = val;
1042 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
1045 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1048 "'%d' invalid for parameter hibernation\n",
1050 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1053 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1056 hsotg->params.hibernation = val;
1059 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
1063 char *property = "g-tx-fifo-size";
1064 struct dwc2_core_params *p = &hsotg->params;
1066 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
1068 /* Read tx fifo sizes */
1069 num = device_property_read_u32_array(hsotg->dev, property, NULL, 0);
1072 device_property_read_u32_array(hsotg->dev, property,
1073 &p->g_tx_fifo_size[1],
1076 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
1078 memcpy(&p->g_tx_fifo_size[1],
1082 num = ARRAY_SIZE(p_tx_fifo);
1085 for (i = 0; i < num; i++) {
1086 if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size))
1089 dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n",
1090 property, i + 1, p->g_tx_fifo_size[i + 1]);
1094 static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg)
1096 struct dwc2_hw_params *hw = &hsotg->hw_params;
1097 struct dwc2_core_params *p = &hsotg->params;
1098 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1101 dwc2_set_param_bool(hsotg, &p->g_dma,
1102 false, "gadget-dma",
1106 /* DMA Descriptor */
1107 dwc2_set_param_bool(hsotg, &p->g_dma_desc, false,
1110 !!hw->dma_desc_enable);
1114 * dwc2_set_parameters() - Set all core parameters.
1116 * @hsotg: Programming view of the DWC_otg controller
1117 * @params: The parameters to set
1119 static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1120 const struct dwc2_core_params *params)
1122 struct dwc2_hw_params *hw = &hsotg->hw_params;
1123 struct dwc2_core_params *p = &hsotg->params;
1124 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1126 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1127 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
1128 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1129 dev_dbg(hsotg->dev, "Setting HOST parameters\n");
1131 dwc2_set_param_bool(hsotg, &p->host_dma,
1136 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1137 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1139 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1140 params->host_support_fs_ls_low_power);
1141 dwc2_set_param_enable_dynamic_fifo(hsotg,
1142 params->enable_dynamic_fifo);
1143 dwc2_set_param_host_rx_fifo_size(hsotg,
1144 params->host_rx_fifo_size);
1145 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
1146 params->host_nperio_tx_fifo_size);
1147 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
1148 params->host_perio_tx_fifo_size);
1149 dwc2_set_param_max_transfer_size(hsotg,
1150 params->max_transfer_size);
1151 dwc2_set_param_max_packet_count(hsotg,
1152 params->max_packet_count);
1153 dwc2_set_param_host_channels(hsotg, params->host_channels);
1154 dwc2_set_param_phy_type(hsotg, params->phy_type);
1155 dwc2_set_param_speed(hsotg, params->speed);
1156 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1157 params->host_ls_low_power_phy_clk);
1158 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1159 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1160 params->phy_ulpi_ext_vbus);
1161 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1162 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1163 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1164 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1165 dwc2_set_param_en_multiple_tx_fifo(hsotg,
1166 params->en_multiple_tx_fifo);
1167 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1168 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1169 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1170 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
1171 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
1172 dwc2_set_param_hibernation(hsotg, params->hibernation);
1175 * Set devicetree-only parameters. These parameters do not
1176 * take any values from @params.
1178 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
1179 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1180 dev_dbg(hsotg->dev, "Setting peripheral device properties\n");
1182 dwc2_set_gadget_dma(hsotg);
1185 * The values for g_rx_fifo_size (2048) and
1186 * g_np_tx_fifo_size (1024) come from the legacy s3c
1187 * gadget driver. These defaults have been hard-coded
1188 * for some time so many platforms depend on these
1189 * values. Leave them as defaults for now and only
1190 * auto-detect if the hardware does not support the
1193 dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size,
1194 true, "g-rx-fifo-size", 2048,
1196 16, hw->rx_fifo_size);
1198 dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size,
1199 true, "g-np-tx-fifo-size", 1024,
1200 hw->dev_nperio_tx_fifo_size,
1201 16, hw->dev_nperio_tx_fifo_size);
1203 dwc2_set_param_tx_fifo_sizes(hsotg);
1208 * Gets host hardware parameters. Forces host mode if not currently in
1209 * host mode. Should be called immediately after a core soft reset in
1210 * order to get the reset values.
1212 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1214 struct dwc2_hw_params *hw = &hsotg->hw_params;
1219 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1222 forced = dwc2_force_mode_if_needed(hsotg, true);
1224 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1225 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1226 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1227 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1230 dwc2_clear_force_mode(hsotg);
1232 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1233 FIFOSIZE_DEPTH_SHIFT;
1234 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1235 FIFOSIZE_DEPTH_SHIFT;
1239 * Gets device hardware parameters. Forces device mode if not
1240 * currently in device mode. Should be called immediately after a core
1241 * soft reset in order to get the reset values.
1243 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1245 struct dwc2_hw_params *hw = &hsotg->hw_params;
1249 if (hsotg->dr_mode == USB_DR_MODE_HOST)
1252 forced = dwc2_force_mode_if_needed(hsotg, false);
1254 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1255 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1258 dwc2_clear_force_mode(hsotg);
1260 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1261 FIFOSIZE_DEPTH_SHIFT;
1265 * During device initialization, read various hardware configuration
1266 * registers and interpret the contents.
1268 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1270 struct dwc2_hw_params *hw = &hsotg->hw_params;
1272 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
1276 * Attempt to ensure this device is really a DWC_otg Controller.
1277 * Read and verify the GSNPSID register contents. The value should be
1278 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
1279 * as in "OTG version 2.xx" or "OTG version 3.xx".
1281 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
1282 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1283 (hw->snpsid & 0xfffff000) != 0x4f543000 &&
1284 (hw->snpsid & 0xffff0000) != 0x55310000 &&
1285 (hw->snpsid & 0xffff0000) != 0x55320000) {
1286 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
1291 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
1292 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
1293 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
1295 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
1296 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1297 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
1298 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1299 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1301 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1302 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1303 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1304 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1305 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1308 * Host specific hardware parameters. Reading these parameters
1309 * requires the controller to be in host mode. The mode will
1310 * be forced, if necessary, to read these values.
1312 dwc2_get_host_hwparams(hsotg);
1313 dwc2_get_dev_hwparams(hsotg);
1316 hw->dev_ep_dirs = hwcfg1;
1319 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1320 GHWCFG2_OP_MODE_SHIFT;
1321 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1322 GHWCFG2_ARCHITECTURE_SHIFT;
1323 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1324 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1325 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1326 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1327 GHWCFG2_HS_PHY_TYPE_SHIFT;
1328 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1329 GHWCFG2_FS_PHY_TYPE_SHIFT;
1330 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1331 GHWCFG2_NUM_DEV_EP_SHIFT;
1332 hw->nperio_tx_q_depth =
1333 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1334 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1335 hw->host_perio_tx_q_depth =
1336 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1337 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1338 hw->dev_token_q_depth =
1339 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1340 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1343 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1344 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1345 hw->max_transfer_size = (1 << (width + 11)) - 1;
1346 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1347 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1348 hw->max_packet_count = (1 << (width + 4)) - 1;
1349 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1350 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1351 GHWCFG3_DFIFO_DEPTH_SHIFT;
1354 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1355 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1356 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1357 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1358 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1359 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1360 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1363 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1364 GRXFSIZ_DEPTH_SHIFT;
1366 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1367 dev_dbg(hsotg->dev, " op_mode=%d\n",
1369 dev_dbg(hsotg->dev, " arch=%d\n",
1371 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1372 hw->dma_desc_enable);
1373 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1374 hw->power_optimized);
1375 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1377 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1379 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1381 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
1382 hw->utmi_phy_data_width);
1383 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1385 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1386 hw->num_dev_perio_in_ep);
1387 dev_dbg(hsotg->dev, " host_channels=%d\n",
1389 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1390 hw->max_transfer_size);
1391 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1392 hw->max_packet_count);
1393 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1394 hw->nperio_tx_q_depth);
1395 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1396 hw->host_perio_tx_q_depth);
1397 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1398 hw->dev_token_q_depth);
1399 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1400 hw->enable_dynamic_fifo);
1401 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1402 hw->en_multiple_tx_fifo);
1403 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1404 hw->total_fifo_size);
1405 dev_dbg(hsotg->dev, " rx_fifo_size=%d\n",
1407 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1408 hw->host_nperio_tx_fifo_size);
1409 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1410 hw->host_perio_tx_fifo_size);
1411 dev_dbg(hsotg->dev, "\n");
1416 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1418 const struct of_device_id *match;
1419 struct dwc2_core_params params;
1421 match = of_match_device(dwc2_of_match_table, hsotg->dev);
1422 if (match && match->data)
1423 params = *((struct dwc2_core_params *)match->data);
1425 params = params_default;
1427 if (dwc2_is_fs_iot(hsotg)) {
1428 params.speed = DWC2_SPEED_PARAM_FULL;
1429 params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
1432 dwc2_set_parameters(hsotg, ¶ms);