drivers/usb/dwc2/params.c

   1 /*
   2  * Copyright (C) 2004-2016 Synopsys, Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions, and the following disclaimer,
   9  *    without modification.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. The names of the above-listed copyright holders may not be used
  14  *    to endorse or promote products derived from this software without
  15  *    specific prior written permission.
  16  *
  17  * ALTERNATIVELY, this software may be distributed under the terms of the
  18  * GNU General Public License ("GPL") as published by the Free Software
  19  * Foundation; either version 2 of the License, or (at your option) any
  20  * later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  23  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  24  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  25  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  26  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  27  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  28  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  29  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  30  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  31  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/of_device.h>
  38
  39 #include "core.h"
  40
  41 static const struct dwc2_core_params params_hi6220 = {
  42         .otg_cap                        = 2,    /* No HNP/SRP capable */
  43         .otg_ver                        = 0,    /* 1.3 */
  44         .dma_desc_enable                = 0,
  45         .dma_desc_fs_enable             = 0,
  46         .speed                          = 0,    /* High Speed */
  47         .enable_dynamic_fifo            = 1,
  48         .en_multiple_tx_fifo            = 1,
  49         .host_rx_fifo_size              = 512,
  50         .host_nperio_tx_fifo_size       = 512,
  51         .host_perio_tx_fifo_size        = 512,
  52         .max_transfer_size              = 65535,
  53         .max_packet_count               = 511,
  54         .host_channels                  = 16,
  55         .phy_type                       = 1,    /* UTMI */
  56         .phy_utmi_width                 = 8,
  57         .phy_ulpi_ddr                   = 0,    /* Single */
  58         .phy_ulpi_ext_vbus              = 0,
  59         .i2c_enable                     = 0,
  60         .ulpi_fs_ls                     = 0,
  61         .host_support_fs_ls_low_power   = 0,
  62         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  63         .ts_dline                       = 0,
  64         .reload_ctl                     = 0,
  65         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
  66                                           GAHBCFG_HBSTLEN_SHIFT,
  67         .uframe_sched                   = 0,
  68         .external_id_pin_ctl            = -1,
  69         .hibernation                    = -1,
  70 };
  71
  72 static const struct dwc2_core_params params_bcm2835 = {
  73         .otg_cap                        = 0,    /* HNP/SRP capable */
  74         .otg_ver                        = 0,    /* 1.3 */
  75         .dma_desc_enable                = 0,
  76         .dma_desc_fs_enable             = 0,
  77         .speed                          = 0,    /* High Speed */
  78         .enable_dynamic_fifo            = 1,
  79         .en_multiple_tx_fifo            = 1,
  80         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  81         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
  82         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
  83         .max_transfer_size              = 65535,
  84         .max_packet_count               = 511,
  85         .host_channels                  = 8,
  86         .phy_type                       = 1,    /* UTMI */
  87         .phy_utmi_width                 = 8,    /* 8 bits */
  88         .phy_ulpi_ddr                   = 0,    /* Single */
  89         .phy_ulpi_ext_vbus              = 0,
  90         .i2c_enable                     = 0,
  91         .ulpi_fs_ls                     = 0,
  92         .host_support_fs_ls_low_power   = 0,
  93         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  94         .ts_dline                       = 0,
  95         .reload_ctl                     = 0,
  96         .ahbcfg                         = 0x10,
  97         .uframe_sched                   = 0,
  98         .external_id_pin_ctl            = -1,
  99         .hibernation                    = -1,
 100 };
 101
 102 static const struct dwc2_core_params params_rk3066 = {
 103         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 104         .otg_ver                        = -1,
 105         .dma_desc_enable                = 0,
 106         .dma_desc_fs_enable             = 0,
 107         .speed                          = -1,
 108         .enable_dynamic_fifo            = 1,
 109         .en_multiple_tx_fifo            = -1,
 110         .host_rx_fifo_size              = 525,  /* 525 DWORDs */
 111         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 112         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 113         .max_transfer_size              = -1,
 114         .max_packet_count               = -1,
 115         .host_channels                  = -1,
 116         .phy_type                       = -1,
 117         .phy_utmi_width                 = -1,
 118         .phy_ulpi_ddr                   = -1,
 119         .phy_ulpi_ext_vbus              = -1,
 120         .i2c_enable                     = -1,
 121         .ulpi_fs_ls                     = -1,
 122         .host_support_fs_ls_low_power   = -1,
 123         .host_ls_low_power_phy_clk      = -1,
 124         .ts_dline                       = -1,
 125         .reload_ctl                     = -1,
 126         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 127                                           GAHBCFG_HBSTLEN_SHIFT,
 128         .uframe_sched                   = -1,
 129         .external_id_pin_ctl            = -1,
 130         .hibernation                    = -1,
 131 };
 132
 133 static const struct dwc2_core_params params_ltq = {
 134         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 135         .otg_ver                        = -1,
 136         .dma_desc_enable                = -1,
 137         .dma_desc_fs_enable             = -1,
 138         .speed                          = -1,
 139         .enable_dynamic_fifo            = -1,
 140         .en_multiple_tx_fifo            = -1,
 141         .host_rx_fifo_size              = 288,  /* 288 DWORDs */
 142         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 143         .host_perio_tx_fifo_size        = 96,   /* 96 DWORDs */
 144         .max_transfer_size              = 65535,
 145         .max_packet_count               = 511,
 146         .host_channels                  = -1,
 147         .phy_type                       = -1,
 148         .phy_utmi_width                 = -1,
 149         .phy_ulpi_ddr                   = -1,
 150         .phy_ulpi_ext_vbus              = -1,
 151         .i2c_enable                     = -1,
 152         .ulpi_fs_ls                     = -1,
 153         .host_support_fs_ls_low_power   = -1,
 154         .host_ls_low_power_phy_clk      = -1,
 155         .ts_dline                       = -1,
 156         .reload_ctl                     = -1,
 157         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 158                                           GAHBCFG_HBSTLEN_SHIFT,
 159         .uframe_sched                   = -1,
 160         .external_id_pin_ctl            = -1,
 161         .hibernation                    = -1,
 162 };
 163
 164 static const struct dwc2_core_params params_amlogic = {
 165         .otg_cap                        = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
 166         .otg_ver                        = -1,
 167         .dma_desc_enable                = 0,
 168         .dma_desc_fs_enable             = 0,
 169         .speed                          = DWC2_SPEED_PARAM_HIGH,
 170         .enable_dynamic_fifo            = 1,
 171         .en_multiple_tx_fifo            = -1,
 172         .host_rx_fifo_size              = 512,
 173         .host_nperio_tx_fifo_size       = 500,
 174         .host_perio_tx_fifo_size        = 500,
 175         .max_transfer_size              = -1,
 176         .max_packet_count               = -1,
 177         .host_channels                  = 16,
 178         .phy_type                       = DWC2_PHY_TYPE_PARAM_UTMI,
 179         .phy_utmi_width                 = -1,
 180         .phy_ulpi_ddr                   = -1,
 181         .phy_ulpi_ext_vbus              = -1,
 182         .i2c_enable                     = -1,
 183         .ulpi_fs_ls                     = -1,
 184         .host_support_fs_ls_low_power   = -1,
 185         .host_ls_low_power_phy_clk      = -1,
 186         .ts_dline                       = -1,
 187         .reload_ctl                     = 1,
 188         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR8 <<
 189                                           GAHBCFG_HBSTLEN_SHIFT,
 190         .uframe_sched                   = 0,
 191         .external_id_pin_ctl            = -1,
 192         .hibernation                    = -1,
 193 };
 194
 195 static const struct dwc2_core_params params_default = {
 196         .otg_cap                        = -1,
 197         .otg_ver                        = -1,
 198
 199         /*
 200          * Disable descriptor dma mode by default as the HW can support
 201          * it, but does not support it for SPLIT transactions.
 202          * Disable it for FS devices as well.
 203          */
 204         .dma_desc_enable                = 0,
 205         .dma_desc_fs_enable             = 0,
 206
 207         .speed                          = -1,
 208         .enable_dynamic_fifo            = -1,
 209         .en_multiple_tx_fifo            = -1,
 210         .host_rx_fifo_size              = -1,
 211         .host_nperio_tx_fifo_size       = -1,
 212         .host_perio_tx_fifo_size        = -1,
 213         .max_transfer_size              = -1,
 214         .max_packet_count               = -1,
 215         .host_channels                  = -1,
 216         .phy_type                       = -1,
 217         .phy_utmi_width                 = -1,
 218         .phy_ulpi_ddr                   = -1,
 219         .phy_ulpi_ext_vbus              = -1,
 220         .i2c_enable                     = -1,
 221         .ulpi_fs_ls                     = -1,
 222         .host_support_fs_ls_low_power   = -1,
 223         .host_ls_low_power_phy_clk      = -1,
 224         .ts_dline                       = -1,
 225         .reload_ctl                     = -1,
 226         .ahbcfg                         = -1,
 227         .uframe_sched                   = -1,
 228         .external_id_pin_ctl            = -1,
 229         .hibernation                    = -1,
 230 };
 231
 232 const struct of_device_id dwc2_of_match_table[] = {
 233         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 234         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
 235         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 236         { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
 237         { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
 238         { .compatible = "snps,dwc2", .data = NULL },
 239         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 240         { .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
 241         { .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
 242         { .compatible = "amcc,dwc-otg", .data = NULL },
 243         {},
 244 };
 245 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 246
 247 static void dwc2_get_device_property(struct dwc2_hsotg *hsotg,
 248                                      char *property, u8 size, u64 *value)
 249 {
 250         u8 val8;
 251         u16 val16;
 252         u32 val32;
 253
 254         switch (size) {
 255         case 0:
 256                 *value = device_property_read_bool(hsotg->dev, property);
 257                 break;
 258         case 1:
 259                 if (device_property_read_u8(hsotg->dev, property, &val8))
 260                         return;
 261
 262                 *value = val8;
 263                 break;
 264         case 2:
 265                 if (device_property_read_u16(hsotg->dev, property, &val16))
 266                         return;
 267
 268                 *value = val16;
 269                 break;
 270         case 4:
 271                 if (device_property_read_u32(hsotg->dev, property, &val32))
 272                         return;
 273
 274                 *value = val32;
 275                 break;
 276         case 8:
 277                 if (device_property_read_u64(hsotg->dev, property, value))
 278                         return;
 279
 280                 break;
 281         default:
 282                 /*
 283                  * The size is checked by the only function that calls
 284                  * this so this should never happen.
 285                  */
 286                 WARN_ON(1);
 287                 return;
 288         }
 289 }
 290
 291 static void dwc2_set_core_param(void *param, u8 size, u64 value)
 292 {
 293         switch (size) {
 294         case 0:
 295                 *((bool *)param) = !!value;
 296                 break;
 297         case 1:
 298                 *((u8 *)param) = (u8)value;
 299                 break;
 300         case 2:
 301                 *((u16 *)param) = (u16)value;
 302                 break;
 303         case 4:
 304                 *((u32 *)param) = (u32)value;
 305                 break;
 306         case 8:
 307                 *((u64 *)param) = (u64)value;
 308                 break;
 309         default:
 310                 /*
 311                  * The size is checked by the only function that calls
 312                  * this so this should never happen.
 313                  */
 314                 WARN_ON(1);
 315                 return;
 316         }
 317 }
 318
 319 /**
 320  * dwc2_set_param() - Set a core parameter
 321  *
 322  * @hsotg: Programming view of the DWC_otg controller
 323  * @param: Pointer to the parameter to set
 324  * @lookup: True if the property should be looked up
 325  * @property: The device property to read
 326  * @legacy: The param value to set if @property is not available. This
 327  *          will typically be the legacy value set in the static
 328  *          params structure.
 329  * @def: The default value
 330  * @min: The minimum value
 331  * @max: The maximum value
 332  * @size: The size of the core parameter in bytes, or 0 for bool.
 333  *
 334  * This function looks up @property and sets the @param to that value.
 335  * If the property doesn't exist it uses the passed-in @value. It will
 336  * verify that the value falls between @min and @max. If it doesn't,
 337  * it will output an error and set the parameter to either @def or,
 338  * failing that, to @min.
 339  *
 340  * The @size is used to write to @param and to query the device
 341  * properties so that this same function can be used with different
 342  * types of parameters.
 343  */
 344 static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param,
 345                            bool lookup, char *property, u64 legacy,
 346                            u64 def, u64 min, u64 max, u8 size)
 347 {
 348         u64 sizemax;
 349         u64 value;
 350
 351         if (WARN_ON(!hsotg || !param || !property))
 352                 return;
 353
 354         if (WARN((size > 8) || ((size & (size - 1)) != 0),
 355                  "Invalid size %d for %s\n", size, property))
 356                 return;
 357
 358         dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n",
 359                  __func__, property, legacy, def, min, max, size);
 360
 361         sizemax = (1ULL << (size * 8)) - 1;
 362         value = legacy;
 363
 364         /* Override legacy settings. */
 365         if (lookup)
 366                 dwc2_get_device_property(hsotg, property, size, &value);
 367
 368         /*
 369          * While the value is not valid, try setting it to the default
 370          * value, and failing that, set it to the minimum.
 371          */
 372         while ((value < min) || (value > max)) {
 373                 /* Print an error unless the value is set to auto. */
 374                 if (value != sizemax)
 375                         dev_err(hsotg->dev, "Invalid value %llu for param %s\n",
 376                                 value, property);
 377
 378                 /*
 379                  * If we are already the default, just set it to the
 380                  * minimum.
 381                  */
 382                 if (value == def) {
 383                         dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n",
 384                                  __func__, min);
 385                         value = min;
 386                         break;
 387                 }
 388
 389                 /* Try the default value */
 390                 dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n",
 391                          __func__, def);
 392                 value = def;
 393         }
 394
 395         dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value);
 396         dwc2_set_core_param(param, size, value);
 397 }
 398
 399 /**
 400  * dwc2_set_param_u16() - Set a u16 parameter
 401  *
 402  * See dwc2_set_param().
 403  */
 404 static void dwc2_set_param_u16(struct dwc2_hsotg *hsotg, u16 *param,
 405                                bool lookup, char *property, u16 legacy,
 406                                u16 def, u16 min, u16 max)
 407 {
 408         dwc2_set_param(hsotg, param, lookup, property,
 409                        legacy, def, min, max, 2);
 410 }
 411
 412 /**
 413  * dwc2_set_param_bool() - Set a bool parameter
 414  *
 415  * See dwc2_set_param().
 416  *
 417  * Note: there is no 'legacy' argument here because there is no legacy
 418  * source of bool params.
 419  */
 420 static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param,
 421                                 bool lookup, char *property,
 422                                 bool def, bool min, bool max)
 423 {
 424         dwc2_set_param(hsotg, param, lookup, property,
 425                        def, def, min, max, 0);
 426 }
 427
 428 #define DWC2_OUT_OF_BOUNDS(a, b, c)     ((a) < (b) || (a) > (c))
 429
 430 /* Parameter access functions */
 431 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
 432 {
 433         int valid = 1;
 434
 435         switch (val) {
 436         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 437                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 438                         valid = 0;
 439                 break;
 440         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 441                 switch (hsotg->hw_params.op_mode) {
 442                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 443                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 444                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 445                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 446                         break;
 447                 default:
 448                         valid = 0;
 449                         break;
 450                 }
 451                 break;
 452         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 453                 /* always valid */
 454                 break;
 455         default:
 456                 valid = 0;
 457                 break;
 458         }
 459
 460         if (!valid) {
 461                 if (val >= 0)
 462                         dev_err(hsotg->dev,
 463                                 "%d invalid for otg_cap parameter. Check HW configuration.\n",
 464                                 val);
 465                 switch (hsotg->hw_params.op_mode) {
 466                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 467                         val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 468                         break;
 469                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 470                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 471                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 472                         val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 473                         break;
 474                 default:
 475                         val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 476                         break;
 477                 }
 478                 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
 479         }
 480
 481         hsotg->params.otg_cap = val;
 482 }
 483
 484 static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
 485 {
 486         int valid = 1;
 487
 488         if (val > 0 && (hsotg->params.host_dma <= 0 ||
 489                         !hsotg->hw_params.dma_desc_enable))
 490                 valid = 0;
 491         if (val < 0)
 492                 valid = 0;
 493
 494         if (!valid) {
 495                 if (val >= 0)
 496                         dev_err(hsotg->dev,
 497                                 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
 498                                 val);
 499                 val = (hsotg->params.host_dma > 0 &&
 500                         hsotg->hw_params.dma_desc_enable);
 501                 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
 502         }
 503
 504         hsotg->params.dma_desc_enable = val;
 505 }
 506
 507 static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
 508 {
 509         int valid = 1;
 510
 511         if (val > 0 && (hsotg->params.host_dma <= 0 ||
 512                         !hsotg->hw_params.dma_desc_enable))
 513                 valid = 0;
 514         if (val < 0)
 515                 valid = 0;
 516
 517         if (!valid) {
 518                 if (val >= 0)
 519                         dev_err(hsotg->dev,
 520                                 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
 521                                 val);
 522                 val = (hsotg->params.host_dma > 0 &&
 523                         hsotg->hw_params.dma_desc_enable);
 524         }
 525
 526         hsotg->params.dma_desc_fs_enable = val;
 527         dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
 528 }
 529
 530 static void
 531 dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
 532                                             int val)
 533 {
 534         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 535                 if (val >= 0) {
 536                         dev_err(hsotg->dev,
 537                                 "Wrong value for host_support_fs_low_power\n");
 538                         dev_err(hsotg->dev,
 539                                 "host_support_fs_low_power must be 0 or 1\n");
 540                 }
 541                 val = 0;
 542                 dev_dbg(hsotg->dev,
 543                         "Setting host_support_fs_low_power to %d\n", val);
 544         }
 545
 546         hsotg->params.host_support_fs_ls_low_power = val;
 547 }
 548
 549 static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
 550                                                int val)
 551 {
 552         int valid = 1;
 553
 554         if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
 555                 valid = 0;
 556         if (val < 0)
 557                 valid = 0;
 558
 559         if (!valid) {
 560                 if (val >= 0)
 561                         dev_err(hsotg->dev,
 562                                 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
 563                                 val);
 564                 val = hsotg->hw_params.enable_dynamic_fifo;
 565                 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
 566         }
 567
 568         hsotg->params.enable_dynamic_fifo = val;
 569 }
 570
 571 static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
 572 {
 573         int valid = 1;
 574
 575         if (val < 16 || val > hsotg->hw_params.rx_fifo_size)
 576                 valid = 0;
 577
 578         if (!valid) {
 579                 if (val >= 0)
 580                         dev_err(hsotg->dev,
 581                                 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
 582                                 val);
 583                 val = hsotg->hw_params.rx_fifo_size;
 584                 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
 585         }
 586
 587         hsotg->params.host_rx_fifo_size = val;
 588 }
 589
 590 static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
 591                                                     int val)
 592 {
 593         int valid = 1;
 594
 595         if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
 596                 valid = 0;
 597
 598         if (!valid) {
 599                 if (val >= 0)
 600                         dev_err(hsotg->dev,
 601                                 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
 602                                 val);
 603                 val = hsotg->hw_params.host_nperio_tx_fifo_size;
 604                 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
 605                         val);
 606         }
 607
 608         hsotg->params.host_nperio_tx_fifo_size = val;
 609 }
 610
 611 static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
 612                                                    int val)
 613 {
 614         int valid = 1;
 615
 616         if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
 617                 valid = 0;
 618
 619         if (!valid) {
 620                 if (val >= 0)
 621                         dev_err(hsotg->dev,
 622                                 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
 623                                 val);
 624                 val = hsotg->hw_params.host_perio_tx_fifo_size;
 625                 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
 626                         val);
 627         }
 628
 629         hsotg->params.host_perio_tx_fifo_size = val;
 630 }
 631
 632 static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
 633 {
 634         int valid = 1;
 635
 636         if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
 637                 valid = 0;
 638
 639         if (!valid) {
 640                 if (val >= 0)
 641                         dev_err(hsotg->dev,
 642                                 "%d invalid for max_transfer_size. Check HW configuration.\n",
 643                                 val);
 644                 val = hsotg->hw_params.max_transfer_size;
 645                 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
 646         }
 647
 648         hsotg->params.max_transfer_size = val;
 649 }
 650
 651 static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
 652 {
 653         int valid = 1;
 654
 655         if (val < 15 || val > hsotg->hw_params.max_packet_count)
 656                 valid = 0;
 657
 658         if (!valid) {
 659                 if (val >= 0)
 660                         dev_err(hsotg->dev,
 661                                 "%d invalid for max_packet_count. Check HW configuration.\n",
 662                                 val);
 663                 val = hsotg->hw_params.max_packet_count;
 664                 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
 665         }
 666
 667         hsotg->params.max_packet_count = val;
 668 }
 669
 670 static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
 671 {
 672         int valid = 1;
 673
 674         if (val < 1 || val > hsotg->hw_params.host_channels)
 675                 valid = 0;
 676
 677         if (!valid) {
 678                 if (val >= 0)
 679                         dev_err(hsotg->dev,
 680                                 "%d invalid for host_channels. Check HW configuration.\n",
 681                                 val);
 682                 val = hsotg->hw_params.host_channels;
 683                 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
 684         }
 685
 686         hsotg->params.host_channels = val;
 687 }
 688
 689 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
 690 {
 691         int valid = 0;
 692         u32 hs_phy_type, fs_phy_type;
 693
 694         if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
 695                                DWC2_PHY_TYPE_PARAM_ULPI)) {
 696                 if (val >= 0) {
 697                         dev_err(hsotg->dev, "Wrong value for phy_type\n");
 698                         dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
 699                 }
 700
 701                 valid = 0;
 702         }
 703
 704         hs_phy_type = hsotg->hw_params.hs_phy_type;
 705         fs_phy_type = hsotg->hw_params.fs_phy_type;
 706         if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
 707             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 708              hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 709                 valid = 1;
 710         else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
 711                  (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
 712                   hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 713                 valid = 1;
 714         else if (val == DWC2_PHY_TYPE_PARAM_FS &&
 715                  fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 716                 valid = 1;
 717
 718         if (!valid) {
 719                 if (val >= 0)
 720                         dev_err(hsotg->dev,
 721                                 "%d invalid for phy_type. Check HW configuration.\n",
 722                                 val);
 723                 val = DWC2_PHY_TYPE_PARAM_FS;
 724                 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 725                         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 726                             hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 727                                 val = DWC2_PHY_TYPE_PARAM_UTMI;
 728                         else
 729                                 val = DWC2_PHY_TYPE_PARAM_ULPI;
 730                 }
 731                 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
 732         }
 733
 734         hsotg->params.phy_type = val;
 735 }
 736
 737 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
 738 {
 739         return hsotg->params.phy_type;
 740 }
 741
 742 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
 743 {
 744         int valid = 1;
 745
 746         if (DWC2_OUT_OF_BOUNDS(val, 0, 2)) {
 747                 if (val >= 0) {
 748                         dev_err(hsotg->dev, "Wrong value for speed parameter\n");
 749                         dev_err(hsotg->dev, "max_speed parameter must be 0, 1, or 2\n");
 750                 }
 751                 valid = 0;
 752         }
 753
 754         if (dwc2_is_hs_iot(hsotg) &&
 755             val == DWC2_SPEED_PARAM_LOW)
 756                 valid = 0;
 757
 758         if (val == DWC2_SPEED_PARAM_HIGH &&
 759             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
 760                 valid = 0;
 761
 762         if (!valid) {
 763                 if (val >= 0)
 764                         dev_err(hsotg->dev,
 765                                 "%d invalid for speed parameter. Check HW configuration.\n",
 766                                 val);
 767                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
 768                                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 769                 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
 770         }
 771
 772         hsotg->params.speed = val;
 773 }
 774
 775 static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
 776                                                      int val)
 777 {
 778         int valid = 1;
 779
 780         if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
 781                                DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
 782                 if (val >= 0) {
 783                         dev_err(hsotg->dev,
 784                                 "Wrong value for host_ls_low_power_phy_clk parameter\n");
 785                         dev_err(hsotg->dev,
 786                                 "host_ls_low_power_phy_clk must be 0 or 1\n");
 787                 }
 788                 valid = 0;
 789         }
 790
 791         if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
 792             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
 793                 valid = 0;
 794
 795         if (!valid) {
 796                 if (val >= 0)
 797                         dev_err(hsotg->dev,
 798                                 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
 799                                 val);
 800                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
 801                         ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
 802                         : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
 803                 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
 804                         val);
 805         }
 806
 807         hsotg->params.host_ls_low_power_phy_clk = val;
 808 }
 809
 810 static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
 811 {
 812         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 813                 if (val >= 0) {
 814                         dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
 815                         dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
 816                 }
 817                 val = 0;
 818                 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
 819         }
 820
 821         hsotg->params.phy_ulpi_ddr = val;
 822 }
 823
 824 static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
 825 {
 826         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 827                 if (val >= 0) {
 828                         dev_err(hsotg->dev,
 829                                 "Wrong value for phy_ulpi_ext_vbus\n");
 830                         dev_err(hsotg->dev,
 831                                 "phy_ulpi_ext_vbus must be 0 or 1\n");
 832                 }
 833                 val = 0;
 834                 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
 835         }
 836
 837         hsotg->params.phy_ulpi_ext_vbus = val;
 838 }
 839
 840 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
 841 {
 842         int valid = 0;
 843
 844         switch (hsotg->hw_params.utmi_phy_data_width) {
 845         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 846                 valid = (val == 8);
 847                 break;
 848         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 849                 valid = (val == 16);
 850                 break;
 851         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 852                 valid = (val == 8 || val == 16);
 853                 break;
 854         }
 855
 856         if (!valid) {
 857                 if (val >= 0) {
 858                         dev_err(hsotg->dev,
 859                                 "%d invalid for phy_utmi_width. Check HW configuration.\n",
 860                                 val);
 861                 }
 862                 val = (hsotg->hw_params.utmi_phy_data_width ==
 863                        GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 864                 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
 865         }
 866
 867         hsotg->params.phy_utmi_width = val;
 868 }
 869
 870 static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
 871 {
 872         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 873                 if (val >= 0) {
 874                         dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
 875                         dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
 876                 }
 877                 val = 0;
 878                 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
 879         }
 880
 881         hsotg->params.ulpi_fs_ls = val;
 882 }
 883
 884 static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
 885 {
 886         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 887                 if (val >= 0) {
 888                         dev_err(hsotg->dev, "Wrong value for ts_dline\n");
 889                         dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
 890                 }
 891                 val = 0;
 892                 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
 893         }
 894
 895         hsotg->params.ts_dline = val;
 896 }
 897
 898 static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
 899 {
 900         int valid = 1;
 901
 902         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 903                 if (val >= 0) {
 904                         dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
 905                         dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
 906                 }
 907
 908                 valid = 0;
 909         }
 910
 911         if (val == 1 && !(hsotg->hw_params.i2c_enable))
 912                 valid = 0;
 913
 914         if (!valid) {
 915                 if (val >= 0)
 916                         dev_err(hsotg->dev,
 917                                 "%d invalid for i2c_enable. Check HW configuration.\n",
 918                                 val);
 919                 val = hsotg->hw_params.i2c_enable;
 920                 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
 921         }
 922
 923         hsotg->params.i2c_enable = val;
 924 }
 925
 926 static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
 927                                                int val)
 928 {
 929         int valid = 1;
 930
 931         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 932                 if (val >= 0) {
 933                         dev_err(hsotg->dev,
 934                                 "Wrong value for en_multiple_tx_fifo,\n");
 935                         dev_err(hsotg->dev,
 936                                 "en_multiple_tx_fifo must be 0 or 1\n");
 937                 }
 938                 valid = 0;
 939         }
 940
 941         if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
 942                 valid = 0;
 943
 944         if (!valid) {
 945                 if (val >= 0)
 946                         dev_err(hsotg->dev,
 947                                 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
 948                                 val);
 949                 val = hsotg->hw_params.en_multiple_tx_fifo;
 950                 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
 951         }
 952
 953         hsotg->params.en_multiple_tx_fifo = val;
 954 }
 955
 956 static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
 957 {
 958         int valid = 1;
 959
 960         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 961                 if (val >= 0) {
 962                         dev_err(hsotg->dev,
 963                                 "'%d' invalid for parameter reload_ctl\n", val);
 964                         dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
 965                 }
 966                 valid = 0;
 967         }
 968
 969         if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
 970                 valid = 0;
 971
 972         if (!valid) {
 973                 if (val >= 0)
 974                         dev_err(hsotg->dev,
 975                                 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
 976                                 val);
 977                 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
 978                 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
 979         }
 980
 981         hsotg->params.reload_ctl = val;
 982 }
 983
 984 static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
 985 {
 986         if (val != -1)
 987                 hsotg->params.ahbcfg = val;
 988         else
 989                 hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
 990                                                 GAHBCFG_HBSTLEN_SHIFT;
 991 }
 992
 993 static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
 994 {
 995         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
 996                 if (val >= 0) {
 997                         dev_err(hsotg->dev,
 998                                 "'%d' invalid for parameter otg_ver\n", val);
 999                         dev_err(hsotg->dev,
1000                                 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
1001                 }
1002                 val = 0;
1003                 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
1004         }
1005
1006         hsotg->params.otg_ver = val;
1007 }
1008
1009 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
1010 {
1011         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1012                 if (val >= 0) {
1013                         dev_err(hsotg->dev,
1014                                 "'%d' invalid for parameter uframe_sched\n",
1015                                 val);
1016                         dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
1017                 }
1018                 val = 1;
1019                 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
1020         }
1021
1022         hsotg->params.uframe_sched = val;
1023 }
1024
1025 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
1026                                                int val)
1027 {
1028         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1029                 if (val >= 0) {
1030                         dev_err(hsotg->dev,
1031                                 "'%d' invalid for parameter external_id_pin_ctl\n",
1032                                 val);
1033                         dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
1034                 }
1035                 val = 0;
1036                 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
1037         }
1038
1039         hsotg->params.external_id_pin_ctl = val;
1040 }
1041
1042 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
1043                                        int val)
1044 {
1045         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
1046                 if (val >= 0) {
1047                         dev_err(hsotg->dev,
1048                                 "'%d' invalid for parameter hibernation\n",
1049                                 val);
1050                         dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
1051                 }
1052                 val = 0;
1053                 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
1054         }
1055
1056         hsotg->params.hibernation = val;
1057 }
1058
1059 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
1060 {
1061         int i;
1062         int num;
1063         char *property = "g-tx-fifo-size";
1064         struct dwc2_core_params *p = &hsotg->params;
1065
1066         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
1067
1068         /* Read tx fifo sizes */
1069         num = device_property_read_u32_array(hsotg->dev, property, NULL, 0);
1070
1071         if (num > 0) {
1072                 device_property_read_u32_array(hsotg->dev, property,
1073                                                &p->g_tx_fifo_size[1],
1074                                                num);
1075         } else {
1076                 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
1077
1078                 memcpy(&p->g_tx_fifo_size[1],
1079                        p_tx_fifo,
1080                        sizeof(p_tx_fifo));
1081
1082                 num = ARRAY_SIZE(p_tx_fifo);
1083         }
1084
1085         for (i = 0; i < num; i++) {
1086                 if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size))
1087                         break;
1088
1089                 dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n",
1090                         property, i + 1, p->g_tx_fifo_size[i + 1]);
1091         }
1092 }
1093
1094 static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg)
1095 {
1096         struct dwc2_hw_params *hw = &hsotg->hw_params;
1097         struct dwc2_core_params *p = &hsotg->params;
1098         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1099
1100         /* Buffer DMA */
1101         dwc2_set_param_bool(hsotg, &p->g_dma,
1102                             false, "gadget-dma",
1103                             true, false,
1104                             dma_capable);
1105
1106         /* DMA Descriptor */
1107         dwc2_set_param_bool(hsotg, &p->g_dma_desc, false,
1108                             "gadget-dma-desc",
1109                             p->g_dma, false,
1110                             !!hw->dma_desc_enable);
1111 }
1112
1113 /**
1114  * dwc2_set_parameters() - Set all core parameters.
1115  *
1116  * @hsotg: Programming view of the DWC_otg controller
1117  * @params: The parameters to set
1118  */
1119 static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1120                                 const struct dwc2_core_params *params)
1121 {
1122         struct dwc2_hw_params *hw = &hsotg->hw_params;
1123         struct dwc2_core_params *p = &hsotg->params;
1124         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
1125
1126         dwc2_set_param_otg_cap(hsotg, params->otg_cap);
1127         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
1128             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1129                 dev_dbg(hsotg->dev, "Setting HOST parameters\n");
1130
1131                 dwc2_set_param_bool(hsotg, &p->host_dma,
1132                                     false, "host-dma",
1133                                     true, false,
1134                                     dma_capable);
1135         }
1136         dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1137         dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
1138
1139         dwc2_set_param_host_support_fs_ls_low_power(hsotg,
1140                         params->host_support_fs_ls_low_power);
1141         dwc2_set_param_enable_dynamic_fifo(hsotg,
1142                         params->enable_dynamic_fifo);
1143         dwc2_set_param_host_rx_fifo_size(hsotg,
1144                         params->host_rx_fifo_size);
1145         dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
1146                         params->host_nperio_tx_fifo_size);
1147         dwc2_set_param_host_perio_tx_fifo_size(hsotg,
1148                         params->host_perio_tx_fifo_size);
1149         dwc2_set_param_max_transfer_size(hsotg,
1150                         params->max_transfer_size);
1151         dwc2_set_param_max_packet_count(hsotg,
1152                         params->max_packet_count);
1153         dwc2_set_param_host_channels(hsotg, params->host_channels);
1154         dwc2_set_param_phy_type(hsotg, params->phy_type);
1155         dwc2_set_param_speed(hsotg, params->speed);
1156         dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
1157                         params->host_ls_low_power_phy_clk);
1158         dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
1159         dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
1160                         params->phy_ulpi_ext_vbus);
1161         dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
1162         dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
1163         dwc2_set_param_ts_dline(hsotg, params->ts_dline);
1164         dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
1165         dwc2_set_param_en_multiple_tx_fifo(hsotg,
1166                         params->en_multiple_tx_fifo);
1167         dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
1168         dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
1169         dwc2_set_param_otg_ver(hsotg, params->otg_ver);
1170         dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
1171         dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
1172         dwc2_set_param_hibernation(hsotg, params->hibernation);
1173
1174         /*
1175          * Set devicetree-only parameters. These parameters do not
1176          * take any values from @params.
1177          */
1178         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
1179             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
1180                 dev_dbg(hsotg->dev, "Setting peripheral device properties\n");
1181
1182                 dwc2_set_gadget_dma(hsotg);
1183
1184                 /*
1185                  * The values for g_rx_fifo_size (2048) and
1186                  * g_np_tx_fifo_size (1024) come from the legacy s3c
1187                  * gadget driver. These defaults have been hard-coded
1188                  * for some time so many platforms depend on these
1189                  * values. Leave them as defaults for now and only
1190                  * auto-detect if the hardware does not support the
1191                  * default.
1192                  */
1193                 dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size,
1194                                    true, "g-rx-fifo-size", 2048,
1195                                    hw->rx_fifo_size,
1196                                    16, hw->rx_fifo_size);
1197
1198                 dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size,
1199                                    true, "g-np-tx-fifo-size", 1024,
1200                                    hw->dev_nperio_tx_fifo_size,
1201                                    16, hw->dev_nperio_tx_fifo_size);
1202
1203                 dwc2_set_param_tx_fifo_sizes(hsotg);
1204         }
1205 }
1206
1207 /*
1208  * Gets host hardware parameters. Forces host mode if not currently in
1209  * host mode. Should be called immediately after a core soft reset in
1210  * order to get the reset values.
1211  */
1212 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1213 {
1214         struct dwc2_hw_params *hw = &hsotg->hw_params;
1215         u32 gnptxfsiz;
1216         u32 hptxfsiz;
1217         bool forced;
1218
1219         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1220                 return;
1221
1222         forced = dwc2_force_mode_if_needed(hsotg, true);
1223
1224         gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1225         hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1226         dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1227         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1228
1229         if (forced)
1230                 dwc2_clear_force_mode(hsotg);
1231
1232         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1233                                        FIFOSIZE_DEPTH_SHIFT;
1234         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1235                                       FIFOSIZE_DEPTH_SHIFT;
1236 }
1237
1238 /*
1239  * Gets device hardware parameters. Forces device mode if not
1240  * currently in device mode. Should be called immediately after a core
1241  * soft reset in order to get the reset values.
1242  */
1243 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1244 {
1245         struct dwc2_hw_params *hw = &hsotg->hw_params;
1246         bool forced;
1247         u32 gnptxfsiz;
1248
1249         if (hsotg->dr_mode == USB_DR_MODE_HOST)
1250                 return;
1251
1252         forced = dwc2_force_mode_if_needed(hsotg, false);
1253
1254         gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1255         dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1256
1257         if (forced)
1258                 dwc2_clear_force_mode(hsotg);
1259
1260         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1261                                        FIFOSIZE_DEPTH_SHIFT;
1262 }
1263
1264 /**
1265  * During device initialization, read various hardware configuration
1266  * registers and interpret the contents.
1267  */
1268 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
1269 {
1270         struct dwc2_hw_params *hw = &hsotg->hw_params;
1271         unsigned int width;
1272         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
1273         u32 grxfsiz;
1274
1275         /*
1276          * Attempt to ensure this device is really a DWC_otg Controller.
1277          * Read and verify the GSNPSID register contents. The value should be
1278          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
1279          * as in "OTG version 2.xx" or "OTG version 3.xx".
1280          */
1281         hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
1282         if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
1283             (hw->snpsid & 0xfffff000) != 0x4f543000 &&
1284             (hw->snpsid & 0xffff0000) != 0x55310000 &&
1285             (hw->snpsid & 0xffff0000) != 0x55320000) {
1286                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
1287                         hw->snpsid);
1288                 return -ENODEV;
1289         }
1290
1291         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
1292                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
1293                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
1294
1295         hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
1296         hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
1297         hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
1298         hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
1299         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
1300
1301         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
1302         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
1303         dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1304         dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1305         dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1306
1307         /*
1308          * Host specific hardware parameters. Reading these parameters
1309          * requires the controller to be in host mode. The mode will
1310          * be forced, if necessary, to read these values.
1311          */
1312         dwc2_get_host_hwparams(hsotg);
1313         dwc2_get_dev_hwparams(hsotg);
1314
1315         /* hwcfg1 */
1316         hw->dev_ep_dirs = hwcfg1;
1317
1318         /* hwcfg2 */
1319         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1320                       GHWCFG2_OP_MODE_SHIFT;
1321         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1322                    GHWCFG2_ARCHITECTURE_SHIFT;
1323         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1324         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1325                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1326         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1327                           GHWCFG2_HS_PHY_TYPE_SHIFT;
1328         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1329                           GHWCFG2_FS_PHY_TYPE_SHIFT;
1330         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1331                          GHWCFG2_NUM_DEV_EP_SHIFT;
1332         hw->nperio_tx_q_depth =
1333                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1334                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1335         hw->host_perio_tx_q_depth =
1336                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1337                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1338         hw->dev_token_q_depth =
1339                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1340                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1341
1342         /* hwcfg3 */
1343         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1344                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1345         hw->max_transfer_size = (1 << (width + 11)) - 1;
1346         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1347                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1348         hw->max_packet_count = (1 << (width + 4)) - 1;
1349         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1350         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1351                               GHWCFG3_DFIFO_DEPTH_SHIFT;
1352
1353         /* hwcfg4 */
1354         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1355         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1356                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1357         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1358         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1359         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1360                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1361
1362         /* fifo sizes */
1363         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1364                                 GRXFSIZ_DEPTH_SHIFT;
1365
1366         dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1367         dev_dbg(hsotg->dev, "  op_mode=%d\n",
1368                 hw->op_mode);
1369         dev_dbg(hsotg->dev, "  arch=%d\n",
1370                 hw->arch);
1371         dev_dbg(hsotg->dev, "  dma_desc_enable=%d\n",
1372                 hw->dma_desc_enable);
1373         dev_dbg(hsotg->dev, "  power_optimized=%d\n",
1374                 hw->power_optimized);
1375         dev_dbg(hsotg->dev, "  i2c_enable=%d\n",
1376                 hw->i2c_enable);
1377         dev_dbg(hsotg->dev, "  hs_phy_type=%d\n",
1378                 hw->hs_phy_type);
1379         dev_dbg(hsotg->dev, "  fs_phy_type=%d\n",
1380                 hw->fs_phy_type);
1381         dev_dbg(hsotg->dev, "  utmi_phy_data_width=%d\n",
1382                 hw->utmi_phy_data_width);
1383         dev_dbg(hsotg->dev, "  num_dev_ep=%d\n",
1384                 hw->num_dev_ep);
1385         dev_dbg(hsotg->dev, "  num_dev_perio_in_ep=%d\n",
1386                 hw->num_dev_perio_in_ep);
1387         dev_dbg(hsotg->dev, "  host_channels=%d\n",
1388                 hw->host_channels);
1389         dev_dbg(hsotg->dev, "  max_transfer_size=%d\n",
1390                 hw->max_transfer_size);
1391         dev_dbg(hsotg->dev, "  max_packet_count=%d\n",
1392                 hw->max_packet_count);
1393         dev_dbg(hsotg->dev, "  nperio_tx_q_depth=0x%0x\n",
1394                 hw->nperio_tx_q_depth);
1395         dev_dbg(hsotg->dev, "  host_perio_tx_q_depth=0x%0x\n",
1396                 hw->host_perio_tx_q_depth);
1397         dev_dbg(hsotg->dev, "  dev_token_q_depth=0x%0x\n",
1398                 hw->dev_token_q_depth);
1399         dev_dbg(hsotg->dev, "  enable_dynamic_fifo=%d\n",
1400                 hw->enable_dynamic_fifo);
1401         dev_dbg(hsotg->dev, "  en_multiple_tx_fifo=%d\n",
1402                 hw->en_multiple_tx_fifo);
1403         dev_dbg(hsotg->dev, "  total_fifo_size=%d\n",
1404                 hw->total_fifo_size);
1405         dev_dbg(hsotg->dev, "  rx_fifo_size=%d\n",
1406                 hw->rx_fifo_size);
1407         dev_dbg(hsotg->dev, "  host_nperio_tx_fifo_size=%d\n",
1408                 hw->host_nperio_tx_fifo_size);
1409         dev_dbg(hsotg->dev, "  host_perio_tx_fifo_size=%d\n",
1410                 hw->host_perio_tx_fifo_size);
1411         dev_dbg(hsotg->dev, "\n");
1412
1413         return 0;
1414 }
1415
1416 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1417 {
1418         const struct of_device_id *match;
1419         struct dwc2_core_params params;
1420
1421         match = of_match_device(dwc2_of_match_table, hsotg->dev);
1422         if (match && match->data)
1423                 params = *((struct dwc2_core_params *)match->data);
1424         else
1425                 params = params_default;
1426
1427         if (dwc2_is_fs_iot(hsotg)) {
1428                 params.speed = DWC2_SPEED_PARAM_FULL;
1429                 params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
1430         }
1431
1432         dwc2_set_parameters(hsotg, &params);
1433
1434         return 0;
1435 }