drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = false;
  72 }
  73
  74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->power_down = 0;
  79 }
  80
  81 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  82 {
  83         struct dwc2_core_params *p = &hsotg->params;
  84
  85         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  86         p->host_rx_fifo_size = 525;
  87         p->host_nperio_tx_fifo_size = 128;
  88         p->host_perio_tx_fifo_size = 256;
  89         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  90                 GAHBCFG_HBSTLEN_SHIFT;
  91         p->power_down = 0;
  92 }
  93
  94 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  95 {
  96         struct dwc2_core_params *p = &hsotg->params;
  97
  98         p->otg_cap = 2;
  99         p->host_rx_fifo_size = 288;
 100         p->host_nperio_tx_fifo_size = 128;
 101         p->host_perio_tx_fifo_size = 96;
 102         p->max_transfer_size = 65535;
 103         p->max_packet_count = 511;
 104         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 105                 GAHBCFG_HBSTLEN_SHIFT;
 106 }
 107
 108 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 109 {
 110         struct dwc2_core_params *p = &hsotg->params;
 111
 112         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 113         p->speed = DWC2_SPEED_PARAM_HIGH;
 114         p->host_rx_fifo_size = 512;
 115         p->host_nperio_tx_fifo_size = 500;
 116         p->host_perio_tx_fifo_size = 500;
 117         p->host_channels = 16;
 118         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 119         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 120                 GAHBCFG_HBSTLEN_SHIFT;
 121         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 122 }
 123
 124 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 125 {
 126         struct dwc2_core_params *p = &hsotg->params;
 127
 128         p->lpm = false;
 129         p->lpm_clock_gating = false;
 130         p->besl = false;
 131         p->hird_threshold_en = false;
 132 }
 133
 134 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 135 {
 136         struct dwc2_core_params *p = &hsotg->params;
 137
 138         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 139 }
 140
 141 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 142 {
 143         struct dwc2_core_params *p = &hsotg->params;
 144
 145         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 146         p->speed = DWC2_SPEED_PARAM_FULL;
 147         p->host_rx_fifo_size = 128;
 148         p->host_nperio_tx_fifo_size = 96;
 149         p->host_perio_tx_fifo_size = 96;
 150         p->max_packet_count = 256;
 151         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 152         p->i2c_enable = false;
 153         p->activate_stm_fs_transceiver = true;
 154 }
 155
 156 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 157 {
 158         struct dwc2_core_params *p = &hsotg->params;
 159
 160         p->host_rx_fifo_size = 622;
 161         p->host_nperio_tx_fifo_size = 128;
 162         p->host_perio_tx_fifo_size = 256;
 163 }
 164
 165 const struct of_device_id dwc2_of_match_table[] = {
 166         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 167         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 168         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 169         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 170         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 171         { .compatible = "snps,dwc2" },
 172         { .compatible = "samsung,s3c6400-hsotg",
 173           .data = dwc2_set_s3c6400_params },
 174         { .compatible = "amlogic,meson8-usb",
 175           .data = dwc2_set_amlogic_params },
 176         { .compatible = "amlogic,meson8b-usb",
 177           .data = dwc2_set_amlogic_params },
 178         { .compatible = "amlogic,meson-gxbb-usb",
 179           .data = dwc2_set_amlogic_params },
 180         { .compatible = "amlogic,meson-g12a-usb",
 181           .data = dwc2_set_amlogic_g12a_params },
 182         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 183         { .compatible = "st,stm32f4x9-fsotg",
 184           .data = dwc2_set_stm32f4x9_fsotg_params },
 185         { .compatible = "st,stm32f4x9-hsotg" },
 186         { .compatible = "st,stm32f7-hsotg",
 187           .data = dwc2_set_stm32f7_hsotg_params },
 188         {},
 189 };
 190 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 191
 192 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 193 {
 194         u8 val;
 195
 196         switch (hsotg->hw_params.op_mode) {
 197         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 198                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 199                 break;
 200         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 201         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 202         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 203                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 204                 break;
 205         default:
 206                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 207                 break;
 208         }
 209
 210         hsotg->params.otg_cap = val;
 211 }
 212
 213 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 214 {
 215         int val;
 216         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 217
 218         val = DWC2_PHY_TYPE_PARAM_FS;
 219         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 220                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 221                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 222                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 223                 else
 224                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 225         }
 226
 227         if (dwc2_is_fs_iot(hsotg))
 228                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 229
 230         hsotg->params.phy_type = val;
 231 }
 232
 233 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 234 {
 235         int val;
 236
 237         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 238                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 239
 240         if (dwc2_is_fs_iot(hsotg))
 241                 val = DWC2_SPEED_PARAM_FULL;
 242
 243         if (dwc2_is_hs_iot(hsotg))
 244                 val = DWC2_SPEED_PARAM_HIGH;
 245
 246         hsotg->params.speed = val;
 247 }
 248
 249 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 250 {
 251         int val;
 252
 253         val = (hsotg->hw_params.utmi_phy_data_width ==
 254                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 255
 256         hsotg->params.phy_utmi_width = val;
 257 }
 258
 259 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 260 {
 261         struct dwc2_core_params *p = &hsotg->params;
 262         int depth_average;
 263         int fifo_count;
 264         int i;
 265
 266         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 267
 268         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 269         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 270         for (i = 1; i <= fifo_count; i++)
 271                 p->g_tx_fifo_size[i] = depth_average;
 272 }
 273
 274 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 275 {
 276         int val;
 277
 278         if (hsotg->hw_params.hibernation)
 279                 val = 2;
 280         else if (hsotg->hw_params.power_optimized)
 281                 val = 1;
 282         else
 283                 val = 0;
 284
 285         hsotg->params.power_down = val;
 286 }
 287
 288 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 289 {
 290         struct dwc2_core_params *p = &hsotg->params;
 291
 292         p->lpm = hsotg->hw_params.lpm_mode;
 293         if (p->lpm) {
 294                 p->lpm_clock_gating = true;
 295                 p->besl = true;
 296                 p->hird_threshold_en = true;
 297                 p->hird_threshold = 4;
 298         } else {
 299                 p->lpm_clock_gating = false;
 300                 p->besl = false;
 301                 p->hird_threshold_en = false;
 302         }
 303 }
 304
 305 /**
 306  * dwc2_set_default_params() - Set all core parameters to their
 307  * auto-detected default values.
 308  *
 309  * @hsotg: Programming view of the DWC_otg controller
 310  *
 311  */
 312 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 313 {
 314         struct dwc2_hw_params *hw = &hsotg->hw_params;
 315         struct dwc2_core_params *p = &hsotg->params;
 316         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 317
 318         dwc2_set_param_otg_cap(hsotg);
 319         dwc2_set_param_phy_type(hsotg);
 320         dwc2_set_param_speed(hsotg);
 321         dwc2_set_param_phy_utmi_width(hsotg);
 322         dwc2_set_param_power_down(hsotg);
 323         dwc2_set_param_lpm(hsotg);
 324         p->phy_ulpi_ddr = false;
 325         p->phy_ulpi_ext_vbus = false;
 326
 327         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 328         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 329         p->i2c_enable = hw->i2c_enable;
 330         p->acg_enable = hw->acg_enable;
 331         p->ulpi_fs_ls = false;
 332         p->ts_dline = false;
 333         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 334         p->uframe_sched = true;
 335         p->external_id_pin_ctl = false;
 336         p->ipg_isoc_en = false;
 337         p->service_interval = false;
 338         p->max_packet_count = hw->max_packet_count;
 339         p->max_transfer_size = hw->max_transfer_size;
 340         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 341         p->ref_clk_per = 33333;
 342         p->sof_cnt_wkup_alert = 100;
 343
 344         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 345             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 346                 p->host_dma = dma_capable;
 347                 p->dma_desc_enable = false;
 348                 p->dma_desc_fs_enable = false;
 349                 p->host_support_fs_ls_low_power = false;
 350                 p->host_ls_low_power_phy_clk = false;
 351                 p->host_channels = hw->host_channels;
 352                 p->host_rx_fifo_size = hw->rx_fifo_size;
 353                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 354                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 355         }
 356
 357         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 358             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 359                 p->g_dma = dma_capable;
 360                 p->g_dma_desc = hw->dma_desc_enable;
 361
 362                 /*
 363                  * The values for g_rx_fifo_size (2048) and
 364                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 365                  * gadget driver. These defaults have been hard-coded
 366                  * for some time so many platforms depend on these
 367                  * values. Leave them as defaults for now and only
 368                  * auto-detect if the hardware does not support the
 369                  * default.
 370                  */
 371                 p->g_rx_fifo_size = 2048;
 372                 p->g_np_tx_fifo_size = 1024;
 373                 dwc2_set_param_tx_fifo_sizes(hsotg);
 374         }
 375 }
 376
 377 /**
 378  * dwc2_get_device_properties() - Read in device properties.
 379  *
 380  * @hsotg: Programming view of the DWC_otg controller
 381  *
 382  * Read in the device properties and adjust core parameters if needed.
 383  */
 384 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 385 {
 386         struct dwc2_core_params *p = &hsotg->params;
 387         int num;
 388
 389         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 390             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 391                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 392                                          &p->g_rx_fifo_size);
 393
 394                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 395                                          &p->g_np_tx_fifo_size);
 396
 397                 num = device_property_read_u32_array(hsotg->dev,
 398                                                      "g-tx-fifo-size",
 399                                                      NULL, 0);
 400
 401                 if (num > 0) {
 402                         num = min(num, 15);
 403                         memset(p->g_tx_fifo_size, 0,
 404                                sizeof(p->g_tx_fifo_size));
 405                         device_property_read_u32_array(hsotg->dev,
 406                                                        "g-tx-fifo-size",
 407                                                        &p->g_tx_fifo_size[1],
 408                                                        num);
 409                 }
 410         }
 411
 412         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 413                 p->oc_disable = true;
 414 }
 415
 416 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 417 {
 418         int valid = 1;
 419
 420         switch (hsotg->params.otg_cap) {
 421         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 422                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 423                         valid = 0;
 424                 break;
 425         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 426                 switch (hsotg->hw_params.op_mode) {
 427                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 428                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 429                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 430                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 431                         break;
 432                 default:
 433                         valid = 0;
 434                         break;
 435                 }
 436                 break;
 437         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 438                 /* always valid */
 439                 break;
 440         default:
 441                 valid = 0;
 442                 break;
 443         }
 444
 445         if (!valid)
 446                 dwc2_set_param_otg_cap(hsotg);
 447 }
 448
 449 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 450 {
 451         int valid = 0;
 452         u32 hs_phy_type;
 453         u32 fs_phy_type;
 454
 455         hs_phy_type = hsotg->hw_params.hs_phy_type;
 456         fs_phy_type = hsotg->hw_params.fs_phy_type;
 457
 458         switch (hsotg->params.phy_type) {
 459         case DWC2_PHY_TYPE_PARAM_FS:
 460                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 461                         valid = 1;
 462                 break;
 463         case DWC2_PHY_TYPE_PARAM_UTMI:
 464                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 465                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 466                         valid = 1;
 467                 break;
 468         case DWC2_PHY_TYPE_PARAM_ULPI:
 469                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 470                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 471                         valid = 1;
 472                 break;
 473         default:
 474                 break;
 475         }
 476
 477         if (!valid)
 478                 dwc2_set_param_phy_type(hsotg);
 479 }
 480
 481 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 482 {
 483         int valid = 1;
 484         int phy_type = hsotg->params.phy_type;
 485         int speed = hsotg->params.speed;
 486
 487         switch (speed) {
 488         case DWC2_SPEED_PARAM_HIGH:
 489                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 490                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 491                         valid = 0;
 492                 break;
 493         case DWC2_SPEED_PARAM_FULL:
 494         case DWC2_SPEED_PARAM_LOW:
 495                 break;
 496         default:
 497                 valid = 0;
 498                 break;
 499         }
 500
 501         if (!valid)
 502                 dwc2_set_param_speed(hsotg);
 503 }
 504
 505 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 506 {
 507         int valid = 0;
 508         int param = hsotg->params.phy_utmi_width;
 509         int width = hsotg->hw_params.utmi_phy_data_width;
 510
 511         switch (width) {
 512         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 513                 valid = (param == 8);
 514                 break;
 515         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 516                 valid = (param == 16);
 517                 break;
 518         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 519                 valid = (param == 8 || param == 16);
 520                 break;
 521         }
 522
 523         if (!valid)
 524                 dwc2_set_param_phy_utmi_width(hsotg);
 525 }
 526
 527 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 528 {
 529         int param = hsotg->params.power_down;
 530
 531         switch (param) {
 532         case DWC2_POWER_DOWN_PARAM_NONE:
 533                 break;
 534         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 535                 if (hsotg->hw_params.power_optimized)
 536                         break;
 537                 dev_dbg(hsotg->dev,
 538                         "Partial power down isn't supported by HW\n");
 539                 param = DWC2_POWER_DOWN_PARAM_NONE;
 540                 break;
 541         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 542                 if (hsotg->hw_params.hibernation)
 543                         break;
 544                 dev_dbg(hsotg->dev,
 545                         "Hibernation isn't supported by HW\n");
 546                 param = DWC2_POWER_DOWN_PARAM_NONE;
 547                 break;
 548         default:
 549                 dev_err(hsotg->dev,
 550                         "%s: Invalid parameter power_down=%d\n",
 551                         __func__, param);
 552                 param = DWC2_POWER_DOWN_PARAM_NONE;
 553                 break;
 554         }
 555
 556         hsotg->params.power_down = param;
 557 }
 558
 559 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 560 {
 561         int fifo_count;
 562         int fifo;
 563         int min;
 564         u32 total = 0;
 565         u32 dptxfszn;
 566
 567         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 568         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 569
 570         for (fifo = 1; fifo <= fifo_count; fifo++)
 571                 total += hsotg->params.g_tx_fifo_size[fifo];
 572
 573         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 574                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 575                          __func__);
 576                 dwc2_set_param_tx_fifo_sizes(hsotg);
 577         }
 578
 579         for (fifo = 1; fifo <= fifo_count; fifo++) {
 580                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 581
 582                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 583                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 584                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 585                                  __func__, fifo,
 586                                  hsotg->params.g_tx_fifo_size[fifo]);
 587                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 588                 }
 589         }
 590 }
 591
 592 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 593                 if ((int)(hsotg->params._param) < (_min) ||             \
 594                     (hsotg->params._param) > (_max)) {                  \
 595                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 596                                  __func__, #_param, hsotg->params._param); \
 597                         hsotg->params._param = (_def);                  \
 598                 }                                                       \
 599         } while (0)
 600
 601 #define CHECK_BOOL(_param, _check) do {                                 \
 602                 if (hsotg->params._param && !(_check)) {                \
 603                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 604                                  __func__, #_param, hsotg->params._param); \
 605                         hsotg->params._param = false;                   \
 606                 }                                                       \
 607         } while (0)
 608
 609 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 610 {
 611         struct dwc2_hw_params *hw = &hsotg->hw_params;
 612         struct dwc2_core_params *p = &hsotg->params;
 613         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 614
 615         dwc2_check_param_otg_cap(hsotg);
 616         dwc2_check_param_phy_type(hsotg);
 617         dwc2_check_param_speed(hsotg);
 618         dwc2_check_param_phy_utmi_width(hsotg);
 619         dwc2_check_param_power_down(hsotg);
 620         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 621         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 622         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 623         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 624         CHECK_BOOL(acg_enable, hw->acg_enable);
 625         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 626         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 627         CHECK_BOOL(lpm, hw->lpm_mode);
 628         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 629         CHECK_BOOL(besl, hsotg->params.lpm);
 630         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 631         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 632         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 633         CHECK_BOOL(service_interval, hw->service_interval_mode);
 634         CHECK_RANGE(max_packet_count,
 635                     15, hw->max_packet_count,
 636                     hw->max_packet_count);
 637         CHECK_RANGE(max_transfer_size,
 638                     2047, hw->max_transfer_size,
 639                     hw->max_transfer_size);
 640
 641         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 642             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 643                 CHECK_BOOL(host_dma, dma_capable);
 644                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 645                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 646                 CHECK_BOOL(host_ls_low_power_phy_clk,
 647                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 648                 CHECK_RANGE(host_channels,
 649                             1, hw->host_channels,
 650                             hw->host_channels);
 651                 CHECK_RANGE(host_rx_fifo_size,
 652                             16, hw->rx_fifo_size,
 653                             hw->rx_fifo_size);
 654                 CHECK_RANGE(host_nperio_tx_fifo_size,
 655                             16, hw->host_nperio_tx_fifo_size,
 656                             hw->host_nperio_tx_fifo_size);
 657                 CHECK_RANGE(host_perio_tx_fifo_size,
 658                             16, hw->host_perio_tx_fifo_size,
 659                             hw->host_perio_tx_fifo_size);
 660         }
 661
 662         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 663             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 664                 CHECK_BOOL(g_dma, dma_capable);
 665                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 666                 CHECK_RANGE(g_rx_fifo_size,
 667                             16, hw->rx_fifo_size,
 668                             hw->rx_fifo_size);
 669                 CHECK_RANGE(g_np_tx_fifo_size,
 670                             16, hw->dev_nperio_tx_fifo_size,
 671                             hw->dev_nperio_tx_fifo_size);
 672                 dwc2_check_param_tx_fifo_sizes(hsotg);
 673         }
 674 }
 675
 676 /*
 677  * Gets host hardware parameters. Forces host mode if not currently in
 678  * host mode. Should be called immediately after a core soft reset in
 679  * order to get the reset values.
 680  */
 681 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 682 {
 683         struct dwc2_hw_params *hw = &hsotg->hw_params;
 684         u32 gnptxfsiz;
 685         u32 hptxfsiz;
 686
 687         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 688                 return;
 689
 690         dwc2_force_mode(hsotg, true);
 691
 692         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 693         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 694
 695         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 696                                        FIFOSIZE_DEPTH_SHIFT;
 697         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 698                                       FIFOSIZE_DEPTH_SHIFT;
 699 }
 700
 701 /*
 702  * Gets device hardware parameters. Forces device mode if not
 703  * currently in device mode. Should be called immediately after a core
 704  * soft reset in order to get the reset values.
 705  */
 706 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 707 {
 708         struct dwc2_hw_params *hw = &hsotg->hw_params;
 709         u32 gnptxfsiz;
 710         int fifo, fifo_count;
 711
 712         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 713                 return;
 714
 715         dwc2_force_mode(hsotg, false);
 716
 717         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 718
 719         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 720
 721         for (fifo = 1; fifo <= fifo_count; fifo++) {
 722                 hw->g_tx_fifo_size[fifo] =
 723                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 724                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 725         }
 726
 727         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 728                                        FIFOSIZE_DEPTH_SHIFT;
 729 }
 730
 731 /**
 732  * During device initialization, read various hardware configuration
 733  * registers and interpret the contents.
 734  *
 735  * @hsotg: Programming view of the DWC_otg controller
 736  *
 737  */
 738 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 739 {
 740         struct dwc2_hw_params *hw = &hsotg->hw_params;
 741         unsigned int width;
 742         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 743         u32 grxfsiz;
 744
 745         /*
 746          * Attempt to ensure this device is really a DWC_otg Controller.
 747          * Read and verify the GSNPSID register contents. The value should be
 748          * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
 749          */
 750
 751         hw->snpsid = dwc2_readl(hsotg, GSNPSID);
 752         if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
 753             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
 754             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
 755                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
 756                         hw->snpsid);
 757                 return -ENODEV;
 758         }
 759
 760         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
 761                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
 762                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
 763
 764         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 765         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 766         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 767         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 768         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 769
 770         /* hwcfg1 */
 771         hw->dev_ep_dirs = hwcfg1;
 772
 773         /* hwcfg2 */
 774         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 775                       GHWCFG2_OP_MODE_SHIFT;
 776         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 777                    GHWCFG2_ARCHITECTURE_SHIFT;
 778         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 779         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 780                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 781         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 782                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 783         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 784                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 785         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 786                          GHWCFG2_NUM_DEV_EP_SHIFT;
 787         hw->nperio_tx_q_depth =
 788                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 789                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 790         hw->host_perio_tx_q_depth =
 791                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 792                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 793         hw->dev_token_q_depth =
 794                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 795                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 796
 797         /* hwcfg3 */
 798         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 799                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 800         hw->max_transfer_size = (1 << (width + 11)) - 1;
 801         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 802                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 803         hw->max_packet_count = (1 << (width + 4)) - 1;
 804         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 805         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 806                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 807         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 808
 809         /* hwcfg4 */
 810         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 811         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 812                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 813         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 814                              GHWCFG4_NUM_IN_EPS_SHIFT;
 815         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 816         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 817         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 818         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 819                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 820         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 821         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 822         hw->service_interval_mode = !!(hwcfg4 &
 823                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 824
 825         /* fifo sizes */
 826         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 827                                 GRXFSIZ_DEPTH_SHIFT;
 828         /*
 829          * Host specific hardware parameters. Reading these parameters
 830          * requires the controller to be in host mode. The mode will
 831          * be forced, if necessary, to read these values.
 832          */
 833         dwc2_get_host_hwparams(hsotg);
 834         dwc2_get_dev_hwparams(hsotg);
 835
 836         return 0;
 837 }
 838
 839 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 840 {
 841         const struct of_device_id *match;
 842         void (*set_params)(void *data);
 843
 844         dwc2_set_default_params(hsotg);
 845         dwc2_get_device_properties(hsotg);
 846
 847         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 848         if (match && match->data) {
 849                 set_params = match->data;
 850                 set_params(hsotg);
 851         }
 852
 853         dwc2_check_params(hsotg);
 854
 855         return 0;
 856 }