1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
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18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation; either version 2 of the License, or (at your option) any
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33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/of_device.h>
42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
44 struct dwc2_core_params *p = &hsotg->params;
46 p->host_rx_fifo_size = 774;
47 p->max_transfer_size = 65535;
48 p->max_packet_count = 511;
52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
54 struct dwc2_core_params *p = &hsotg->params;
56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
57 p->speed = DWC2_SPEED_PARAM_HIGH;
58 p->host_rx_fifo_size = 512;
59 p->host_nperio_tx_fifo_size = 512;
60 p->host_perio_tx_fifo_size = 512;
61 p->max_transfer_size = 65535;
62 p->max_packet_count = 511;
63 p->host_channels = 16;
64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
65 p->phy_utmi_width = 8;
66 p->i2c_enable = false;
67 p->reload_ctl = false;
68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
69 GAHBCFG_HBSTLEN_SHIFT;
70 p->change_speed_quirk = true;
71 p->power_down = false;
74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
76 struct dwc2_core_params *p = &hsotg->params;
81 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
83 struct dwc2_core_params *p = &hsotg->params;
85 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
86 p->host_rx_fifo_size = 525;
87 p->host_nperio_tx_fifo_size = 128;
88 p->host_perio_tx_fifo_size = 256;
89 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
90 GAHBCFG_HBSTLEN_SHIFT;
94 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
96 struct dwc2_core_params *p = &hsotg->params;
99 p->host_rx_fifo_size = 288;
100 p->host_nperio_tx_fifo_size = 128;
101 p->host_perio_tx_fifo_size = 96;
102 p->max_transfer_size = 65535;
103 p->max_packet_count = 511;
104 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
105 GAHBCFG_HBSTLEN_SHIFT;
108 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
110 struct dwc2_core_params *p = &hsotg->params;
112 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
113 p->speed = DWC2_SPEED_PARAM_HIGH;
114 p->host_rx_fifo_size = 512;
115 p->host_nperio_tx_fifo_size = 500;
116 p->host_perio_tx_fifo_size = 500;
117 p->host_channels = 16;
118 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
119 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
120 GAHBCFG_HBSTLEN_SHIFT;
121 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
124 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
126 struct dwc2_core_params *p = &hsotg->params;
129 p->lpm_clock_gating = false;
131 p->hird_threshold_en = false;
134 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
136 struct dwc2_core_params *p = &hsotg->params;
138 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
141 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
143 struct dwc2_core_params *p = &hsotg->params;
145 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
146 p->speed = DWC2_SPEED_PARAM_FULL;
147 p->host_rx_fifo_size = 128;
148 p->host_nperio_tx_fifo_size = 96;
149 p->host_perio_tx_fifo_size = 96;
150 p->max_packet_count = 256;
151 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
152 p->i2c_enable = false;
153 p->activate_stm_fs_transceiver = true;
156 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
158 struct dwc2_core_params *p = &hsotg->params;
160 p->host_rx_fifo_size = 622;
161 p->host_nperio_tx_fifo_size = 128;
162 p->host_perio_tx_fifo_size = 256;
165 const struct of_device_id dwc2_of_match_table[] = {
166 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
167 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
168 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
169 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
170 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
171 { .compatible = "snps,dwc2" },
172 { .compatible = "samsung,s3c6400-hsotg",
173 .data = dwc2_set_s3c6400_params },
174 { .compatible = "amlogic,meson8-usb",
175 .data = dwc2_set_amlogic_params },
176 { .compatible = "amlogic,meson8b-usb",
177 .data = dwc2_set_amlogic_params },
178 { .compatible = "amlogic,meson-gxbb-usb",
179 .data = dwc2_set_amlogic_params },
180 { .compatible = "amlogic,meson-g12a-usb",
181 .data = dwc2_set_amlogic_g12a_params },
182 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
183 { .compatible = "st,stm32f4x9-fsotg",
184 .data = dwc2_set_stm32f4x9_fsotg_params },
185 { .compatible = "st,stm32f4x9-hsotg" },
186 { .compatible = "st,stm32f7-hsotg",
187 .data = dwc2_set_stm32f7_hsotg_params },
190 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
192 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
196 switch (hsotg->hw_params.op_mode) {
197 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
198 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
200 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
201 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
202 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
203 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
206 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
210 hsotg->params.otg_cap = val;
213 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
216 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
218 val = DWC2_PHY_TYPE_PARAM_FS;
219 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
220 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
221 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
222 val = DWC2_PHY_TYPE_PARAM_UTMI;
224 val = DWC2_PHY_TYPE_PARAM_ULPI;
227 if (dwc2_is_fs_iot(hsotg))
228 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
230 hsotg->params.phy_type = val;
233 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
237 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
238 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
240 if (dwc2_is_fs_iot(hsotg))
241 val = DWC2_SPEED_PARAM_FULL;
243 if (dwc2_is_hs_iot(hsotg))
244 val = DWC2_SPEED_PARAM_HIGH;
246 hsotg->params.speed = val;
249 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
253 val = (hsotg->hw_params.utmi_phy_data_width ==
254 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
256 hsotg->params.phy_utmi_width = val;
259 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
261 struct dwc2_core_params *p = &hsotg->params;
266 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
268 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
269 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
270 for (i = 1; i <= fifo_count; i++)
271 p->g_tx_fifo_size[i] = depth_average;
274 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
278 if (hsotg->hw_params.hibernation)
280 else if (hsotg->hw_params.power_optimized)
285 hsotg->params.power_down = val;
289 * dwc2_set_default_params() - Set all core parameters to their
290 * auto-detected default values.
292 * @hsotg: Programming view of the DWC_otg controller
295 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
297 struct dwc2_hw_params *hw = &hsotg->hw_params;
298 struct dwc2_core_params *p = &hsotg->params;
299 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
301 dwc2_set_param_otg_cap(hsotg);
302 dwc2_set_param_phy_type(hsotg);
303 dwc2_set_param_speed(hsotg);
304 dwc2_set_param_phy_utmi_width(hsotg);
305 dwc2_set_param_power_down(hsotg);
306 p->phy_ulpi_ddr = false;
307 p->phy_ulpi_ext_vbus = false;
309 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
310 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
311 p->i2c_enable = hw->i2c_enable;
312 p->acg_enable = hw->acg_enable;
313 p->ulpi_fs_ls = false;
315 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
316 p->uframe_sched = true;
317 p->external_id_pin_ctl = false;
319 p->lpm_clock_gating = true;
321 p->hird_threshold_en = true;
322 p->hird_threshold = 4;
323 p->ipg_isoc_en = false;
324 p->service_interval = false;
325 p->max_packet_count = hw->max_packet_count;
326 p->max_transfer_size = hw->max_transfer_size;
327 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
328 p->ref_clk_per = 33333;
329 p->sof_cnt_wkup_alert = 100;
331 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
332 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
333 p->host_dma = dma_capable;
334 p->dma_desc_enable = false;
335 p->dma_desc_fs_enable = false;
336 p->host_support_fs_ls_low_power = false;
337 p->host_ls_low_power_phy_clk = false;
338 p->host_channels = hw->host_channels;
339 p->host_rx_fifo_size = hw->rx_fifo_size;
340 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
341 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
344 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
345 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
346 p->g_dma = dma_capable;
347 p->g_dma_desc = hw->dma_desc_enable;
350 * The values for g_rx_fifo_size (2048) and
351 * g_np_tx_fifo_size (1024) come from the legacy s3c
352 * gadget driver. These defaults have been hard-coded
353 * for some time so many platforms depend on these
354 * values. Leave them as defaults for now and only
355 * auto-detect if the hardware does not support the
358 p->g_rx_fifo_size = 2048;
359 p->g_np_tx_fifo_size = 1024;
360 dwc2_set_param_tx_fifo_sizes(hsotg);
365 * dwc2_get_device_properties() - Read in device properties.
367 * @hsotg: Programming view of the DWC_otg controller
369 * Read in the device properties and adjust core parameters if needed.
371 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
373 struct dwc2_core_params *p = &hsotg->params;
376 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
377 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
378 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
381 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
382 &p->g_np_tx_fifo_size);
384 num = device_property_read_u32_array(hsotg->dev,
390 memset(p->g_tx_fifo_size, 0,
391 sizeof(p->g_tx_fifo_size));
392 device_property_read_u32_array(hsotg->dev,
394 &p->g_tx_fifo_size[1],
399 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
400 p->oc_disable = true;
403 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
407 switch (hsotg->params.otg_cap) {
408 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
409 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
412 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
413 switch (hsotg->hw_params.op_mode) {
414 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
415 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
416 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
417 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
424 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
433 dwc2_set_param_otg_cap(hsotg);
436 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
442 hs_phy_type = hsotg->hw_params.hs_phy_type;
443 fs_phy_type = hsotg->hw_params.fs_phy_type;
445 switch (hsotg->params.phy_type) {
446 case DWC2_PHY_TYPE_PARAM_FS:
447 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
450 case DWC2_PHY_TYPE_PARAM_UTMI:
451 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
452 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
455 case DWC2_PHY_TYPE_PARAM_ULPI:
456 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
457 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
465 dwc2_set_param_phy_type(hsotg);
468 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
471 int phy_type = hsotg->params.phy_type;
472 int speed = hsotg->params.speed;
475 case DWC2_SPEED_PARAM_HIGH:
476 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
477 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
480 case DWC2_SPEED_PARAM_FULL:
481 case DWC2_SPEED_PARAM_LOW:
489 dwc2_set_param_speed(hsotg);
492 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
495 int param = hsotg->params.phy_utmi_width;
496 int width = hsotg->hw_params.utmi_phy_data_width;
499 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
500 valid = (param == 8);
502 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
503 valid = (param == 16);
505 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
506 valid = (param == 8 || param == 16);
511 dwc2_set_param_phy_utmi_width(hsotg);
514 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
516 int param = hsotg->params.power_down;
519 case DWC2_POWER_DOWN_PARAM_NONE:
521 case DWC2_POWER_DOWN_PARAM_PARTIAL:
522 if (hsotg->hw_params.power_optimized)
525 "Partial power down isn't supported by HW\n");
526 param = DWC2_POWER_DOWN_PARAM_NONE;
528 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
529 if (hsotg->hw_params.hibernation)
532 "Hibernation isn't supported by HW\n");
533 param = DWC2_POWER_DOWN_PARAM_NONE;
537 "%s: Invalid parameter power_down=%d\n",
539 param = DWC2_POWER_DOWN_PARAM_NONE;
543 hsotg->params.power_down = param;
546 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
554 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
555 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
557 for (fifo = 1; fifo <= fifo_count; fifo++)
558 total += hsotg->params.g_tx_fifo_size[fifo];
560 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
561 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
563 dwc2_set_param_tx_fifo_sizes(hsotg);
566 for (fifo = 1; fifo <= fifo_count; fifo++) {
567 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
569 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
570 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
571 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
573 hsotg->params.g_tx_fifo_size[fifo]);
574 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
579 #define CHECK_RANGE(_param, _min, _max, _def) do { \
580 if ((int)(hsotg->params._param) < (_min) || \
581 (hsotg->params._param) > (_max)) { \
582 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
583 __func__, #_param, hsotg->params._param); \
584 hsotg->params._param = (_def); \
588 #define CHECK_BOOL(_param, _check) do { \
589 if (hsotg->params._param && !(_check)) { \
590 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
591 __func__, #_param, hsotg->params._param); \
592 hsotg->params._param = false; \
596 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
598 struct dwc2_hw_params *hw = &hsotg->hw_params;
599 struct dwc2_core_params *p = &hsotg->params;
600 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
602 dwc2_check_param_otg_cap(hsotg);
603 dwc2_check_param_phy_type(hsotg);
604 dwc2_check_param_speed(hsotg);
605 dwc2_check_param_phy_utmi_width(hsotg);
606 dwc2_check_param_power_down(hsotg);
607 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
608 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
609 CHECK_BOOL(i2c_enable, hw->i2c_enable);
610 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
611 CHECK_BOOL(acg_enable, hw->acg_enable);
612 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
613 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
614 CHECK_BOOL(lpm, hw->lpm_mode);
615 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
616 CHECK_BOOL(besl, hsotg->params.lpm);
617 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
618 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
619 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
620 CHECK_BOOL(service_interval, hw->service_interval_mode);
621 CHECK_RANGE(max_packet_count,
622 15, hw->max_packet_count,
623 hw->max_packet_count);
624 CHECK_RANGE(max_transfer_size,
625 2047, hw->max_transfer_size,
626 hw->max_transfer_size);
628 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
629 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
630 CHECK_BOOL(host_dma, dma_capable);
631 CHECK_BOOL(dma_desc_enable, p->host_dma);
632 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
633 CHECK_BOOL(host_ls_low_power_phy_clk,
634 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
635 CHECK_RANGE(host_channels,
636 1, hw->host_channels,
638 CHECK_RANGE(host_rx_fifo_size,
639 16, hw->rx_fifo_size,
641 CHECK_RANGE(host_nperio_tx_fifo_size,
642 16, hw->host_nperio_tx_fifo_size,
643 hw->host_nperio_tx_fifo_size);
644 CHECK_RANGE(host_perio_tx_fifo_size,
645 16, hw->host_perio_tx_fifo_size,
646 hw->host_perio_tx_fifo_size);
649 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
650 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
651 CHECK_BOOL(g_dma, dma_capable);
652 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
653 CHECK_RANGE(g_rx_fifo_size,
654 16, hw->rx_fifo_size,
656 CHECK_RANGE(g_np_tx_fifo_size,
657 16, hw->dev_nperio_tx_fifo_size,
658 hw->dev_nperio_tx_fifo_size);
659 dwc2_check_param_tx_fifo_sizes(hsotg);
664 * Gets host hardware parameters. Forces host mode if not currently in
665 * host mode. Should be called immediately after a core soft reset in
666 * order to get the reset values.
668 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
670 struct dwc2_hw_params *hw = &hsotg->hw_params;
674 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
677 dwc2_force_mode(hsotg, true);
679 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
680 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
682 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
683 FIFOSIZE_DEPTH_SHIFT;
684 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
685 FIFOSIZE_DEPTH_SHIFT;
689 * Gets device hardware parameters. Forces device mode if not
690 * currently in device mode. Should be called immediately after a core
691 * soft reset in order to get the reset values.
693 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
695 struct dwc2_hw_params *hw = &hsotg->hw_params;
697 int fifo, fifo_count;
699 if (hsotg->dr_mode == USB_DR_MODE_HOST)
702 dwc2_force_mode(hsotg, false);
704 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
706 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
708 for (fifo = 1; fifo <= fifo_count; fifo++) {
709 hw->g_tx_fifo_size[fifo] =
710 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
711 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
714 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
715 FIFOSIZE_DEPTH_SHIFT;
719 * During device initialization, read various hardware configuration
720 * registers and interpret the contents.
722 * @hsotg: Programming view of the DWC_otg controller
725 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
727 struct dwc2_hw_params *hw = &hsotg->hw_params;
729 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
733 * Attempt to ensure this device is really a DWC_otg Controller.
734 * Read and verify the GSNPSID register contents. The value should be
735 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
738 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
739 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
740 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
741 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
742 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
747 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
748 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
749 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
751 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
752 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
753 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
754 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
755 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
758 hw->dev_ep_dirs = hwcfg1;
761 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
762 GHWCFG2_OP_MODE_SHIFT;
763 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
764 GHWCFG2_ARCHITECTURE_SHIFT;
765 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
766 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
767 GHWCFG2_NUM_HOST_CHAN_SHIFT);
768 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
769 GHWCFG2_HS_PHY_TYPE_SHIFT;
770 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
771 GHWCFG2_FS_PHY_TYPE_SHIFT;
772 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
773 GHWCFG2_NUM_DEV_EP_SHIFT;
774 hw->nperio_tx_q_depth =
775 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
776 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
777 hw->host_perio_tx_q_depth =
778 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
779 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
780 hw->dev_token_q_depth =
781 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
782 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
785 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
786 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
787 hw->max_transfer_size = (1 << (width + 11)) - 1;
788 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
789 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
790 hw->max_packet_count = (1 << (width + 4)) - 1;
791 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
792 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
793 GHWCFG3_DFIFO_DEPTH_SHIFT;
794 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
797 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
798 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
799 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
800 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
801 GHWCFG4_NUM_IN_EPS_SHIFT;
802 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
803 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
804 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
805 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
806 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
807 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
808 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
809 hw->service_interval_mode = !!(hwcfg4 &
810 GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
813 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
816 * Host specific hardware parameters. Reading these parameters
817 * requires the controller to be in host mode. The mode will
818 * be forced, if necessary, to read these values.
820 dwc2_get_host_hwparams(hsotg);
821 dwc2_get_dev_hwparams(hsotg);
826 int dwc2_init_params(struct dwc2_hsotg *hsotg)
828 const struct of_device_id *match;
829 void (*set_params)(void *data);
831 dwc2_set_default_params(hsotg);
832 dwc2_get_device_properties(hsotg);
834 match = of_match_device(dwc2_of_match_table, hsotg->dev);
835 if (match && match->data) {
836 set_params = match->data;
840 dwc2_check_params(hsotg);