drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = false;
  72 }
  73
  74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->power_down = 0;
  79 }
  80
  81 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  82 {
  83         struct dwc2_core_params *p = &hsotg->params;
  84
  85         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  86         p->host_rx_fifo_size = 525;
  87         p->host_nperio_tx_fifo_size = 128;
  88         p->host_perio_tx_fifo_size = 256;
  89         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  90                 GAHBCFG_HBSTLEN_SHIFT;
  91         p->power_down = 0;
  92 }
  93
  94 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  95 {
  96         struct dwc2_core_params *p = &hsotg->params;
  97
  98         p->otg_cap = 2;
  99         p->host_rx_fifo_size = 288;
 100         p->host_nperio_tx_fifo_size = 128;
 101         p->host_perio_tx_fifo_size = 96;
 102         p->max_transfer_size = 65535;
 103         p->max_packet_count = 511;
 104         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 105                 GAHBCFG_HBSTLEN_SHIFT;
 106 }
 107
 108 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 109 {
 110         struct dwc2_core_params *p = &hsotg->params;
 111
 112         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 113         p->speed = DWC2_SPEED_PARAM_HIGH;
 114         p->host_rx_fifo_size = 512;
 115         p->host_nperio_tx_fifo_size = 500;
 116         p->host_perio_tx_fifo_size = 500;
 117         p->host_channels = 16;
 118         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 119         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 120                 GAHBCFG_HBSTLEN_SHIFT;
 121         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 122 }
 123
 124 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 125 {
 126         struct dwc2_core_params *p = &hsotg->params;
 127
 128         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 129 }
 130
 131 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 132 {
 133         struct dwc2_core_params *p = &hsotg->params;
 134
 135         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 136         p->speed = DWC2_SPEED_PARAM_FULL;
 137         p->host_rx_fifo_size = 128;
 138         p->host_nperio_tx_fifo_size = 96;
 139         p->host_perio_tx_fifo_size = 96;
 140         p->max_packet_count = 256;
 141         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 142         p->i2c_enable = false;
 143         p->activate_stm_fs_transceiver = true;
 144 }
 145
 146 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 147 {
 148         struct dwc2_core_params *p = &hsotg->params;
 149
 150         p->host_rx_fifo_size = 622;
 151         p->host_nperio_tx_fifo_size = 128;
 152         p->host_perio_tx_fifo_size = 256;
 153 }
 154
 155 const struct of_device_id dwc2_of_match_table[] = {
 156         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 157         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 158         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 159         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 160         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 161         { .compatible = "snps,dwc2" },
 162         { .compatible = "samsung,s3c6400-hsotg",
 163           .data = dwc2_set_s3c6400_params },
 164         { .compatible = "amlogic,meson8-usb",
 165           .data = dwc2_set_amlogic_params },
 166         { .compatible = "amlogic,meson8b-usb",
 167           .data = dwc2_set_amlogic_params },
 168         { .compatible = "amlogic,meson-gxbb-usb",
 169           .data = dwc2_set_amlogic_params },
 170         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 171         { .compatible = "st,stm32f4x9-fsotg",
 172           .data = dwc2_set_stm32f4x9_fsotg_params },
 173         { .compatible = "st,stm32f4x9-hsotg" },
 174         { .compatible = "st,stm32f7-hsotg",
 175           .data = dwc2_set_stm32f7_hsotg_params },
 176         {},
 177 };
 178 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 179
 180 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 181 {
 182         u8 val;
 183
 184         switch (hsotg->hw_params.op_mode) {
 185         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 186                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 187                 break;
 188         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 189         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 190         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 191                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 192                 break;
 193         default:
 194                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 195                 break;
 196         }
 197
 198         hsotg->params.otg_cap = val;
 199 }
 200
 201 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 202 {
 203         int val;
 204         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 205
 206         val = DWC2_PHY_TYPE_PARAM_FS;
 207         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 208                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 209                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 210                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 211                 else
 212                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 213         }
 214
 215         if (dwc2_is_fs_iot(hsotg))
 216                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 217
 218         hsotg->params.phy_type = val;
 219 }
 220
 221 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 222 {
 223         int val;
 224
 225         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 226                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 227
 228         if (dwc2_is_fs_iot(hsotg))
 229                 val = DWC2_SPEED_PARAM_FULL;
 230
 231         if (dwc2_is_hs_iot(hsotg))
 232                 val = DWC2_SPEED_PARAM_HIGH;
 233
 234         hsotg->params.speed = val;
 235 }
 236
 237 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 238 {
 239         int val;
 240
 241         val = (hsotg->hw_params.utmi_phy_data_width ==
 242                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 243
 244         hsotg->params.phy_utmi_width = val;
 245 }
 246
 247 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 248 {
 249         struct dwc2_core_params *p = &hsotg->params;
 250         int depth_average;
 251         int fifo_count;
 252         int i;
 253
 254         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 255
 256         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 257         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 258         for (i = 1; i <= fifo_count; i++)
 259                 p->g_tx_fifo_size[i] = depth_average;
 260 }
 261
 262 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 263 {
 264         int val;
 265
 266         if (hsotg->hw_params.hibernation)
 267                 val = 2;
 268         else if (hsotg->hw_params.power_optimized)
 269                 val = 1;
 270         else
 271                 val = 0;
 272
 273         hsotg->params.power_down = val;
 274 }
 275
 276 /**
 277  * dwc2_set_default_params() - Set all core parameters to their
 278  * auto-detected default values.
 279  *
 280  * @hsotg: Programming view of the DWC_otg controller
 281  *
 282  */
 283 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 284 {
 285         struct dwc2_hw_params *hw = &hsotg->hw_params;
 286         struct dwc2_core_params *p = &hsotg->params;
 287         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 288
 289         dwc2_set_param_otg_cap(hsotg);
 290         dwc2_set_param_phy_type(hsotg);
 291         dwc2_set_param_speed(hsotg);
 292         dwc2_set_param_phy_utmi_width(hsotg);
 293         dwc2_set_param_power_down(hsotg);
 294         p->phy_ulpi_ddr = false;
 295         p->phy_ulpi_ext_vbus = false;
 296
 297         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 298         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 299         p->i2c_enable = hw->i2c_enable;
 300         p->acg_enable = hw->acg_enable;
 301         p->ulpi_fs_ls = false;
 302         p->ts_dline = false;
 303         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 304         p->uframe_sched = true;
 305         p->external_id_pin_ctl = false;
 306         p->lpm = true;
 307         p->lpm_clock_gating = true;
 308         p->besl = true;
 309         p->hird_threshold_en = true;
 310         p->hird_threshold = 4;
 311         p->ipg_isoc_en = false;
 312         p->service_interval = false;
 313         p->max_packet_count = hw->max_packet_count;
 314         p->max_transfer_size = hw->max_transfer_size;
 315         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 316         p->ref_clk_per = 33333;
 317         p->sof_cnt_wkup_alert = 100;
 318
 319         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 320             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 321                 p->host_dma = dma_capable;
 322                 p->dma_desc_enable = false;
 323                 p->dma_desc_fs_enable = false;
 324                 p->host_support_fs_ls_low_power = false;
 325                 p->host_ls_low_power_phy_clk = false;
 326                 p->host_channels = hw->host_channels;
 327                 p->host_rx_fifo_size = hw->rx_fifo_size;
 328                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 329                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 330         }
 331
 332         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 333             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 334                 p->g_dma = dma_capable;
 335                 p->g_dma_desc = hw->dma_desc_enable;
 336
 337                 /*
 338                  * The values for g_rx_fifo_size (2048) and
 339                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 340                  * gadget driver. These defaults have been hard-coded
 341                  * for some time so many platforms depend on these
 342                  * values. Leave them as defaults for now and only
 343                  * auto-detect if the hardware does not support the
 344                  * default.
 345                  */
 346                 p->g_rx_fifo_size = 2048;
 347                 p->g_np_tx_fifo_size = 1024;
 348                 dwc2_set_param_tx_fifo_sizes(hsotg);
 349         }
 350 }
 351
 352 /**
 353  * dwc2_get_device_properties() - Read in device properties.
 354  *
 355  * @hsotg: Programming view of the DWC_otg controller
 356  *
 357  * Read in the device properties and adjust core parameters if needed.
 358  */
 359 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 360 {
 361         struct dwc2_core_params *p = &hsotg->params;
 362         int num;
 363
 364         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 365             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 366                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 367                                          &p->g_rx_fifo_size);
 368
 369                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 370                                          &p->g_np_tx_fifo_size);
 371
 372                 num = device_property_read_u32_array(hsotg->dev,
 373                                                      "g-tx-fifo-size",
 374                                                      NULL, 0);
 375
 376                 if (num > 0) {
 377                         num = min(num, 15);
 378                         memset(p->g_tx_fifo_size, 0,
 379                                sizeof(p->g_tx_fifo_size));
 380                         device_property_read_u32_array(hsotg->dev,
 381                                                        "g-tx-fifo-size",
 382                                                        &p->g_tx_fifo_size[1],
 383                                                        num);
 384                 }
 385         }
 386
 387         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 388                 p->oc_disable = true;
 389 }
 390
 391 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 392 {
 393         int valid = 1;
 394
 395         switch (hsotg->params.otg_cap) {
 396         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 397                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 398                         valid = 0;
 399                 break;
 400         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 401                 switch (hsotg->hw_params.op_mode) {
 402                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 403                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 404                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 405                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 406                         break;
 407                 default:
 408                         valid = 0;
 409                         break;
 410                 }
 411                 break;
 412         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 413                 /* always valid */
 414                 break;
 415         default:
 416                 valid = 0;
 417                 break;
 418         }
 419
 420         if (!valid)
 421                 dwc2_set_param_otg_cap(hsotg);
 422 }
 423
 424 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 425 {
 426         int valid = 0;
 427         u32 hs_phy_type;
 428         u32 fs_phy_type;
 429
 430         hs_phy_type = hsotg->hw_params.hs_phy_type;
 431         fs_phy_type = hsotg->hw_params.fs_phy_type;
 432
 433         switch (hsotg->params.phy_type) {
 434         case DWC2_PHY_TYPE_PARAM_FS:
 435                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 436                         valid = 1;
 437                 break;
 438         case DWC2_PHY_TYPE_PARAM_UTMI:
 439                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 440                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 441                         valid = 1;
 442                 break;
 443         case DWC2_PHY_TYPE_PARAM_ULPI:
 444                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 445                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 446                         valid = 1;
 447                 break;
 448         default:
 449                 break;
 450         }
 451
 452         if (!valid)
 453                 dwc2_set_param_phy_type(hsotg);
 454 }
 455
 456 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 457 {
 458         int valid = 1;
 459         int phy_type = hsotg->params.phy_type;
 460         int speed = hsotg->params.speed;
 461
 462         switch (speed) {
 463         case DWC2_SPEED_PARAM_HIGH:
 464                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 465                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 466                         valid = 0;
 467                 break;
 468         case DWC2_SPEED_PARAM_FULL:
 469         case DWC2_SPEED_PARAM_LOW:
 470                 break;
 471         default:
 472                 valid = 0;
 473                 break;
 474         }
 475
 476         if (!valid)
 477                 dwc2_set_param_speed(hsotg);
 478 }
 479
 480 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 481 {
 482         int valid = 0;
 483         int param = hsotg->params.phy_utmi_width;
 484         int width = hsotg->hw_params.utmi_phy_data_width;
 485
 486         switch (width) {
 487         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 488                 valid = (param == 8);
 489                 break;
 490         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 491                 valid = (param == 16);
 492                 break;
 493         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 494                 valid = (param == 8 || param == 16);
 495                 break;
 496         }
 497
 498         if (!valid)
 499                 dwc2_set_param_phy_utmi_width(hsotg);
 500 }
 501
 502 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 503 {
 504         int param = hsotg->params.power_down;
 505
 506         switch (param) {
 507         case DWC2_POWER_DOWN_PARAM_NONE:
 508                 break;
 509         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 510                 if (hsotg->hw_params.power_optimized)
 511                         break;
 512                 dev_dbg(hsotg->dev,
 513                         "Partial power down isn't supported by HW\n");
 514                 param = DWC2_POWER_DOWN_PARAM_NONE;
 515                 break;
 516         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 517                 if (hsotg->hw_params.hibernation)
 518                         break;
 519                 dev_dbg(hsotg->dev,
 520                         "Hibernation isn't supported by HW\n");
 521                 param = DWC2_POWER_DOWN_PARAM_NONE;
 522                 break;
 523         default:
 524                 dev_err(hsotg->dev,
 525                         "%s: Invalid parameter power_down=%d\n",
 526                         __func__, param);
 527                 param = DWC2_POWER_DOWN_PARAM_NONE;
 528                 break;
 529         }
 530
 531         hsotg->params.power_down = param;
 532 }
 533
 534 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 535 {
 536         int fifo_count;
 537         int fifo;
 538         int min;
 539         u32 total = 0;
 540         u32 dptxfszn;
 541
 542         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 543         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 544
 545         for (fifo = 1; fifo <= fifo_count; fifo++)
 546                 total += hsotg->params.g_tx_fifo_size[fifo];
 547
 548         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 549                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 550                          __func__);
 551                 dwc2_set_param_tx_fifo_sizes(hsotg);
 552         }
 553
 554         for (fifo = 1; fifo <= fifo_count; fifo++) {
 555                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 556
 557                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 558                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 559                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 560                                  __func__, fifo,
 561                                  hsotg->params.g_tx_fifo_size[fifo]);
 562                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 563                 }
 564         }
 565 }
 566
 567 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 568                 if ((int)(hsotg->params._param) < (_min) ||             \
 569                     (hsotg->params._param) > (_max)) {                  \
 570                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 571                                  __func__, #_param, hsotg->params._param); \
 572                         hsotg->params._param = (_def);                  \
 573                 }                                                       \
 574         } while (0)
 575
 576 #define CHECK_BOOL(_param, _check) do {                                 \
 577                 if (hsotg->params._param && !(_check)) {                \
 578                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 579                                  __func__, #_param, hsotg->params._param); \
 580                         hsotg->params._param = false;                   \
 581                 }                                                       \
 582         } while (0)
 583
 584 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 585 {
 586         struct dwc2_hw_params *hw = &hsotg->hw_params;
 587         struct dwc2_core_params *p = &hsotg->params;
 588         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 589
 590         dwc2_check_param_otg_cap(hsotg);
 591         dwc2_check_param_phy_type(hsotg);
 592         dwc2_check_param_speed(hsotg);
 593         dwc2_check_param_phy_utmi_width(hsotg);
 594         dwc2_check_param_power_down(hsotg);
 595         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 596         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 597         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 598         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 599         CHECK_BOOL(acg_enable, hw->acg_enable);
 600         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 601         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 602         CHECK_BOOL(lpm, hw->lpm_mode);
 603         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 604         CHECK_BOOL(besl, hsotg->params.lpm);
 605         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 606         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 607         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 608         CHECK_BOOL(service_interval, hw->service_interval_mode);
 609         CHECK_RANGE(max_packet_count,
 610                     15, hw->max_packet_count,
 611                     hw->max_packet_count);
 612         CHECK_RANGE(max_transfer_size,
 613                     2047, hw->max_transfer_size,
 614                     hw->max_transfer_size);
 615
 616         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 617             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 618                 CHECK_BOOL(host_dma, dma_capable);
 619                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 620                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 621                 CHECK_BOOL(host_ls_low_power_phy_clk,
 622                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 623                 CHECK_RANGE(host_channels,
 624                             1, hw->host_channels,
 625                             hw->host_channels);
 626                 CHECK_RANGE(host_rx_fifo_size,
 627                             16, hw->rx_fifo_size,
 628                             hw->rx_fifo_size);
 629                 CHECK_RANGE(host_nperio_tx_fifo_size,
 630                             16, hw->host_nperio_tx_fifo_size,
 631                             hw->host_nperio_tx_fifo_size);
 632                 CHECK_RANGE(host_perio_tx_fifo_size,
 633                             16, hw->host_perio_tx_fifo_size,
 634                             hw->host_perio_tx_fifo_size);
 635         }
 636
 637         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 638             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 639                 CHECK_BOOL(g_dma, dma_capable);
 640                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 641                 CHECK_RANGE(g_rx_fifo_size,
 642                             16, hw->rx_fifo_size,
 643                             hw->rx_fifo_size);
 644                 CHECK_RANGE(g_np_tx_fifo_size,
 645                             16, hw->dev_nperio_tx_fifo_size,
 646                             hw->dev_nperio_tx_fifo_size);
 647                 dwc2_check_param_tx_fifo_sizes(hsotg);
 648         }
 649 }
 650
 651 /*
 652  * Gets host hardware parameters. Forces host mode if not currently in
 653  * host mode. Should be called immediately after a core soft reset in
 654  * order to get the reset values.
 655  */
 656 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 657 {
 658         struct dwc2_hw_params *hw = &hsotg->hw_params;
 659         u32 gnptxfsiz;
 660         u32 hptxfsiz;
 661
 662         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 663                 return;
 664
 665         dwc2_force_mode(hsotg, true);
 666
 667         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 668         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 669
 670         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 671                                        FIFOSIZE_DEPTH_SHIFT;
 672         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 673                                       FIFOSIZE_DEPTH_SHIFT;
 674 }
 675
 676 /*
 677  * Gets device hardware parameters. Forces device mode if not
 678  * currently in device mode. Should be called immediately after a core
 679  * soft reset in order to get the reset values.
 680  */
 681 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 682 {
 683         struct dwc2_hw_params *hw = &hsotg->hw_params;
 684         u32 gnptxfsiz;
 685         int fifo, fifo_count;
 686
 687         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 688                 return;
 689
 690         dwc2_force_mode(hsotg, false);
 691
 692         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 693
 694         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 695
 696         for (fifo = 1; fifo <= fifo_count; fifo++) {
 697                 hw->g_tx_fifo_size[fifo] =
 698                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 699                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 700         }
 701
 702         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 703                                        FIFOSIZE_DEPTH_SHIFT;
 704 }
 705
 706 /**
 707  * During device initialization, read various hardware configuration
 708  * registers and interpret the contents.
 709  *
 710  * @hsotg: Programming view of the DWC_otg controller
 711  *
 712  */
 713 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 714 {
 715         struct dwc2_hw_params *hw = &hsotg->hw_params;
 716         unsigned int width;
 717         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 718         u32 grxfsiz;
 719
 720         /*
 721          * Attempt to ensure this device is really a DWC_otg Controller.
 722          * Read and verify the GSNPSID register contents. The value should be
 723          * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
 724          */
 725
 726         hw->snpsid = dwc2_readl(hsotg, GSNPSID);
 727         if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
 728             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
 729             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
 730                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
 731                         hw->snpsid);
 732                 return -ENODEV;
 733         }
 734
 735         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
 736                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
 737                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
 738
 739         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 740         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 741         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 742         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 743         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 744
 745         /* hwcfg1 */
 746         hw->dev_ep_dirs = hwcfg1;
 747
 748         /* hwcfg2 */
 749         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 750                       GHWCFG2_OP_MODE_SHIFT;
 751         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 752                    GHWCFG2_ARCHITECTURE_SHIFT;
 753         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 754         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 755                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 756         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 757                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 758         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 759                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 760         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 761                          GHWCFG2_NUM_DEV_EP_SHIFT;
 762         hw->nperio_tx_q_depth =
 763                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 764                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 765         hw->host_perio_tx_q_depth =
 766                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 767                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 768         hw->dev_token_q_depth =
 769                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 770                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 771
 772         /* hwcfg3 */
 773         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 774                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 775         hw->max_transfer_size = (1 << (width + 11)) - 1;
 776         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 777                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 778         hw->max_packet_count = (1 << (width + 4)) - 1;
 779         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 780         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 781                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 782         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 783
 784         /* hwcfg4 */
 785         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 786         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 787                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 788         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 789                              GHWCFG4_NUM_IN_EPS_SHIFT;
 790         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 791         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 792         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 793         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 794                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 795         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 796         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 797         hw->service_interval_mode = !!(hwcfg4 &
 798                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 799
 800         /* fifo sizes */
 801         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 802                                 GRXFSIZ_DEPTH_SHIFT;
 803         /*
 804          * Host specific hardware parameters. Reading these parameters
 805          * requires the controller to be in host mode. The mode will
 806          * be forced, if necessary, to read these values.
 807          */
 808         dwc2_get_host_hwparams(hsotg);
 809         dwc2_get_dev_hwparams(hsotg);
 810
 811         return 0;
 812 }
 813
 814 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 815 {
 816         const struct of_device_id *match;
 817         void (*set_params)(void *data);
 818
 819         dwc2_set_default_params(hsotg);
 820         dwc2_get_device_properties(hsotg);
 821
 822         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 823         if (match && match->data) {
 824                 set_params = match->data;
 825                 set_params(hsotg);
 826         }
 827
 828         dwc2_check_params(hsotg);
 829
 830         return 0;
 831 }