drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39 #include <linux/usb/of.h>
  40
  41 #include "core.h"
  42
  43 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  44 {
  45         struct dwc2_core_params *p = &hsotg->params;
  46
  47         p->host_rx_fifo_size = 774;
  48         p->max_transfer_size = 65535;
  49         p->max_packet_count = 511;
  50         p->ahbcfg = 0x10;
  51 }
  52
  53 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  54 {
  55         struct dwc2_core_params *p = &hsotg->params;
  56
  57         p->otg_caps.hnp_support = false;
  58         p->otg_caps.srp_support = false;
  59         p->speed = DWC2_SPEED_PARAM_HIGH;
  60         p->host_rx_fifo_size = 512;
  61         p->host_nperio_tx_fifo_size = 512;
  62         p->host_perio_tx_fifo_size = 512;
  63         p->max_transfer_size = 65535;
  64         p->max_packet_count = 511;
  65         p->host_channels = 16;
  66         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  67         p->phy_utmi_width = 8;
  68         p->i2c_enable = false;
  69         p->reload_ctl = false;
  70         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  71                 GAHBCFG_HBSTLEN_SHIFT;
  72         p->change_speed_quirk = true;
  73         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  74 }
  75
  76 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
  77 {
  78         struct dwc2_core_params *p = &hsotg->params;
  79
  80         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  81         p->no_clock_gating = true;
  82         p->phy_utmi_width = 8;
  83 }
  84
  85 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
  86 {
  87         struct dwc2_core_params *p = &hsotg->params;
  88
  89         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  90         p->no_clock_gating = true;
  91 }
  92
  93 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  94 {
  95         struct dwc2_core_params *p = &hsotg->params;
  96
  97         p->otg_caps.hnp_support = false;
  98         p->otg_caps.srp_support = false;
  99         p->host_rx_fifo_size = 525;
 100         p->host_nperio_tx_fifo_size = 128;
 101         p->host_perio_tx_fifo_size = 256;
 102         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 103                 GAHBCFG_HBSTLEN_SHIFT;
 104         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 105 }
 106
 107 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
 108 {
 109         struct dwc2_core_params *p = &hsotg->params;
 110
 111         p->otg_caps.hnp_support = false;
 112         p->otg_caps.srp_support = false;
 113         p->host_rx_fifo_size = 288;
 114         p->host_nperio_tx_fifo_size = 128;
 115         p->host_perio_tx_fifo_size = 96;
 116         p->max_transfer_size = 65535;
 117         p->max_packet_count = 511;
 118         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 119                 GAHBCFG_HBSTLEN_SHIFT;
 120 }
 121
 122 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 123 {
 124         struct dwc2_core_params *p = &hsotg->params;
 125
 126         p->otg_caps.hnp_support = false;
 127         p->otg_caps.srp_support = false;
 128         p->speed = DWC2_SPEED_PARAM_HIGH;
 129         p->host_rx_fifo_size = 512;
 130         p->host_nperio_tx_fifo_size = 500;
 131         p->host_perio_tx_fifo_size = 500;
 132         p->host_channels = 16;
 133         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 134         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 135                 GAHBCFG_HBSTLEN_SHIFT;
 136         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 137 }
 138
 139 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 140 {
 141         struct dwc2_core_params *p = &hsotg->params;
 142
 143         p->lpm = false;
 144         p->lpm_clock_gating = false;
 145         p->besl = false;
 146         p->hird_threshold_en = false;
 147 }
 148
 149 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 150 {
 151         struct dwc2_core_params *p = &hsotg->params;
 152
 153         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 154 }
 155
 156 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 157 {
 158         struct dwc2_core_params *p = &hsotg->params;
 159
 160         p->otg_caps.hnp_support = false;
 161         p->otg_caps.srp_support = false;
 162         p->speed = DWC2_SPEED_PARAM_FULL;
 163         p->host_rx_fifo_size = 128;
 164         p->host_nperio_tx_fifo_size = 96;
 165         p->host_perio_tx_fifo_size = 96;
 166         p->max_packet_count = 256;
 167         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 168         p->i2c_enable = false;
 169         p->activate_stm_fs_transceiver = true;
 170 }
 171
 172 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 173 {
 174         struct dwc2_core_params *p = &hsotg->params;
 175
 176         p->host_rx_fifo_size = 622;
 177         p->host_nperio_tx_fifo_size = 128;
 178         p->host_perio_tx_fifo_size = 256;
 179 }
 180
 181 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
 182 {
 183         struct dwc2_core_params *p = &hsotg->params;
 184
 185         p->otg_caps.hnp_support = false;
 186         p->otg_caps.srp_support = false;
 187         p->otg_caps.otg_rev = 0x200;
 188         p->speed = DWC2_SPEED_PARAM_FULL;
 189         p->host_rx_fifo_size = 128;
 190         p->host_nperio_tx_fifo_size = 96;
 191         p->host_perio_tx_fifo_size = 96;
 192         p->max_packet_count = 256;
 193         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 194         p->i2c_enable = false;
 195         p->activate_stm_fs_transceiver = true;
 196         p->activate_stm_id_vb_detection = true;
 197         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 198         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 199         p->host_support_fs_ls_low_power = true;
 200         p->host_ls_low_power_phy_clk = true;
 201 }
 202
 203 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 204 {
 205         struct dwc2_core_params *p = &hsotg->params;
 206
 207         p->otg_caps.hnp_support = false;
 208         p->otg_caps.srp_support = false;
 209         p->otg_caps.otg_rev = 0x200;
 210         p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
 211         p->host_rx_fifo_size = 440;
 212         p->host_nperio_tx_fifo_size = 256;
 213         p->host_perio_tx_fifo_size = 256;
 214         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 215         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 216         p->lpm = false;
 217         p->lpm_clock_gating = false;
 218         p->besl = false;
 219         p->hird_threshold_en = false;
 220 }
 221
 222 const struct of_device_id dwc2_of_match_table[] = {
 223         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 224         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 225         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 226         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 227         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 228         { .compatible = "snps,dwc2" },
 229         { .compatible = "samsung,s3c6400-hsotg",
 230           .data = dwc2_set_s3c6400_params },
 231         { .compatible = "amlogic,meson8-usb",
 232           .data = dwc2_set_amlogic_params },
 233         { .compatible = "amlogic,meson8b-usb",
 234           .data = dwc2_set_amlogic_params },
 235         { .compatible = "amlogic,meson-gxbb-usb",
 236           .data = dwc2_set_amlogic_params },
 237         { .compatible = "amlogic,meson-g12a-usb",
 238           .data = dwc2_set_amlogic_g12a_params },
 239         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 240         { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
 241         { .compatible = "st,stm32f4x9-fsotg",
 242           .data = dwc2_set_stm32f4x9_fsotg_params },
 243         { .compatible = "st,stm32f4x9-hsotg" },
 244         { .compatible = "st,stm32f7-hsotg",
 245           .data = dwc2_set_stm32f7_hsotg_params },
 246         { .compatible = "st,stm32mp15-fsotg",
 247           .data = dwc2_set_stm32mp15_fsotg_params },
 248         { .compatible = "st,stm32mp15-hsotg",
 249           .data = dwc2_set_stm32mp15_hsotg_params },
 250         { .compatible = "intel,socfpga-agilex-hsotg",
 251           .data = dwc2_set_socfpga_agilex_params },
 252         {},
 253 };
 254 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 255
 256 const struct acpi_device_id dwc2_acpi_match[] = {
 257         { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
 258         { },
 259 };
 260 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
 261
 262 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 263 {
 264         switch (hsotg->hw_params.op_mode) {
 265         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 266                 hsotg->params.otg_caps.hnp_support = true;
 267                 hsotg->params.otg_caps.srp_support = true;
 268                 break;
 269         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 270         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 271         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 272                 hsotg->params.otg_caps.hnp_support = false;
 273                 hsotg->params.otg_caps.srp_support = true;
 274                 break;
 275         default:
 276                 hsotg->params.otg_caps.hnp_support = false;
 277                 hsotg->params.otg_caps.srp_support = false;
 278                 break;
 279         }
 280 }
 281
 282 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 283 {
 284         int val;
 285         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 286
 287         val = DWC2_PHY_TYPE_PARAM_FS;
 288         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 289                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 290                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 291                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 292                 else
 293                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 294         }
 295
 296         if (dwc2_is_fs_iot(hsotg))
 297                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 298
 299         hsotg->params.phy_type = val;
 300 }
 301
 302 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 303 {
 304         int val;
 305
 306         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 307                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 308
 309         if (dwc2_is_fs_iot(hsotg))
 310                 val = DWC2_SPEED_PARAM_FULL;
 311
 312         if (dwc2_is_hs_iot(hsotg))
 313                 val = DWC2_SPEED_PARAM_HIGH;
 314
 315         hsotg->params.speed = val;
 316 }
 317
 318 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 319 {
 320         int val;
 321
 322         val = (hsotg->hw_params.utmi_phy_data_width ==
 323                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 324
 325         if (hsotg->phy) {
 326                 /*
 327                  * If using the generic PHY framework, check if the PHY bus
 328                  * width is 8-bit and set the phyif appropriately.
 329                  */
 330                 if (phy_get_bus_width(hsotg->phy) == 8)
 331                         val = 8;
 332         }
 333
 334         hsotg->params.phy_utmi_width = val;
 335 }
 336
 337 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 338 {
 339         struct dwc2_core_params *p = &hsotg->params;
 340         int depth_average;
 341         int fifo_count;
 342         int i;
 343
 344         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 345
 346         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 347         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 348         for (i = 1; i <= fifo_count; i++)
 349                 p->g_tx_fifo_size[i] = depth_average;
 350 }
 351
 352 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 353 {
 354         int val;
 355
 356         if (hsotg->hw_params.hibernation)
 357                 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
 358         else if (hsotg->hw_params.power_optimized)
 359                 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
 360         else
 361                 val = DWC2_POWER_DOWN_PARAM_NONE;
 362
 363         hsotg->params.power_down = val;
 364 }
 365
 366 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 367 {
 368         struct dwc2_core_params *p = &hsotg->params;
 369
 370         p->lpm = hsotg->hw_params.lpm_mode;
 371         if (p->lpm) {
 372                 p->lpm_clock_gating = true;
 373                 p->besl = true;
 374                 p->hird_threshold_en = true;
 375                 p->hird_threshold = 4;
 376         } else {
 377                 p->lpm_clock_gating = false;
 378                 p->besl = false;
 379                 p->hird_threshold_en = false;
 380         }
 381 }
 382
 383 /**
 384  * dwc2_set_default_params() - Set all core parameters to their
 385  * auto-detected default values.
 386  *
 387  * @hsotg: Programming view of the DWC_otg controller
 388  *
 389  */
 390 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 391 {
 392         struct dwc2_hw_params *hw = &hsotg->hw_params;
 393         struct dwc2_core_params *p = &hsotg->params;
 394         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 395
 396         dwc2_set_param_otg_cap(hsotg);
 397         dwc2_set_param_phy_type(hsotg);
 398         dwc2_set_param_speed(hsotg);
 399         dwc2_set_param_phy_utmi_width(hsotg);
 400         dwc2_set_param_power_down(hsotg);
 401         dwc2_set_param_lpm(hsotg);
 402         p->phy_ulpi_ddr = false;
 403         p->phy_ulpi_ext_vbus = false;
 404
 405         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 406         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 407         p->i2c_enable = hw->i2c_enable;
 408         p->acg_enable = hw->acg_enable;
 409         p->ulpi_fs_ls = false;
 410         p->ts_dline = false;
 411         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 412         p->uframe_sched = true;
 413         p->external_id_pin_ctl = false;
 414         p->ipg_isoc_en = false;
 415         p->service_interval = false;
 416         p->max_packet_count = hw->max_packet_count;
 417         p->max_transfer_size = hw->max_transfer_size;
 418         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 419         p->ref_clk_per = 33333;
 420         p->sof_cnt_wkup_alert = 100;
 421
 422         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 423             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 424                 p->host_dma = dma_capable;
 425                 p->dma_desc_enable = false;
 426                 p->dma_desc_fs_enable = false;
 427                 p->host_support_fs_ls_low_power = false;
 428                 p->host_ls_low_power_phy_clk = false;
 429                 p->host_channels = hw->host_channels;
 430                 p->host_rx_fifo_size = hw->rx_fifo_size;
 431                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 432                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 433         }
 434
 435         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 436             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 437                 p->g_dma = dma_capable;
 438                 p->g_dma_desc = hw->dma_desc_enable;
 439
 440                 /*
 441                  * The values for g_rx_fifo_size (2048) and
 442                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 443                  * gadget driver. These defaults have been hard-coded
 444                  * for some time so many platforms depend on these
 445                  * values. Leave them as defaults for now and only
 446                  * auto-detect if the hardware does not support the
 447                  * default.
 448                  */
 449                 p->g_rx_fifo_size = 2048;
 450                 p->g_np_tx_fifo_size = 1024;
 451                 dwc2_set_param_tx_fifo_sizes(hsotg);
 452         }
 453 }
 454
 455 /**
 456  * dwc2_get_device_properties() - Read in device properties.
 457  *
 458  * @hsotg: Programming view of the DWC_otg controller
 459  *
 460  * Read in the device properties and adjust core parameters if needed.
 461  */
 462 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 463 {
 464         struct dwc2_core_params *p = &hsotg->params;
 465         int num;
 466
 467         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 468             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 469                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 470                                          &p->g_rx_fifo_size);
 471
 472                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 473                                          &p->g_np_tx_fifo_size);
 474
 475                 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
 476                 if (num > 0) {
 477                         num = min(num, 15);
 478                         memset(p->g_tx_fifo_size, 0,
 479                                sizeof(p->g_tx_fifo_size));
 480                         device_property_read_u32_array(hsotg->dev,
 481                                                        "g-tx-fifo-size",
 482                                                        &p->g_tx_fifo_size[1],
 483                                                        num);
 484                 }
 485
 486                 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
 487         }
 488
 489         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 490                 p->oc_disable = true;
 491 }
 492
 493 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 494 {
 495         int valid = 1;
 496
 497         if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
 498                 /* check HNP && SRP capable */
 499                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 500                         valid = 0;
 501         } else if (!hsotg->params.otg_caps.hnp_support) {
 502                 /* check SRP only capable */
 503                 if (hsotg->params.otg_caps.srp_support) {
 504                         switch (hsotg->hw_params.op_mode) {
 505                         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 506                         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 507                         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 508                         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 509                                 break;
 510                         default:
 511                                 valid = 0;
 512                                 break;
 513                         }
 514                 }
 515                 /* else: NO HNP && NO SRP capable: always valid */
 516         } else {
 517                 valid = 0;
 518         }
 519
 520         if (!valid)
 521                 dwc2_set_param_otg_cap(hsotg);
 522 }
 523
 524 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 525 {
 526         int valid = 0;
 527         u32 hs_phy_type;
 528         u32 fs_phy_type;
 529
 530         hs_phy_type = hsotg->hw_params.hs_phy_type;
 531         fs_phy_type = hsotg->hw_params.fs_phy_type;
 532
 533         switch (hsotg->params.phy_type) {
 534         case DWC2_PHY_TYPE_PARAM_FS:
 535                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 536                         valid = 1;
 537                 break;
 538         case DWC2_PHY_TYPE_PARAM_UTMI:
 539                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 540                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 541                         valid = 1;
 542                 break;
 543         case DWC2_PHY_TYPE_PARAM_ULPI:
 544                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 545                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 546                         valid = 1;
 547                 break;
 548         default:
 549                 break;
 550         }
 551
 552         if (!valid)
 553                 dwc2_set_param_phy_type(hsotg);
 554 }
 555
 556 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 557 {
 558         int valid = 1;
 559         int phy_type = hsotg->params.phy_type;
 560         int speed = hsotg->params.speed;
 561
 562         switch (speed) {
 563         case DWC2_SPEED_PARAM_HIGH:
 564                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 565                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 566                         valid = 0;
 567                 break;
 568         case DWC2_SPEED_PARAM_FULL:
 569         case DWC2_SPEED_PARAM_LOW:
 570                 break;
 571         default:
 572                 valid = 0;
 573                 break;
 574         }
 575
 576         if (!valid)
 577                 dwc2_set_param_speed(hsotg);
 578 }
 579
 580 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 581 {
 582         int valid = 0;
 583         int param = hsotg->params.phy_utmi_width;
 584         int width = hsotg->hw_params.utmi_phy_data_width;
 585
 586         switch (width) {
 587         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 588                 valid = (param == 8);
 589                 break;
 590         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 591                 valid = (param == 16);
 592                 break;
 593         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 594                 valid = (param == 8 || param == 16);
 595                 break;
 596         }
 597
 598         if (!valid)
 599                 dwc2_set_param_phy_utmi_width(hsotg);
 600 }
 601
 602 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 603 {
 604         int param = hsotg->params.power_down;
 605
 606         switch (param) {
 607         case DWC2_POWER_DOWN_PARAM_NONE:
 608                 break;
 609         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 610                 if (hsotg->hw_params.power_optimized)
 611                         break;
 612                 dev_dbg(hsotg->dev,
 613                         "Partial power down isn't supported by HW\n");
 614                 param = DWC2_POWER_DOWN_PARAM_NONE;
 615                 break;
 616         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 617                 if (hsotg->hw_params.hibernation)
 618                         break;
 619                 dev_dbg(hsotg->dev,
 620                         "Hibernation isn't supported by HW\n");
 621                 param = DWC2_POWER_DOWN_PARAM_NONE;
 622                 break;
 623         default:
 624                 dev_err(hsotg->dev,
 625                         "%s: Invalid parameter power_down=%d\n",
 626                         __func__, param);
 627                 param = DWC2_POWER_DOWN_PARAM_NONE;
 628                 break;
 629         }
 630
 631         hsotg->params.power_down = param;
 632 }
 633
 634 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 635 {
 636         int fifo_count;
 637         int fifo;
 638         int min;
 639         u32 total = 0;
 640         u32 dptxfszn;
 641
 642         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 643         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 644
 645         for (fifo = 1; fifo <= fifo_count; fifo++)
 646                 total += hsotg->params.g_tx_fifo_size[fifo];
 647
 648         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 649                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 650                          __func__);
 651                 dwc2_set_param_tx_fifo_sizes(hsotg);
 652         }
 653
 654         for (fifo = 1; fifo <= fifo_count; fifo++) {
 655                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 656
 657                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 658                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 659                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 660                                  __func__, fifo,
 661                                  hsotg->params.g_tx_fifo_size[fifo]);
 662                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 663                 }
 664         }
 665 }
 666
 667 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 668                 if ((int)(hsotg->params._param) < (_min) ||             \
 669                     (hsotg->params._param) > (_max)) {                  \
 670                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 671                                  __func__, #_param, hsotg->params._param); \
 672                         hsotg->params._param = (_def);                  \
 673                 }                                                       \
 674         } while (0)
 675
 676 #define CHECK_BOOL(_param, _check) do {                                 \
 677                 if (hsotg->params._param && !(_check)) {                \
 678                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 679                                  __func__, #_param, hsotg->params._param); \
 680                         hsotg->params._param = false;                   \
 681                 }                                                       \
 682         } while (0)
 683
 684 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 685 {
 686         struct dwc2_hw_params *hw = &hsotg->hw_params;
 687         struct dwc2_core_params *p = &hsotg->params;
 688         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 689
 690         dwc2_check_param_otg_cap(hsotg);
 691         dwc2_check_param_phy_type(hsotg);
 692         dwc2_check_param_speed(hsotg);
 693         dwc2_check_param_phy_utmi_width(hsotg);
 694         dwc2_check_param_power_down(hsotg);
 695         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 696         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 697         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 698         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 699         CHECK_BOOL(acg_enable, hw->acg_enable);
 700         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 701         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 702         CHECK_BOOL(lpm, hw->lpm_mode);
 703         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 704         CHECK_BOOL(besl, hsotg->params.lpm);
 705         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 706         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 707         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 708         CHECK_BOOL(service_interval, hw->service_interval_mode);
 709         CHECK_RANGE(max_packet_count,
 710                     15, hw->max_packet_count,
 711                     hw->max_packet_count);
 712         CHECK_RANGE(max_transfer_size,
 713                     2047, hw->max_transfer_size,
 714                     hw->max_transfer_size);
 715
 716         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 717             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 718                 CHECK_BOOL(host_dma, dma_capable);
 719                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 720                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 721                 CHECK_BOOL(host_ls_low_power_phy_clk,
 722                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 723                 CHECK_RANGE(host_channels,
 724                             1, hw->host_channels,
 725                             hw->host_channels);
 726                 CHECK_RANGE(host_rx_fifo_size,
 727                             16, hw->rx_fifo_size,
 728                             hw->rx_fifo_size);
 729                 CHECK_RANGE(host_nperio_tx_fifo_size,
 730                             16, hw->host_nperio_tx_fifo_size,
 731                             hw->host_nperio_tx_fifo_size);
 732                 CHECK_RANGE(host_perio_tx_fifo_size,
 733                             16, hw->host_perio_tx_fifo_size,
 734                             hw->host_perio_tx_fifo_size);
 735         }
 736
 737         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 738             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 739                 CHECK_BOOL(g_dma, dma_capable);
 740                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 741                 CHECK_RANGE(g_rx_fifo_size,
 742                             16, hw->rx_fifo_size,
 743                             hw->rx_fifo_size);
 744                 CHECK_RANGE(g_np_tx_fifo_size,
 745                             16, hw->dev_nperio_tx_fifo_size,
 746                             hw->dev_nperio_tx_fifo_size);
 747                 dwc2_check_param_tx_fifo_sizes(hsotg);
 748         }
 749 }
 750
 751 /*
 752  * Gets host hardware parameters. Forces host mode if not currently in
 753  * host mode. Should be called immediately after a core soft reset in
 754  * order to get the reset values.
 755  */
 756 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 757 {
 758         struct dwc2_hw_params *hw = &hsotg->hw_params;
 759         u32 gnptxfsiz;
 760         u32 hptxfsiz;
 761
 762         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 763                 return;
 764
 765         dwc2_force_mode(hsotg, true);
 766
 767         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 768         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 769
 770         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 771                                        FIFOSIZE_DEPTH_SHIFT;
 772         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 773                                       FIFOSIZE_DEPTH_SHIFT;
 774 }
 775
 776 /*
 777  * Gets device hardware parameters. Forces device mode if not
 778  * currently in device mode. Should be called immediately after a core
 779  * soft reset in order to get the reset values.
 780  */
 781 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 782 {
 783         struct dwc2_hw_params *hw = &hsotg->hw_params;
 784         u32 gnptxfsiz;
 785         int fifo, fifo_count;
 786
 787         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 788                 return;
 789
 790         dwc2_force_mode(hsotg, false);
 791
 792         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 793
 794         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 795
 796         for (fifo = 1; fifo <= fifo_count; fifo++) {
 797                 hw->g_tx_fifo_size[fifo] =
 798                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 799                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 800         }
 801
 802         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 803                                        FIFOSIZE_DEPTH_SHIFT;
 804 }
 805
 806 /**
 807  * dwc2_get_hwparams() - During device initialization, read various hardware
 808  *                       configuration registers and interpret the contents.
 809  *
 810  * @hsotg: Programming view of the DWC_otg controller
 811  *
 812  */
 813 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 814 {
 815         struct dwc2_hw_params *hw = &hsotg->hw_params;
 816         unsigned int width;
 817         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 818         u32 grxfsiz;
 819
 820         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 821         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 822         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 823         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 824         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 825
 826         /* hwcfg1 */
 827         hw->dev_ep_dirs = hwcfg1;
 828
 829         /* hwcfg2 */
 830         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 831                       GHWCFG2_OP_MODE_SHIFT;
 832         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 833                    GHWCFG2_ARCHITECTURE_SHIFT;
 834         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 835         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 836                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 837         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 838                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 839         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 840                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 841         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 842                          GHWCFG2_NUM_DEV_EP_SHIFT;
 843         hw->nperio_tx_q_depth =
 844                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 845                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 846         hw->host_perio_tx_q_depth =
 847                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 848                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 849         hw->dev_token_q_depth =
 850                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 851                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 852
 853         /* hwcfg3 */
 854         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 855                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 856         hw->max_transfer_size = (1 << (width + 11)) - 1;
 857         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 858                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 859         hw->max_packet_count = (1 << (width + 4)) - 1;
 860         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 861         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 862                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 863         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 864
 865         /* hwcfg4 */
 866         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 867         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 868                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 869         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 870                              GHWCFG4_NUM_IN_EPS_SHIFT;
 871         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 872         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 873         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 874         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 875                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 876         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 877         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 878         hw->service_interval_mode = !!(hwcfg4 &
 879                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 880
 881         /* fifo sizes */
 882         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 883                                 GRXFSIZ_DEPTH_SHIFT;
 884         /*
 885          * Host specific hardware parameters. Reading these parameters
 886          * requires the controller to be in host mode. The mode will
 887          * be forced, if necessary, to read these values.
 888          */
 889         dwc2_get_host_hwparams(hsotg);
 890         dwc2_get_dev_hwparams(hsotg);
 891
 892         return 0;
 893 }
 894
 895 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
 896
 897 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 898 {
 899         const struct of_device_id *match;
 900         set_params_cb set_params;
 901
 902         dwc2_set_default_params(hsotg);
 903         dwc2_get_device_properties(hsotg);
 904
 905         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 906         if (match && match->data) {
 907                 set_params = match->data;
 908                 set_params(hsotg);
 909         } else {
 910                 const struct acpi_device_id *amatch;
 911
 912                 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev);
 913                 if (amatch && amatch->driver_data) {
 914                         set_params = (set_params_cb)amatch->driver_data;
 915                         set_params(hsotg);
 916                 }
 917         }
 918
 919         dwc2_check_params(hsotg);
 920
 921         return 0;
 922 }