1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #define HSOTG_REG(x) (x)
43 #define GOTGCTL HSOTG_REG(0x000)
44 #define GOTGCTL_CHIRPEN BIT(27)
45 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
46 #define GOTGCTL_MULT_VALID_BC_SHIFT 22
47 #define GOTGCTL_OTGVER BIT(20)
48 #define GOTGCTL_BSESVLD BIT(19)
49 #define GOTGCTL_ASESVLD BIT(18)
50 #define GOTGCTL_DBNC_SHORT BIT(17)
51 #define GOTGCTL_CONID_B BIT(16)
52 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
53 #define GOTGCTL_DEVHNPEN BIT(11)
54 #define GOTGCTL_HSTSETHNPEN BIT(10)
55 #define GOTGCTL_HNPREQ BIT(9)
56 #define GOTGCTL_HSTNEGSCS BIT(8)
57 #define GOTGCTL_BVALOVAL BIT(7)
58 #define GOTGCTL_BVALOEN BIT(6)
59 #define GOTGCTL_AVALOVAL BIT(5)
60 #define GOTGCTL_AVALOEN BIT(4)
61 #define GOTGCTL_VBVALOVAL BIT(3)
62 #define GOTGCTL_VBVALOEN BIT(2)
63 #define GOTGCTL_SESREQ BIT(1)
64 #define GOTGCTL_SESREQSCS BIT(0)
66 #define GOTGINT HSOTG_REG(0x004)
67 #define GOTGINT_DBNCE_DONE BIT(19)
68 #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
69 #define GOTGINT_HST_NEG_DET BIT(17)
70 #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
71 #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
72 #define GOTGINT_SES_END_DET BIT(2)
74 #define GAHBCFG HSOTG_REG(0x008)
75 #define GAHBCFG_AHB_SINGLE BIT(23)
76 #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
77 #define GAHBCFG_REM_MEM_SUPP BIT(21)
78 #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
79 #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
80 #define GAHBCFG_DMA_EN BIT(5)
81 #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
82 #define GAHBCFG_HBSTLEN_SHIFT 1
83 #define GAHBCFG_HBSTLEN_SINGLE 0
84 #define GAHBCFG_HBSTLEN_INCR 1
85 #define GAHBCFG_HBSTLEN_INCR4 3
86 #define GAHBCFG_HBSTLEN_INCR8 5
87 #define GAHBCFG_HBSTLEN_INCR16 7
88 #define GAHBCFG_GLBL_INTR_EN BIT(0)
89 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
90 GAHBCFG_NP_TXF_EMP_LVL | \
94 #define GUSBCFG HSOTG_REG(0x00C)
95 #define GUSBCFG_FORCEDEVMODE BIT(30)
96 #define GUSBCFG_FORCEHOSTMODE BIT(29)
97 #define GUSBCFG_TXENDDELAY BIT(28)
98 #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
99 #define GUSBCFG_ICUSBCAP BIT(26)
100 #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
101 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
102 #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
103 #define GUSBCFG_TERMSELDLPULSE BIT(22)
104 #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
105 #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
106 #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
107 #define GUSBCFG_ULPI_AUTO_RES BIT(18)
108 #define GUSBCFG_ULPI_FS_LS BIT(17)
109 #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
110 #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
111 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
112 #define GUSBCFG_USBTRDTIM_SHIFT 10
113 #define GUSBCFG_HNPCAP BIT(9)
114 #define GUSBCFG_SRPCAP BIT(8)
115 #define GUSBCFG_DDRSEL BIT(7)
116 #define GUSBCFG_PHYSEL BIT(6)
117 #define GUSBCFG_FSINTF BIT(5)
118 #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
119 #define GUSBCFG_PHYIF16 BIT(3)
120 #define GUSBCFG_PHYIF8 (0 << 3)
121 #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
122 #define GUSBCFG_TOUTCAL_SHIFT 0
123 #define GUSBCFG_TOUTCAL_LIMIT 0x7
124 #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
126 #define GRSTCTL HSOTG_REG(0x010)
127 #define GRSTCTL_AHBIDLE BIT(31)
128 #define GRSTCTL_DMAREQ BIT(30)
129 #define GRSTCTL_CSFTRST_DONE BIT(29)
130 #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
131 #define GRSTCTL_TXFNUM_SHIFT 6
132 #define GRSTCTL_TXFNUM_LIMIT 0x1f
133 #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
134 #define GRSTCTL_TXFFLSH BIT(5)
135 #define GRSTCTL_RXFFLSH BIT(4)
136 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
137 #define GRSTCTL_FRMCNTRRST BIT(2)
138 #define GRSTCTL_HSFTRST BIT(1)
139 #define GRSTCTL_CSFTRST BIT(0)
141 #define GINTSTS HSOTG_REG(0x014)
142 #define GINTMSK HSOTG_REG(0x018)
143 #define GINTSTS_WKUPINT BIT(31)
144 #define GINTSTS_SESSREQINT BIT(30)
145 #define GINTSTS_DISCONNINT BIT(29)
146 #define GINTSTS_CONIDSTSCHNG BIT(28)
147 #define GINTSTS_LPMTRANRCVD BIT(27)
148 #define GINTSTS_PTXFEMP BIT(26)
149 #define GINTSTS_HCHINT BIT(25)
150 #define GINTSTS_PRTINT BIT(24)
151 #define GINTSTS_RESETDET BIT(23)
152 #define GINTSTS_FET_SUSP BIT(22)
153 #define GINTSTS_INCOMPL_IP BIT(21)
154 #define GINTSTS_INCOMPL_SOOUT BIT(21)
155 #define GINTSTS_INCOMPL_SOIN BIT(20)
156 #define GINTSTS_OEPINT BIT(19)
157 #define GINTSTS_IEPINT BIT(18)
158 #define GINTSTS_EPMIS BIT(17)
159 #define GINTSTS_RESTOREDONE BIT(16)
160 #define GINTSTS_EOPF BIT(15)
161 #define GINTSTS_ISOUTDROP BIT(14)
162 #define GINTSTS_ENUMDONE BIT(13)
163 #define GINTSTS_USBRST BIT(12)
164 #define GINTSTS_USBSUSP BIT(11)
165 #define GINTSTS_ERLYSUSP BIT(10)
166 #define GINTSTS_I2CINT BIT(9)
167 #define GINTSTS_ULPI_CK_INT BIT(8)
168 #define GINTSTS_GOUTNAKEFF BIT(7)
169 #define GINTSTS_GINNAKEFF BIT(6)
170 #define GINTSTS_NPTXFEMP BIT(5)
171 #define GINTSTS_RXFLVL BIT(4)
172 #define GINTSTS_SOF BIT(3)
173 #define GINTSTS_OTGINT BIT(2)
174 #define GINTSTS_MODEMIS BIT(1)
175 #define GINTSTS_CURMODE_HOST BIT(0)
177 #define GRXSTSR HSOTG_REG(0x01C)
178 #define GRXSTSP HSOTG_REG(0x020)
179 #define GRXSTS_FN_MASK (0x7f << 25)
180 #define GRXSTS_FN_SHIFT 25
181 #define GRXSTS_PKTSTS_MASK (0xf << 17)
182 #define GRXSTS_PKTSTS_SHIFT 17
183 #define GRXSTS_PKTSTS_GLOBALOUTNAK 1
184 #define GRXSTS_PKTSTS_OUTRX 2
185 #define GRXSTS_PKTSTS_HCHIN 2
186 #define GRXSTS_PKTSTS_OUTDONE 3
187 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
188 #define GRXSTS_PKTSTS_SETUPDONE 4
189 #define GRXSTS_PKTSTS_DATATOGGLEERR 5
190 #define GRXSTS_PKTSTS_SETUPRX 6
191 #define GRXSTS_PKTSTS_HCHHALTED 7
192 #define GRXSTS_HCHNUM_MASK (0xf << 0)
193 #define GRXSTS_HCHNUM_SHIFT 0
194 #define GRXSTS_DPID_MASK (0x3 << 15)
195 #define GRXSTS_DPID_SHIFT 15
196 #define GRXSTS_BYTECNT_MASK (0x7ff << 4)
197 #define GRXSTS_BYTECNT_SHIFT 4
198 #define GRXSTS_EPNUM_MASK (0xf << 0)
199 #define GRXSTS_EPNUM_SHIFT 0
201 #define GRXFSIZ HSOTG_REG(0x024)
202 #define GRXFSIZ_DEPTH_MASK (0xffff << 0)
203 #define GRXFSIZ_DEPTH_SHIFT 0
205 #define GNPTXFSIZ HSOTG_REG(0x028)
206 /* Use FIFOSIZE_* constants to access this register */
208 #define GNPTXSTS HSOTG_REG(0x02C)
209 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
210 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
211 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
212 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
213 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
214 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
215 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
216 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
218 #define GI2CCTL HSOTG_REG(0x0030)
219 #define GI2CCTL_BSYDNE BIT(31)
220 #define GI2CCTL_RW BIT(30)
221 #define GI2CCTL_I2CDATSE0 BIT(28)
222 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
223 #define GI2CCTL_I2CDEVADDR_SHIFT 26
224 #define GI2CCTL_I2CSUSPCTL BIT(25)
225 #define GI2CCTL_ACK BIT(24)
226 #define GI2CCTL_I2CEN BIT(23)
227 #define GI2CCTL_ADDR_MASK (0x7f << 16)
228 #define GI2CCTL_ADDR_SHIFT 16
229 #define GI2CCTL_REGADDR_MASK (0xff << 8)
230 #define GI2CCTL_REGADDR_SHIFT 8
231 #define GI2CCTL_RWDATA_MASK (0xff << 0)
232 #define GI2CCTL_RWDATA_SHIFT 0
234 #define GPVNDCTL HSOTG_REG(0x0034)
235 #define GGPIO HSOTG_REG(0x0038)
236 #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
237 #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
238 #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
240 #define GUID HSOTG_REG(0x003c)
241 #define GSNPSID HSOTG_REG(0x0040)
242 #define GHWCFG1 HSOTG_REG(0x0044)
243 #define GSNPSID_ID_MASK GENMASK(31, 16)
245 #define GHWCFG2 HSOTG_REG(0x0048)
246 #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
247 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
248 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
249 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
250 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
251 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
252 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
253 #define GHWCFG2_MULTI_PROC_INT BIT(20)
254 #define GHWCFG2_DYNAMIC_FIFO BIT(19)
255 #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
256 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
257 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
258 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
259 #define GHWCFG2_NUM_DEV_EP_SHIFT 10
260 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
261 #define GHWCFG2_FS_PHY_TYPE_SHIFT 8
262 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
263 #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
264 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
265 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
266 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
267 #define GHWCFG2_HS_PHY_TYPE_SHIFT 6
268 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
269 #define GHWCFG2_HS_PHY_TYPE_UTMI 1
270 #define GHWCFG2_HS_PHY_TYPE_ULPI 2
271 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
272 #define GHWCFG2_POINT2POINT BIT(5)
273 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
274 #define GHWCFG2_ARCHITECTURE_SHIFT 3
275 #define GHWCFG2_SLAVE_ONLY_ARCH 0
276 #define GHWCFG2_EXT_DMA_ARCH 1
277 #define GHWCFG2_INT_DMA_ARCH 2
278 #define GHWCFG2_OP_MODE_MASK (0x7 << 0)
279 #define GHWCFG2_OP_MODE_SHIFT 0
280 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
281 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
282 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
283 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
284 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
285 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
286 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
287 #define GHWCFG2_OP_MODE_UNDEFINED 7
289 #define GHWCFG3 HSOTG_REG(0x004c)
290 #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
291 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
292 #define GHWCFG3_OTG_LPM_EN BIT(15)
293 #define GHWCFG3_BC_SUPPORT BIT(14)
294 #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
295 #define GHWCFG3_ADP_SUPP BIT(12)
296 #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
297 #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
298 #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
299 #define GHWCFG3_I2C BIT(8)
300 #define GHWCFG3_OTG_FUNC BIT(7)
301 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
302 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
303 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
304 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
306 #define GHWCFG4 HSOTG_REG(0x0050)
307 #define GHWCFG4_DESC_DMA_DYN BIT(31)
308 #define GHWCFG4_DESC_DMA BIT(30)
309 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
310 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
311 #define GHWCFG4_DED_FIFO_EN BIT(25)
312 #define GHWCFG4_DED_FIFO_SHIFT 25
313 #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
314 #define GHWCFG4_B_VALID_FILT_EN BIT(23)
315 #define GHWCFG4_A_VALID_FILT_EN BIT(22)
316 #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
317 #define GHWCFG4_IDDIG_FILT_EN BIT(20)
318 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
319 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
320 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
321 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
322 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
323 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
324 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
325 #define GHWCFG4_ACG_SUPPORTED BIT(12)
326 #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
327 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
328 #define GHWCFG4_XHIBER BIT(7)
329 #define GHWCFG4_HIBER BIT(6)
330 #define GHWCFG4_MIN_AHB_FREQ BIT(5)
331 #define GHWCFG4_POWER_OPTIMIZ BIT(4)
332 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
333 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
335 #define GLPMCFG HSOTG_REG(0x0054)
336 #define GLPMCFG_INVSELHSIC BIT(31)
337 #define GLPMCFG_HSICCON BIT(30)
338 #define GLPMCFG_RSTRSLPSTS BIT(29)
339 #define GLPMCFG_ENBESL BIT(28)
340 #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
341 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
342 #define GLPMCFG_SNDLPM BIT(24)
343 #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
344 #define GLPMCFG_RETRY_CNT_SHIFT 21
345 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
346 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22)
347 #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
348 #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
349 #define GLPMCFG_L1RESUMEOK BIT(16)
350 #define GLPMCFG_SLPSTS BIT(15)
351 #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
352 #define GLPMCFG_COREL1RES_SHIFT 13
353 #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
354 #define GLPMCFG_HIRD_THRES_SHIFT 8
355 #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
356 #define GLPMCFG_ENBLSLPM BIT(7)
357 #define GLPMCFG_BREMOTEWAKE BIT(6)
358 #define GLPMCFG_HIRD_MASK (0xf << 2)
359 #define GLPMCFG_HIRD_SHIFT 2
360 #define GLPMCFG_APPL1RES BIT(1)
361 #define GLPMCFG_LPMCAP BIT(0)
363 #define GPWRDN HSOTG_REG(0x0058)
364 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
365 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
366 #define GPWRDN_ADP_INT BIT(23)
367 #define GPWRDN_BSESSVLD BIT(22)
368 #define GPWRDN_IDSTS BIT(21)
369 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
370 #define GPWRDN_LINESTATE_SHIFT 19
371 #define GPWRDN_STS_CHGINT_MSK BIT(18)
372 #define GPWRDN_STS_CHGINT BIT(17)
373 #define GPWRDN_SRP_DET_MSK BIT(16)
374 #define GPWRDN_SRP_DET BIT(15)
375 #define GPWRDN_CONNECT_DET_MSK BIT(14)
376 #define GPWRDN_CONNECT_DET BIT(13)
377 #define GPWRDN_DISCONN_DET_MSK BIT(12)
378 #define GPWRDN_DISCONN_DET BIT(11)
379 #define GPWRDN_RST_DET_MSK BIT(10)
380 #define GPWRDN_RST_DET BIT(9)
381 #define GPWRDN_LNSTSCHG_MSK BIT(8)
382 #define GPWRDN_LNSTSCHG BIT(7)
383 #define GPWRDN_DIS_VBUS BIT(6)
384 #define GPWRDN_PWRDNSWTCH BIT(5)
385 #define GPWRDN_PWRDNRSTN BIT(4)
386 #define GPWRDN_PWRDNCLMP BIT(3)
387 #define GPWRDN_RESTORE BIT(2)
388 #define GPWRDN_PMUACTV BIT(1)
389 #define GPWRDN_PMUINTSEL BIT(0)
391 #define GDFIFOCFG HSOTG_REG(0x005c)
392 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
393 #define GDFIFOCFG_EPINFOBASE_SHIFT 16
394 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
395 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0
397 #define ADPCTL HSOTG_REG(0x0060)
398 #define ADPCTL_AR_MASK (0x3 << 27)
399 #define ADPCTL_AR_SHIFT 27
400 #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
401 #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
402 #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
403 #define ADPCTL_ADP_TMOUT_INT BIT(23)
404 #define ADPCTL_ADP_SNS_INT BIT(22)
405 #define ADPCTL_ADP_PRB_INT BIT(21)
406 #define ADPCTL_ADPENA BIT(20)
407 #define ADPCTL_ADPRES BIT(19)
408 #define ADPCTL_ENASNS BIT(18)
409 #define ADPCTL_ENAPRB BIT(17)
410 #define ADPCTL_RTIM_MASK (0x7ff << 6)
411 #define ADPCTL_RTIM_SHIFT 6
412 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
413 #define ADPCTL_PRB_PER_SHIFT 4
414 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
415 #define ADPCTL_PRB_DELTA_SHIFT 2
416 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
417 #define ADPCTL_PRB_DSCHRG_SHIFT 0
419 #define GREFCLK HSOTG_REG(0x0064)
420 #define GREFCLK_REFCLKPER_MASK (0x1ffff << 15)
421 #define GREFCLK_REFCLKPER_SHIFT 15
422 #define GREFCLK_REF_CLK_MODE BIT(14)
423 #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff)
424 #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0
426 #define GINTMSK2 HSOTG_REG(0x0068)
427 #define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0)
429 #define GINTSTS2 HSOTG_REG(0x006c)
430 #define GINTSTS2_WKUP_ALERT_INT BIT(0)
432 #define HPTXFSIZ HSOTG_REG(0x100)
433 /* Use FIFOSIZE_* constants to access this register */
435 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
436 /* Use FIFOSIZE_* constants to access this register */
438 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
439 #define FIFOSIZE_DEPTH_MASK (0xffff << 16)
440 #define FIFOSIZE_DEPTH_SHIFT 16
441 #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
442 #define FIFOSIZE_STARTADDR_SHIFT 0
443 #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
445 /* Device mode registers */
447 #define DCFG HSOTG_REG(0x800)
448 #define DCFG_DESCDMA_EN BIT(23)
449 #define DCFG_EPMISCNT_MASK (0x1f << 18)
450 #define DCFG_EPMISCNT_SHIFT 18
451 #define DCFG_EPMISCNT_LIMIT 0x1f
452 #define DCFG_EPMISCNT(_x) ((_x) << 18)
453 #define DCFG_IPG_ISOC_SUPPORDED BIT(17)
454 #define DCFG_PERFRINT_MASK (0x3 << 11)
455 #define DCFG_PERFRINT_SHIFT 11
456 #define DCFG_PERFRINT_LIMIT 0x3
457 #define DCFG_PERFRINT(_x) ((_x) << 11)
458 #define DCFG_DEVADDR_MASK (0x7f << 4)
459 #define DCFG_DEVADDR_SHIFT 4
460 #define DCFG_DEVADDR_LIMIT 0x7f
461 #define DCFG_DEVADDR(_x) ((_x) << 4)
462 #define DCFG_NZ_STS_OUT_HSHK BIT(2)
463 #define DCFG_DEVSPD_MASK (0x3 << 0)
464 #define DCFG_DEVSPD_SHIFT 0
465 #define DCFG_DEVSPD_HS 0
466 #define DCFG_DEVSPD_FS 1
467 #define DCFG_DEVSPD_LS 2
468 #define DCFG_DEVSPD_FS48 3
470 #define DCTL HSOTG_REG(0x804)
471 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
472 #define DCTL_PWRONPRGDONE BIT(11)
473 #define DCTL_CGOUTNAK BIT(10)
474 #define DCTL_SGOUTNAK BIT(9)
475 #define DCTL_CGNPINNAK BIT(8)
476 #define DCTL_SGNPINNAK BIT(7)
477 #define DCTL_TSTCTL_MASK (0x7 << 4)
478 #define DCTL_TSTCTL_SHIFT 4
479 #define DCTL_GOUTNAKSTS BIT(3)
480 #define DCTL_GNPINNAKSTS BIT(2)
481 #define DCTL_SFTDISCON BIT(1)
482 #define DCTL_RMTWKUPSIG BIT(0)
484 #define DSTS HSOTG_REG(0x808)
485 #define DSTS_SOFFN_MASK (0x3fff << 8)
486 #define DSTS_SOFFN_SHIFT 8
487 #define DSTS_SOFFN_LIMIT 0x3fff
488 #define DSTS_SOFFN(_x) ((_x) << 8)
489 #define DSTS_ERRATICERR BIT(3)
490 #define DSTS_ENUMSPD_MASK (0x3 << 1)
491 #define DSTS_ENUMSPD_SHIFT 1
492 #define DSTS_ENUMSPD_HS 0
493 #define DSTS_ENUMSPD_FS 1
494 #define DSTS_ENUMSPD_LS 2
495 #define DSTS_ENUMSPD_FS48 3
496 #define DSTS_SUSPSTS BIT(0)
498 #define DIEPMSK HSOTG_REG(0x810)
499 #define DIEPMSK_NAKMSK BIT(13)
500 #define DIEPMSK_BNAININTRMSK BIT(9)
501 #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
502 #define DIEPMSK_TXFIFOEMPTY BIT(7)
503 #define DIEPMSK_INEPNAKEFFMSK BIT(6)
504 #define DIEPMSK_INTKNEPMISMSK BIT(5)
505 #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
506 #define DIEPMSK_TIMEOUTMSK BIT(3)
507 #define DIEPMSK_AHBERRMSK BIT(2)
508 #define DIEPMSK_EPDISBLDMSK BIT(1)
509 #define DIEPMSK_XFERCOMPLMSK BIT(0)
511 #define DOEPMSK HSOTG_REG(0x814)
512 #define DOEPMSK_BNAMSK BIT(9)
513 #define DOEPMSK_BACK2BACKSETUP BIT(6)
514 #define DOEPMSK_STSPHSERCVDMSK BIT(5)
515 #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
516 #define DOEPMSK_SETUPMSK BIT(3)
517 #define DOEPMSK_AHBERRMSK BIT(2)
518 #define DOEPMSK_EPDISBLDMSK BIT(1)
519 #define DOEPMSK_XFERCOMPLMSK BIT(0)
521 #define DAINT HSOTG_REG(0x818)
522 #define DAINTMSK HSOTG_REG(0x81C)
523 #define DAINT_OUTEP_SHIFT 16
524 #define DAINT_OUTEP(_x) (1 << ((_x) + 16))
525 #define DAINT_INEP(_x) (1 << (_x))
527 #define DTKNQR1 HSOTG_REG(0x820)
528 #define DTKNQR2 HSOTG_REG(0x824)
529 #define DTKNQR3 HSOTG_REG(0x830)
530 #define DTKNQR4 HSOTG_REG(0x834)
531 #define DIEPEMPMSK HSOTG_REG(0x834)
533 #define DVBUSDIS HSOTG_REG(0x828)
534 #define DVBUSPULSE HSOTG_REG(0x82C)
536 #define DIEPCTL0 HSOTG_REG(0x900)
537 #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
539 #define DOEPCTL0 HSOTG_REG(0xB00)
540 #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
543 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
544 * bits[25..22] - should always be zero, this isn't a periodic endpoint
545 * bits[10..0] - MPS setting different for EP0
547 #define D0EPCTL_MPS_MASK (0x3 << 0)
548 #define D0EPCTL_MPS_SHIFT 0
549 #define D0EPCTL_MPS_64 0
550 #define D0EPCTL_MPS_32 1
551 #define D0EPCTL_MPS_16 2
552 #define D0EPCTL_MPS_8 3
554 #define DXEPCTL_EPENA BIT(31)
555 #define DXEPCTL_EPDIS BIT(30)
556 #define DXEPCTL_SETD1PID BIT(29)
557 #define DXEPCTL_SETODDFR BIT(29)
558 #define DXEPCTL_SETD0PID BIT(28)
559 #define DXEPCTL_SETEVENFR BIT(28)
560 #define DXEPCTL_SNAK BIT(27)
561 #define DXEPCTL_CNAK BIT(26)
562 #define DXEPCTL_TXFNUM_MASK (0xf << 22)
563 #define DXEPCTL_TXFNUM_SHIFT 22
564 #define DXEPCTL_TXFNUM_LIMIT 0xf
565 #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
566 #define DXEPCTL_STALL BIT(21)
567 #define DXEPCTL_SNP BIT(20)
568 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
569 #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
570 #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
571 #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
572 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
574 #define DXEPCTL_NAKSTS BIT(17)
575 #define DXEPCTL_DPID BIT(16)
576 #define DXEPCTL_EOFRNUM BIT(16)
577 #define DXEPCTL_USBACTEP BIT(15)
578 #define DXEPCTL_NEXTEP_MASK (0xf << 11)
579 #define DXEPCTL_NEXTEP_SHIFT 11
580 #define DXEPCTL_NEXTEP_LIMIT 0xf
581 #define DXEPCTL_NEXTEP(_x) ((_x) << 11)
582 #define DXEPCTL_MPS_MASK (0x7ff << 0)
583 #define DXEPCTL_MPS_SHIFT 0
584 #define DXEPCTL_MPS_LIMIT 0x7ff
585 #define DXEPCTL_MPS(_x) ((_x) << 0)
587 #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
588 #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
589 #define DXEPINT_SETUP_RCVD BIT(15)
590 #define DXEPINT_NYETINTRPT BIT(14)
591 #define DXEPINT_NAKINTRPT BIT(13)
592 #define DXEPINT_BBLEERRINTRPT BIT(12)
593 #define DXEPINT_PKTDRPSTS BIT(11)
594 #define DXEPINT_BNAINTR BIT(9)
595 #define DXEPINT_TXFIFOUNDRN BIT(8)
596 #define DXEPINT_OUTPKTERR BIT(8)
597 #define DXEPINT_TXFEMP BIT(7)
598 #define DXEPINT_INEPNAKEFF BIT(6)
599 #define DXEPINT_BACK2BACKSETUP BIT(6)
600 #define DXEPINT_INTKNEPMIS BIT(5)
601 #define DXEPINT_STSPHSERCVD BIT(5)
602 #define DXEPINT_INTKNTXFEMP BIT(4)
603 #define DXEPINT_OUTTKNEPDIS BIT(4)
604 #define DXEPINT_TIMEOUT BIT(3)
605 #define DXEPINT_SETUP BIT(3)
606 #define DXEPINT_AHBERR BIT(2)
607 #define DXEPINT_EPDISBLD BIT(1)
608 #define DXEPINT_XFERCOMPL BIT(0)
610 #define DIEPTSIZ0 HSOTG_REG(0x910)
611 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
612 #define DIEPTSIZ0_PKTCNT_SHIFT 19
613 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
614 #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
615 #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
616 #define DIEPTSIZ0_XFERSIZE_SHIFT 0
617 #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
618 #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
620 #define DOEPTSIZ0 HSOTG_REG(0xB10)
621 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
622 #define DOEPTSIZ0_SUPCNT_SHIFT 29
623 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
624 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
625 #define DOEPTSIZ0_PKTCNT BIT(19)
626 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
627 #define DOEPTSIZ0_XFERSIZE_SHIFT 0
629 #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
630 #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
631 #define DXEPTSIZ_MC_MASK (0x3 << 29)
632 #define DXEPTSIZ_MC_SHIFT 29
633 #define DXEPTSIZ_MC_LIMIT 0x3
634 #define DXEPTSIZ_MC(_x) ((_x) << 29)
635 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
636 #define DXEPTSIZ_PKTCNT_SHIFT 19
637 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
638 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
639 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
640 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
641 #define DXEPTSIZ_XFERSIZE_SHIFT 0
642 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
643 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
644 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
646 #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
647 #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
649 #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
651 #define PCGCTL HSOTG_REG(0x0e00)
652 #define PCGCTL_IF_DEV_MODE BIT(31)
653 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
654 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
655 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
656 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
657 #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
658 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
659 #define PCGCTL_MAX_TERMSEL BIT(19)
660 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
661 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
662 #define PCGCTL_PORT_POWER BIT(16)
663 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
664 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
665 #define PCGCTL_ESS_REG_RESTORED BIT(13)
666 #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
667 #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
668 #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
669 #define PCGCTL_RESTOREMODE BIT(9)
670 #define PCGCTL_RESETAFTSUSP BIT(8)
671 #define PCGCTL_DEEP_SLEEP BIT(7)
672 #define PCGCTL_PHY_IN_SLEEP BIT(6)
673 #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
674 #define PCGCTL_RSTPDWNMODULE BIT(3)
675 #define PCGCTL_PWRCLMP BIT(2)
676 #define PCGCTL_GATEHCLK BIT(1)
677 #define PCGCTL_STOPPCLK BIT(0)
679 #define PCGCCTL1 HSOTG_REG(0xe04)
680 #define PCGCCTL1_TIMER (0x3 << 1)
681 #define PCGCCTL1_GATEEN BIT(0)
683 #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
685 /* Host Mode Registers */
687 #define HCFG HSOTG_REG(0x0400)
688 #define HCFG_MODECHTIMEN BIT(31)
689 #define HCFG_PERSCHEDENA BIT(26)
690 #define HCFG_FRLISTEN_MASK (0x3 << 24)
691 #define HCFG_FRLISTEN_SHIFT 24
692 #define HCFG_FRLISTEN_8 (0 << 24)
693 #define FRLISTEN_8_SIZE 8
694 #define HCFG_FRLISTEN_16 BIT(24)
695 #define FRLISTEN_16_SIZE 16
696 #define HCFG_FRLISTEN_32 (2 << 24)
697 #define FRLISTEN_32_SIZE 32
698 #define HCFG_FRLISTEN_64 (3 << 24)
699 #define FRLISTEN_64_SIZE 64
700 #define HCFG_DESCDMA BIT(23)
701 #define HCFG_RESVALID_MASK (0xff << 8)
702 #define HCFG_RESVALID_SHIFT 8
703 #define HCFG_ENA32KHZ BIT(7)
704 #define HCFG_FSLSSUPP BIT(2)
705 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
706 #define HCFG_FSLSPCLKSEL_SHIFT 0
707 #define HCFG_FSLSPCLKSEL_30_60_MHZ 0
708 #define HCFG_FSLSPCLKSEL_48_MHZ 1
709 #define HCFG_FSLSPCLKSEL_6_MHZ 2
711 #define HFIR HSOTG_REG(0x0404)
712 #define HFIR_FRINT_MASK (0xffff << 0)
713 #define HFIR_FRINT_SHIFT 0
714 #define HFIR_RLDCTRL BIT(16)
716 #define HFNUM HSOTG_REG(0x0408)
717 #define HFNUM_FRREM_MASK (0xffff << 16)
718 #define HFNUM_FRREM_SHIFT 16
719 #define HFNUM_FRNUM_MASK (0xffff << 0)
720 #define HFNUM_FRNUM_SHIFT 0
721 #define HFNUM_MAX_FRNUM 0x3fff
723 #define HPTXSTS HSOTG_REG(0x0410)
724 #define TXSTS_QTOP_ODD BIT(31)
725 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
726 #define TXSTS_QTOP_CHNEP_SHIFT 27
727 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
728 #define TXSTS_QTOP_TOKEN_SHIFT 25
729 #define TXSTS_QTOP_TERMINATE BIT(24)
730 #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
731 #define TXSTS_QSPCAVAIL_SHIFT 16
732 #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
733 #define TXSTS_FSPCAVAIL_SHIFT 0
735 #define HAINT HSOTG_REG(0x0414)
736 #define HAINTMSK HSOTG_REG(0x0418)
737 #define HFLBADDR HSOTG_REG(0x041c)
739 #define HPRT0 HSOTG_REG(0x0440)
740 #define HPRT0_SPD_MASK (0x3 << 17)
741 #define HPRT0_SPD_SHIFT 17
742 #define HPRT0_SPD_HIGH_SPEED 0
743 #define HPRT0_SPD_FULL_SPEED 1
744 #define HPRT0_SPD_LOW_SPEED 2
745 #define HPRT0_TSTCTL_MASK (0xf << 13)
746 #define HPRT0_TSTCTL_SHIFT 13
747 #define HPRT0_PWR BIT(12)
748 #define HPRT0_LNSTS_MASK (0x3 << 10)
749 #define HPRT0_LNSTS_SHIFT 10
750 #define HPRT0_RST BIT(8)
751 #define HPRT0_SUSP BIT(7)
752 #define HPRT0_RES BIT(6)
753 #define HPRT0_OVRCURRCHG BIT(5)
754 #define HPRT0_OVRCURRACT BIT(4)
755 #define HPRT0_ENACHG BIT(3)
756 #define HPRT0_ENA BIT(2)
757 #define HPRT0_CONNDET BIT(1)
758 #define HPRT0_CONNSTS BIT(0)
760 #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
761 #define HCCHAR_CHENA BIT(31)
762 #define HCCHAR_CHDIS BIT(30)
763 #define HCCHAR_ODDFRM BIT(29)
764 #define HCCHAR_DEVADDR_MASK (0x7f << 22)
765 #define HCCHAR_DEVADDR_SHIFT 22
766 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
767 #define HCCHAR_MULTICNT_SHIFT 20
768 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
769 #define HCCHAR_EPTYPE_SHIFT 18
770 #define HCCHAR_LSPDDEV BIT(17)
771 #define HCCHAR_EPDIR BIT(15)
772 #define HCCHAR_EPNUM_MASK (0xf << 11)
773 #define HCCHAR_EPNUM_SHIFT 11
774 #define HCCHAR_MPS_MASK (0x7ff << 0)
775 #define HCCHAR_MPS_SHIFT 0
777 #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
778 #define HCSPLT_SPLTENA BIT(31)
779 #define HCSPLT_COMPSPLT BIT(16)
780 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
781 #define HCSPLT_XACTPOS_SHIFT 14
782 #define HCSPLT_XACTPOS_MID 0
783 #define HCSPLT_XACTPOS_END 1
784 #define HCSPLT_XACTPOS_BEGIN 2
785 #define HCSPLT_XACTPOS_ALL 3
786 #define HCSPLT_HUBADDR_MASK (0x7f << 7)
787 #define HCSPLT_HUBADDR_SHIFT 7
788 #define HCSPLT_PRTADDR_MASK (0x7f << 0)
789 #define HCSPLT_PRTADDR_SHIFT 0
791 #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
792 #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
793 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
794 #define HCINTMSK_FRM_LIST_ROLL BIT(13)
795 #define HCINTMSK_XCS_XACT BIT(12)
796 #define HCINTMSK_BNA BIT(11)
797 #define HCINTMSK_DATATGLERR BIT(10)
798 #define HCINTMSK_FRMOVRUN BIT(9)
799 #define HCINTMSK_BBLERR BIT(8)
800 #define HCINTMSK_XACTERR BIT(7)
801 #define HCINTMSK_NYET BIT(6)
802 #define HCINTMSK_ACK BIT(5)
803 #define HCINTMSK_NAK BIT(4)
804 #define HCINTMSK_STALL BIT(3)
805 #define HCINTMSK_AHBERR BIT(2)
806 #define HCINTMSK_CHHLTD BIT(1)
807 #define HCINTMSK_XFERCOMPL BIT(0)
809 #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
810 #define TSIZ_DOPNG BIT(31)
811 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
812 #define TSIZ_SC_MC_PID_SHIFT 29
813 #define TSIZ_SC_MC_PID_DATA0 0
814 #define TSIZ_SC_MC_PID_DATA2 1
815 #define TSIZ_SC_MC_PID_DATA1 2
816 #define TSIZ_SC_MC_PID_MDATA 3
817 #define TSIZ_SC_MC_PID_SETUP 3
818 #define TSIZ_PKTCNT_MASK (0x3ff << 19)
819 #define TSIZ_PKTCNT_SHIFT 19
820 #define TSIZ_NTD_MASK (0xff << 8)
821 #define TSIZ_NTD_SHIFT 8
822 #define TSIZ_SCHINFO_MASK (0xff << 0)
823 #define TSIZ_SCHINFO_SHIFT 0
824 #define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
825 #define TSIZ_XFERSIZE_SHIFT 0
827 #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
829 #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
831 #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
834 * struct dwc2_dma_desc - DMA descriptor structure,
835 * used for both host and gadget modes
837 * @status: DMA descriptor status quadlet
838 * @buf: DMA descriptor data buffer pointer
840 * DMA Descriptor structure contains two quadlets:
841 * Status quadlet and Data buffer pointer.
843 struct dwc2_dma_desc {
848 /* Host Mode DMA descriptor status quadlet */
850 #define HOST_DMA_A BIT(31)
851 #define HOST_DMA_STS_MASK (0x3 << 28)
852 #define HOST_DMA_STS_SHIFT 28
853 #define HOST_DMA_STS_PKTERR BIT(28)
854 #define HOST_DMA_EOL BIT(26)
855 #define HOST_DMA_IOC BIT(25)
856 #define HOST_DMA_SUP BIT(24)
857 #define HOST_DMA_ALT_QTD BIT(23)
858 #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
859 #define HOST_DMA_QTD_OFFSET_SHIFT 17
860 #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
861 #define HOST_DMA_ISOC_NBYTES_SHIFT 0
862 #define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
863 #define HOST_DMA_NBYTES_SHIFT 0
864 #define HOST_DMA_NBYTES_LIMIT 131071
866 /* Device Mode DMA descriptor status quadlet */
868 #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
869 #define DEV_DMA_BUFF_STS_SHIFT 30
870 #define DEV_DMA_BUFF_STS_HREADY 0
871 #define DEV_DMA_BUFF_STS_DMABUSY 1
872 #define DEV_DMA_BUFF_STS_DMADONE 2
873 #define DEV_DMA_BUFF_STS_HBUSY 3
874 #define DEV_DMA_STS_MASK (0x3 << 28)
875 #define DEV_DMA_STS_SHIFT 28
876 #define DEV_DMA_STS_SUCC 0
877 #define DEV_DMA_STS_BUFF_FLUSH 1
878 #define DEV_DMA_STS_BUFF_ERR 3
879 #define DEV_DMA_L BIT(27)
880 #define DEV_DMA_SHORT BIT(26)
881 #define DEV_DMA_IOC BIT(25)
882 #define DEV_DMA_SR BIT(24)
883 #define DEV_DMA_MTRF BIT(23)
884 #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
885 #define DEV_DMA_ISOC_PID_SHIFT 23
886 #define DEV_DMA_ISOC_PID_DATA0 0
887 #define DEV_DMA_ISOC_PID_DATA2 1
888 #define DEV_DMA_ISOC_PID_DATA1 2
889 #define DEV_DMA_ISOC_PID_MDATA 3
890 #define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
891 #define DEV_DMA_ISOC_FRNUM_SHIFT 12
892 #define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
893 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
894 #define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
895 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
896 #define DEV_DMA_ISOC_NBYTES_SHIFT 0
897 #define DEV_DMA_NBYTES_MASK (0xffff << 0)
898 #define DEV_DMA_NBYTES_SHIFT 0
899 #define DEV_DMA_NBYTES_LIMIT 0xffff
901 #define MAX_DMA_DESC_NUM_GENERIC 64
902 #define MAX_DMA_DESC_NUM_HS_ISOC 256
904 #endif /* __DWC2_HW_H__ */
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