1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the core HCD code, and implements the Linux hc_driver
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
80 /* Clear any pending interrupts */
81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
97 dwc2_writel(hsotg, intmsk, GINTMSK);
100 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
102 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
104 switch (hsotg->hw_params.arch) {
105 case GHWCFG2_EXT_DMA_ARCH:
106 dev_err(hsotg->dev, "External DMA Mode not supported\n");
109 case GHWCFG2_INT_DMA_ARCH:
110 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
111 if (hsotg->params.ahbcfg != -1) {
112 ahbcfg &= GAHBCFG_CTRL_MASK;
113 ahbcfg |= hsotg->params.ahbcfg &
118 case GHWCFG2_SLAVE_ONLY_ARCH:
120 dev_dbg(hsotg->dev, "Slave Only Mode\n");
124 if (hsotg->params.host_dma)
125 ahbcfg |= GAHBCFG_DMA_EN;
127 hsotg->params.dma_desc_enable = false;
129 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
134 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
141 switch (hsotg->hw_params.op_mode) {
142 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
143 if (hsotg->params.otg_cap ==
144 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
145 usbcfg |= GUSBCFG_HNPCAP;
146 if (hsotg->params.otg_cap !=
147 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
148 usbcfg |= GUSBCFG_SRPCAP;
151 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
152 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
153 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
154 if (hsotg->params.otg_cap !=
155 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
156 usbcfg |= GUSBCFG_SRPCAP;
159 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
160 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
161 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
166 dwc2_writel(hsotg, usbcfg, GUSBCFG);
169 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
171 if (hsotg->vbus_supply)
172 return regulator_enable(hsotg->vbus_supply);
177 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
179 if (hsotg->vbus_supply)
180 return regulator_disable(hsotg->vbus_supply);
186 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
188 * @hsotg: Programming view of DWC_otg controller
190 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
194 dev_dbg(hsotg->dev, "%s()\n", __func__);
196 /* Disable all interrupts */
197 dwc2_writel(hsotg, 0, GINTMSK);
198 dwc2_writel(hsotg, 0, HAINTMSK);
200 /* Enable the common interrupts */
201 dwc2_enable_common_interrupts(hsotg);
203 /* Enable host mode interrupts without disturbing common interrupts */
204 intmsk = dwc2_readl(hsotg, GINTMSK);
205 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
206 dwc2_writel(hsotg, intmsk, GINTMSK);
210 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
212 * @hsotg: Programming view of DWC_otg controller
214 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
216 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
218 /* Disable host mode interrupts without disturbing common interrupts */
219 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
220 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
221 dwc2_writel(hsotg, intmsk, GINTMSK);
225 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
226 * For system that have a total fifo depth that is smaller than the default
229 * @hsotg: Programming view of DWC_otg controller
231 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
233 struct dwc2_core_params *params = &hsotg->params;
234 struct dwc2_hw_params *hw = &hsotg->hw_params;
235 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
237 total_fifo_size = hw->total_fifo_size;
238 rxfsiz = params->host_rx_fifo_size;
239 nptxfsiz = params->host_nperio_tx_fifo_size;
240 ptxfsiz = params->host_perio_tx_fifo_size;
243 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
244 * allocation with support for high bandwidth endpoints. Synopsys
245 * defines MPS(Max Packet size) for a periodic EP=1024, and for
246 * non-periodic as 512.
248 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
250 * For Buffer DMA mode/Scatter Gather DMA mode
251 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
252 * with n = number of host channel.
253 * 2 * ((1024/4) + 2) = 516
255 rxfsiz = 516 + hw->host_channels;
258 * min non-periodic tx fifo depth
259 * 2 * (largest non-periodic USB packet used / 4)
265 * min periodic tx fifo depth
266 * (largest packet size*MC)/4
271 params->host_rx_fifo_size = rxfsiz;
272 params->host_nperio_tx_fifo_size = nptxfsiz;
273 params->host_perio_tx_fifo_size = ptxfsiz;
277 * If the summation of RX, NPTX and PTX fifo sizes is still
278 * bigger than the total_fifo_size, then we have a problem.
280 * We won't be able to allocate as many endpoints. Right now,
281 * we're just printing an error message, but ideally this FIFO
282 * allocation algorithm would be improved in the future.
284 * FIXME improve this FIFO allocation algorithm.
286 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
287 dev_err(hsotg->dev, "invalid fifo sizes\n");
290 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
292 struct dwc2_core_params *params = &hsotg->params;
293 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
295 if (!params->enable_dynamic_fifo)
298 dwc2_calculate_dynamic_fifo(hsotg);
301 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
302 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
303 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
304 grxfsiz |= params->host_rx_fifo_size <<
305 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
306 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
307 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
308 dwc2_readl(hsotg, GRXFSIZ));
310 /* Non-periodic Tx FIFO */
311 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
312 dwc2_readl(hsotg, GNPTXFSIZ));
313 nptxfsiz = params->host_nperio_tx_fifo_size <<
314 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
315 nptxfsiz |= params->host_rx_fifo_size <<
316 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
317 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
318 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
319 dwc2_readl(hsotg, GNPTXFSIZ));
321 /* Periodic Tx FIFO */
322 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
323 dwc2_readl(hsotg, HPTXFSIZ));
324 hptxfsiz = params->host_perio_tx_fifo_size <<
325 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
326 hptxfsiz |= (params->host_rx_fifo_size +
327 params->host_nperio_tx_fifo_size) <<
328 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
329 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
330 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
331 dwc2_readl(hsotg, HPTXFSIZ));
333 if (hsotg->params.en_multiple_tx_fifo &&
334 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
336 * This feature was implemented in 2.91a version
337 * Global DFIFOCFG calculation for Host mode -
338 * include RxFIFO, NPTXFIFO and HPTXFIFO
340 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
341 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
342 dfifocfg |= (params->host_rx_fifo_size +
343 params->host_nperio_tx_fifo_size +
344 params->host_perio_tx_fifo_size) <<
345 GDFIFOCFG_EPINFOBASE_SHIFT &
346 GDFIFOCFG_EPINFOBASE_MASK;
347 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
352 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
353 * the HFIR register according to PHY type and speed
355 * @hsotg: Programming view of DWC_otg controller
357 * NOTE: The caller can modify the value of the HFIR register only after the
358 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
361 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
365 int clock = 60; /* default value */
367 usbcfg = dwc2_readl(hsotg, GUSBCFG);
368 hprt0 = dwc2_readl(hsotg, HPRT0);
370 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
371 !(usbcfg & GUSBCFG_PHYIF16))
373 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
374 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
376 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
377 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
379 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
380 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
382 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
383 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
385 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
386 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
388 if ((usbcfg & GUSBCFG_PHYSEL) &&
389 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
392 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
393 /* High speed case */
394 return 125 * clock - 1;
397 return 1000 * clock - 1;
401 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
404 * @hsotg: Programming view of DWC_otg controller
405 * @dest: Destination buffer for the packet
406 * @bytes: Number of bytes to copy to the destination
408 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
410 u32 *data_buf = (u32 *)dest;
411 int word_count = (bytes + 3) / 4;
415 * Todo: Account for the case where dest is not dword aligned. This
416 * requires reading data from the FIFO into a u32 temp buffer, then
417 * moving it into the data buffer.
420 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
422 for (i = 0; i < word_count; i++, data_buf++)
423 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
427 * dwc2_dump_channel_info() - Prints the state of a host channel
429 * @hsotg: Programming view of DWC_otg controller
430 * @chan: Pointer to the channel to dump
432 * Must be called with interrupt disabled and spinlock held
434 * NOTE: This function will be removed once the peripheral controller code
435 * is integrated and the driver is stable
437 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
438 struct dwc2_host_chan *chan)
441 int num_channels = hsotg->params.host_channels;
452 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
453 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
454 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
455 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
457 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
458 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
460 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
462 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
463 chan->dev_addr, chan->ep_num, chan->ep_is_in);
464 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
465 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
466 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
467 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
468 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
469 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
470 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
471 (unsigned long)chan->xfer_dma);
472 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
473 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
474 dev_dbg(hsotg->dev, " NP inactive sched:\n");
475 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
477 dev_dbg(hsotg->dev, " %p\n", qh);
478 dev_dbg(hsotg->dev, " NP waiting sched:\n");
479 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
481 dev_dbg(hsotg->dev, " %p\n", qh);
482 dev_dbg(hsotg->dev, " NP active sched:\n");
483 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
485 dev_dbg(hsotg->dev, " %p\n", qh);
486 dev_dbg(hsotg->dev, " Channels:\n");
487 for (i = 0; i < num_channels; i++) {
488 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
490 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
492 #endif /* VERBOSE_DEBUG */
495 static int _dwc2_hcd_start(struct usb_hcd *hcd);
497 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
499 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
501 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
502 _dwc2_hcd_start(hcd);
505 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
507 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
509 hcd->self.is_b_host = 0;
512 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
513 int *hub_addr, int *hub_port)
515 struct urb *urb = context;
518 *hub_addr = urb->dev->tt->hub->devnum;
521 *hub_port = urb->dev->ttport;
525 * =========================================================================
526 * Low Level Host Channel Access Functions
527 * =========================================================================
530 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
531 struct dwc2_host_chan *chan)
533 u32 hcintmsk = HCINTMSK_CHHLTD;
535 switch (chan->ep_type) {
536 case USB_ENDPOINT_XFER_CONTROL:
537 case USB_ENDPOINT_XFER_BULK:
538 dev_vdbg(hsotg->dev, "control/bulk\n");
539 hcintmsk |= HCINTMSK_XFERCOMPL;
540 hcintmsk |= HCINTMSK_STALL;
541 hcintmsk |= HCINTMSK_XACTERR;
542 hcintmsk |= HCINTMSK_DATATGLERR;
543 if (chan->ep_is_in) {
544 hcintmsk |= HCINTMSK_BBLERR;
546 hcintmsk |= HCINTMSK_NAK;
547 hcintmsk |= HCINTMSK_NYET;
549 hcintmsk |= HCINTMSK_ACK;
552 if (chan->do_split) {
553 hcintmsk |= HCINTMSK_NAK;
554 if (chan->complete_split)
555 hcintmsk |= HCINTMSK_NYET;
557 hcintmsk |= HCINTMSK_ACK;
560 if (chan->error_state)
561 hcintmsk |= HCINTMSK_ACK;
564 case USB_ENDPOINT_XFER_INT:
566 dev_vdbg(hsotg->dev, "intr\n");
567 hcintmsk |= HCINTMSK_XFERCOMPL;
568 hcintmsk |= HCINTMSK_NAK;
569 hcintmsk |= HCINTMSK_STALL;
570 hcintmsk |= HCINTMSK_XACTERR;
571 hcintmsk |= HCINTMSK_DATATGLERR;
572 hcintmsk |= HCINTMSK_FRMOVRUN;
575 hcintmsk |= HCINTMSK_BBLERR;
576 if (chan->error_state)
577 hcintmsk |= HCINTMSK_ACK;
578 if (chan->do_split) {
579 if (chan->complete_split)
580 hcintmsk |= HCINTMSK_NYET;
582 hcintmsk |= HCINTMSK_ACK;
586 case USB_ENDPOINT_XFER_ISOC:
588 dev_vdbg(hsotg->dev, "isoc\n");
589 hcintmsk |= HCINTMSK_XFERCOMPL;
590 hcintmsk |= HCINTMSK_FRMOVRUN;
591 hcintmsk |= HCINTMSK_ACK;
593 if (chan->ep_is_in) {
594 hcintmsk |= HCINTMSK_XACTERR;
595 hcintmsk |= HCINTMSK_BBLERR;
599 dev_err(hsotg->dev, "## Unknown EP type ##\n");
603 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
605 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
608 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
609 struct dwc2_host_chan *chan)
611 u32 hcintmsk = HCINTMSK_CHHLTD;
614 * For Descriptor DMA mode core halts the channel on AHB error.
615 * Interrupt is not required.
617 if (!hsotg->params.dma_desc_enable) {
619 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
620 hcintmsk |= HCINTMSK_AHBERR;
623 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
624 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
625 hcintmsk |= HCINTMSK_XFERCOMPL;
628 if (chan->error_state && !chan->do_split &&
629 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
631 dev_vdbg(hsotg->dev, "setting ACK\n");
632 hcintmsk |= HCINTMSK_ACK;
633 if (chan->ep_is_in) {
634 hcintmsk |= HCINTMSK_DATATGLERR;
635 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
636 hcintmsk |= HCINTMSK_NAK;
640 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
642 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
645 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
646 struct dwc2_host_chan *chan)
650 if (hsotg->params.host_dma) {
652 dev_vdbg(hsotg->dev, "DMA enabled\n");
653 dwc2_hc_enable_dma_ints(hsotg, chan);
656 dev_vdbg(hsotg->dev, "DMA disabled\n");
657 dwc2_hc_enable_slave_ints(hsotg, chan);
660 /* Enable the top level host channel interrupt */
661 intmsk = dwc2_readl(hsotg, HAINTMSK);
662 intmsk |= 1 << chan->hc_num;
663 dwc2_writel(hsotg, intmsk, HAINTMSK);
665 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
667 /* Make sure host channel interrupts are enabled */
668 intmsk = dwc2_readl(hsotg, GINTMSK);
669 intmsk |= GINTSTS_HCHINT;
670 dwc2_writel(hsotg, intmsk, GINTMSK);
672 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
676 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
677 * a specific endpoint
679 * @hsotg: Programming view of DWC_otg controller
680 * @chan: Information needed to initialize the host channel
682 * The HCCHARn register is set up with the characteristics specified in chan.
683 * Host channel interrupts that may need to be serviced while this transfer is
684 * in progress are enabled.
686 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
688 u8 hc_num = chan->hc_num;
694 dev_vdbg(hsotg->dev, "%s()\n", __func__);
696 /* Clear old interrupt conditions for this host channel */
697 hcintmsk = 0xffffffff;
698 hcintmsk &= ~HCINTMSK_RESERVED14_31;
699 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
701 /* Enable channel interrupts required for this transfer */
702 dwc2_hc_enable_ints(hsotg, chan);
705 * Program the HCCHARn register with the endpoint characteristics for
706 * the current transfer
708 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
709 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
711 hcchar |= HCCHAR_EPDIR;
712 if (chan->speed == USB_SPEED_LOW)
713 hcchar |= HCCHAR_LSPDDEV;
714 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
715 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
716 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
718 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
721 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
723 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
725 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
727 dev_vdbg(hsotg->dev, " Is In: %d\n",
729 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
730 chan->speed == USB_SPEED_LOW);
731 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
733 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
737 /* Program the HCSPLT register for SPLITs */
738 if (chan->do_split) {
741 "Programming HC %d with split --> %s\n",
743 chan->complete_split ? "CSPLIT" : "SSPLIT");
744 if (chan->complete_split)
745 hcsplt |= HCSPLT_COMPSPLT;
746 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
748 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
750 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
753 dev_vdbg(hsotg->dev, " comp split %d\n",
754 chan->complete_split);
755 dev_vdbg(hsotg->dev, " xact pos %d\n",
757 dev_vdbg(hsotg->dev, " hub addr %d\n",
759 dev_vdbg(hsotg->dev, " hub port %d\n",
761 dev_vdbg(hsotg->dev, " is_in %d\n",
763 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
765 dev_vdbg(hsotg->dev, " xferlen %d\n",
770 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
774 * dwc2_hc_halt() - Attempts to halt a host channel
776 * @hsotg: Controller register interface
777 * @chan: Host channel to halt
778 * @halt_status: Reason for halting the channel
780 * This function should only be called in Slave mode or to abort a transfer in
781 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
782 * controller halts the channel when the transfer is complete or a condition
783 * occurs that requires application intervention.
785 * In slave mode, checks for a free request queue entry, then sets the Channel
786 * Enable and Channel Disable bits of the Host Channel Characteristics
787 * register of the specified channel to intiate the halt. If there is no free
788 * request queue entry, sets only the Channel Disable bit of the HCCHARn
789 * register to flush requests for this channel. In the latter case, sets a
790 * flag to indicate that the host channel needs to be halted when a request
791 * queue slot is open.
793 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
794 * HCCHARn register. The controller ensures there is space in the request
795 * queue before submitting the halt request.
797 * Some time may elapse before the core flushes any posted requests for this
798 * host channel and halts. The Channel Halted interrupt handler completes the
799 * deactivation of the host channel.
801 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
802 enum dwc2_halt_status halt_status)
804 u32 nptxsts, hptxsts, hcchar;
807 dev_vdbg(hsotg->dev, "%s()\n", __func__);
810 * In buffer DMA or external DMA mode channel can't be halted
811 * for non-split periodic channels. At the end of the next
812 * uframe/frame (in the worst case), the core generates a channel
813 * halted and disables the channel automatically.
815 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
816 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
817 if (!chan->do_split &&
818 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
819 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
820 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
826 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
827 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
829 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
830 halt_status == DWC2_HC_XFER_AHB_ERR) {
832 * Disable all channel interrupts except Ch Halted. The QTD
833 * and QH state associated with this transfer has been cleared
834 * (in the case of URB_DEQUEUE), so the channel needs to be
835 * shut down carefully to prevent crashes.
837 u32 hcintmsk = HCINTMSK_CHHLTD;
839 dev_vdbg(hsotg->dev, "dequeue/error\n");
840 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
843 * Make sure no other interrupts besides halt are currently
844 * pending. Handling another interrupt could cause a crash due
845 * to the QTD and QH state.
847 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
850 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
851 * even if the channel was already halted for some other
854 chan->halt_status = halt_status;
856 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
857 if (!(hcchar & HCCHAR_CHENA)) {
859 * The channel is either already halted or it hasn't
860 * started yet. In DMA mode, the transfer may halt if
861 * it finishes normally or a condition occurs that
862 * requires driver intervention. Don't want to halt
863 * the channel again. In either Slave or DMA mode,
864 * it's possible that the transfer has been assigned
865 * to a channel, but not started yet when an URB is
866 * dequeued. Don't want to halt a channel that hasn't
872 if (chan->halt_pending) {
874 * A halt has already been issued for this channel. This might
875 * happen when a transfer is aborted by a higher level in
879 "*** %s: Channel %d, chan->halt_pending already set ***\n",
880 __func__, chan->hc_num);
884 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
886 /* No need to set the bit in DDMA for disabling the channel */
887 /* TODO check it everywhere channel is disabled */
888 if (!hsotg->params.dma_desc_enable) {
890 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
891 hcchar |= HCCHAR_CHENA;
894 dev_dbg(hsotg->dev, "desc DMA enabled\n");
896 hcchar |= HCCHAR_CHDIS;
898 if (!hsotg->params.host_dma) {
900 dev_vdbg(hsotg->dev, "DMA not enabled\n");
901 hcchar |= HCCHAR_CHENA;
903 /* Check for space in the request queue to issue the halt */
904 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
905 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
906 dev_vdbg(hsotg->dev, "control/bulk\n");
907 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
908 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
909 dev_vdbg(hsotg->dev, "Disabling channel\n");
910 hcchar &= ~HCCHAR_CHENA;
914 dev_vdbg(hsotg->dev, "isoc/intr\n");
915 hptxsts = dwc2_readl(hsotg, HPTXSTS);
916 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
917 hsotg->queuing_high_bandwidth) {
919 dev_vdbg(hsotg->dev, "Disabling channel\n");
920 hcchar &= ~HCCHAR_CHENA;
925 dev_vdbg(hsotg->dev, "DMA enabled\n");
928 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
929 chan->halt_status = halt_status;
931 if (hcchar & HCCHAR_CHENA) {
933 dev_vdbg(hsotg->dev, "Channel enabled\n");
934 chan->halt_pending = 1;
935 chan->halt_on_queue = 0;
938 dev_vdbg(hsotg->dev, "Channel disabled\n");
939 chan->halt_on_queue = 1;
943 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
945 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
947 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
949 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
950 chan->halt_on_queue);
951 dev_vdbg(hsotg->dev, " halt_status: %d\n",
957 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
959 * @hsotg: Programming view of DWC_otg controller
960 * @chan: Identifies the host channel to clean up
962 * This function is normally called after a transfer is done and the host
963 * channel is being released
965 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
969 chan->xfer_started = 0;
971 list_del_init(&chan->split_order_list_entry);
974 * Clear channel interrupt enables and any unhandled channel interrupt
977 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
978 hcintmsk = 0xffffffff;
979 hcintmsk &= ~HCINTMSK_RESERVED14_31;
980 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
984 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
985 * which frame a periodic transfer should occur
987 * @hsotg: Programming view of DWC_otg controller
988 * @chan: Identifies the host channel to set up and its properties
989 * @hcchar: Current value of the HCCHAR register for the specified host channel
991 * This function has no effect on non-periodic transfers
993 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
994 struct dwc2_host_chan *chan, u32 *hcchar)
996 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
997 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1007 * Try to figure out if we're an even or odd frame. If we set
1008 * even and the current frame number is even the the transfer
1009 * will happen immediately. Similar if both are odd. If one is
1010 * even and the other is odd then the transfer will happen when
1011 * the frame number ticks.
1013 * There's a bit of a balancing act to get this right.
1014 * Sometimes we may want to send data in the current frame (AK
1015 * right away). We might want to do this if the frame number
1016 * _just_ ticked, but we might also want to do this in order
1017 * to continue a split transaction that happened late in a
1018 * microframe (so we didn't know to queue the next transfer
1019 * until the frame number had ticked). The problem is that we
1020 * need a lot of knowledge to know if there's actually still
1021 * time to send things or if it would be better to wait until
1024 * We can look at how much time is left in the current frame
1025 * and make a guess about whether we'll have time to transfer.
1029 /* Get speed host is running at */
1030 host_speed = (chan->speed != USB_SPEED_HIGH &&
1031 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1033 /* See how many bytes are in the periodic FIFO right now */
1034 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1035 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1036 bytes_in_fifo = sizeof(u32) *
1037 (hsotg->params.host_perio_tx_fifo_size -
1041 * Roughly estimate bus time for everything in the periodic
1042 * queue + our new transfer. This is "rough" because we're
1043 * using a function that makes takes into account IN/OUT
1044 * and INT/ISO and we're just slamming in one value for all
1045 * transfers. This should be an over-estimate and that should
1046 * be OK, but we can probably tighten it.
1048 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1049 chan->xfer_len + bytes_in_fifo);
1050 xfer_us = NS_TO_US(xfer_ns);
1052 /* See what frame number we'll be at by the time we finish */
1053 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1055 /* This is when we were scheduled to be on the wire */
1056 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1059 * If we'd finish _after_ the frame we're scheduled in then
1060 * it's hopeless. Just schedule right away and hope for the
1061 * best. Note that it _might_ be wise to call back into the
1062 * scheduler to pick a better frame, but this is better than
1065 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1066 dwc2_sch_vdbg(hsotg,
1067 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1068 chan->qh, wire_frame, frame_number,
1069 dwc2_frame_num_dec(frame_number,
1071 wire_frame = frame_number;
1074 * We picked a different frame number; communicate this
1075 * back to the scheduler so it doesn't try to schedule
1076 * another in the same frame.
1078 * Remember that next_active_frame is 1 before the wire
1081 chan->qh->next_active_frame =
1082 dwc2_frame_num_dec(frame_number, 1);
1086 *hcchar |= HCCHAR_ODDFRM;
1088 *hcchar &= ~HCCHAR_ODDFRM;
1092 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1094 /* Set up the initial PID for the transfer */
1095 if (chan->speed == USB_SPEED_HIGH) {
1096 if (chan->ep_is_in) {
1097 if (chan->multi_count == 1)
1098 chan->data_pid_start = DWC2_HC_PID_DATA0;
1099 else if (chan->multi_count == 2)
1100 chan->data_pid_start = DWC2_HC_PID_DATA1;
1102 chan->data_pid_start = DWC2_HC_PID_DATA2;
1104 if (chan->multi_count == 1)
1105 chan->data_pid_start = DWC2_HC_PID_DATA0;
1107 chan->data_pid_start = DWC2_HC_PID_MDATA;
1110 chan->data_pid_start = DWC2_HC_PID_DATA0;
1115 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1118 * @hsotg: Programming view of DWC_otg controller
1119 * @chan: Information needed to initialize the host channel
1121 * This function should only be called in Slave mode. For a channel associated
1122 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1123 * associated with a periodic EP, the periodic Tx FIFO is written.
1125 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1126 * the number of bytes written to the Tx FIFO.
1128 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1129 struct dwc2_host_chan *chan)
1132 u32 remaining_count;
1135 u32 *data_buf = (u32 *)chan->xfer_buf;
1138 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1140 remaining_count = chan->xfer_len - chan->xfer_count;
1141 if (remaining_count > chan->max_packet)
1142 byte_count = chan->max_packet;
1144 byte_count = remaining_count;
1146 dword_count = (byte_count + 3) / 4;
1148 if (((unsigned long)data_buf & 0x3) == 0) {
1149 /* xfer_buf is DWORD aligned */
1150 for (i = 0; i < dword_count; i++, data_buf++)
1151 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1153 /* xfer_buf is not DWORD aligned */
1154 for (i = 0; i < dword_count; i++, data_buf++) {
1155 u32 data = data_buf[0] | data_buf[1] << 8 |
1156 data_buf[2] << 16 | data_buf[3] << 24;
1157 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1161 chan->xfer_count += byte_count;
1162 chan->xfer_buf += byte_count;
1166 * dwc2_hc_do_ping() - Starts a PING transfer
1168 * @hsotg: Programming view of DWC_otg controller
1169 * @chan: Information needed to initialize the host channel
1171 * This function should only be called in Slave mode. The Do Ping bit is set in
1172 * the HCTSIZ register, then the channel is enabled.
1174 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1175 struct dwc2_host_chan *chan)
1181 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1184 hctsiz = TSIZ_DOPNG;
1185 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1186 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1188 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1189 hcchar |= HCCHAR_CHENA;
1190 hcchar &= ~HCCHAR_CHDIS;
1191 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1195 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1196 * channel and starts the transfer
1198 * @hsotg: Programming view of DWC_otg controller
1199 * @chan: Information needed to initialize the host channel. The xfer_len value
1200 * may be reduced to accommodate the max widths of the XferSize and
1201 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1202 * changed to reflect the final xfer_len value.
1204 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1205 * the caller must ensure that there is sufficient space in the request queue
1208 * For an OUT transfer in Slave mode, it loads a data packet into the
1209 * appropriate FIFO. If necessary, additional data packets are loaded in the
1212 * For an IN transfer in Slave mode, a data packet is requested. The data
1213 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1214 * additional data packets are requested in the Host ISR.
1216 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1217 * register along with a packet count of 1 and the channel is enabled. This
1218 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1219 * simply set to 0 since no data transfer occurs in this case.
1221 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1222 * all the information required to perform the subsequent data transfer. In
1223 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1224 * controller performs the entire PING protocol, then starts the data
1227 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1228 struct dwc2_host_chan *chan)
1230 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1231 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1238 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1240 if (chan->do_ping) {
1241 if (!hsotg->params.host_dma) {
1243 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1244 dwc2_hc_do_ping(hsotg, chan);
1245 chan->xfer_started = 1;
1250 dev_vdbg(hsotg->dev, "ping, DMA\n");
1252 hctsiz |= TSIZ_DOPNG;
1255 if (chan->do_split) {
1257 dev_vdbg(hsotg->dev, "split\n");
1260 if (chan->complete_split && !chan->ep_is_in)
1262 * For CSPLIT OUT Transfer, set the size to 0 so the
1263 * core doesn't expect any data written to the FIFO
1266 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1267 chan->xfer_len = chan->max_packet;
1268 else if (!chan->ep_is_in && chan->xfer_len > 188)
1269 chan->xfer_len = 188;
1271 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1274 /* For split set ec_mc for immediate retries */
1275 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1276 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1282 dev_vdbg(hsotg->dev, "no split\n");
1284 * Ensure that the transfer length and packet count will fit
1285 * in the widths allocated for them in the HCTSIZn register
1287 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1288 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1290 * Make sure the transfer size is no larger than one
1291 * (micro)frame's worth of data. (A check was done
1292 * when the periodic transfer was accepted to ensure
1293 * that a (micro)frame's worth of data can be
1294 * programmed into a channel.)
1296 u32 max_periodic_len =
1297 chan->multi_count * chan->max_packet;
1299 if (chan->xfer_len > max_periodic_len)
1300 chan->xfer_len = max_periodic_len;
1301 } else if (chan->xfer_len > max_hc_xfer_size) {
1303 * Make sure that xfer_len is a multiple of max packet
1307 max_hc_xfer_size - chan->max_packet + 1;
1310 if (chan->xfer_len > 0) {
1311 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1313 if (num_packets > max_hc_pkt_count) {
1314 num_packets = max_hc_pkt_count;
1315 chan->xfer_len = num_packets * chan->max_packet;
1318 /* Need 1 packet for transfer length of 0 */
1324 * Always program an integral # of max packets for IN
1327 chan->xfer_len = num_packets * chan->max_packet;
1329 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1330 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1332 * Make sure that the multi_count field matches the
1333 * actual transfer length
1335 chan->multi_count = num_packets;
1337 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1338 dwc2_set_pid_isoc(chan);
1340 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1343 /* The ec_mc gets the multi_count for non-split */
1344 ec_mc = chan->multi_count;
1347 chan->start_pkt_count = num_packets;
1348 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1349 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1350 TSIZ_SC_MC_PID_MASK;
1351 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1353 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1354 hctsiz, chan->hc_num);
1356 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1358 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1359 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1360 TSIZ_XFERSIZE_SHIFT);
1361 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1362 (hctsiz & TSIZ_PKTCNT_MASK) >>
1364 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1365 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1366 TSIZ_SC_MC_PID_SHIFT);
1369 if (hsotg->params.host_dma) {
1370 dma_addr_t dma_addr;
1372 if (chan->align_buf) {
1374 dev_vdbg(hsotg->dev, "align_buf\n");
1375 dma_addr = chan->align_buf;
1377 dma_addr = chan->xfer_dma;
1379 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1382 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1383 (unsigned long)dma_addr, chan->hc_num);
1386 /* Start the split */
1387 if (chan->do_split) {
1388 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1390 hcsplt |= HCSPLT_SPLTENA;
1391 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1394 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1395 hcchar &= ~HCCHAR_MULTICNT_MASK;
1396 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1397 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1399 if (hcchar & HCCHAR_CHDIS)
1400 dev_warn(hsotg->dev,
1401 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1402 __func__, chan->hc_num, hcchar);
1404 /* Set host channel enable after all other setup is complete */
1405 hcchar |= HCCHAR_CHENA;
1406 hcchar &= ~HCCHAR_CHDIS;
1409 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1410 (hcchar & HCCHAR_MULTICNT_MASK) >>
1411 HCCHAR_MULTICNT_SHIFT);
1413 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1415 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1418 chan->xfer_started = 1;
1421 if (!hsotg->params.host_dma &&
1422 !chan->ep_is_in && chan->xfer_len > 0)
1423 /* Load OUT packet into the appropriate Tx FIFO */
1424 dwc2_hc_write_packet(hsotg, chan);
1428 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1429 * host channel and starts the transfer in Descriptor DMA mode
1431 * @hsotg: Programming view of DWC_otg controller
1432 * @chan: Information needed to initialize the host channel
1434 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1435 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1436 * with micro-frame bitmap.
1438 * Initializes HCDMA register with descriptor list address and CTD value then
1439 * starts the transfer via enabling the channel.
1441 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1442 struct dwc2_host_chan *chan)
1448 hctsiz |= TSIZ_DOPNG;
1450 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1451 dwc2_set_pid_isoc(chan);
1453 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1454 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1455 TSIZ_SC_MC_PID_MASK;
1457 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1458 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1460 /* Non-zero only for high-speed interrupt endpoints */
1461 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1464 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1466 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1467 chan->data_pid_start);
1468 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1471 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1473 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1474 chan->desc_list_sz, DMA_TO_DEVICE);
1476 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1479 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1480 &chan->desc_list_addr, chan->hc_num);
1482 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1483 hcchar &= ~HCCHAR_MULTICNT_MASK;
1484 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1485 HCCHAR_MULTICNT_MASK;
1487 if (hcchar & HCCHAR_CHDIS)
1488 dev_warn(hsotg->dev,
1489 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1490 __func__, chan->hc_num, hcchar);
1492 /* Set host channel enable after all other setup is complete */
1493 hcchar |= HCCHAR_CHENA;
1494 hcchar &= ~HCCHAR_CHDIS;
1497 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1498 (hcchar & HCCHAR_MULTICNT_MASK) >>
1499 HCCHAR_MULTICNT_SHIFT);
1501 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1503 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1506 chan->xfer_started = 1;
1511 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1512 * a previous call to dwc2_hc_start_transfer()
1514 * @hsotg: Programming view of DWC_otg controller
1515 * @chan: Information needed to initialize the host channel
1517 * The caller must ensure there is sufficient space in the request queue and Tx
1518 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1519 * the controller acts autonomously to complete transfers programmed to a host
1522 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1523 * if there is any data remaining to be queued. For an IN transfer, another
1524 * data packet is always requested. For the SETUP phase of a control transfer,
1525 * this function does nothing.
1527 * Return: 1 if a new request is queued, 0 if no more requests are required
1530 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1531 struct dwc2_host_chan *chan)
1534 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1538 /* SPLITs always queue just once per channel */
1541 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1542 /* SETUPs are queued only once since they can't be NAK'd */
1545 if (chan->ep_is_in) {
1547 * Always queue another request for other IN transfers. If
1548 * back-to-back INs are issued and NAKs are received for both,
1549 * the driver may still be processing the first NAK when the
1550 * second NAK is received. When the interrupt handler clears
1551 * the NAK interrupt for the first NAK, the second NAK will
1552 * not be seen. So we can't depend on the NAK interrupt
1553 * handler to requeue a NAK'd request. Instead, IN requests
1554 * are issued each time this function is called. When the
1555 * transfer completes, the extra requests for the channel will
1558 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1560 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1561 hcchar |= HCCHAR_CHENA;
1562 hcchar &= ~HCCHAR_CHDIS;
1564 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1566 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1573 if (chan->xfer_count < chan->xfer_len) {
1574 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1575 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1576 u32 hcchar = dwc2_readl(hsotg,
1577 HCCHAR(chan->hc_num));
1579 dwc2_hc_set_even_odd_frame(hsotg, chan,
1583 /* Load OUT packet into the appropriate Tx FIFO */
1584 dwc2_hc_write_packet(hsotg, chan);
1593 * =========================================================================
1595 * =========================================================================
1599 * Processes all the URBs in a single list of QHs. Completes them with
1600 * -ETIMEDOUT and frees the QTD.
1602 * Must be called with interrupt disabled and spinlock held
1604 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1605 struct list_head *qh_list)
1607 struct dwc2_qh *qh, *qh_tmp;
1608 struct dwc2_qtd *qtd, *qtd_tmp;
1610 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1611 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1613 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1614 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1619 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1620 struct list_head *qh_list)
1622 struct dwc2_qtd *qtd, *qtd_tmp;
1623 struct dwc2_qh *qh, *qh_tmp;
1624 unsigned long flags;
1627 /* The list hasn't been initialized yet */
1630 spin_lock_irqsave(&hsotg->lock, flags);
1632 /* Ensure there are no QTDs or URBs left */
1633 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1635 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1636 dwc2_hcd_qh_unlink(hsotg, qh);
1638 /* Free each QTD in the QH's QTD list */
1639 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1641 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1643 if (qh->channel && qh->channel->qh == qh)
1644 qh->channel->qh = NULL;
1646 spin_unlock_irqrestore(&hsotg->lock, flags);
1647 dwc2_hcd_qh_free(hsotg, qh);
1648 spin_lock_irqsave(&hsotg->lock, flags);
1651 spin_unlock_irqrestore(&hsotg->lock, flags);
1655 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1656 * and periodic schedules. The QTD associated with each URB is removed from
1657 * the schedule and freed. This function may be called when a disconnect is
1658 * detected or when the HCD is being stopped.
1660 * Must be called with interrupt disabled and spinlock held
1662 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1664 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1665 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1666 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1667 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1668 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1669 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1670 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1674 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1676 * @hsotg: Pointer to struct dwc2_hsotg
1678 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1682 if (hsotg->op_state == OTG_STATE_B_HOST) {
1684 * Reset the port. During a HNP mode switch the reset
1685 * needs to occur within 1ms and have a duration of at
1688 hprt0 = dwc2_read_hprt0(hsotg);
1690 dwc2_writel(hsotg, hprt0, HPRT0);
1693 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1694 msecs_to_jiffies(50));
1697 /* Must be called with interrupt disabled and spinlock held */
1698 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1700 int num_channels = hsotg->params.host_channels;
1701 struct dwc2_host_chan *channel;
1705 if (!hsotg->params.host_dma) {
1706 /* Flush out any channel requests in slave mode */
1707 for (i = 0; i < num_channels; i++) {
1708 channel = hsotg->hc_ptr_array[i];
1709 if (!list_empty(&channel->hc_list_entry))
1711 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1712 if (hcchar & HCCHAR_CHENA) {
1713 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1714 hcchar |= HCCHAR_CHDIS;
1715 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1720 for (i = 0; i < num_channels; i++) {
1721 channel = hsotg->hc_ptr_array[i];
1722 if (!list_empty(&channel->hc_list_entry))
1724 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1725 if (hcchar & HCCHAR_CHENA) {
1726 /* Halt the channel */
1727 hcchar |= HCCHAR_CHDIS;
1728 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1731 dwc2_hc_cleanup(hsotg, channel);
1732 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1734 * Added for Descriptor DMA to prevent channel double cleanup in
1735 * release_channel_ddma(), which is called from ep_disable when
1736 * device disconnects
1740 /* All channels have been freed, mark them available */
1741 if (hsotg->params.uframe_sched) {
1742 hsotg->available_host_channels =
1743 hsotg->params.host_channels;
1745 hsotg->non_periodic_channels = 0;
1746 hsotg->periodic_channels = 0;
1751 * dwc2_hcd_connect() - Handles connect of the HCD
1753 * @hsotg: Pointer to struct dwc2_hsotg
1755 * Must be called with interrupt disabled and spinlock held
1757 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1759 if (hsotg->lx_state != DWC2_L0)
1760 usb_hcd_resume_root_hub(hsotg->priv);
1762 hsotg->flags.b.port_connect_status_change = 1;
1763 hsotg->flags.b.port_connect_status = 1;
1767 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1769 * @hsotg: Pointer to struct dwc2_hsotg
1770 * @force: If true, we won't try to reconnect even if we see device connected.
1772 * Must be called with interrupt disabled and spinlock held
1774 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1779 /* Set status flags for the hub driver */
1780 hsotg->flags.b.port_connect_status_change = 1;
1781 hsotg->flags.b.port_connect_status = 0;
1784 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1785 * interrupt mask and status bits and disabling subsequent host
1786 * channel interrupts.
1788 intr = dwc2_readl(hsotg, GINTMSK);
1789 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1790 dwc2_writel(hsotg, intr, GINTMSK);
1791 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1792 dwc2_writel(hsotg, intr, GINTSTS);
1795 * Turn off the vbus power only if the core has transitioned to device
1796 * mode. If still in host mode, need to keep power on to detect a
1799 if (dwc2_is_device_mode(hsotg)) {
1800 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1801 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1802 dwc2_writel(hsotg, 0, HPRT0);
1805 dwc2_disable_host_interrupts(hsotg);
1808 /* Respond with an error status to all URBs in the schedule */
1809 dwc2_kill_all_urbs(hsotg);
1811 if (dwc2_is_host_mode(hsotg))
1812 /* Clean up any host channels that were in use */
1813 dwc2_hcd_cleanup_channels(hsotg);
1815 dwc2_host_disconnect(hsotg);
1818 * Add an extra check here to see if we're actually connected but
1819 * we don't have a detection interrupt pending. This can happen if:
1820 * 1. hardware sees connect
1821 * 2. hardware sees disconnect
1822 * 3. hardware sees connect
1823 * 4. dwc2_port_intr() - clears connect interrupt
1824 * 5. dwc2_handle_common_intr() - calls here
1826 * Without the extra check here we will end calling disconnect
1827 * and won't get any future interrupts to handle the connect.
1830 hprt0 = dwc2_readl(hsotg, HPRT0);
1831 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1832 dwc2_hcd_connect(hsotg);
1837 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1839 * @hsotg: Pointer to struct dwc2_hsotg
1841 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1843 if (hsotg->bus_suspended) {
1844 hsotg->flags.b.port_suspend_change = 1;
1845 usb_hcd_resume_root_hub(hsotg->priv);
1848 if (hsotg->lx_state == DWC2_L1)
1849 hsotg->flags.b.port_l1_change = 1;
1853 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1855 * @hsotg: Pointer to struct dwc2_hsotg
1857 * Must be called with interrupt disabled and spinlock held
1859 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1861 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1864 * The root hub should be disconnected before this function is called.
1865 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1866 * and the QH lists (via ..._hcd_endpoint_disable).
1869 /* Turn off all host-specific interrupts */
1870 dwc2_disable_host_interrupts(hsotg);
1872 /* Turn off the vbus power */
1873 dev_dbg(hsotg->dev, "PortPower off\n");
1874 dwc2_writel(hsotg, 0, HPRT0);
1877 /* Caller must hold driver lock */
1878 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1879 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
1880 struct dwc2_qtd *qtd)
1886 if (!hsotg->flags.b.port_connect_status) {
1887 /* No longer connected */
1888 dev_err(hsotg->dev, "Not connected\n");
1892 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1894 /* Some configurations cannot support LS traffic on a FS root port */
1895 if ((dev_speed == USB_SPEED_LOW) &&
1896 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1897 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1898 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1899 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1901 if (prtspd == HPRT0_SPD_FULL_SPEED)
1908 dwc2_hcd_qtd_init(qtd, urb);
1909 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1912 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
1917 intr_mask = dwc2_readl(hsotg, GINTMSK);
1918 if (!(intr_mask & GINTSTS_SOF)) {
1919 enum dwc2_transaction_type tr_type;
1921 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
1922 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
1924 * Do not schedule SG transactions until qtd has
1925 * URB_GIVEBACK_ASAP set
1929 tr_type = dwc2_hcd_select_transactions(hsotg);
1930 if (tr_type != DWC2_TRANSACTION_NONE)
1931 dwc2_hcd_queue_transactions(hsotg, tr_type);
1937 /* Must be called with interrupt disabled and spinlock held */
1938 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1939 struct dwc2_hcd_urb *urb)
1942 struct dwc2_qtd *urb_qtd;
1946 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1952 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1958 if (urb_qtd->in_process && qh->channel) {
1959 dwc2_dump_channel_info(hsotg, qh->channel);
1961 /* The QTD is in process (it has been assigned to a channel) */
1962 if (hsotg->flags.b.port_connect_status)
1964 * If still connected (i.e. in host mode), halt the
1965 * channel so it can be used for other transfers. If
1966 * no longer connected, the host registers can't be
1967 * written to halt the channel since the core is in
1970 dwc2_hc_halt(hsotg, qh->channel,
1971 DWC2_HC_XFER_URB_DEQUEUE);
1975 * Free the QTD and clean up the associated QH. Leave the QH in the
1976 * schedule if it has any remaining QTDs.
1978 if (!hsotg->params.dma_desc_enable) {
1979 u8 in_process = urb_qtd->in_process;
1981 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1983 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1985 } else if (list_empty(&qh->qtd_list)) {
1986 dwc2_hcd_qh_unlink(hsotg, qh);
1989 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1995 /* Must NOT be called with interrupt disabled or spinlock held */
1996 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
1997 struct usb_host_endpoint *ep, int retry)
1999 struct dwc2_qtd *qtd, *qtd_tmp;
2001 unsigned long flags;
2004 spin_lock_irqsave(&hsotg->lock, flags);
2012 while (!list_empty(&qh->qtd_list) && retry--) {
2015 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2020 spin_unlock_irqrestore(&hsotg->lock, flags);
2022 spin_lock_irqsave(&hsotg->lock, flags);
2030 dwc2_hcd_qh_unlink(hsotg, qh);
2032 /* Free each QTD in the QH's QTD list */
2033 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2034 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2038 if (qh->channel && qh->channel->qh == qh)
2039 qh->channel->qh = NULL;
2041 spin_unlock_irqrestore(&hsotg->lock, flags);
2043 dwc2_hcd_qh_free(hsotg, qh);
2049 spin_unlock_irqrestore(&hsotg->lock, flags);
2054 /* Must be called with interrupt disabled and spinlock held */
2055 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2056 struct usb_host_endpoint *ep)
2058 struct dwc2_qh *qh = ep->hcpriv;
2063 qh->data_toggle = DWC2_HC_PID_DATA0;
2069 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2070 * prepares the core for device mode or host mode operation
2072 * @hsotg: Programming view of the DWC_otg controller
2073 * @initial_setup: If true then this is the first init for this instance.
2075 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2080 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2082 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2084 /* Set ULPI External VBUS bit if needed */
2085 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2086 if (hsotg->params.phy_ulpi_ext_vbus)
2087 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2089 /* Set external TS Dline pulsing bit if needed */
2090 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2091 if (hsotg->params.ts_dline)
2092 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2094 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2097 * Reset the Controller
2099 * We only need to reset the controller if this is a re-init.
2100 * For the first init we know for sure that earlier code reset us (it
2101 * needed to in order to properly detect various parameters).
2103 if (!initial_setup) {
2104 retval = dwc2_core_reset(hsotg, false);
2106 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2113 * This needs to happen in FS mode before any other programming occurs
2115 retval = dwc2_phy_init(hsotg, initial_setup);
2119 /* Program the GAHBCFG Register */
2120 retval = dwc2_gahbcfg_init(hsotg);
2124 /* Program the GUSBCFG register */
2125 dwc2_gusbcfg_init(hsotg);
2127 /* Program the GOTGCTL register */
2128 otgctl = dwc2_readl(hsotg, GOTGCTL);
2129 otgctl &= ~GOTGCTL_OTGVER;
2130 dwc2_writel(hsotg, otgctl, GOTGCTL);
2132 /* Clear the SRP success bit for FS-I2c */
2133 hsotg->srp_success = 0;
2135 /* Enable common interrupts */
2136 dwc2_enable_common_interrupts(hsotg);
2139 * Do device or host initialization based on mode during PCD and
2140 * HCD initialization
2142 if (dwc2_is_host_mode(hsotg)) {
2143 dev_dbg(hsotg->dev, "Host Mode\n");
2144 hsotg->op_state = OTG_STATE_A_HOST;
2146 dev_dbg(hsotg->dev, "Device Mode\n");
2147 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2154 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2157 * @hsotg: Programming view of DWC_otg controller
2159 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2160 * request queues. Host channels are reset to ensure that they are ready for
2161 * performing transfers.
2163 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2165 u32 hcfg, hfir, otgctl, usbcfg;
2167 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2169 /* Set HS/FS Timeout Calibration to 7 (max available value).
2170 * The number of PHY clocks that the application programs in
2171 * this field is added to the high/full speed interpacket timeout
2172 * duration in the core to account for any additional delays
2173 * introduced by the PHY. This can be required, because the delay
2174 * introduced by the PHY in generating the linestate condition
2175 * can vary from one PHY to another.
2177 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2178 usbcfg |= GUSBCFG_TOUTCAL(7);
2179 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2181 /* Restart the Phy Clock */
2182 dwc2_writel(hsotg, 0, PCGCTL);
2184 /* Initialize Host Configuration Register */
2185 dwc2_init_fs_ls_pclk_sel(hsotg);
2186 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2187 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2188 hcfg = dwc2_readl(hsotg, HCFG);
2189 hcfg |= HCFG_FSLSSUPP;
2190 dwc2_writel(hsotg, hcfg, HCFG);
2194 * This bit allows dynamic reloading of the HFIR register during
2195 * runtime. This bit needs to be programmed during initial configuration
2196 * and its value must not be changed during runtime.
2198 if (hsotg->params.reload_ctl) {
2199 hfir = dwc2_readl(hsotg, HFIR);
2200 hfir |= HFIR_RLDCTRL;
2201 dwc2_writel(hsotg, hfir, HFIR);
2204 if (hsotg->params.dma_desc_enable) {
2205 u32 op_mode = hsotg->hw_params.op_mode;
2207 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2208 !hsotg->hw_params.dma_desc_enable ||
2209 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2210 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2211 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2213 "Hardware does not support descriptor DMA mode -\n");
2215 "falling back to buffer DMA mode.\n");
2216 hsotg->params.dma_desc_enable = false;
2218 hcfg = dwc2_readl(hsotg, HCFG);
2219 hcfg |= HCFG_DESCDMA;
2220 dwc2_writel(hsotg, hcfg, HCFG);
2224 /* Configure data FIFO sizes */
2225 dwc2_config_fifos(hsotg);
2227 /* TODO - check this */
2228 /* Clear Host Set HNP Enable in the OTG Control Register */
2229 otgctl = dwc2_readl(hsotg, GOTGCTL);
2230 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2231 dwc2_writel(hsotg, otgctl, GOTGCTL);
2233 /* Make sure the FIFOs are flushed */
2234 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2235 dwc2_flush_rx_fifo(hsotg);
2237 /* Clear Host Set HNP Enable in the OTG Control Register */
2238 otgctl = dwc2_readl(hsotg, GOTGCTL);
2239 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2240 dwc2_writel(hsotg, otgctl, GOTGCTL);
2242 if (!hsotg->params.dma_desc_enable) {
2243 int num_channels, i;
2246 /* Flush out any leftover queued requests */
2247 num_channels = hsotg->params.host_channels;
2248 for (i = 0; i < num_channels; i++) {
2249 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2250 if (hcchar & HCCHAR_CHENA) {
2251 hcchar &= ~HCCHAR_CHENA;
2252 hcchar |= HCCHAR_CHDIS;
2253 hcchar &= ~HCCHAR_EPDIR;
2254 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2258 /* Halt all channels to put them into a known state */
2259 for (i = 0; i < num_channels; i++) {
2260 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2261 if (hcchar & HCCHAR_CHENA) {
2262 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2263 hcchar &= ~HCCHAR_EPDIR;
2264 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2265 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2268 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2271 dev_warn(hsotg->dev,
2272 "Unable to clear enable on channel %d\n",
2279 /* Enable ACG feature in host mode, if supported */
2280 dwc2_enable_acg(hsotg);
2282 /* Turn on the vbus power */
2283 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2284 if (hsotg->op_state == OTG_STATE_A_HOST) {
2285 u32 hprt0 = dwc2_read_hprt0(hsotg);
2287 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2288 !!(hprt0 & HPRT0_PWR));
2289 if (!(hprt0 & HPRT0_PWR)) {
2291 dwc2_writel(hsotg, hprt0, HPRT0);
2295 dwc2_enable_host_interrupts(hsotg);
2299 * Initializes dynamic portions of the DWC_otg HCD state
2301 * Must be called with interrupt disabled and spinlock held
2303 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2305 struct dwc2_host_chan *chan, *chan_tmp;
2309 hsotg->flags.d32 = 0;
2310 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2312 if (hsotg->params.uframe_sched) {
2313 hsotg->available_host_channels =
2314 hsotg->params.host_channels;
2316 hsotg->non_periodic_channels = 0;
2317 hsotg->periodic_channels = 0;
2321 * Put all channels in the free channel list and clean up channel
2324 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2326 list_del_init(&chan->hc_list_entry);
2328 num_channels = hsotg->params.host_channels;
2329 for (i = 0; i < num_channels; i++) {
2330 chan = hsotg->hc_ptr_array[i];
2331 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2332 dwc2_hc_cleanup(hsotg, chan);
2335 /* Initialize the DWC core for host mode operation */
2336 dwc2_core_host_init(hsotg);
2339 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2340 struct dwc2_host_chan *chan,
2341 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2343 int hub_addr, hub_port;
2346 chan->xact_pos = qtd->isoc_split_pos;
2347 chan->complete_split = qtd->complete_split;
2348 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2349 chan->hub_addr = (u8)hub_addr;
2350 chan->hub_port = (u8)hub_port;
2353 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2354 struct dwc2_host_chan *chan,
2355 struct dwc2_qtd *qtd)
2357 struct dwc2_hcd_urb *urb = qtd->urb;
2358 struct dwc2_hcd_iso_packet_desc *frame_desc;
2360 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2361 case USB_ENDPOINT_XFER_CONTROL:
2362 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2364 switch (qtd->control_phase) {
2365 case DWC2_CONTROL_SETUP:
2366 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2369 chan->data_pid_start = DWC2_HC_PID_SETUP;
2370 if (hsotg->params.host_dma)
2371 chan->xfer_dma = urb->setup_dma;
2373 chan->xfer_buf = urb->setup_packet;
2377 case DWC2_CONTROL_DATA:
2378 dev_vdbg(hsotg->dev, " Control data transaction\n");
2379 chan->data_pid_start = qtd->data_toggle;
2382 case DWC2_CONTROL_STATUS:
2384 * Direction is opposite of data direction or IN if no
2387 dev_vdbg(hsotg->dev, " Control status transaction\n");
2388 if (urb->length == 0)
2392 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2395 chan->data_pid_start = DWC2_HC_PID_DATA1;
2397 if (hsotg->params.host_dma)
2398 chan->xfer_dma = hsotg->status_buf_dma;
2400 chan->xfer_buf = hsotg->status_buf;
2405 case USB_ENDPOINT_XFER_BULK:
2406 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2409 case USB_ENDPOINT_XFER_INT:
2410 chan->ep_type = USB_ENDPOINT_XFER_INT;
2413 case USB_ENDPOINT_XFER_ISOC:
2414 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2415 if (hsotg->params.dma_desc_enable)
2418 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2419 frame_desc->status = 0;
2421 if (hsotg->params.host_dma) {
2422 chan->xfer_dma = urb->dma;
2423 chan->xfer_dma += frame_desc->offset +
2424 qtd->isoc_split_offset;
2426 chan->xfer_buf = urb->buf;
2427 chan->xfer_buf += frame_desc->offset +
2428 qtd->isoc_split_offset;
2431 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2433 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2434 if (chan->xfer_len <= 188)
2435 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2437 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2443 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2445 struct dwc2_host_chan *chan)
2447 if (!hsotg->unaligned_cache ||
2448 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2451 if (!qh->dw_align_buf) {
2452 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2453 GFP_ATOMIC | GFP_DMA);
2454 if (!qh->dw_align_buf)
2458 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2459 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2462 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2463 dev_err(hsotg->dev, "can't map align_buf\n");
2464 chan->align_buf = 0;
2468 chan->align_buf = qh->dw_align_buf_dma;
2472 #define DWC2_USB_DMA_ALIGN 4
2474 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2476 void *stored_xfer_buffer;
2479 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2482 /* Restore urb->transfer_buffer from the end of the allocated area */
2483 memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2484 urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2486 if (usb_urb_dir_in(urb)) {
2487 if (usb_pipeisoc(urb->pipe))
2488 length = urb->transfer_buffer_length;
2490 length = urb->actual_length;
2492 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2494 kfree(urb->transfer_buffer);
2495 urb->transfer_buffer = stored_xfer_buffer;
2497 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2500 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2503 size_t kmalloc_size;
2505 if (urb->num_sgs || urb->sg ||
2506 urb->transfer_buffer_length == 0 ||
2507 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2511 * Allocate a buffer with enough padding for original transfer_buffer
2512 * pointer. This allocation is guaranteed to be aligned properly for
2515 kmalloc_size = urb->transfer_buffer_length +
2516 sizeof(urb->transfer_buffer);
2518 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2523 * Position value of original urb->transfer_buffer pointer to the end
2524 * of allocation for later referencing
2526 memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2527 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2529 if (usb_urb_dir_out(urb))
2530 memcpy(kmalloc_ptr, urb->transfer_buffer,
2531 urb->transfer_buffer_length);
2532 urb->transfer_buffer = kmalloc_ptr;
2534 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2539 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2544 /* We assume setup_dma is always aligned; warn if not */
2545 WARN_ON_ONCE(urb->setup_dma &&
2546 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2548 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2552 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2554 dwc2_free_dma_aligned_buffer(urb);
2559 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2561 usb_hcd_unmap_urb_for_dma(hcd, urb);
2562 dwc2_free_dma_aligned_buffer(urb);
2566 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2567 * channel and initializes the host channel to perform the transactions. The
2568 * host channel is removed from the free list.
2570 * @hsotg: The HCD state structure
2571 * @qh: Transactions from the first QTD for this QH are selected and assigned
2572 * to a free host channel
2574 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2576 struct dwc2_host_chan *chan;
2577 struct dwc2_hcd_urb *urb;
2578 struct dwc2_qtd *qtd;
2581 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2583 if (list_empty(&qh->qtd_list)) {
2584 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2588 if (list_empty(&hsotg->free_hc_list)) {
2589 dev_dbg(hsotg->dev, "No free channel to assign\n");
2593 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2596 /* Remove host channel from free list */
2597 list_del_init(&chan->hc_list_entry);
2599 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2602 qtd->in_process = 1;
2605 * Use usb_pipedevice to determine device address. This address is
2606 * 0 before the SET_ADDRESS command and the correct address afterward.
2608 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2609 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2610 chan->speed = qh->dev_speed;
2611 chan->max_packet = dwc2_max_packet(qh->maxp);
2613 chan->xfer_started = 0;
2614 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2615 chan->error_state = (qtd->error_count > 0);
2616 chan->halt_on_queue = 0;
2617 chan->halt_pending = 0;
2621 * The following values may be modified in the transfer type section
2622 * below. The xfer_len value may be reduced when the transfer is
2623 * started to accommodate the max widths of the XferSize and PktCnt
2624 * fields in the HCTSIZn register.
2627 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2631 chan->do_ping = qh->ping_state;
2633 chan->data_pid_start = qh->data_toggle;
2634 chan->multi_count = 1;
2636 if (urb->actual_length > urb->length &&
2637 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2638 urb->actual_length = urb->length;
2640 if (hsotg->params.host_dma)
2641 chan->xfer_dma = urb->dma + urb->actual_length;
2643 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2645 chan->xfer_len = urb->length - urb->actual_length;
2646 chan->xfer_count = 0;
2648 /* Set the split attributes if required */
2650 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2654 /* Set the transfer attributes */
2655 dwc2_hc_init_xfer(hsotg, chan, qtd);
2657 /* For non-dword aligned buffers */
2658 if (hsotg->params.host_dma && qh->do_split &&
2659 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2660 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2661 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2663 "Failed to allocate memory to handle non-aligned buffer\n");
2664 /* Add channel back to free list */
2665 chan->align_buf = 0;
2666 chan->multi_count = 0;
2667 list_add_tail(&chan->hc_list_entry,
2668 &hsotg->free_hc_list);
2669 qtd->in_process = 0;
2675 * We assume that DMA is always aligned in non-split
2676 * case or split out case. Warn if not.
2678 WARN_ON_ONCE(hsotg->params.host_dma &&
2679 (chan->xfer_dma & 0x3));
2680 chan->align_buf = 0;
2683 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2684 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2686 * This value may be modified when the transfer is started
2687 * to reflect the actual transfer length
2689 chan->multi_count = dwc2_hb_mult(qh->maxp);
2691 if (hsotg->params.dma_desc_enable) {
2692 chan->desc_list_addr = qh->desc_list_dma;
2693 chan->desc_list_sz = qh->desc_list_sz;
2696 dwc2_hc_init(hsotg, chan);
2703 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2704 * schedule and assigns them to available host channels. Called from the HCD
2705 * interrupt handler functions.
2707 * @hsotg: The HCD state structure
2709 * Return: The types of new transactions that were assigned to host channels
2711 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2712 struct dwc2_hsotg *hsotg)
2714 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2715 struct list_head *qh_ptr;
2719 #ifdef DWC2_DEBUG_SOF
2720 dev_vdbg(hsotg->dev, " Select Transactions\n");
2723 /* Process entries in the periodic ready list */
2724 qh_ptr = hsotg->periodic_sched_ready.next;
2725 while (qh_ptr != &hsotg->periodic_sched_ready) {
2726 if (list_empty(&hsotg->free_hc_list))
2728 if (hsotg->params.uframe_sched) {
2729 if (hsotg->available_host_channels <= 1)
2731 hsotg->available_host_channels--;
2733 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2734 if (dwc2_assign_and_init_hc(hsotg, qh))
2738 * Move the QH from the periodic ready schedule to the
2739 * periodic assigned schedule
2741 qh_ptr = qh_ptr->next;
2742 list_move_tail(&qh->qh_list_entry,
2743 &hsotg->periodic_sched_assigned);
2744 ret_val = DWC2_TRANSACTION_PERIODIC;
2748 * Process entries in the inactive portion of the non-periodic
2749 * schedule. Some free host channels may not be used if they are
2750 * reserved for periodic transfers.
2752 num_channels = hsotg->params.host_channels;
2753 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2754 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2755 if (!hsotg->params.uframe_sched &&
2756 hsotg->non_periodic_channels >= num_channels -
2757 hsotg->periodic_channels)
2759 if (list_empty(&hsotg->free_hc_list))
2761 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2762 if (hsotg->params.uframe_sched) {
2763 if (hsotg->available_host_channels < 1)
2765 hsotg->available_host_channels--;
2768 if (dwc2_assign_and_init_hc(hsotg, qh))
2772 * Move the QH from the non-periodic inactive schedule to the
2773 * non-periodic active schedule
2775 qh_ptr = qh_ptr->next;
2776 list_move_tail(&qh->qh_list_entry,
2777 &hsotg->non_periodic_sched_active);
2779 if (ret_val == DWC2_TRANSACTION_NONE)
2780 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2782 ret_val = DWC2_TRANSACTION_ALL;
2784 if (!hsotg->params.uframe_sched)
2785 hsotg->non_periodic_channels++;
2792 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2793 * a host channel associated with either a periodic or non-periodic transfer
2795 * @hsotg: The HCD state structure
2796 * @chan: Host channel descriptor associated with either a periodic or
2797 * non-periodic transfer
2798 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2799 * for periodic transfers or the non-periodic Tx FIFO
2800 * for non-periodic transfers
2802 * Return: 1 if a request is queued and more requests may be needed to
2803 * complete the transfer, 0 if no more requests are required for this
2804 * transfer, -1 if there is insufficient space in the Tx FIFO
2806 * This function assumes that there is space available in the appropriate
2807 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2808 * it checks whether space is available in the appropriate Tx FIFO.
2810 * Must be called with interrupt disabled and spinlock held
2812 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2813 struct dwc2_host_chan *chan,
2814 u16 fifo_dwords_avail)
2819 /* Put ourselves on the list to keep order straight */
2820 list_move_tail(&chan->split_order_list_entry,
2821 &hsotg->split_order);
2823 if (hsotg->params.host_dma) {
2824 if (hsotg->params.dma_desc_enable) {
2825 if (!chan->xfer_started ||
2826 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2827 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2828 chan->qh->ping_state = 0;
2830 } else if (!chan->xfer_started) {
2831 dwc2_hc_start_transfer(hsotg, chan);
2832 chan->qh->ping_state = 0;
2834 } else if (chan->halt_pending) {
2835 /* Don't queue a request if the channel has been halted */
2836 } else if (chan->halt_on_queue) {
2837 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2838 } else if (chan->do_ping) {
2839 if (!chan->xfer_started)
2840 dwc2_hc_start_transfer(hsotg, chan);
2841 } else if (!chan->ep_is_in ||
2842 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2843 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2844 if (!chan->xfer_started) {
2845 dwc2_hc_start_transfer(hsotg, chan);
2848 retval = dwc2_hc_continue_transfer(hsotg, chan);
2854 if (!chan->xfer_started) {
2855 dwc2_hc_start_transfer(hsotg, chan);
2858 retval = dwc2_hc_continue_transfer(hsotg, chan);
2866 * Processes periodic channels for the next frame and queues transactions for
2867 * these channels to the DWC_otg controller. After queueing transactions, the
2868 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2869 * to queue as Periodic Tx FIFO or request queue space becomes available.
2870 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2872 * Must be called with interrupt disabled and spinlock held
2874 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2876 struct list_head *qh_ptr;
2882 bool no_queue_space = false;
2883 bool no_fifo_space = false;
2886 /* If empty list then just adjust interrupt enables */
2887 if (list_empty(&hsotg->periodic_sched_assigned))
2891 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2893 tx_status = dwc2_readl(hsotg, HPTXSTS);
2894 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2895 TXSTS_QSPCAVAIL_SHIFT;
2896 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2897 TXSTS_FSPCAVAIL_SHIFT;
2900 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2902 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2906 qh_ptr = hsotg->periodic_sched_assigned.next;
2907 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2908 tx_status = dwc2_readl(hsotg, HPTXSTS);
2909 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2910 TXSTS_QSPCAVAIL_SHIFT;
2911 if (qspcavail == 0) {
2912 no_queue_space = true;
2916 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2918 qh_ptr = qh_ptr->next;
2922 /* Make sure EP's TT buffer is clean before queueing qtds */
2923 if (qh->tt_buffer_dirty) {
2924 qh_ptr = qh_ptr->next;
2929 * Set a flag if we're queuing high-bandwidth in slave mode.
2930 * The flag prevents any halts to get into the request queue in
2931 * the middle of multiple high-bandwidth packets getting queued.
2933 if (!hsotg->params.host_dma &&
2934 qh->channel->multi_count > 1)
2935 hsotg->queuing_high_bandwidth = 1;
2937 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2938 TXSTS_FSPCAVAIL_SHIFT;
2939 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2941 no_fifo_space = true;
2946 * In Slave mode, stay on the current transfer until there is
2947 * nothing more to do or the high-bandwidth request count is
2948 * reached. In DMA mode, only need to queue one request. The
2949 * controller automatically handles multiple packets for
2950 * high-bandwidth transfers.
2952 if (hsotg->params.host_dma || status == 0 ||
2953 qh->channel->requests == qh->channel->multi_count) {
2954 qh_ptr = qh_ptr->next;
2956 * Move the QH from the periodic assigned schedule to
2957 * the periodic queued schedule
2959 list_move_tail(&qh->qh_list_entry,
2960 &hsotg->periodic_sched_queued);
2962 /* done queuing high bandwidth */
2963 hsotg->queuing_high_bandwidth = 0;
2968 if (no_queue_space || no_fifo_space ||
2969 (!hsotg->params.host_dma &&
2970 !list_empty(&hsotg->periodic_sched_assigned))) {
2972 * May need to queue more transactions as the request
2973 * queue or Tx FIFO empties. Enable the periodic Tx
2974 * FIFO empty interrupt. (Always use the half-empty
2975 * level to ensure that new requests are loaded as
2976 * soon as possible.)
2978 gintmsk = dwc2_readl(hsotg, GINTMSK);
2979 if (!(gintmsk & GINTSTS_PTXFEMP)) {
2980 gintmsk |= GINTSTS_PTXFEMP;
2981 dwc2_writel(hsotg, gintmsk, GINTMSK);
2985 * Disable the Tx FIFO empty interrupt since there are
2986 * no more transactions that need to be queued right
2987 * now. This function is called from interrupt
2988 * handlers to queue more transactions as transfer
2991 gintmsk = dwc2_readl(hsotg, GINTMSK);
2992 if (gintmsk & GINTSTS_PTXFEMP) {
2993 gintmsk &= ~GINTSTS_PTXFEMP;
2994 dwc2_writel(hsotg, gintmsk, GINTMSK);
3000 * Processes active non-periodic channels and queues transactions for these
3001 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3002 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3003 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3004 * FIFO Empty interrupt is disabled.
3006 * Must be called with interrupt disabled and spinlock held
3008 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3010 struct list_head *orig_qh_ptr;
3017 int no_queue_space = 0;
3018 int no_fifo_space = 0;
3021 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3023 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3024 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3025 TXSTS_QSPCAVAIL_SHIFT;
3026 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3027 TXSTS_FSPCAVAIL_SHIFT;
3028 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3030 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3034 * Keep track of the starting point. Skip over the start-of-list
3037 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3038 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3039 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3042 * Process once through the active list or until no more space is
3043 * available in the request queue or the Tx FIFO
3046 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3047 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3048 TXSTS_QSPCAVAIL_SHIFT;
3049 if (!hsotg->params.host_dma && qspcavail == 0) {
3054 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3059 /* Make sure EP's TT buffer is clean before queueing qtds */
3060 if (qh->tt_buffer_dirty)
3063 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3064 TXSTS_FSPCAVAIL_SHIFT;
3065 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3069 } else if (status < 0) {
3074 /* Advance to next QH, skipping start-of-list entry */
3075 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3076 if (hsotg->non_periodic_qh_ptr ==
3077 &hsotg->non_periodic_sched_active)
3078 hsotg->non_periodic_qh_ptr =
3079 hsotg->non_periodic_qh_ptr->next;
3080 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3082 if (!hsotg->params.host_dma) {
3083 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3084 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3085 TXSTS_QSPCAVAIL_SHIFT;
3086 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3087 TXSTS_FSPCAVAIL_SHIFT;
3088 dev_vdbg(hsotg->dev,
3089 " NP Tx Req Queue Space Avail (after queue): %d\n",
3091 dev_vdbg(hsotg->dev,
3092 " NP Tx FIFO Space Avail (after queue): %d\n",
3095 if (more_to_do || no_queue_space || no_fifo_space) {
3097 * May need to queue more transactions as the request
3098 * queue or Tx FIFO empties. Enable the non-periodic
3099 * Tx FIFO empty interrupt. (Always use the half-empty
3100 * level to ensure that new requests are loaded as
3101 * soon as possible.)
3103 gintmsk = dwc2_readl(hsotg, GINTMSK);
3104 gintmsk |= GINTSTS_NPTXFEMP;
3105 dwc2_writel(hsotg, gintmsk, GINTMSK);
3108 * Disable the Tx FIFO empty interrupt since there are
3109 * no more transactions that need to be queued right
3110 * now. This function is called from interrupt
3111 * handlers to queue more transactions as transfer
3114 gintmsk = dwc2_readl(hsotg, GINTMSK);
3115 gintmsk &= ~GINTSTS_NPTXFEMP;
3116 dwc2_writel(hsotg, gintmsk, GINTMSK);
3122 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3123 * and queues transactions for these channels to the DWC_otg controller. Called
3124 * from the HCD interrupt handler functions.
3126 * @hsotg: The HCD state structure
3127 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3130 * Must be called with interrupt disabled and spinlock held
3132 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3133 enum dwc2_transaction_type tr_type)
3135 #ifdef DWC2_DEBUG_SOF
3136 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3138 /* Process host channels associated with periodic transfers */
3139 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3140 tr_type == DWC2_TRANSACTION_ALL)
3141 dwc2_process_periodic_channels(hsotg);
3143 /* Process host channels associated with non-periodic transfers */
3144 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3145 tr_type == DWC2_TRANSACTION_ALL) {
3146 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3147 dwc2_process_non_periodic_channels(hsotg);
3150 * Ensure NP Tx FIFO empty interrupt is disabled when
3151 * there are no non-periodic transfers to process
3153 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3155 gintmsk &= ~GINTSTS_NPTXFEMP;
3156 dwc2_writel(hsotg, gintmsk, GINTMSK);
3161 static void dwc2_conn_id_status_change(struct work_struct *work)
3163 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3167 unsigned long flags;
3169 dev_dbg(hsotg->dev, "%s()\n", __func__);
3171 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3172 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3173 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3174 !!(gotgctl & GOTGCTL_CONID_B));
3176 /* B-Device connector (Device Mode) */
3177 if (gotgctl & GOTGCTL_CONID_B) {
3178 dwc2_vbus_supply_exit(hsotg);
3179 /* Wait for switch to device mode */
3180 dev_dbg(hsotg->dev, "connId B\n");
3181 if (hsotg->bus_suspended) {
3182 dev_info(hsotg->dev,
3183 "Do port resume before switching to device mode\n");
3184 dwc2_port_resume(hsotg);
3186 while (!dwc2_is_device_mode(hsotg)) {
3187 dev_info(hsotg->dev,
3188 "Waiting for Peripheral Mode, Mode=%s\n",
3189 dwc2_is_host_mode(hsotg) ? "Host" :
3193 * Sometimes the initial GOTGCTRL read is wrong, so
3194 * check it again and jump to host mode if that was
3197 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3198 if (!(gotgctl & GOTGCTL_CONID_B))
3205 "Connection id status change timed out\n");
3206 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3207 dwc2_core_init(hsotg, false);
3208 dwc2_enable_global_interrupts(hsotg);
3209 spin_lock_irqsave(&hsotg->lock, flags);
3210 dwc2_hsotg_core_init_disconnected(hsotg, false);
3211 spin_unlock_irqrestore(&hsotg->lock, flags);
3212 /* Enable ACG feature in device mode,if supported */
3213 dwc2_enable_acg(hsotg);
3214 dwc2_hsotg_core_connect(hsotg);
3217 /* A-Device connector (Host Mode) */
3218 dev_dbg(hsotg->dev, "connId A\n");
3219 while (!dwc2_is_host_mode(hsotg)) {
3220 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3221 dwc2_is_host_mode(hsotg) ?
3222 "Host" : "Peripheral");
3229 "Connection id status change timed out\n");
3231 spin_lock_irqsave(&hsotg->lock, flags);
3232 dwc2_hsotg_disconnect(hsotg);
3233 spin_unlock_irqrestore(&hsotg->lock, flags);
3235 hsotg->op_state = OTG_STATE_A_HOST;
3236 /* Initialize the Core for Host mode */
3237 dwc2_core_init(hsotg, false);
3238 dwc2_enable_global_interrupts(hsotg);
3239 dwc2_hcd_start(hsotg);
3243 static void dwc2_wakeup_detected(struct timer_list *t)
3245 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3248 dev_dbg(hsotg->dev, "%s()\n", __func__);
3251 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3252 * so that OPT tests pass with all PHYs.)
3254 hprt0 = dwc2_read_hprt0(hsotg);
3255 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3256 hprt0 &= ~HPRT0_RES;
3257 dwc2_writel(hsotg, hprt0, HPRT0);
3258 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3259 dwc2_readl(hsotg, HPRT0));
3261 dwc2_hcd_rem_wakeup(hsotg);
3262 hsotg->bus_suspended = false;
3264 /* Change to L0 state */
3265 hsotg->lx_state = DWC2_L0;
3268 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3270 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3272 return hcd->self.b_hnp_enable;
3275 /* Must NOT be called with interrupt disabled or spinlock held */
3276 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3278 unsigned long flags;
3283 dev_dbg(hsotg->dev, "%s()\n", __func__);
3285 spin_lock_irqsave(&hsotg->lock, flags);
3287 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3288 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3289 gotgctl |= GOTGCTL_HSTSETHNPEN;
3290 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3291 hsotg->op_state = OTG_STATE_A_SUSPEND;
3294 hprt0 = dwc2_read_hprt0(hsotg);
3295 hprt0 |= HPRT0_SUSP;
3296 dwc2_writel(hsotg, hprt0, HPRT0);
3298 hsotg->bus_suspended = true;
3301 * If power_down is supported, Phy clock will be suspended
3302 * after registers are backuped.
3304 if (!hsotg->params.power_down) {
3305 /* Suspend the Phy Clock */
3306 pcgctl = dwc2_readl(hsotg, PCGCTL);
3307 pcgctl |= PCGCTL_STOPPCLK;
3308 dwc2_writel(hsotg, pcgctl, PCGCTL);
3312 /* For HNP the bus must be suspended for at least 200ms */
3313 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3314 pcgctl = dwc2_readl(hsotg, PCGCTL);
3315 pcgctl &= ~PCGCTL_STOPPCLK;
3316 dwc2_writel(hsotg, pcgctl, PCGCTL);
3318 spin_unlock_irqrestore(&hsotg->lock, flags);
3322 spin_unlock_irqrestore(&hsotg->lock, flags);
3326 /* Must NOT be called with interrupt disabled or spinlock held */
3327 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3329 unsigned long flags;
3333 spin_lock_irqsave(&hsotg->lock, flags);
3336 * If power_down is supported, Phy clock is already resumed
3337 * after registers restore.
3339 if (!hsotg->params.power_down) {
3340 pcgctl = dwc2_readl(hsotg, PCGCTL);
3341 pcgctl &= ~PCGCTL_STOPPCLK;
3342 dwc2_writel(hsotg, pcgctl, PCGCTL);
3343 spin_unlock_irqrestore(&hsotg->lock, flags);
3345 spin_lock_irqsave(&hsotg->lock, flags);
3348 hprt0 = dwc2_read_hprt0(hsotg);
3350 hprt0 &= ~HPRT0_SUSP;
3351 dwc2_writel(hsotg, hprt0, HPRT0);
3352 spin_unlock_irqrestore(&hsotg->lock, flags);
3354 msleep(USB_RESUME_TIMEOUT);
3356 spin_lock_irqsave(&hsotg->lock, flags);
3357 hprt0 = dwc2_read_hprt0(hsotg);
3358 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3359 dwc2_writel(hsotg, hprt0, HPRT0);
3360 hsotg->bus_suspended = false;
3361 spin_unlock_irqrestore(&hsotg->lock, flags);
3364 /* Handles hub class-specific requests */
3365 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3366 u16 wvalue, u16 windex, char *buf, u16 wlength)
3368 struct usb_hub_descriptor *hub_desc;
3377 case ClearHubFeature:
3378 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3381 case C_HUB_LOCAL_POWER:
3382 case C_HUB_OVER_CURRENT:
3383 /* Nothing required here */
3389 "ClearHubFeature request %1xh unknown\n",
3394 case ClearPortFeature:
3395 if (wvalue != USB_PORT_FEAT_L1)
3396 if (!windex || windex > 1)
3399 case USB_PORT_FEAT_ENABLE:
3401 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3402 hprt0 = dwc2_read_hprt0(hsotg);
3404 dwc2_writel(hsotg, hprt0, HPRT0);
3407 case USB_PORT_FEAT_SUSPEND:
3409 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3411 if (hsotg->bus_suspended) {
3412 if (hsotg->hibernated)
3413 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3415 dwc2_port_resume(hsotg);
3419 case USB_PORT_FEAT_POWER:
3421 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3422 hprt0 = dwc2_read_hprt0(hsotg);
3423 pwr = hprt0 & HPRT0_PWR;
3424 hprt0 &= ~HPRT0_PWR;
3425 dwc2_writel(hsotg, hprt0, HPRT0);
3427 dwc2_vbus_supply_exit(hsotg);
3430 case USB_PORT_FEAT_INDICATOR:
3432 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3433 /* Port indicator not supported */
3436 case USB_PORT_FEAT_C_CONNECTION:
3438 * Clears driver's internal Connect Status Change flag
3441 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3442 hsotg->flags.b.port_connect_status_change = 0;
3445 case USB_PORT_FEAT_C_RESET:
3446 /* Clears driver's internal Port Reset Change flag */
3448 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3449 hsotg->flags.b.port_reset_change = 0;
3452 case USB_PORT_FEAT_C_ENABLE:
3454 * Clears the driver's internal Port Enable/Disable
3458 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3459 hsotg->flags.b.port_enable_change = 0;
3462 case USB_PORT_FEAT_C_SUSPEND:
3464 * Clears the driver's internal Port Suspend Change
3465 * flag, which is set when resume signaling on the host
3469 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3470 hsotg->flags.b.port_suspend_change = 0;
3473 case USB_PORT_FEAT_C_PORT_L1:
3475 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3476 hsotg->flags.b.port_l1_change = 0;
3479 case USB_PORT_FEAT_C_OVER_CURRENT:
3481 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3482 hsotg->flags.b.port_over_current_change = 0;
3488 "ClearPortFeature request %1xh unknown or unsupported\n",
3493 case GetHubDescriptor:
3494 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3495 hub_desc = (struct usb_hub_descriptor *)buf;
3496 hub_desc->bDescLength = 9;
3497 hub_desc->bDescriptorType = USB_DT_HUB;
3498 hub_desc->bNbrPorts = 1;
3499 hub_desc->wHubCharacteristics =
3500 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3501 HUB_CHAR_INDV_PORT_OCPM);
3502 hub_desc->bPwrOn2PwrGood = 1;
3503 hub_desc->bHubContrCurrent = 0;
3504 hub_desc->u.hs.DeviceRemovable[0] = 0;
3505 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3509 dev_dbg(hsotg->dev, "GetHubStatus\n");
3514 dev_vdbg(hsotg->dev,
3515 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3517 if (!windex || windex > 1)
3521 if (hsotg->flags.b.port_connect_status_change)
3522 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3523 if (hsotg->flags.b.port_enable_change)
3524 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3525 if (hsotg->flags.b.port_suspend_change)
3526 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3527 if (hsotg->flags.b.port_l1_change)
3528 port_status |= USB_PORT_STAT_C_L1 << 16;
3529 if (hsotg->flags.b.port_reset_change)
3530 port_status |= USB_PORT_STAT_C_RESET << 16;
3531 if (hsotg->flags.b.port_over_current_change) {
3532 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3533 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3536 if (!hsotg->flags.b.port_connect_status) {
3538 * The port is disconnected, which means the core is
3539 * either in device mode or it soon will be. Just
3540 * return 0's for the remainder of the port status
3541 * since the port register can't be read if the core
3542 * is in device mode.
3544 *(__le32 *)buf = cpu_to_le32(port_status);
3548 hprt0 = dwc2_readl(hsotg, HPRT0);
3549 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3551 if (hprt0 & HPRT0_CONNSTS)
3552 port_status |= USB_PORT_STAT_CONNECTION;
3553 if (hprt0 & HPRT0_ENA)
3554 port_status |= USB_PORT_STAT_ENABLE;
3555 if (hprt0 & HPRT0_SUSP)
3556 port_status |= USB_PORT_STAT_SUSPEND;
3557 if (hprt0 & HPRT0_OVRCURRACT)
3558 port_status |= USB_PORT_STAT_OVERCURRENT;
3559 if (hprt0 & HPRT0_RST)
3560 port_status |= USB_PORT_STAT_RESET;
3561 if (hprt0 & HPRT0_PWR)
3562 port_status |= USB_PORT_STAT_POWER;
3564 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3565 if (speed == HPRT0_SPD_HIGH_SPEED)
3566 port_status |= USB_PORT_STAT_HIGH_SPEED;
3567 else if (speed == HPRT0_SPD_LOW_SPEED)
3568 port_status |= USB_PORT_STAT_LOW_SPEED;
3570 if (hprt0 & HPRT0_TSTCTL_MASK)
3571 port_status |= USB_PORT_STAT_TEST;
3572 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3574 if (hsotg->params.dma_desc_fs_enable) {
3576 * Enable descriptor DMA only if a full speed
3577 * device is connected.
3579 if (hsotg->new_connection &&
3581 (USB_PORT_STAT_CONNECTION |
3582 USB_PORT_STAT_HIGH_SPEED |
3583 USB_PORT_STAT_LOW_SPEED)) ==
3584 USB_PORT_STAT_CONNECTION)) {
3587 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3588 hsotg->params.dma_desc_enable = true;
3589 hcfg = dwc2_readl(hsotg, HCFG);
3590 hcfg |= HCFG_DESCDMA;
3591 dwc2_writel(hsotg, hcfg, HCFG);
3592 hsotg->new_connection = false;
3596 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3597 *(__le32 *)buf = cpu_to_le32(port_status);
3601 dev_dbg(hsotg->dev, "SetHubFeature\n");
3602 /* No HUB features supported */
3605 case SetPortFeature:
3606 dev_dbg(hsotg->dev, "SetPortFeature\n");
3607 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3610 if (!hsotg->flags.b.port_connect_status) {
3612 * The port is disconnected, which means the core is
3613 * either in device mode or it soon will be. Just
3614 * return without doing anything since the port
3615 * register can't be written if the core is in device
3622 case USB_PORT_FEAT_SUSPEND:
3624 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3625 if (windex != hsotg->otg_port)
3627 if (hsotg->params.power_down == 2)
3628 dwc2_enter_hibernation(hsotg, 1);
3630 dwc2_port_suspend(hsotg, windex);
3633 case USB_PORT_FEAT_POWER:
3635 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3636 hprt0 = dwc2_read_hprt0(hsotg);
3637 pwr = hprt0 & HPRT0_PWR;
3639 dwc2_writel(hsotg, hprt0, HPRT0);
3641 dwc2_vbus_supply_init(hsotg);
3644 case USB_PORT_FEAT_RESET:
3645 if (hsotg->params.power_down == 2 &&
3647 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3648 hprt0 = dwc2_read_hprt0(hsotg);
3650 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3651 pcgctl = dwc2_readl(hsotg, PCGCTL);
3652 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3653 dwc2_writel(hsotg, pcgctl, PCGCTL);
3654 /* ??? Original driver does this */
3655 dwc2_writel(hsotg, 0, PCGCTL);
3657 hprt0 = dwc2_read_hprt0(hsotg);
3658 pwr = hprt0 & HPRT0_PWR;
3659 /* Clear suspend bit if resetting from suspend state */
3660 hprt0 &= ~HPRT0_SUSP;
3663 * When B-Host the Port reset bit is set in the Start
3664 * HCD Callback function, so that the reset is started
3665 * within 1ms of the HNP success interrupt
3667 if (!dwc2_hcd_is_b_host(hsotg)) {
3668 hprt0 |= HPRT0_PWR | HPRT0_RST;
3670 "In host mode, hprt0=%08x\n", hprt0);
3671 dwc2_writel(hsotg, hprt0, HPRT0);
3673 dwc2_vbus_supply_init(hsotg);
3676 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3678 hprt0 &= ~HPRT0_RST;
3679 dwc2_writel(hsotg, hprt0, HPRT0);
3680 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3683 case USB_PORT_FEAT_INDICATOR:
3685 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3689 case USB_PORT_FEAT_TEST:
3690 hprt0 = dwc2_read_hprt0(hsotg);
3692 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3693 hprt0 &= ~HPRT0_TSTCTL_MASK;
3694 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3695 dwc2_writel(hsotg, hprt0, HPRT0);
3701 "SetPortFeature %1xh unknown or unsupported\n",
3711 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3712 typereq, windex, wvalue);
3719 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3726 retval = (hsotg->flags.b.port_connect_status_change ||
3727 hsotg->flags.b.port_reset_change ||
3728 hsotg->flags.b.port_enable_change ||
3729 hsotg->flags.b.port_suspend_change ||
3730 hsotg->flags.b.port_over_current_change);
3734 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3735 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3736 hsotg->flags.b.port_connect_status_change);
3737 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3738 hsotg->flags.b.port_reset_change);
3739 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3740 hsotg->flags.b.port_enable_change);
3741 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3742 hsotg->flags.b.port_suspend_change);
3743 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3744 hsotg->flags.b.port_over_current_change);
3750 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3752 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3754 #ifdef DWC2_DEBUG_SOF
3755 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3756 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3758 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3761 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3763 u32 hprt = dwc2_readl(hsotg, HPRT0);
3764 u32 hfir = dwc2_readl(hsotg, HFIR);
3765 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3766 unsigned int us_per_frame;
3767 unsigned int frame_number;
3768 unsigned int remaining;
3769 unsigned int interval;
3770 unsigned int phy_clks;
3772 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3773 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3775 /* Extract fields */
3776 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3777 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3778 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3781 * Number of phy clocks since the last tick of the frame number after
3784 phy_clks = (interval - remaining) +
3785 DIV_ROUND_UP(interval * us, us_per_frame);
3787 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3790 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3792 return hsotg->op_state == OTG_STATE_B_HOST;
3795 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3799 struct dwc2_hcd_urb *urb;
3801 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
3803 urb->packet_count = iso_desc_count;
3807 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3808 struct dwc2_hcd_urb *urb, u8 dev_addr,
3809 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3812 ep_type == USB_ENDPOINT_XFER_BULK ||
3813 ep_type == USB_ENDPOINT_XFER_CONTROL)
3814 dev_vdbg(hsotg->dev,
3815 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3816 dev_addr, ep_num, ep_dir, ep_type, mps);
3817 urb->pipe_info.dev_addr = dev_addr;
3818 urb->pipe_info.ep_num = ep_num;
3819 urb->pipe_info.pipe_type = ep_type;
3820 urb->pipe_info.pipe_dir = ep_dir;
3821 urb->pipe_info.mps = mps;
3825 * NOTE: This function will be removed once the peripheral controller code
3826 * is integrated and the driver is stable
3828 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3831 struct dwc2_host_chan *chan;
3832 struct dwc2_hcd_urb *urb;
3833 struct dwc2_qtd *qtd;
3839 num_channels = hsotg->params.host_channels;
3840 dev_dbg(hsotg->dev, "\n");
3842 "************************************************************\n");
3843 dev_dbg(hsotg->dev, "HCD State:\n");
3844 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3846 for (i = 0; i < num_channels; i++) {
3847 chan = hsotg->hc_ptr_array[i];
3848 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3850 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3851 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3852 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3853 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3854 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3855 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3856 chan->data_pid_start);
3857 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3858 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3859 chan->xfer_started);
3860 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3861 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3862 (unsigned long)chan->xfer_dma);
3863 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3864 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3865 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3866 chan->halt_on_queue);
3867 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3868 chan->halt_pending);
3869 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3870 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3871 dev_dbg(hsotg->dev, " complete_split: %d\n",
3872 chan->complete_split);
3873 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3874 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3875 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3876 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3877 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3879 if (chan->xfer_started) {
3880 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3882 hfnum = dwc2_readl(hsotg, HFNUM);
3883 hcchar = dwc2_readl(hsotg, HCCHAR(i));
3884 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3885 hcint = dwc2_readl(hsotg, HCINT(i));
3886 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3887 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3888 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3889 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3890 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3891 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3894 if (!(chan->xfer_started && chan->qh))
3897 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3898 if (!qtd->in_process)
3901 dev_dbg(hsotg->dev, " URB Info:\n");
3902 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3906 " Dev: %d, EP: %d %s\n",
3907 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3908 dwc2_hcd_get_ep_num(&urb->pipe_info),
3909 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3912 " Max packet size: %d\n",
3913 dwc2_hcd_get_mps(&urb->pipe_info));
3915 " transfer_buffer: %p\n",
3918 " transfer_dma: %08lx\n",
3919 (unsigned long)urb->dma);
3921 " transfer_buffer_length: %d\n",
3923 dev_dbg(hsotg->dev, " actual_length: %d\n",
3924 urb->actual_length);
3929 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3930 hsotg->non_periodic_channels);
3931 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3932 hsotg->periodic_channels);
3933 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3934 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3935 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3936 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3937 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3938 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3939 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3940 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3941 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3942 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3943 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3944 dwc2_dump_global_registers(hsotg);
3945 dwc2_dump_host_registers(hsotg);
3947 "************************************************************\n");
3948 dev_dbg(hsotg->dev, "\n");
3952 struct wrapper_priv_data {
3953 struct dwc2_hsotg *hsotg;
3956 /* Gets the dwc2_hsotg from a usb_hcd */
3957 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
3959 struct wrapper_priv_data *p;
3961 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
3966 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
3968 * This will get the dwc2_tt structure (and ttport) associated with the given
3969 * context (which is really just a struct urb pointer).
3971 * The first time this is called for a given TT we allocate memory for our
3972 * structure. When everyone is done and has called dwc2_host_put_tt_info()
3973 * then the refcount for the structure will go to 0 and we'll free it.
3975 * @hsotg: The HCD state structure for the DWC OTG controller.
3976 * @context: The priv pointer from a struct dwc2_hcd_urb.
3977 * @mem_flags: Flags for allocating memory.
3978 * @ttport: We'll return this device's port number here. That's used to
3979 * reference into the bitmap if we're on a multi_tt hub.
3981 * Return: a pointer to a struct dwc2_tt. Don't forget to call
3982 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
3985 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
3986 gfp_t mem_flags, int *ttport)
3988 struct urb *urb = context;
3989 struct dwc2_tt *dwc_tt = NULL;
3992 *ttport = urb->dev->ttport;
3994 dwc_tt = urb->dev->tt->hcpriv;
3999 * For single_tt we need one schedule. For multi_tt
4000 * we need one per port.
4002 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4003 sizeof(dwc_tt->periodic_bitmaps[0]);
4004 if (urb->dev->tt->multi)
4005 bitmap_size *= urb->dev->tt->hub->maxchild;
4007 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4012 dwc_tt->usb_tt = urb->dev->tt;
4013 dwc_tt->usb_tt->hcpriv = dwc_tt;
4023 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4025 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4026 * of the structure are done.
4028 * It's OK to call this with NULL.
4030 * @hsotg: The HCD state structure for the DWC OTG controller.
4031 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4033 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4035 /* Model kfree and make put of NULL a no-op */
4039 WARN_ON(dwc_tt->refcount < 1);
4042 if (!dwc_tt->refcount) {
4043 dwc_tt->usb_tt->hcpriv = NULL;
4048 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4050 struct urb *urb = context;
4052 return urb->dev->speed;
4055 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4058 struct usb_bus *bus = hcd_to_bus(hcd);
4061 bus->bandwidth_allocated += bw / urb->interval;
4062 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4063 bus->bandwidth_isoc_reqs++;
4065 bus->bandwidth_int_reqs++;
4068 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4071 struct usb_bus *bus = hcd_to_bus(hcd);
4074 bus->bandwidth_allocated -= bw / urb->interval;
4075 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4076 bus->bandwidth_isoc_reqs--;
4078 bus->bandwidth_int_reqs--;
4082 * Sets the final status of an URB and returns it to the upper layer. Any
4083 * required cleanup of the URB is performed.
4085 * Must be called with interrupt disabled and spinlock held
4087 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4094 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4099 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4103 urb = qtd->urb->priv;
4105 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4109 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4112 dev_vdbg(hsotg->dev,
4113 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4114 __func__, urb, usb_pipedevice(urb->pipe),
4115 usb_pipeendpoint(urb->pipe),
4116 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4117 urb->actual_length);
4119 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4120 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4121 for (i = 0; i < urb->number_of_packets; ++i) {
4122 urb->iso_frame_desc[i].actual_length =
4123 dwc2_hcd_urb_get_iso_desc_actual_length(
4125 urb->iso_frame_desc[i].status =
4126 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4130 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4131 for (i = 0; i < urb->number_of_packets; i++)
4132 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4133 i, urb->iso_frame_desc[i].status);
4136 urb->status = status;
4138 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4139 urb->actual_length < urb->transfer_buffer_length)
4140 urb->status = -EREMOTEIO;
4143 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4144 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4145 struct usb_host_endpoint *ep = urb->ep;
4148 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4149 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4153 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4158 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4162 * Work queue function for starting the HCD when A-Cable is connected
4164 static void dwc2_hcd_start_func(struct work_struct *work)
4166 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4169 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4170 dwc2_host_start(hsotg);
4174 * Reset work queue function
4176 static void dwc2_hcd_reset_func(struct work_struct *work)
4178 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4180 unsigned long flags;
4183 dev_dbg(hsotg->dev, "USB RESET function called\n");
4185 spin_lock_irqsave(&hsotg->lock, flags);
4187 hprt0 = dwc2_read_hprt0(hsotg);
4188 hprt0 &= ~HPRT0_RST;
4189 dwc2_writel(hsotg, hprt0, HPRT0);
4190 hsotg->flags.b.port_reset_change = 1;
4192 spin_unlock_irqrestore(&hsotg->lock, flags);
4195 static void dwc2_hcd_phy_reset_func(struct work_struct *work)
4197 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4201 ret = phy_reset(hsotg->phy);
4203 dev_warn(hsotg->dev, "PHY reset failed\n");
4207 * =========================================================================
4208 * Linux HC Driver Functions
4209 * =========================================================================
4213 * Initializes the DWC_otg controller and its root hub and prepares it for host
4214 * mode operation. Activates the root port. Returns 0 on success and a negative
4215 * error code on failure.
4217 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4219 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4220 struct usb_bus *bus = hcd_to_bus(hcd);
4221 unsigned long flags;
4225 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4227 spin_lock_irqsave(&hsotg->lock, flags);
4228 hsotg->lx_state = DWC2_L0;
4229 hcd->state = HC_STATE_RUNNING;
4230 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4232 if (dwc2_is_device_mode(hsotg)) {
4233 spin_unlock_irqrestore(&hsotg->lock, flags);
4234 return 0; /* why 0 ?? */
4237 dwc2_hcd_reinit(hsotg);
4239 hprt0 = dwc2_read_hprt0(hsotg);
4240 /* Has vbus power been turned on in dwc2_core_host_init ? */
4241 if (hprt0 & HPRT0_PWR) {
4242 /* Enable external vbus supply before resuming root hub */
4243 spin_unlock_irqrestore(&hsotg->lock, flags);
4244 ret = dwc2_vbus_supply_init(hsotg);
4247 spin_lock_irqsave(&hsotg->lock, flags);
4250 /* Initialize and connect root hub if one is not already attached */
4251 if (bus->root_hub) {
4252 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4253 /* Inform the HUB driver to resume */
4254 usb_hcd_resume_root_hub(hcd);
4257 spin_unlock_irqrestore(&hsotg->lock, flags);
4263 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4266 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4268 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4269 unsigned long flags;
4272 /* Turn off all host-specific interrupts */
4273 dwc2_disable_host_interrupts(hsotg);
4275 /* Wait for interrupt processing to finish */
4276 synchronize_irq(hcd->irq);
4278 spin_lock_irqsave(&hsotg->lock, flags);
4279 hprt0 = dwc2_read_hprt0(hsotg);
4280 /* Ensure hcd is disconnected */
4281 dwc2_hcd_disconnect(hsotg, true);
4282 dwc2_hcd_stop(hsotg);
4283 hsotg->lx_state = DWC2_L3;
4284 hcd->state = HC_STATE_HALT;
4285 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4286 spin_unlock_irqrestore(&hsotg->lock, flags);
4288 /* keep balanced supply init/exit by checking HPRT0_PWR */
4289 if (hprt0 & HPRT0_PWR)
4290 dwc2_vbus_supply_exit(hsotg);
4292 usleep_range(1000, 3000);
4295 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4297 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4298 unsigned long flags;
4303 spin_lock_irqsave(&hsotg->lock, flags);
4305 if (dwc2_is_device_mode(hsotg))
4308 if (hsotg->lx_state != DWC2_L0)
4311 if (!HCD_HW_ACCESSIBLE(hcd))
4314 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4317 if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL)
4318 goto skip_power_saving;
4321 * Drive USB suspend and disable port Power
4322 * if usb bus is not suspended.
4324 if (!hsotg->bus_suspended) {
4325 hprt0 = dwc2_read_hprt0(hsotg);
4326 if (hprt0 & HPRT0_CONNSTS) {
4327 hprt0 |= HPRT0_SUSP;
4328 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
4329 hprt0 &= ~HPRT0_PWR;
4330 dwc2_writel(hsotg, hprt0, HPRT0);
4332 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4333 spin_unlock_irqrestore(&hsotg->lock, flags);
4334 dwc2_vbus_supply_exit(hsotg);
4335 spin_lock_irqsave(&hsotg->lock, flags);
4337 pcgctl = readl(hsotg->regs + PCGCTL);
4338 pcgctl |= PCGCTL_STOPPCLK;
4339 writel(pcgctl, hsotg->regs + PCGCTL);
4343 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4344 /* Enter partial_power_down */
4345 ret = dwc2_enter_partial_power_down(hsotg);
4347 if (ret != -ENOTSUPP)
4349 "enter partial_power_down failed\n");
4350 goto skip_power_saving;
4353 /* After entering partial_power_down, hardware is no more accessible */
4354 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4357 /* Ask phy to be suspended */
4358 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4359 spin_unlock_irqrestore(&hsotg->lock, flags);
4360 usb_phy_set_suspend(hsotg->uphy, true);
4361 spin_lock_irqsave(&hsotg->lock, flags);
4365 hsotg->lx_state = DWC2_L2;
4367 spin_unlock_irqrestore(&hsotg->lock, flags);
4372 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4374 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4375 unsigned long flags;
4379 spin_lock_irqsave(&hsotg->lock, flags);
4381 if (dwc2_is_device_mode(hsotg))
4384 if (hsotg->lx_state != DWC2_L2)
4387 if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
4388 hsotg->lx_state = DWC2_L0;
4393 * Enable power if not already done.
4394 * This must not be spinlocked since duration
4395 * of this call is unknown.
4397 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4398 spin_unlock_irqrestore(&hsotg->lock, flags);
4399 usb_phy_set_suspend(hsotg->uphy, false);
4400 spin_lock_irqsave(&hsotg->lock, flags);
4403 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4405 * Set HW accessible bit before powering on the controller
4406 * since an interrupt may rise.
4408 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4411 /* Exit partial_power_down */
4412 ret = dwc2_exit_partial_power_down(hsotg, true);
4413 if (ret && (ret != -ENOTSUPP))
4414 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4416 pcgctl = readl(hsotg->regs + PCGCTL);
4417 pcgctl &= ~PCGCTL_STOPPCLK;
4418 writel(pcgctl, hsotg->regs + PCGCTL);
4421 hsotg->lx_state = DWC2_L0;
4423 spin_unlock_irqrestore(&hsotg->lock, flags);
4425 if (hsotg->bus_suspended) {
4426 spin_lock_irqsave(&hsotg->lock, flags);
4427 hsotg->flags.b.port_suspend_change = 1;
4428 spin_unlock_irqrestore(&hsotg->lock, flags);
4429 dwc2_port_resume(hsotg);
4431 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4432 dwc2_vbus_supply_init(hsotg);
4434 /* Wait for controller to correctly update D+/D- level */
4435 usleep_range(3000, 5000);
4439 * Clear Port Enable and Port Status changes.
4440 * Enable Port Power.
4442 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4443 HPRT0_ENACHG, HPRT0);
4444 /* Wait for controller to detect Port Connect */
4445 usleep_range(5000, 7000);
4450 spin_unlock_irqrestore(&hsotg->lock, flags);
4455 /* Returns the current frame number */
4456 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4458 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4460 return dwc2_hcd_get_frame_number(hsotg);
4463 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4466 #ifdef VERBOSE_DEBUG
4467 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4468 char *pipetype = NULL;
4471 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4472 dev_vdbg(hsotg->dev, " Device address: %d\n",
4473 usb_pipedevice(urb->pipe));
4474 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4475 usb_pipeendpoint(urb->pipe),
4476 usb_pipein(urb->pipe) ? "IN" : "OUT");
4478 switch (usb_pipetype(urb->pipe)) {
4480 pipetype = "CONTROL";
4485 case PIPE_INTERRUPT:
4486 pipetype = "INTERRUPT";
4488 case PIPE_ISOCHRONOUS:
4489 pipetype = "ISOCHRONOUS";
4493 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4494 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4497 switch (urb->dev->speed) {
4498 case USB_SPEED_HIGH:
4501 case USB_SPEED_FULL:
4512 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4513 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4514 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4515 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4516 urb->transfer_buffer_length);
4517 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4518 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4519 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4520 urb->setup_packet, (unsigned long)urb->setup_dma);
4521 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4523 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4526 for (i = 0; i < urb->number_of_packets; i++) {
4527 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4528 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4529 urb->iso_frame_desc[i].offset,
4530 urb->iso_frame_desc[i].length);
4537 * Starts processing a USB transfer request specified by a USB Request Block
4538 * (URB). mem_flags indicates the type of memory allocation to use while
4539 * processing this URB.
4541 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4544 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4545 struct usb_host_endpoint *ep = urb->ep;
4546 struct dwc2_hcd_urb *dwc2_urb;
4549 int alloc_bandwidth = 0;
4553 unsigned long flags;
4555 bool qh_allocated = false;
4556 struct dwc2_qtd *qtd;
4559 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4560 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4566 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4567 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4568 spin_lock_irqsave(&hsotg->lock, flags);
4569 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4570 alloc_bandwidth = 1;
4571 spin_unlock_irqrestore(&hsotg->lock, flags);
4574 switch (usb_pipetype(urb->pipe)) {
4576 ep_type = USB_ENDPOINT_XFER_CONTROL;
4578 case PIPE_ISOCHRONOUS:
4579 ep_type = USB_ENDPOINT_XFER_ISOC;
4582 ep_type = USB_ENDPOINT_XFER_BULK;
4584 case PIPE_INTERRUPT:
4585 ep_type = USB_ENDPOINT_XFER_INT;
4589 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4594 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4595 usb_pipeendpoint(urb->pipe), ep_type,
4596 usb_pipein(urb->pipe),
4597 usb_maxpacket(urb->dev, urb->pipe,
4598 !(usb_pipein(urb->pipe))));
4600 buf = urb->transfer_buffer;
4602 if (hcd->self.uses_dma) {
4603 if (!buf && (urb->transfer_dma & 3)) {
4605 "%s: unaligned transfer with no transfer_buffer",
4612 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4613 tflags |= URB_GIVEBACK_ASAP;
4614 if (urb->transfer_flags & URB_ZERO_PACKET)
4615 tflags |= URB_SEND_ZERO_PACKET;
4617 dwc2_urb->priv = urb;
4618 dwc2_urb->buf = buf;
4619 dwc2_urb->dma = urb->transfer_dma;
4620 dwc2_urb->length = urb->transfer_buffer_length;
4621 dwc2_urb->setup_packet = urb->setup_packet;
4622 dwc2_urb->setup_dma = urb->setup_dma;
4623 dwc2_urb->flags = tflags;
4624 dwc2_urb->interval = urb->interval;
4625 dwc2_urb->status = -EINPROGRESS;
4627 for (i = 0; i < urb->number_of_packets; ++i)
4628 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4629 urb->iso_frame_desc[i].offset,
4630 urb->iso_frame_desc[i].length);
4632 urb->hcpriv = dwc2_urb;
4633 qh = (struct dwc2_qh *)ep->hcpriv;
4634 /* Create QH for the endpoint if it doesn't exist */
4636 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4642 qh_allocated = true;
4645 qtd = kzalloc(sizeof(*qtd), mem_flags);
4651 spin_lock_irqsave(&hsotg->lock, flags);
4652 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4656 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4660 if (alloc_bandwidth) {
4661 dwc2_allocate_bus_bandwidth(hcd,
4662 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4666 spin_unlock_irqrestore(&hsotg->lock, flags);
4671 dwc2_urb->priv = NULL;
4672 usb_hcd_unlink_urb_from_ep(hcd, urb);
4673 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4674 qh->channel->qh = NULL;
4676 spin_unlock_irqrestore(&hsotg->lock, flags);
4682 struct dwc2_qtd *qtd2, *qtd2_tmp;
4685 dwc2_hcd_qh_unlink(hsotg, qh);
4686 /* Free each QTD in the QH's QTD list */
4687 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4689 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4690 dwc2_hcd_qh_free(hsotg, qh);
4699 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4701 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4704 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4706 unsigned long flags;
4708 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4709 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4711 spin_lock_irqsave(&hsotg->lock, flags);
4713 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4718 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4722 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4724 usb_hcd_unlink_urb_from_ep(hcd, urb);
4729 /* Higher layer software sets URB status */
4730 spin_unlock(&hsotg->lock);
4731 usb_hcd_giveback_urb(hcd, urb, status);
4732 spin_lock(&hsotg->lock);
4734 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4735 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4737 spin_unlock_irqrestore(&hsotg->lock, flags);
4743 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4744 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4745 * must already be dequeued.
4747 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4748 struct usb_host_endpoint *ep)
4750 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4753 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4754 ep->desc.bEndpointAddress, ep->hcpriv);
4755 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4759 * Resets endpoint specific parameter values, in current version used to reset
4760 * the data toggle (as a WA). This function can be called from usb_clear_halt
4763 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4764 struct usb_host_endpoint *ep)
4766 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4767 unsigned long flags;
4770 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4771 ep->desc.bEndpointAddress);
4773 spin_lock_irqsave(&hsotg->lock, flags);
4774 dwc2_hcd_endpoint_reset(hsotg, ep);
4775 spin_unlock_irqrestore(&hsotg->lock, flags);
4779 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4780 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4783 * This function is called by the USB core when an interrupt occurs
4785 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4787 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4789 return dwc2_handle_hcd_intr(hsotg);
4793 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4794 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4795 * is the status change indicator for the single root port. Returns 1 if either
4796 * change indicator is 1, otherwise returns 0.
4798 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4800 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4802 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4806 /* Handles hub class-specific requests */
4807 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4808 u16 windex, char *buf, u16 wlength)
4810 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4811 wvalue, windex, buf, wlength);
4815 /* Handles hub TT buffer clear completions */
4816 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4817 struct usb_host_endpoint *ep)
4819 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4821 unsigned long flags;
4827 spin_lock_irqsave(&hsotg->lock, flags);
4828 qh->tt_buffer_dirty = 0;
4830 if (hsotg->flags.b.port_connect_status)
4831 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4833 spin_unlock_irqrestore(&hsotg->lock, flags);
4837 * HPRT0_SPD_HIGH_SPEED: high speed
4838 * HPRT0_SPD_FULL_SPEED: full speed
4840 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4842 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4844 if (hsotg->params.speed == speed)
4847 hsotg->params.speed = speed;
4848 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4851 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4853 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4855 if (!hsotg->params.change_speed_quirk)
4859 * On removal, set speed to default high-speed.
4861 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4862 udev->parent->speed < USB_SPEED_HIGH) {
4863 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4864 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4868 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4870 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4872 if (!hsotg->params.change_speed_quirk)
4875 if (udev->speed == USB_SPEED_HIGH) {
4876 dev_info(hsotg->dev, "Set speed to high-speed\n");
4877 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4878 } else if ((udev->speed == USB_SPEED_FULL ||
4879 udev->speed == USB_SPEED_LOW)) {
4881 * Change speed setting to full-speed if there's
4882 * a full-speed or low-speed device plugged in.
4884 dev_info(hsotg->dev, "Set speed to full-speed\n");
4885 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4891 static struct hc_driver dwc2_hc_driver = {
4892 .description = "dwc2_hsotg",
4893 .product_desc = "DWC OTG Controller",
4894 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4896 .irq = _dwc2_hcd_irq,
4897 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4899 .start = _dwc2_hcd_start,
4900 .stop = _dwc2_hcd_stop,
4901 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4902 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4903 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4904 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4905 .get_frame_number = _dwc2_hcd_get_frame_number,
4907 .hub_status_data = _dwc2_hcd_hub_status_data,
4908 .hub_control = _dwc2_hcd_hub_control,
4909 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4911 .bus_suspend = _dwc2_hcd_suspend,
4912 .bus_resume = _dwc2_hcd_resume,
4914 .map_urb_for_dma = dwc2_map_urb_for_dma,
4915 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4919 * Frees secondary storage associated with the dwc2_hsotg structure contained
4920 * in the struct usb_hcd field
4922 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4928 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4930 /* Free memory for QH/QTD lists */
4931 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4932 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4933 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4934 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4935 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4936 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4937 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4939 /* Free memory for the host channels */
4940 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4941 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4944 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4946 hsotg->hc_ptr_array[i] = NULL;
4951 if (hsotg->params.host_dma) {
4952 if (hsotg->status_buf) {
4953 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4955 hsotg->status_buf_dma);
4956 hsotg->status_buf = NULL;
4959 kfree(hsotg->status_buf);
4960 hsotg->status_buf = NULL;
4963 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
4965 /* Disable all interrupts */
4966 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
4967 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
4968 dwc2_writel(hsotg, 0, GINTMSK);
4970 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
4971 dctl = dwc2_readl(hsotg, DCTL);
4972 dctl |= DCTL_SFTDISCON;
4973 dwc2_writel(hsotg, dctl, DCTL);
4976 if (hsotg->wq_otg) {
4977 if (!cancel_work_sync(&hsotg->wf_otg))
4978 flush_workqueue(hsotg->wq_otg);
4979 destroy_workqueue(hsotg->wq_otg);
4982 cancel_work_sync(&hsotg->phy_reset_work);
4984 del_timer(&hsotg->wkp_timer);
4987 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
4989 /* Turn off all host-specific interrupts */
4990 dwc2_disable_host_interrupts(hsotg);
4992 dwc2_hcd_free(hsotg);
4996 * Initializes the HCD. This function allocates memory for and initializes the
4997 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
4998 * USB bus with the core and calls the hc_driver->start() function. It returns
4999 * a negative error on failure.
5001 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5003 struct platform_device *pdev = to_platform_device(hsotg->dev);
5004 struct resource *res;
5005 struct usb_hcd *hcd;
5006 struct dwc2_host_chan *channel;
5008 int i, num_channels;
5014 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5018 hcfg = dwc2_readl(hsotg, HCFG);
5019 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5021 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5022 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5023 sizeof(*hsotg->frame_num_array),
5025 if (!hsotg->frame_num_array)
5027 hsotg->last_frame_num_array =
5028 kcalloc(FRAME_NUM_ARRAY_SIZE,
5029 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5030 if (!hsotg->last_frame_num_array)
5033 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5035 /* Check if the bus driver or platform code has setup a dma_mask */
5036 if (hsotg->params.host_dma &&
5037 !hsotg->dev->dma_mask) {
5038 dev_warn(hsotg->dev,
5039 "dma_mask not set, disabling DMA\n");
5040 hsotg->params.host_dma = false;
5041 hsotg->params.dma_desc_enable = false;
5044 /* Set device flags indicating whether the HCD supports DMA */
5045 if (hsotg->params.host_dma) {
5046 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5047 dev_warn(hsotg->dev, "can't set DMA mask\n");
5048 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5049 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5052 if (hsotg->params.change_speed_quirk) {
5053 dwc2_hc_driver.free_dev = dwc2_free_dev;
5054 dwc2_hc_driver.reset_device = dwc2_reset_device;
5057 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5061 if (!hsotg->params.host_dma)
5062 hcd->self.uses_dma = 0;
5066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5067 hcd->rsrc_start = res->start;
5068 hcd->rsrc_len = resource_size(res);
5070 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5074 * Disable the global interrupt until all the interrupt handlers are
5077 dwc2_disable_global_interrupts(hsotg);
5079 /* Initialize the DWC_otg core, and select the Phy type */
5080 retval = dwc2_core_init(hsotg, true);
5084 /* Create new workqueue and init work */
5086 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5087 if (!hsotg->wq_otg) {
5088 dev_err(hsotg->dev, "Failed to create workqueue\n");
5091 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5093 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5095 /* Initialize the non-periodic schedule */
5096 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5097 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5098 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5100 /* Initialize the periodic schedule */
5101 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5102 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5103 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5104 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5106 INIT_LIST_HEAD(&hsotg->split_order);
5109 * Create a host channel descriptor for each host channel implemented
5110 * in the controller. Initialize the channel descriptor array.
5112 INIT_LIST_HEAD(&hsotg->free_hc_list);
5113 num_channels = hsotg->params.host_channels;
5114 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5116 for (i = 0; i < num_channels; i++) {
5117 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5120 channel->hc_num = i;
5121 INIT_LIST_HEAD(&channel->split_order_list_entry);
5122 hsotg->hc_ptr_array[i] = channel;
5125 /* Initialize work */
5126 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5127 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5128 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5131 * Allocate space for storing data on status transactions. Normally no
5132 * data is sent, but this space acts as a bit bucket. This must be
5133 * done after usb_add_hcd since that function allocates the DMA buffer
5136 if (hsotg->params.host_dma)
5137 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5138 DWC2_HCD_STATUS_BUF_SIZE,
5139 &hsotg->status_buf_dma, GFP_KERNEL);
5141 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5144 if (!hsotg->status_buf)
5148 * Create kmem caches to handle descriptor buffers in descriptor
5150 * Alignment must be set to 512 bytes.
5152 if (hsotg->params.dma_desc_enable ||
5153 hsotg->params.dma_desc_fs_enable) {
5154 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5155 sizeof(struct dwc2_dma_desc) *
5156 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5158 if (!hsotg->desc_gen_cache) {
5160 "unable to create dwc2 generic desc cache\n");
5163 * Disable descriptor dma mode since it will not be
5166 hsotg->params.dma_desc_enable = false;
5167 hsotg->params.dma_desc_fs_enable = false;
5170 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5171 sizeof(struct dwc2_dma_desc) *
5172 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5173 if (!hsotg->desc_hsisoc_cache) {
5175 "unable to create dwc2 hs isoc desc cache\n");
5177 kmem_cache_destroy(hsotg->desc_gen_cache);
5180 * Disable descriptor dma mode since it will not be
5183 hsotg->params.dma_desc_enable = false;
5184 hsotg->params.dma_desc_fs_enable = false;
5188 if (hsotg->params.host_dma) {
5190 * Create kmem caches to handle non-aligned buffer
5191 * in Buffer DMA mode.
5193 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5194 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5195 SLAB_CACHE_DMA, NULL);
5196 if (!hsotg->unaligned_cache)
5198 "unable to create dwc2 unaligned cache\n");
5201 hsotg->otg_port = 1;
5202 hsotg->frame_list = NULL;
5203 hsotg->frame_list_dma = 0;
5204 hsotg->periodic_qh_count = 0;
5206 /* Initiate lx_state to L3 disconnected state */
5207 hsotg->lx_state = DWC2_L3;
5209 hcd->self.otg_port = hsotg->otg_port;
5211 /* Don't support SG list at this point */
5212 hcd->self.sg_tablesize = 0;
5214 if (!IS_ERR_OR_NULL(hsotg->uphy))
5215 otg_set_host(hsotg->uphy->otg, &hcd->self);
5218 * Finish generic HCD initialization and start the HCD. This function
5219 * allocates the DMA buffer pool, registers the USB bus, requests the
5220 * IRQ line, and calls hcd_start method.
5222 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5226 device_wakeup_enable(hcd->self.controller);
5228 dwc2_hcd_dump_state(hsotg);
5230 dwc2_enable_global_interrupts(hsotg);
5235 kmem_cache_destroy(hsotg->unaligned_cache);
5236 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5237 kmem_cache_destroy(hsotg->desc_gen_cache);
5239 dwc2_hcd_release(hsotg);
5244 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5245 kfree(hsotg->last_frame_num_array);
5246 kfree(hsotg->frame_num_array);
5249 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5255 * Frees memory and resources associated with the HCD and deregisters the bus.
5257 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5259 struct usb_hcd *hcd;
5261 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5263 hcd = dwc2_hsotg_to_hcd(hsotg);
5264 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5267 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5272 if (!IS_ERR_OR_NULL(hsotg->uphy))
5273 otg_set_host(hsotg->uphy->otg, NULL);
5275 usb_remove_hcd(hcd);
5278 kmem_cache_destroy(hsotg->unaligned_cache);
5279 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5280 kmem_cache_destroy(hsotg->desc_gen_cache);
5282 dwc2_hcd_release(hsotg);
5285 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5286 kfree(hsotg->last_frame_num_array);
5287 kfree(hsotg->frame_num_array);
5292 * dwc2_backup_host_registers() - Backup controller host registers.
5293 * When suspending usb bus, registers needs to be backuped
5294 * if controller power is disabled once suspended.
5296 * @hsotg: Programming view of the DWC_otg controller
5298 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5300 struct dwc2_hregs_backup *hr;
5303 dev_dbg(hsotg->dev, "%s\n", __func__);
5305 /* Backup Host regs */
5306 hr = &hsotg->hr_backup;
5307 hr->hcfg = dwc2_readl(hsotg, HCFG);
5308 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5309 for (i = 0; i < hsotg->params.host_channels; ++i)
5310 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5312 hr->hprt0 = dwc2_read_hprt0(hsotg);
5313 hr->hfir = dwc2_readl(hsotg, HFIR);
5314 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5321 * dwc2_restore_host_registers() - Restore controller host registers.
5322 * When resuming usb bus, device registers needs to be restored
5323 * if controller power were disabled.
5325 * @hsotg: Programming view of the DWC_otg controller
5327 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5329 struct dwc2_hregs_backup *hr;
5332 dev_dbg(hsotg->dev, "%s\n", __func__);
5334 /* Restore host regs */
5335 hr = &hsotg->hr_backup;
5337 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5343 dwc2_writel(hsotg, hr->hcfg, HCFG);
5344 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5346 for (i = 0; i < hsotg->params.host_channels; ++i)
5347 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5349 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5350 dwc2_writel(hsotg, hr->hfir, HFIR);
5351 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5352 hsotg->frame_number = 0;
5358 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5360 * @hsotg: Programming view of the DWC_otg controller
5362 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5364 unsigned long flags;
5371 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5372 ret = dwc2_backup_global_registers(hsotg);
5374 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5378 ret = dwc2_backup_host_registers(hsotg);
5380 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5385 /* Enter USB Suspend Mode */
5386 hprt0 = dwc2_readl(hsotg, HPRT0);
5387 hprt0 |= HPRT0_SUSP;
5388 hprt0 &= ~HPRT0_ENA;
5389 dwc2_writel(hsotg, hprt0, HPRT0);
5391 /* Wait for the HPRT0.PrtSusp register field to be set */
5392 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5393 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5396 * We need to disable interrupts to prevent servicing of any IRQ
5397 * during going to hibernation
5399 spin_lock_irqsave(&hsotg->lock, flags);
5400 hsotg->lx_state = DWC2_L2;
5402 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5403 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5404 /* ULPI interface */
5405 /* Suspend the Phy Clock */
5406 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5407 pcgcctl |= PCGCTL_STOPPCLK;
5408 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5411 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5412 gpwrdn |= GPWRDN_PMUACTV;
5413 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5416 /* UTMI+ Interface */
5417 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5418 gpwrdn |= GPWRDN_PMUACTV;
5419 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5422 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5423 pcgcctl |= PCGCTL_STOPPCLK;
5424 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5428 /* Enable interrupts from wake up logic */
5429 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5430 gpwrdn |= GPWRDN_PMUINTSEL;
5431 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5434 /* Unmask host mode interrupts in GPWRDN */
5435 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5436 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5437 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5438 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5439 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5442 /* Enable Power Down Clamp */
5443 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5444 gpwrdn |= GPWRDN_PWRDNCLMP;
5445 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5448 /* Switch off VDD */
5449 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5450 gpwrdn |= GPWRDN_PWRDNSWTCH;
5451 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5453 hsotg->hibernated = 1;
5454 hsotg->bus_suspended = 1;
5455 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5456 spin_unlock_irqrestore(&hsotg->lock, flags);
5461 * dwc2_host_exit_hibernation()
5463 * @hsotg: Programming view of the DWC_otg controller
5464 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5465 * @param reset: indicates whether resume is initiated by Reset.
5467 * Return: non-zero if failed to enter to hibernation.
5469 * This function is for exiting from Host mode hibernation by
5470 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5472 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5478 struct dwc2_gregs_backup *gr;
5479 struct dwc2_hregs_backup *hr;
5481 gr = &hsotg->gr_backup;
5482 hr = &hsotg->hr_backup;
5485 "%s: called with rem_wakeup = %d reset = %d\n",
5486 __func__, rem_wakeup, reset);
5488 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5489 hsotg->hibernated = 0;
5492 * This step is not described in functional spec but if not wait for
5493 * this delay, mismatch interrupts occurred because just after restore
5494 * core is in Device mode(gintsts.curmode == 0)
5498 /* Clear all pending interupts */
5499 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5501 /* De-assert Restore */
5502 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5503 gpwrdn &= ~GPWRDN_RESTORE;
5504 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5507 /* Restore GUSBCFG, HCFG */
5508 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5509 dwc2_writel(hsotg, hr->hcfg, HCFG);
5511 /* De-assert Wakeup Logic */
5512 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5513 gpwrdn &= ~GPWRDN_PMUACTV;
5514 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5519 hprt0 &= ~HPRT0_ENA;
5520 hprt0 &= ~HPRT0_SUSP;
5521 dwc2_writel(hsotg, hprt0, HPRT0);
5525 hprt0 &= ~HPRT0_ENA;
5526 hprt0 &= ~HPRT0_SUSP;
5530 dwc2_writel(hsotg, hprt0, HPRT0);
5532 /* Wait for Resume time and then program HPRT again */
5534 hprt0 &= ~HPRT0_RST;
5535 dwc2_writel(hsotg, hprt0, HPRT0);
5538 dwc2_writel(hsotg, hprt0, HPRT0);
5540 /* Wait for Resume time and then program HPRT again */
5542 hprt0 &= ~HPRT0_RES;
5543 dwc2_writel(hsotg, hprt0, HPRT0);
5545 /* Clear all interrupt status */
5546 hprt0 = dwc2_readl(hsotg, HPRT0);
5547 hprt0 |= HPRT0_CONNDET;
5548 hprt0 |= HPRT0_ENACHG;
5549 hprt0 &= ~HPRT0_ENA;
5550 dwc2_writel(hsotg, hprt0, HPRT0);
5552 hprt0 = dwc2_readl(hsotg, HPRT0);
5554 /* Clear all pending interupts */
5555 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5557 /* Restore global registers */
5558 ret = dwc2_restore_global_registers(hsotg);
5560 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5565 /* Restore host registers */
5566 ret = dwc2_restore_host_registers(hsotg);
5568 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5573 dwc2_hcd_rem_wakeup(hsotg);
5575 hsotg->hibernated = 0;
5576 hsotg->bus_suspended = 0;
5577 hsotg->lx_state = DWC2_L0;
5578 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");