1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the core HCD code, and implements the Linux hc_driver
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
80 /* Clear any pending interrupts */
81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
97 dwc2_writel(hsotg, intmsk, GINTMSK);
101 * Initializes the FSLSPClkSel field of the HCFG register depending on the
104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110 hsotg->params.ulpi_fs_ls) ||
111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
113 val = HCFG_FSLSPCLKSEL_48_MHZ;
115 /* High speed PHY running at full speed or high speed */
116 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg, HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hsotg, hcfg, HCFG);
126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
128 u32 usbcfg, ggpio, i2cctl;
132 * core_init() is now called on every switch so only call the
133 * following for the first time through
136 dev_dbg(hsotg->dev, "FS PHY selected\n");
138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(hsotg, usbcfg, GUSBCFG);
143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false);
148 "%s: Reset failed, aborting", __func__);
153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg, GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n");
158 * STM32F4x9 uses the GGPIO register as general
159 * core configuration register.
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(hsotg, ggpio, GGPIO);
168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
169 * do this on HNP Dev/Host mode switches (done in dev_init and
172 if (dwc2_is_host_mode(hsotg))
173 dwc2_init_fs_ls_pclk_sel(hsotg);
175 if (hsotg->params.i2c_enable) {
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg, GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(hsotg, usbcfg, GUSBCFG);
183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg, GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(hsotg, i2cctl, GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(hsotg, i2cctl, GI2CCTL);
196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
198 u32 usbcfg, usbcfg_old;
204 usbcfg = dwc2_readl(hsotg, GUSBCFG);
208 * HS PHY parameters. These parameters are preserved during soft reset
209 * so only program the first time. Do a soft reset immediately after
212 switch (hsotg->params.phy_type) {
213 case DWC2_PHY_TYPE_PARAM_ULPI:
215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218 if (hsotg->params.phy_ulpi_ddr)
219 usbcfg |= GUSBCFG_DDRSEL;
221 /* Set external VBUS indicator as needed. */
222 if (hsotg->params.oc_disable)
223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224 GUSBCFG_INDICATORPASSTHROUGH);
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227 /* UTMI+ interface */
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->params.phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(hsotg, usbcfg, GUSBCFG);
241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false);
245 "%s: Reset failed, aborting", __func__);
253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261 /* If FS/LS mode with FS/LS PHY */
262 retval = dwc2_fs_phy_init(hsotg, select_phy);
267 retval = dwc2_hs_phy_init(hsotg, select_phy);
272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg, GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(hsotg, usbcfg, GUSBCFG);
281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
292 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH:
296 dev_err(hsotg->dev, "External DMA Mode not supported\n");
299 case GHWCFG2_INT_DMA_ARCH:
300 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
301 if (hsotg->params.ahbcfg != -1) {
302 ahbcfg &= GAHBCFG_CTRL_MASK;
303 ahbcfg |= hsotg->params.ahbcfg &
308 case GHWCFG2_SLAVE_ONLY_ARCH:
310 dev_dbg(hsotg->dev, "Slave Only Mode\n");
314 if (hsotg->params.host_dma)
315 ahbcfg |= GAHBCFG_DMA_EN;
317 hsotg->params.dma_desc_enable = false;
319 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
328 usbcfg = dwc2_readl(hsotg, GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
331 switch (hsotg->hw_params.op_mode) {
332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
333 if (hsotg->params.otg_cap ==
334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
335 usbcfg |= GUSBCFG_HNPCAP;
336 if (hsotg->params.otg_cap !=
337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_SRPCAP;
341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
344 if (hsotg->params.otg_cap !=
345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
346 usbcfg |= GUSBCFG_SRPCAP;
349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
356 dwc2_writel(hsotg, usbcfg, GUSBCFG);
359 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
361 if (hsotg->vbus_supply)
362 return regulator_enable(hsotg->vbus_supply);
367 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
369 if (hsotg->vbus_supply)
370 return regulator_disable(hsotg->vbus_supply);
376 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
378 * @hsotg: Programming view of DWC_otg controller
380 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
384 dev_dbg(hsotg->dev, "%s()\n", __func__);
386 /* Disable all interrupts */
387 dwc2_writel(hsotg, 0, GINTMSK);
388 dwc2_writel(hsotg, 0, HAINTMSK);
390 /* Enable the common interrupts */
391 dwc2_enable_common_interrupts(hsotg);
393 /* Enable host mode interrupts without disturbing common interrupts */
394 intmsk = dwc2_readl(hsotg, GINTMSK);
395 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
396 dwc2_writel(hsotg, intmsk, GINTMSK);
400 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
402 * @hsotg: Programming view of DWC_otg controller
404 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
406 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
408 /* Disable host mode interrupts without disturbing common interrupts */
409 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
410 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
411 dwc2_writel(hsotg, intmsk, GINTMSK);
415 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
416 * For system that have a total fifo depth that is smaller than the default
419 * @hsotg: Programming view of DWC_otg controller
421 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
423 struct dwc2_core_params *params = &hsotg->params;
424 struct dwc2_hw_params *hw = &hsotg->hw_params;
425 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
427 total_fifo_size = hw->total_fifo_size;
428 rxfsiz = params->host_rx_fifo_size;
429 nptxfsiz = params->host_nperio_tx_fifo_size;
430 ptxfsiz = params->host_perio_tx_fifo_size;
433 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
434 * allocation with support for high bandwidth endpoints. Synopsys
435 * defines MPS(Max Packet size) for a periodic EP=1024, and for
436 * non-periodic as 512.
438 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
440 * For Buffer DMA mode/Scatter Gather DMA mode
441 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
442 * with n = number of host channel.
443 * 2 * ((1024/4) + 2) = 516
445 rxfsiz = 516 + hw->host_channels;
448 * min non-periodic tx fifo depth
449 * 2 * (largest non-periodic USB packet used / 4)
455 * min periodic tx fifo depth
456 * (largest packet size*MC)/4
461 params->host_rx_fifo_size = rxfsiz;
462 params->host_nperio_tx_fifo_size = nptxfsiz;
463 params->host_perio_tx_fifo_size = ptxfsiz;
467 * If the summation of RX, NPTX and PTX fifo sizes is still
468 * bigger than the total_fifo_size, then we have a problem.
470 * We won't be able to allocate as many endpoints. Right now,
471 * we're just printing an error message, but ideally this FIFO
472 * allocation algorithm would be improved in the future.
474 * FIXME improve this FIFO allocation algorithm.
476 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
477 dev_err(hsotg->dev, "invalid fifo sizes\n");
480 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
482 struct dwc2_core_params *params = &hsotg->params;
483 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
485 if (!params->enable_dynamic_fifo)
488 dwc2_calculate_dynamic_fifo(hsotg);
491 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
492 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
493 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
494 grxfsiz |= params->host_rx_fifo_size <<
495 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
496 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
497 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
498 dwc2_readl(hsotg, GRXFSIZ));
500 /* Non-periodic Tx FIFO */
501 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
502 dwc2_readl(hsotg, GNPTXFSIZ));
503 nptxfsiz = params->host_nperio_tx_fifo_size <<
504 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
505 nptxfsiz |= params->host_rx_fifo_size <<
506 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
507 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
508 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
509 dwc2_readl(hsotg, GNPTXFSIZ));
511 /* Periodic Tx FIFO */
512 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
513 dwc2_readl(hsotg, HPTXFSIZ));
514 hptxfsiz = params->host_perio_tx_fifo_size <<
515 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
516 hptxfsiz |= (params->host_rx_fifo_size +
517 params->host_nperio_tx_fifo_size) <<
518 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
519 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
520 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
521 dwc2_readl(hsotg, HPTXFSIZ));
523 if (hsotg->params.en_multiple_tx_fifo &&
524 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
526 * This feature was implemented in 2.91a version
527 * Global DFIFOCFG calculation for Host mode -
528 * include RxFIFO, NPTXFIFO and HPTXFIFO
530 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
531 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
532 dfifocfg |= (params->host_rx_fifo_size +
533 params->host_nperio_tx_fifo_size +
534 params->host_perio_tx_fifo_size) <<
535 GDFIFOCFG_EPINFOBASE_SHIFT &
536 GDFIFOCFG_EPINFOBASE_MASK;
537 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
542 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
543 * the HFIR register according to PHY type and speed
545 * @hsotg: Programming view of DWC_otg controller
547 * NOTE: The caller can modify the value of the HFIR register only after the
548 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
551 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
555 int clock = 60; /* default value */
557 usbcfg = dwc2_readl(hsotg, GUSBCFG);
558 hprt0 = dwc2_readl(hsotg, HPRT0);
560 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
561 !(usbcfg & GUSBCFG_PHYIF16))
563 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
564 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
566 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
567 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
569 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
570 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
572 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
573 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
575 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
576 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
578 if ((usbcfg & GUSBCFG_PHYSEL) &&
579 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
582 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
583 /* High speed case */
584 return 125 * clock - 1;
587 return 1000 * clock - 1;
591 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
594 * @hsotg: Programming view of DWC_otg controller
595 * @dest: Destination buffer for the packet
596 * @bytes: Number of bytes to copy to the destination
598 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
600 u32 *data_buf = (u32 *)dest;
601 int word_count = (bytes + 3) / 4;
605 * Todo: Account for the case where dest is not dword aligned. This
606 * requires reading data from the FIFO into a u32 temp buffer, then
607 * moving it into the data buffer.
610 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
612 for (i = 0; i < word_count; i++, data_buf++)
613 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
617 * dwc2_dump_channel_info() - Prints the state of a host channel
619 * @hsotg: Programming view of DWC_otg controller
620 * @chan: Pointer to the channel to dump
622 * Must be called with interrupt disabled and spinlock held
624 * NOTE: This function will be removed once the peripheral controller code
625 * is integrated and the driver is stable
627 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
628 struct dwc2_host_chan *chan)
631 int num_channels = hsotg->params.host_channels;
642 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
643 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
644 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
645 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
647 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
648 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
650 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
652 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
653 chan->dev_addr, chan->ep_num, chan->ep_is_in);
654 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
655 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
656 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
657 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
658 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
659 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
660 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
661 (unsigned long)chan->xfer_dma);
662 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
663 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
664 dev_dbg(hsotg->dev, " NP inactive sched:\n");
665 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
667 dev_dbg(hsotg->dev, " %p\n", qh);
668 dev_dbg(hsotg->dev, " NP waiting sched:\n");
669 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
671 dev_dbg(hsotg->dev, " %p\n", qh);
672 dev_dbg(hsotg->dev, " NP active sched:\n");
673 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
675 dev_dbg(hsotg->dev, " %p\n", qh);
676 dev_dbg(hsotg->dev, " Channels:\n");
677 for (i = 0; i < num_channels; i++) {
678 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
680 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
682 #endif /* VERBOSE_DEBUG */
685 static int _dwc2_hcd_start(struct usb_hcd *hcd);
687 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
689 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
691 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
692 _dwc2_hcd_start(hcd);
695 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
697 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
699 hcd->self.is_b_host = 0;
702 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
703 int *hub_addr, int *hub_port)
705 struct urb *urb = context;
708 *hub_addr = urb->dev->tt->hub->devnum;
711 *hub_port = urb->dev->ttport;
715 * =========================================================================
716 * Low Level Host Channel Access Functions
717 * =========================================================================
720 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
721 struct dwc2_host_chan *chan)
723 u32 hcintmsk = HCINTMSK_CHHLTD;
725 switch (chan->ep_type) {
726 case USB_ENDPOINT_XFER_CONTROL:
727 case USB_ENDPOINT_XFER_BULK:
728 dev_vdbg(hsotg->dev, "control/bulk\n");
729 hcintmsk |= HCINTMSK_XFERCOMPL;
730 hcintmsk |= HCINTMSK_STALL;
731 hcintmsk |= HCINTMSK_XACTERR;
732 hcintmsk |= HCINTMSK_DATATGLERR;
733 if (chan->ep_is_in) {
734 hcintmsk |= HCINTMSK_BBLERR;
736 hcintmsk |= HCINTMSK_NAK;
737 hcintmsk |= HCINTMSK_NYET;
739 hcintmsk |= HCINTMSK_ACK;
742 if (chan->do_split) {
743 hcintmsk |= HCINTMSK_NAK;
744 if (chan->complete_split)
745 hcintmsk |= HCINTMSK_NYET;
747 hcintmsk |= HCINTMSK_ACK;
750 if (chan->error_state)
751 hcintmsk |= HCINTMSK_ACK;
754 case USB_ENDPOINT_XFER_INT:
756 dev_vdbg(hsotg->dev, "intr\n");
757 hcintmsk |= HCINTMSK_XFERCOMPL;
758 hcintmsk |= HCINTMSK_NAK;
759 hcintmsk |= HCINTMSK_STALL;
760 hcintmsk |= HCINTMSK_XACTERR;
761 hcintmsk |= HCINTMSK_DATATGLERR;
762 hcintmsk |= HCINTMSK_FRMOVRUN;
765 hcintmsk |= HCINTMSK_BBLERR;
766 if (chan->error_state)
767 hcintmsk |= HCINTMSK_ACK;
768 if (chan->do_split) {
769 if (chan->complete_split)
770 hcintmsk |= HCINTMSK_NYET;
772 hcintmsk |= HCINTMSK_ACK;
776 case USB_ENDPOINT_XFER_ISOC:
778 dev_vdbg(hsotg->dev, "isoc\n");
779 hcintmsk |= HCINTMSK_XFERCOMPL;
780 hcintmsk |= HCINTMSK_FRMOVRUN;
781 hcintmsk |= HCINTMSK_ACK;
783 if (chan->ep_is_in) {
784 hcintmsk |= HCINTMSK_XACTERR;
785 hcintmsk |= HCINTMSK_BBLERR;
789 dev_err(hsotg->dev, "## Unknown EP type ##\n");
793 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
795 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
798 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
799 struct dwc2_host_chan *chan)
801 u32 hcintmsk = HCINTMSK_CHHLTD;
804 * For Descriptor DMA mode core halts the channel on AHB error.
805 * Interrupt is not required.
807 if (!hsotg->params.dma_desc_enable) {
809 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
810 hcintmsk |= HCINTMSK_AHBERR;
813 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
814 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
815 hcintmsk |= HCINTMSK_XFERCOMPL;
818 if (chan->error_state && !chan->do_split &&
819 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
821 dev_vdbg(hsotg->dev, "setting ACK\n");
822 hcintmsk |= HCINTMSK_ACK;
823 if (chan->ep_is_in) {
824 hcintmsk |= HCINTMSK_DATATGLERR;
825 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
826 hcintmsk |= HCINTMSK_NAK;
830 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
832 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
835 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
836 struct dwc2_host_chan *chan)
840 if (hsotg->params.host_dma) {
842 dev_vdbg(hsotg->dev, "DMA enabled\n");
843 dwc2_hc_enable_dma_ints(hsotg, chan);
846 dev_vdbg(hsotg->dev, "DMA disabled\n");
847 dwc2_hc_enable_slave_ints(hsotg, chan);
850 /* Enable the top level host channel interrupt */
851 intmsk = dwc2_readl(hsotg, HAINTMSK);
852 intmsk |= 1 << chan->hc_num;
853 dwc2_writel(hsotg, intmsk, HAINTMSK);
855 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
857 /* Make sure host channel interrupts are enabled */
858 intmsk = dwc2_readl(hsotg, GINTMSK);
859 intmsk |= GINTSTS_HCHINT;
860 dwc2_writel(hsotg, intmsk, GINTMSK);
862 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
866 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
867 * a specific endpoint
869 * @hsotg: Programming view of DWC_otg controller
870 * @chan: Information needed to initialize the host channel
872 * The HCCHARn register is set up with the characteristics specified in chan.
873 * Host channel interrupts that may need to be serviced while this transfer is
874 * in progress are enabled.
876 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
878 u8 hc_num = chan->hc_num;
884 dev_vdbg(hsotg->dev, "%s()\n", __func__);
886 /* Clear old interrupt conditions for this host channel */
887 hcintmsk = 0xffffffff;
888 hcintmsk &= ~HCINTMSK_RESERVED14_31;
889 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
891 /* Enable channel interrupts required for this transfer */
892 dwc2_hc_enable_ints(hsotg, chan);
895 * Program the HCCHARn register with the endpoint characteristics for
896 * the current transfer
898 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
899 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
901 hcchar |= HCCHAR_EPDIR;
902 if (chan->speed == USB_SPEED_LOW)
903 hcchar |= HCCHAR_LSPDDEV;
904 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
905 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
906 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
908 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
911 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
913 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
915 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
917 dev_vdbg(hsotg->dev, " Is In: %d\n",
919 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
920 chan->speed == USB_SPEED_LOW);
921 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
923 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
927 /* Program the HCSPLT register for SPLITs */
928 if (chan->do_split) {
931 "Programming HC %d with split --> %s\n",
933 chan->complete_split ? "CSPLIT" : "SSPLIT");
934 if (chan->complete_split)
935 hcsplt |= HCSPLT_COMPSPLT;
936 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
938 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
940 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
943 dev_vdbg(hsotg->dev, " comp split %d\n",
944 chan->complete_split);
945 dev_vdbg(hsotg->dev, " xact pos %d\n",
947 dev_vdbg(hsotg->dev, " hub addr %d\n",
949 dev_vdbg(hsotg->dev, " hub port %d\n",
951 dev_vdbg(hsotg->dev, " is_in %d\n",
953 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
955 dev_vdbg(hsotg->dev, " xferlen %d\n",
960 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
964 * dwc2_hc_halt() - Attempts to halt a host channel
966 * @hsotg: Controller register interface
967 * @chan: Host channel to halt
968 * @halt_status: Reason for halting the channel
970 * This function should only be called in Slave mode or to abort a transfer in
971 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
972 * controller halts the channel when the transfer is complete or a condition
973 * occurs that requires application intervention.
975 * In slave mode, checks for a free request queue entry, then sets the Channel
976 * Enable and Channel Disable bits of the Host Channel Characteristics
977 * register of the specified channel to intiate the halt. If there is no free
978 * request queue entry, sets only the Channel Disable bit of the HCCHARn
979 * register to flush requests for this channel. In the latter case, sets a
980 * flag to indicate that the host channel needs to be halted when a request
981 * queue slot is open.
983 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
984 * HCCHARn register. The controller ensures there is space in the request
985 * queue before submitting the halt request.
987 * Some time may elapse before the core flushes any posted requests for this
988 * host channel and halts. The Channel Halted interrupt handler completes the
989 * deactivation of the host channel.
991 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
992 enum dwc2_halt_status halt_status)
994 u32 nptxsts, hptxsts, hcchar;
997 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1000 * In buffer DMA or external DMA mode channel can't be halted
1001 * for non-split periodic channels. At the end of the next
1002 * uframe/frame (in the worst case), the core generates a channel
1003 * halted and disables the channel automatically.
1005 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1006 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1007 if (!chan->do_split &&
1008 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1009 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1010 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1016 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1017 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1019 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1020 halt_status == DWC2_HC_XFER_AHB_ERR) {
1022 * Disable all channel interrupts except Ch Halted. The QTD
1023 * and QH state associated with this transfer has been cleared
1024 * (in the case of URB_DEQUEUE), so the channel needs to be
1025 * shut down carefully to prevent crashes.
1027 u32 hcintmsk = HCINTMSK_CHHLTD;
1029 dev_vdbg(hsotg->dev, "dequeue/error\n");
1030 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
1033 * Make sure no other interrupts besides halt are currently
1034 * pending. Handling another interrupt could cause a crash due
1035 * to the QTD and QH state.
1037 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
1040 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1041 * even if the channel was already halted for some other
1044 chan->halt_status = halt_status;
1046 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1047 if (!(hcchar & HCCHAR_CHENA)) {
1049 * The channel is either already halted or it hasn't
1050 * started yet. In DMA mode, the transfer may halt if
1051 * it finishes normally or a condition occurs that
1052 * requires driver intervention. Don't want to halt
1053 * the channel again. In either Slave or DMA mode,
1054 * it's possible that the transfer has been assigned
1055 * to a channel, but not started yet when an URB is
1056 * dequeued. Don't want to halt a channel that hasn't
1062 if (chan->halt_pending) {
1064 * A halt has already been issued for this channel. This might
1065 * happen when a transfer is aborted by a higher level in
1068 dev_vdbg(hsotg->dev,
1069 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1070 __func__, chan->hc_num);
1074 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1076 /* No need to set the bit in DDMA for disabling the channel */
1077 /* TODO check it everywhere channel is disabled */
1078 if (!hsotg->params.dma_desc_enable) {
1080 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1081 hcchar |= HCCHAR_CHENA;
1084 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1086 hcchar |= HCCHAR_CHDIS;
1088 if (!hsotg->params.host_dma) {
1090 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1091 hcchar |= HCCHAR_CHENA;
1093 /* Check for space in the request queue to issue the halt */
1094 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1095 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1096 dev_vdbg(hsotg->dev, "control/bulk\n");
1097 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
1098 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1099 dev_vdbg(hsotg->dev, "Disabling channel\n");
1100 hcchar &= ~HCCHAR_CHENA;
1104 dev_vdbg(hsotg->dev, "isoc/intr\n");
1105 hptxsts = dwc2_readl(hsotg, HPTXSTS);
1106 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1107 hsotg->queuing_high_bandwidth) {
1109 dev_vdbg(hsotg->dev, "Disabling channel\n");
1110 hcchar &= ~HCCHAR_CHENA;
1115 dev_vdbg(hsotg->dev, "DMA enabled\n");
1118 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1119 chan->halt_status = halt_status;
1121 if (hcchar & HCCHAR_CHENA) {
1123 dev_vdbg(hsotg->dev, "Channel enabled\n");
1124 chan->halt_pending = 1;
1125 chan->halt_on_queue = 0;
1128 dev_vdbg(hsotg->dev, "Channel disabled\n");
1129 chan->halt_on_queue = 1;
1133 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1135 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1137 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1138 chan->halt_pending);
1139 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1140 chan->halt_on_queue);
1141 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1147 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1149 * @hsotg: Programming view of DWC_otg controller
1150 * @chan: Identifies the host channel to clean up
1152 * This function is normally called after a transfer is done and the host
1153 * channel is being released
1155 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1159 chan->xfer_started = 0;
1161 list_del_init(&chan->split_order_list_entry);
1164 * Clear channel interrupt enables and any unhandled channel interrupt
1167 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
1168 hcintmsk = 0xffffffff;
1169 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1170 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
1174 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1175 * which frame a periodic transfer should occur
1177 * @hsotg: Programming view of DWC_otg controller
1178 * @chan: Identifies the host channel to set up and its properties
1179 * @hcchar: Current value of the HCCHAR register for the specified host channel
1181 * This function has no effect on non-periodic transfers
1183 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1184 struct dwc2_host_chan *chan, u32 *hcchar)
1186 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1187 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1197 * Try to figure out if we're an even or odd frame. If we set
1198 * even and the current frame number is even the the transfer
1199 * will happen immediately. Similar if both are odd. If one is
1200 * even and the other is odd then the transfer will happen when
1201 * the frame number ticks.
1203 * There's a bit of a balancing act to get this right.
1204 * Sometimes we may want to send data in the current frame (AK
1205 * right away). We might want to do this if the frame number
1206 * _just_ ticked, but we might also want to do this in order
1207 * to continue a split transaction that happened late in a
1208 * microframe (so we didn't know to queue the next transfer
1209 * until the frame number had ticked). The problem is that we
1210 * need a lot of knowledge to know if there's actually still
1211 * time to send things or if it would be better to wait until
1214 * We can look at how much time is left in the current frame
1215 * and make a guess about whether we'll have time to transfer.
1219 /* Get speed host is running at */
1220 host_speed = (chan->speed != USB_SPEED_HIGH &&
1221 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1223 /* See how many bytes are in the periodic FIFO right now */
1224 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1225 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1226 bytes_in_fifo = sizeof(u32) *
1227 (hsotg->params.host_perio_tx_fifo_size -
1231 * Roughly estimate bus time for everything in the periodic
1232 * queue + our new transfer. This is "rough" because we're
1233 * using a function that makes takes into account IN/OUT
1234 * and INT/ISO and we're just slamming in one value for all
1235 * transfers. This should be an over-estimate and that should
1236 * be OK, but we can probably tighten it.
1238 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1239 chan->xfer_len + bytes_in_fifo);
1240 xfer_us = NS_TO_US(xfer_ns);
1242 /* See what frame number we'll be at by the time we finish */
1243 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1245 /* This is when we were scheduled to be on the wire */
1246 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1249 * If we'd finish _after_ the frame we're scheduled in then
1250 * it's hopeless. Just schedule right away and hope for the
1251 * best. Note that it _might_ be wise to call back into the
1252 * scheduler to pick a better frame, but this is better than
1255 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1256 dwc2_sch_vdbg(hsotg,
1257 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1258 chan->qh, wire_frame, frame_number,
1259 dwc2_frame_num_dec(frame_number,
1261 wire_frame = frame_number;
1264 * We picked a different frame number; communicate this
1265 * back to the scheduler so it doesn't try to schedule
1266 * another in the same frame.
1268 * Remember that next_active_frame is 1 before the wire
1271 chan->qh->next_active_frame =
1272 dwc2_frame_num_dec(frame_number, 1);
1276 *hcchar |= HCCHAR_ODDFRM;
1278 *hcchar &= ~HCCHAR_ODDFRM;
1282 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1284 /* Set up the initial PID for the transfer */
1285 if (chan->speed == USB_SPEED_HIGH) {
1286 if (chan->ep_is_in) {
1287 if (chan->multi_count == 1)
1288 chan->data_pid_start = DWC2_HC_PID_DATA0;
1289 else if (chan->multi_count == 2)
1290 chan->data_pid_start = DWC2_HC_PID_DATA1;
1292 chan->data_pid_start = DWC2_HC_PID_DATA2;
1294 if (chan->multi_count == 1)
1295 chan->data_pid_start = DWC2_HC_PID_DATA0;
1297 chan->data_pid_start = DWC2_HC_PID_MDATA;
1300 chan->data_pid_start = DWC2_HC_PID_DATA0;
1305 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1308 * @hsotg: Programming view of DWC_otg controller
1309 * @chan: Information needed to initialize the host channel
1311 * This function should only be called in Slave mode. For a channel associated
1312 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1313 * associated with a periodic EP, the periodic Tx FIFO is written.
1315 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1316 * the number of bytes written to the Tx FIFO.
1318 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1319 struct dwc2_host_chan *chan)
1322 u32 remaining_count;
1325 u32 *data_buf = (u32 *)chan->xfer_buf;
1328 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1330 remaining_count = chan->xfer_len - chan->xfer_count;
1331 if (remaining_count > chan->max_packet)
1332 byte_count = chan->max_packet;
1334 byte_count = remaining_count;
1336 dword_count = (byte_count + 3) / 4;
1338 if (((unsigned long)data_buf & 0x3) == 0) {
1339 /* xfer_buf is DWORD aligned */
1340 for (i = 0; i < dword_count; i++, data_buf++)
1341 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1343 /* xfer_buf is not DWORD aligned */
1344 for (i = 0; i < dword_count; i++, data_buf++) {
1345 u32 data = data_buf[0] | data_buf[1] << 8 |
1346 data_buf[2] << 16 | data_buf[3] << 24;
1347 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1351 chan->xfer_count += byte_count;
1352 chan->xfer_buf += byte_count;
1356 * dwc2_hc_do_ping() - Starts a PING transfer
1358 * @hsotg: Programming view of DWC_otg controller
1359 * @chan: Information needed to initialize the host channel
1361 * This function should only be called in Slave mode. The Do Ping bit is set in
1362 * the HCTSIZ register, then the channel is enabled.
1364 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1365 struct dwc2_host_chan *chan)
1371 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1374 hctsiz = TSIZ_DOPNG;
1375 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1376 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1378 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1379 hcchar |= HCCHAR_CHENA;
1380 hcchar &= ~HCCHAR_CHDIS;
1381 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1385 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1386 * channel and starts the transfer
1388 * @hsotg: Programming view of DWC_otg controller
1389 * @chan: Information needed to initialize the host channel. The xfer_len value
1390 * may be reduced to accommodate the max widths of the XferSize and
1391 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1392 * changed to reflect the final xfer_len value.
1394 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1395 * the caller must ensure that there is sufficient space in the request queue
1398 * For an OUT transfer in Slave mode, it loads a data packet into the
1399 * appropriate FIFO. If necessary, additional data packets are loaded in the
1402 * For an IN transfer in Slave mode, a data packet is requested. The data
1403 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1404 * additional data packets are requested in the Host ISR.
1406 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1407 * register along with a packet count of 1 and the channel is enabled. This
1408 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1409 * simply set to 0 since no data transfer occurs in this case.
1411 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1412 * all the information required to perform the subsequent data transfer. In
1413 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1414 * controller performs the entire PING protocol, then starts the data
1417 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1418 struct dwc2_host_chan *chan)
1420 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1421 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1428 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1430 if (chan->do_ping) {
1431 if (!hsotg->params.host_dma) {
1433 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1434 dwc2_hc_do_ping(hsotg, chan);
1435 chan->xfer_started = 1;
1440 dev_vdbg(hsotg->dev, "ping, DMA\n");
1442 hctsiz |= TSIZ_DOPNG;
1445 if (chan->do_split) {
1447 dev_vdbg(hsotg->dev, "split\n");
1450 if (chan->complete_split && !chan->ep_is_in)
1452 * For CSPLIT OUT Transfer, set the size to 0 so the
1453 * core doesn't expect any data written to the FIFO
1456 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1457 chan->xfer_len = chan->max_packet;
1458 else if (!chan->ep_is_in && chan->xfer_len > 188)
1459 chan->xfer_len = 188;
1461 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1464 /* For split set ec_mc for immediate retries */
1465 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1466 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1472 dev_vdbg(hsotg->dev, "no split\n");
1474 * Ensure that the transfer length and packet count will fit
1475 * in the widths allocated for them in the HCTSIZn register
1477 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1478 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1480 * Make sure the transfer size is no larger than one
1481 * (micro)frame's worth of data. (A check was done
1482 * when the periodic transfer was accepted to ensure
1483 * that a (micro)frame's worth of data can be
1484 * programmed into a channel.)
1486 u32 max_periodic_len =
1487 chan->multi_count * chan->max_packet;
1489 if (chan->xfer_len > max_periodic_len)
1490 chan->xfer_len = max_periodic_len;
1491 } else if (chan->xfer_len > max_hc_xfer_size) {
1493 * Make sure that xfer_len is a multiple of max packet
1497 max_hc_xfer_size - chan->max_packet + 1;
1500 if (chan->xfer_len > 0) {
1501 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1503 if (num_packets > max_hc_pkt_count) {
1504 num_packets = max_hc_pkt_count;
1505 chan->xfer_len = num_packets * chan->max_packet;
1508 /* Need 1 packet for transfer length of 0 */
1514 * Always program an integral # of max packets for IN
1517 chan->xfer_len = num_packets * chan->max_packet;
1519 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1520 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1522 * Make sure that the multi_count field matches the
1523 * actual transfer length
1525 chan->multi_count = num_packets;
1527 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1528 dwc2_set_pid_isoc(chan);
1530 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1533 /* The ec_mc gets the multi_count for non-split */
1534 ec_mc = chan->multi_count;
1537 chan->start_pkt_count = num_packets;
1538 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1539 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1540 TSIZ_SC_MC_PID_MASK;
1541 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1543 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1544 hctsiz, chan->hc_num);
1546 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1548 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1549 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1550 TSIZ_XFERSIZE_SHIFT);
1551 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1552 (hctsiz & TSIZ_PKTCNT_MASK) >>
1554 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1555 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1556 TSIZ_SC_MC_PID_SHIFT);
1559 if (hsotg->params.host_dma) {
1560 dma_addr_t dma_addr;
1562 if (chan->align_buf) {
1564 dev_vdbg(hsotg->dev, "align_buf\n");
1565 dma_addr = chan->align_buf;
1567 dma_addr = chan->xfer_dma;
1569 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1572 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1573 (unsigned long)dma_addr, chan->hc_num);
1576 /* Start the split */
1577 if (chan->do_split) {
1578 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1580 hcsplt |= HCSPLT_SPLTENA;
1581 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1584 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1585 hcchar &= ~HCCHAR_MULTICNT_MASK;
1586 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1587 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1589 if (hcchar & HCCHAR_CHDIS)
1590 dev_warn(hsotg->dev,
1591 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1592 __func__, chan->hc_num, hcchar);
1594 /* Set host channel enable after all other setup is complete */
1595 hcchar |= HCCHAR_CHENA;
1596 hcchar &= ~HCCHAR_CHDIS;
1599 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1600 (hcchar & HCCHAR_MULTICNT_MASK) >>
1601 HCCHAR_MULTICNT_SHIFT);
1603 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1605 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1608 chan->xfer_started = 1;
1611 if (!hsotg->params.host_dma &&
1612 !chan->ep_is_in && chan->xfer_len > 0)
1613 /* Load OUT packet into the appropriate Tx FIFO */
1614 dwc2_hc_write_packet(hsotg, chan);
1618 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1619 * host channel and starts the transfer in Descriptor DMA mode
1621 * @hsotg: Programming view of DWC_otg controller
1622 * @chan: Information needed to initialize the host channel
1624 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1625 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1626 * with micro-frame bitmap.
1628 * Initializes HCDMA register with descriptor list address and CTD value then
1629 * starts the transfer via enabling the channel.
1631 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1632 struct dwc2_host_chan *chan)
1638 hctsiz |= TSIZ_DOPNG;
1640 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1641 dwc2_set_pid_isoc(chan);
1643 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1644 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1645 TSIZ_SC_MC_PID_MASK;
1647 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1648 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1650 /* Non-zero only for high-speed interrupt endpoints */
1651 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1654 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1656 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1657 chan->data_pid_start);
1658 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1661 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1663 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1664 chan->desc_list_sz, DMA_TO_DEVICE);
1666 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1669 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1670 &chan->desc_list_addr, chan->hc_num);
1672 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1673 hcchar &= ~HCCHAR_MULTICNT_MASK;
1674 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1675 HCCHAR_MULTICNT_MASK;
1677 if (hcchar & HCCHAR_CHDIS)
1678 dev_warn(hsotg->dev,
1679 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1680 __func__, chan->hc_num, hcchar);
1682 /* Set host channel enable after all other setup is complete */
1683 hcchar |= HCCHAR_CHENA;
1684 hcchar &= ~HCCHAR_CHDIS;
1687 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1688 (hcchar & HCCHAR_MULTICNT_MASK) >>
1689 HCCHAR_MULTICNT_SHIFT);
1691 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1693 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1696 chan->xfer_started = 1;
1701 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1702 * a previous call to dwc2_hc_start_transfer()
1704 * @hsotg: Programming view of DWC_otg controller
1705 * @chan: Information needed to initialize the host channel
1707 * The caller must ensure there is sufficient space in the request queue and Tx
1708 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1709 * the controller acts autonomously to complete transfers programmed to a host
1712 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1713 * if there is any data remaining to be queued. For an IN transfer, another
1714 * data packet is always requested. For the SETUP phase of a control transfer,
1715 * this function does nothing.
1717 * Return: 1 if a new request is queued, 0 if no more requests are required
1720 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1721 struct dwc2_host_chan *chan)
1724 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1728 /* SPLITs always queue just once per channel */
1731 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1732 /* SETUPs are queued only once since they can't be NAK'd */
1735 if (chan->ep_is_in) {
1737 * Always queue another request for other IN transfers. If
1738 * back-to-back INs are issued and NAKs are received for both,
1739 * the driver may still be processing the first NAK when the
1740 * second NAK is received. When the interrupt handler clears
1741 * the NAK interrupt for the first NAK, the second NAK will
1742 * not be seen. So we can't depend on the NAK interrupt
1743 * handler to requeue a NAK'd request. Instead, IN requests
1744 * are issued each time this function is called. When the
1745 * transfer completes, the extra requests for the channel will
1748 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1750 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1751 hcchar |= HCCHAR_CHENA;
1752 hcchar &= ~HCCHAR_CHDIS;
1754 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1756 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1763 if (chan->xfer_count < chan->xfer_len) {
1764 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1765 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1766 u32 hcchar = dwc2_readl(hsotg,
1767 HCCHAR(chan->hc_num));
1769 dwc2_hc_set_even_odd_frame(hsotg, chan,
1773 /* Load OUT packet into the appropriate Tx FIFO */
1774 dwc2_hc_write_packet(hsotg, chan);
1783 * =========================================================================
1785 * =========================================================================
1789 * Processes all the URBs in a single list of QHs. Completes them with
1790 * -ETIMEDOUT and frees the QTD.
1792 * Must be called with interrupt disabled and spinlock held
1794 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1795 struct list_head *qh_list)
1797 struct dwc2_qh *qh, *qh_tmp;
1798 struct dwc2_qtd *qtd, *qtd_tmp;
1800 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1801 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1803 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1804 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1809 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1810 struct list_head *qh_list)
1812 struct dwc2_qtd *qtd, *qtd_tmp;
1813 struct dwc2_qh *qh, *qh_tmp;
1814 unsigned long flags;
1817 /* The list hasn't been initialized yet */
1820 spin_lock_irqsave(&hsotg->lock, flags);
1822 /* Ensure there are no QTDs or URBs left */
1823 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1825 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1826 dwc2_hcd_qh_unlink(hsotg, qh);
1828 /* Free each QTD in the QH's QTD list */
1829 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1831 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1833 if (qh->channel && qh->channel->qh == qh)
1834 qh->channel->qh = NULL;
1836 spin_unlock_irqrestore(&hsotg->lock, flags);
1837 dwc2_hcd_qh_free(hsotg, qh);
1838 spin_lock_irqsave(&hsotg->lock, flags);
1841 spin_unlock_irqrestore(&hsotg->lock, flags);
1845 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1846 * and periodic schedules. The QTD associated with each URB is removed from
1847 * the schedule and freed. This function may be called when a disconnect is
1848 * detected or when the HCD is being stopped.
1850 * Must be called with interrupt disabled and spinlock held
1852 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1854 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1855 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1856 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1857 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1858 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1859 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1860 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1864 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1866 * @hsotg: Pointer to struct dwc2_hsotg
1868 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1872 if (hsotg->op_state == OTG_STATE_B_HOST) {
1874 * Reset the port. During a HNP mode switch the reset
1875 * needs to occur within 1ms and have a duration of at
1878 hprt0 = dwc2_read_hprt0(hsotg);
1880 dwc2_writel(hsotg, hprt0, HPRT0);
1883 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1884 msecs_to_jiffies(50));
1887 /* Must be called with interrupt disabled and spinlock held */
1888 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1890 int num_channels = hsotg->params.host_channels;
1891 struct dwc2_host_chan *channel;
1895 if (!hsotg->params.host_dma) {
1896 /* Flush out any channel requests in slave mode */
1897 for (i = 0; i < num_channels; i++) {
1898 channel = hsotg->hc_ptr_array[i];
1899 if (!list_empty(&channel->hc_list_entry))
1901 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1902 if (hcchar & HCCHAR_CHENA) {
1903 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1904 hcchar |= HCCHAR_CHDIS;
1905 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1910 for (i = 0; i < num_channels; i++) {
1911 channel = hsotg->hc_ptr_array[i];
1912 if (!list_empty(&channel->hc_list_entry))
1914 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1915 if (hcchar & HCCHAR_CHENA) {
1916 /* Halt the channel */
1917 hcchar |= HCCHAR_CHDIS;
1918 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1921 dwc2_hc_cleanup(hsotg, channel);
1922 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1924 * Added for Descriptor DMA to prevent channel double cleanup in
1925 * release_channel_ddma(), which is called from ep_disable when
1926 * device disconnects
1930 /* All channels have been freed, mark them available */
1931 if (hsotg->params.uframe_sched) {
1932 hsotg->available_host_channels =
1933 hsotg->params.host_channels;
1935 hsotg->non_periodic_channels = 0;
1936 hsotg->periodic_channels = 0;
1941 * dwc2_hcd_connect() - Handles connect of the HCD
1943 * @hsotg: Pointer to struct dwc2_hsotg
1945 * Must be called with interrupt disabled and spinlock held
1947 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1949 if (hsotg->lx_state != DWC2_L0)
1950 usb_hcd_resume_root_hub(hsotg->priv);
1952 hsotg->flags.b.port_connect_status_change = 1;
1953 hsotg->flags.b.port_connect_status = 1;
1957 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1959 * @hsotg: Pointer to struct dwc2_hsotg
1960 * @force: If true, we won't try to reconnect even if we see device connected.
1962 * Must be called with interrupt disabled and spinlock held
1964 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1969 /* Set status flags for the hub driver */
1970 hsotg->flags.b.port_connect_status_change = 1;
1971 hsotg->flags.b.port_connect_status = 0;
1974 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1975 * interrupt mask and status bits and disabling subsequent host
1976 * channel interrupts.
1978 intr = dwc2_readl(hsotg, GINTMSK);
1979 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1980 dwc2_writel(hsotg, intr, GINTMSK);
1981 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1982 dwc2_writel(hsotg, intr, GINTSTS);
1985 * Turn off the vbus power only if the core has transitioned to device
1986 * mode. If still in host mode, need to keep power on to detect a
1989 if (dwc2_is_device_mode(hsotg)) {
1990 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1991 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1992 dwc2_writel(hsotg, 0, HPRT0);
1995 dwc2_disable_host_interrupts(hsotg);
1998 /* Respond with an error status to all URBs in the schedule */
1999 dwc2_kill_all_urbs(hsotg);
2001 if (dwc2_is_host_mode(hsotg))
2002 /* Clean up any host channels that were in use */
2003 dwc2_hcd_cleanup_channels(hsotg);
2005 dwc2_host_disconnect(hsotg);
2008 * Add an extra check here to see if we're actually connected but
2009 * we don't have a detection interrupt pending. This can happen if:
2010 * 1. hardware sees connect
2011 * 2. hardware sees disconnect
2012 * 3. hardware sees connect
2013 * 4. dwc2_port_intr() - clears connect interrupt
2014 * 5. dwc2_handle_common_intr() - calls here
2016 * Without the extra check here we will end calling disconnect
2017 * and won't get any future interrupts to handle the connect.
2020 hprt0 = dwc2_readl(hsotg, HPRT0);
2021 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2022 dwc2_hcd_connect(hsotg);
2027 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2029 * @hsotg: Pointer to struct dwc2_hsotg
2031 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2033 if (hsotg->bus_suspended) {
2034 hsotg->flags.b.port_suspend_change = 1;
2035 usb_hcd_resume_root_hub(hsotg->priv);
2038 if (hsotg->lx_state == DWC2_L1)
2039 hsotg->flags.b.port_l1_change = 1;
2043 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2045 * @hsotg: Pointer to struct dwc2_hsotg
2047 * Must be called with interrupt disabled and spinlock held
2049 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2051 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2054 * The root hub should be disconnected before this function is called.
2055 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2056 * and the QH lists (via ..._hcd_endpoint_disable).
2059 /* Turn off all host-specific interrupts */
2060 dwc2_disable_host_interrupts(hsotg);
2062 /* Turn off the vbus power */
2063 dev_dbg(hsotg->dev, "PortPower off\n");
2064 dwc2_writel(hsotg, 0, HPRT0);
2067 /* Caller must hold driver lock */
2068 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2069 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2070 struct dwc2_qtd *qtd)
2076 if (!hsotg->flags.b.port_connect_status) {
2077 /* No longer connected */
2078 dev_err(hsotg->dev, "Not connected\n");
2082 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2084 /* Some configurations cannot support LS traffic on a FS root port */
2085 if ((dev_speed == USB_SPEED_LOW) &&
2086 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2087 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2088 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
2089 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2091 if (prtspd == HPRT0_SPD_FULL_SPEED)
2098 dwc2_hcd_qtd_init(qtd, urb);
2099 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2102 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2107 intr_mask = dwc2_readl(hsotg, GINTMSK);
2108 if (!(intr_mask & GINTSTS_SOF)) {
2109 enum dwc2_transaction_type tr_type;
2111 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2112 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2114 * Do not schedule SG transactions until qtd has
2115 * URB_GIVEBACK_ASAP set
2119 tr_type = dwc2_hcd_select_transactions(hsotg);
2120 if (tr_type != DWC2_TRANSACTION_NONE)
2121 dwc2_hcd_queue_transactions(hsotg, tr_type);
2127 /* Must be called with interrupt disabled and spinlock held */
2128 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2129 struct dwc2_hcd_urb *urb)
2132 struct dwc2_qtd *urb_qtd;
2136 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2142 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2148 if (urb_qtd->in_process && qh->channel) {
2149 dwc2_dump_channel_info(hsotg, qh->channel);
2151 /* The QTD is in process (it has been assigned to a channel) */
2152 if (hsotg->flags.b.port_connect_status)
2154 * If still connected (i.e. in host mode), halt the
2155 * channel so it can be used for other transfers. If
2156 * no longer connected, the host registers can't be
2157 * written to halt the channel since the core is in
2160 dwc2_hc_halt(hsotg, qh->channel,
2161 DWC2_HC_XFER_URB_DEQUEUE);
2165 * Free the QTD and clean up the associated QH. Leave the QH in the
2166 * schedule if it has any remaining QTDs.
2168 if (!hsotg->params.dma_desc_enable) {
2169 u8 in_process = urb_qtd->in_process;
2171 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2173 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2175 } else if (list_empty(&qh->qtd_list)) {
2176 dwc2_hcd_qh_unlink(hsotg, qh);
2179 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2185 /* Must NOT be called with interrupt disabled or spinlock held */
2186 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2187 struct usb_host_endpoint *ep, int retry)
2189 struct dwc2_qtd *qtd, *qtd_tmp;
2191 unsigned long flags;
2194 spin_lock_irqsave(&hsotg->lock, flags);
2202 while (!list_empty(&qh->qtd_list) && retry--) {
2205 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2210 spin_unlock_irqrestore(&hsotg->lock, flags);
2212 spin_lock_irqsave(&hsotg->lock, flags);
2220 dwc2_hcd_qh_unlink(hsotg, qh);
2222 /* Free each QTD in the QH's QTD list */
2223 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2224 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2228 if (qh->channel && qh->channel->qh == qh)
2229 qh->channel->qh = NULL;
2231 spin_unlock_irqrestore(&hsotg->lock, flags);
2233 dwc2_hcd_qh_free(hsotg, qh);
2239 spin_unlock_irqrestore(&hsotg->lock, flags);
2244 /* Must be called with interrupt disabled and spinlock held */
2245 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2246 struct usb_host_endpoint *ep)
2248 struct dwc2_qh *qh = ep->hcpriv;
2253 qh->data_toggle = DWC2_HC_PID_DATA0;
2259 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2260 * prepares the core for device mode or host mode operation
2262 * @hsotg: Programming view of the DWC_otg controller
2263 * @initial_setup: If true then this is the first init for this instance.
2265 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2270 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2272 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2274 /* Set ULPI External VBUS bit if needed */
2275 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2276 if (hsotg->params.phy_ulpi_ext_vbus)
2277 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2279 /* Set external TS Dline pulsing bit if needed */
2280 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2281 if (hsotg->params.ts_dline)
2282 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2287 * Reset the Controller
2289 * We only need to reset the controller if this is a re-init.
2290 * For the first init we know for sure that earlier code reset us (it
2291 * needed to in order to properly detect various parameters).
2293 if (!initial_setup) {
2294 retval = dwc2_core_reset(hsotg, false);
2296 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2303 * This needs to happen in FS mode before any other programming occurs
2305 retval = dwc2_phy_init(hsotg, initial_setup);
2309 /* Program the GAHBCFG Register */
2310 retval = dwc2_gahbcfg_init(hsotg);
2314 /* Program the GUSBCFG register */
2315 dwc2_gusbcfg_init(hsotg);
2317 /* Program the GOTGCTL register */
2318 otgctl = dwc2_readl(hsotg, GOTGCTL);
2319 otgctl &= ~GOTGCTL_OTGVER;
2320 dwc2_writel(hsotg, otgctl, GOTGCTL);
2322 /* Clear the SRP success bit for FS-I2c */
2323 hsotg->srp_success = 0;
2325 /* Enable common interrupts */
2326 dwc2_enable_common_interrupts(hsotg);
2329 * Do device or host initialization based on mode during PCD and
2330 * HCD initialization
2332 if (dwc2_is_host_mode(hsotg)) {
2333 dev_dbg(hsotg->dev, "Host Mode\n");
2334 hsotg->op_state = OTG_STATE_A_HOST;
2336 dev_dbg(hsotg->dev, "Device Mode\n");
2337 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2344 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2347 * @hsotg: Programming view of DWC_otg controller
2349 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2350 * request queues. Host channels are reset to ensure that they are ready for
2351 * performing transfers.
2353 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2355 u32 hcfg, hfir, otgctl, usbcfg;
2357 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2359 /* Set HS/FS Timeout Calibration to 7 (max available value).
2360 * The number of PHY clocks that the application programs in
2361 * this field is added to the high/full speed interpacket timeout
2362 * duration in the core to account for any additional delays
2363 * introduced by the PHY. This can be required, because the delay
2364 * introduced by the PHY in generating the linestate condition
2365 * can vary from one PHY to another.
2367 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2368 usbcfg |= GUSBCFG_TOUTCAL(7);
2369 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2371 /* Restart the Phy Clock */
2372 dwc2_writel(hsotg, 0, PCGCTL);
2374 /* Initialize Host Configuration Register */
2375 dwc2_init_fs_ls_pclk_sel(hsotg);
2376 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2377 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2378 hcfg = dwc2_readl(hsotg, HCFG);
2379 hcfg |= HCFG_FSLSSUPP;
2380 dwc2_writel(hsotg, hcfg, HCFG);
2384 * This bit allows dynamic reloading of the HFIR register during
2385 * runtime. This bit needs to be programmed during initial configuration
2386 * and its value must not be changed during runtime.
2388 if (hsotg->params.reload_ctl) {
2389 hfir = dwc2_readl(hsotg, HFIR);
2390 hfir |= HFIR_RLDCTRL;
2391 dwc2_writel(hsotg, hfir, HFIR);
2394 if (hsotg->params.dma_desc_enable) {
2395 u32 op_mode = hsotg->hw_params.op_mode;
2397 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2398 !hsotg->hw_params.dma_desc_enable ||
2399 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2400 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2401 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2403 "Hardware does not support descriptor DMA mode -\n");
2405 "falling back to buffer DMA mode.\n");
2406 hsotg->params.dma_desc_enable = false;
2408 hcfg = dwc2_readl(hsotg, HCFG);
2409 hcfg |= HCFG_DESCDMA;
2410 dwc2_writel(hsotg, hcfg, HCFG);
2414 /* Configure data FIFO sizes */
2415 dwc2_config_fifos(hsotg);
2417 /* TODO - check this */
2418 /* Clear Host Set HNP Enable in the OTG Control Register */
2419 otgctl = dwc2_readl(hsotg, GOTGCTL);
2420 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2421 dwc2_writel(hsotg, otgctl, GOTGCTL);
2423 /* Make sure the FIFOs are flushed */
2424 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2425 dwc2_flush_rx_fifo(hsotg);
2427 /* Clear Host Set HNP Enable in the OTG Control Register */
2428 otgctl = dwc2_readl(hsotg, GOTGCTL);
2429 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2430 dwc2_writel(hsotg, otgctl, GOTGCTL);
2432 if (!hsotg->params.dma_desc_enable) {
2433 int num_channels, i;
2436 /* Flush out any leftover queued requests */
2437 num_channels = hsotg->params.host_channels;
2438 for (i = 0; i < num_channels; i++) {
2439 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2440 hcchar &= ~HCCHAR_CHENA;
2441 hcchar |= HCCHAR_CHDIS;
2442 hcchar &= ~HCCHAR_EPDIR;
2443 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2446 /* Halt all channels to put them into a known state */
2447 for (i = 0; i < num_channels; i++) {
2448 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2449 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2450 hcchar &= ~HCCHAR_EPDIR;
2451 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2452 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2455 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2456 HCCHAR_CHENA, 1000)) {
2457 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2463 /* Enable ACG feature in host mode, if supported */
2464 dwc2_enable_acg(hsotg);
2466 /* Turn on the vbus power */
2467 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2468 if (hsotg->op_state == OTG_STATE_A_HOST) {
2469 u32 hprt0 = dwc2_read_hprt0(hsotg);
2471 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2472 !!(hprt0 & HPRT0_PWR));
2473 if (!(hprt0 & HPRT0_PWR)) {
2475 dwc2_writel(hsotg, hprt0, HPRT0);
2479 dwc2_enable_host_interrupts(hsotg);
2483 * Initializes dynamic portions of the DWC_otg HCD state
2485 * Must be called with interrupt disabled and spinlock held
2487 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2489 struct dwc2_host_chan *chan, *chan_tmp;
2493 hsotg->flags.d32 = 0;
2494 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2496 if (hsotg->params.uframe_sched) {
2497 hsotg->available_host_channels =
2498 hsotg->params.host_channels;
2500 hsotg->non_periodic_channels = 0;
2501 hsotg->periodic_channels = 0;
2505 * Put all channels in the free channel list and clean up channel
2508 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2510 list_del_init(&chan->hc_list_entry);
2512 num_channels = hsotg->params.host_channels;
2513 for (i = 0; i < num_channels; i++) {
2514 chan = hsotg->hc_ptr_array[i];
2515 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2516 dwc2_hc_cleanup(hsotg, chan);
2519 /* Initialize the DWC core for host mode operation */
2520 dwc2_core_host_init(hsotg);
2523 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2524 struct dwc2_host_chan *chan,
2525 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2527 int hub_addr, hub_port;
2530 chan->xact_pos = qtd->isoc_split_pos;
2531 chan->complete_split = qtd->complete_split;
2532 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2533 chan->hub_addr = (u8)hub_addr;
2534 chan->hub_port = (u8)hub_port;
2537 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2538 struct dwc2_host_chan *chan,
2539 struct dwc2_qtd *qtd)
2541 struct dwc2_hcd_urb *urb = qtd->urb;
2542 struct dwc2_hcd_iso_packet_desc *frame_desc;
2544 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2545 case USB_ENDPOINT_XFER_CONTROL:
2546 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2548 switch (qtd->control_phase) {
2549 case DWC2_CONTROL_SETUP:
2550 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2553 chan->data_pid_start = DWC2_HC_PID_SETUP;
2554 if (hsotg->params.host_dma)
2555 chan->xfer_dma = urb->setup_dma;
2557 chan->xfer_buf = urb->setup_packet;
2561 case DWC2_CONTROL_DATA:
2562 dev_vdbg(hsotg->dev, " Control data transaction\n");
2563 chan->data_pid_start = qtd->data_toggle;
2566 case DWC2_CONTROL_STATUS:
2568 * Direction is opposite of data direction or IN if no
2571 dev_vdbg(hsotg->dev, " Control status transaction\n");
2572 if (urb->length == 0)
2576 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2579 chan->data_pid_start = DWC2_HC_PID_DATA1;
2581 if (hsotg->params.host_dma)
2582 chan->xfer_dma = hsotg->status_buf_dma;
2584 chan->xfer_buf = hsotg->status_buf;
2589 case USB_ENDPOINT_XFER_BULK:
2590 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2593 case USB_ENDPOINT_XFER_INT:
2594 chan->ep_type = USB_ENDPOINT_XFER_INT;
2597 case USB_ENDPOINT_XFER_ISOC:
2598 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2599 if (hsotg->params.dma_desc_enable)
2602 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2603 frame_desc->status = 0;
2605 if (hsotg->params.host_dma) {
2606 chan->xfer_dma = urb->dma;
2607 chan->xfer_dma += frame_desc->offset +
2608 qtd->isoc_split_offset;
2610 chan->xfer_buf = urb->buf;
2611 chan->xfer_buf += frame_desc->offset +
2612 qtd->isoc_split_offset;
2615 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2617 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2618 if (chan->xfer_len <= 188)
2619 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2621 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2627 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2629 struct dwc2_host_chan *chan)
2631 if (!hsotg->unaligned_cache ||
2632 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2635 if (!qh->dw_align_buf) {
2636 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2637 GFP_ATOMIC | GFP_DMA);
2638 if (!qh->dw_align_buf)
2642 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2643 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2646 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2647 dev_err(hsotg->dev, "can't map align_buf\n");
2648 chan->align_buf = 0;
2652 chan->align_buf = qh->dw_align_buf_dma;
2656 #define DWC2_USB_DMA_ALIGN 4
2658 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2660 void *stored_xfer_buffer;
2663 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2666 /* Restore urb->transfer_buffer from the end of the allocated area */
2667 memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2668 urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2670 if (usb_urb_dir_in(urb)) {
2671 if (usb_pipeisoc(urb->pipe))
2672 length = urb->transfer_buffer_length;
2674 length = urb->actual_length;
2676 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2678 kfree(urb->transfer_buffer);
2679 urb->transfer_buffer = stored_xfer_buffer;
2681 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2684 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2687 size_t kmalloc_size;
2689 if (urb->num_sgs || urb->sg ||
2690 urb->transfer_buffer_length == 0 ||
2691 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2695 * Allocate a buffer with enough padding for original transfer_buffer
2696 * pointer. This allocation is guaranteed to be aligned properly for
2699 kmalloc_size = urb->transfer_buffer_length +
2700 sizeof(urb->transfer_buffer);
2702 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2707 * Position value of original urb->transfer_buffer pointer to the end
2708 * of allocation for later referencing
2710 memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2711 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2713 if (usb_urb_dir_out(urb))
2714 memcpy(kmalloc_ptr, urb->transfer_buffer,
2715 urb->transfer_buffer_length);
2716 urb->transfer_buffer = kmalloc_ptr;
2718 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2723 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2728 /* We assume setup_dma is always aligned; warn if not */
2729 WARN_ON_ONCE(urb->setup_dma &&
2730 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2732 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2736 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2738 dwc2_free_dma_aligned_buffer(urb);
2743 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2745 usb_hcd_unmap_urb_for_dma(hcd, urb);
2746 dwc2_free_dma_aligned_buffer(urb);
2750 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2751 * channel and initializes the host channel to perform the transactions. The
2752 * host channel is removed from the free list.
2754 * @hsotg: The HCD state structure
2755 * @qh: Transactions from the first QTD for this QH are selected and assigned
2756 * to a free host channel
2758 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2760 struct dwc2_host_chan *chan;
2761 struct dwc2_hcd_urb *urb;
2762 struct dwc2_qtd *qtd;
2765 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2767 if (list_empty(&qh->qtd_list)) {
2768 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2772 if (list_empty(&hsotg->free_hc_list)) {
2773 dev_dbg(hsotg->dev, "No free channel to assign\n");
2777 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2780 /* Remove host channel from free list */
2781 list_del_init(&chan->hc_list_entry);
2783 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2786 qtd->in_process = 1;
2789 * Use usb_pipedevice to determine device address. This address is
2790 * 0 before the SET_ADDRESS command and the correct address afterward.
2792 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2793 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2794 chan->speed = qh->dev_speed;
2795 chan->max_packet = dwc2_max_packet(qh->maxp);
2797 chan->xfer_started = 0;
2798 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2799 chan->error_state = (qtd->error_count > 0);
2800 chan->halt_on_queue = 0;
2801 chan->halt_pending = 0;
2805 * The following values may be modified in the transfer type section
2806 * below. The xfer_len value may be reduced when the transfer is
2807 * started to accommodate the max widths of the XferSize and PktCnt
2808 * fields in the HCTSIZn register.
2811 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2815 chan->do_ping = qh->ping_state;
2817 chan->data_pid_start = qh->data_toggle;
2818 chan->multi_count = 1;
2820 if (urb->actual_length > urb->length &&
2821 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2822 urb->actual_length = urb->length;
2824 if (hsotg->params.host_dma)
2825 chan->xfer_dma = urb->dma + urb->actual_length;
2827 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2829 chan->xfer_len = urb->length - urb->actual_length;
2830 chan->xfer_count = 0;
2832 /* Set the split attributes if required */
2834 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2838 /* Set the transfer attributes */
2839 dwc2_hc_init_xfer(hsotg, chan, qtd);
2841 /* For non-dword aligned buffers */
2842 if (hsotg->params.host_dma && qh->do_split &&
2843 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2844 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2845 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2847 "Failed to allocate memory to handle non-aligned buffer\n");
2848 /* Add channel back to free list */
2849 chan->align_buf = 0;
2850 chan->multi_count = 0;
2851 list_add_tail(&chan->hc_list_entry,
2852 &hsotg->free_hc_list);
2853 qtd->in_process = 0;
2859 * We assume that DMA is always aligned in non-split
2860 * case or split out case. Warn if not.
2862 WARN_ON_ONCE(hsotg->params.host_dma &&
2863 (chan->xfer_dma & 0x3));
2864 chan->align_buf = 0;
2867 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2868 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2870 * This value may be modified when the transfer is started
2871 * to reflect the actual transfer length
2873 chan->multi_count = dwc2_hb_mult(qh->maxp);
2875 if (hsotg->params.dma_desc_enable) {
2876 chan->desc_list_addr = qh->desc_list_dma;
2877 chan->desc_list_sz = qh->desc_list_sz;
2880 dwc2_hc_init(hsotg, chan);
2887 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2888 * schedule and assigns them to available host channels. Called from the HCD
2889 * interrupt handler functions.
2891 * @hsotg: The HCD state structure
2893 * Return: The types of new transactions that were assigned to host channels
2895 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2896 struct dwc2_hsotg *hsotg)
2898 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2899 struct list_head *qh_ptr;
2903 #ifdef DWC2_DEBUG_SOF
2904 dev_vdbg(hsotg->dev, " Select Transactions\n");
2907 /* Process entries in the periodic ready list */
2908 qh_ptr = hsotg->periodic_sched_ready.next;
2909 while (qh_ptr != &hsotg->periodic_sched_ready) {
2910 if (list_empty(&hsotg->free_hc_list))
2912 if (hsotg->params.uframe_sched) {
2913 if (hsotg->available_host_channels <= 1)
2915 hsotg->available_host_channels--;
2917 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2918 if (dwc2_assign_and_init_hc(hsotg, qh))
2922 * Move the QH from the periodic ready schedule to the
2923 * periodic assigned schedule
2925 qh_ptr = qh_ptr->next;
2926 list_move_tail(&qh->qh_list_entry,
2927 &hsotg->periodic_sched_assigned);
2928 ret_val = DWC2_TRANSACTION_PERIODIC;
2932 * Process entries in the inactive portion of the non-periodic
2933 * schedule. Some free host channels may not be used if they are
2934 * reserved for periodic transfers.
2936 num_channels = hsotg->params.host_channels;
2937 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2938 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2939 if (!hsotg->params.uframe_sched &&
2940 hsotg->non_periodic_channels >= num_channels -
2941 hsotg->periodic_channels)
2943 if (list_empty(&hsotg->free_hc_list))
2945 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2946 if (hsotg->params.uframe_sched) {
2947 if (hsotg->available_host_channels < 1)
2949 hsotg->available_host_channels--;
2952 if (dwc2_assign_and_init_hc(hsotg, qh))
2956 * Move the QH from the non-periodic inactive schedule to the
2957 * non-periodic active schedule
2959 qh_ptr = qh_ptr->next;
2960 list_move_tail(&qh->qh_list_entry,
2961 &hsotg->non_periodic_sched_active);
2963 if (ret_val == DWC2_TRANSACTION_NONE)
2964 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2966 ret_val = DWC2_TRANSACTION_ALL;
2968 if (!hsotg->params.uframe_sched)
2969 hsotg->non_periodic_channels++;
2976 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2977 * a host channel associated with either a periodic or non-periodic transfer
2979 * @hsotg: The HCD state structure
2980 * @chan: Host channel descriptor associated with either a periodic or
2981 * non-periodic transfer
2982 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2983 * for periodic transfers or the non-periodic Tx FIFO
2984 * for non-periodic transfers
2986 * Return: 1 if a request is queued and more requests may be needed to
2987 * complete the transfer, 0 if no more requests are required for this
2988 * transfer, -1 if there is insufficient space in the Tx FIFO
2990 * This function assumes that there is space available in the appropriate
2991 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2992 * it checks whether space is available in the appropriate Tx FIFO.
2994 * Must be called with interrupt disabled and spinlock held
2996 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2997 struct dwc2_host_chan *chan,
2998 u16 fifo_dwords_avail)
3003 /* Put ourselves on the list to keep order straight */
3004 list_move_tail(&chan->split_order_list_entry,
3005 &hsotg->split_order);
3007 if (hsotg->params.host_dma) {
3008 if (hsotg->params.dma_desc_enable) {
3009 if (!chan->xfer_started ||
3010 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
3011 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
3012 chan->qh->ping_state = 0;
3014 } else if (!chan->xfer_started) {
3015 dwc2_hc_start_transfer(hsotg, chan);
3016 chan->qh->ping_state = 0;
3018 } else if (chan->halt_pending) {
3019 /* Don't queue a request if the channel has been halted */
3020 } else if (chan->halt_on_queue) {
3021 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3022 } else if (chan->do_ping) {
3023 if (!chan->xfer_started)
3024 dwc2_hc_start_transfer(hsotg, chan);
3025 } else if (!chan->ep_is_in ||
3026 chan->data_pid_start == DWC2_HC_PID_SETUP) {
3027 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3028 if (!chan->xfer_started) {
3029 dwc2_hc_start_transfer(hsotg, chan);
3032 retval = dwc2_hc_continue_transfer(hsotg, chan);
3038 if (!chan->xfer_started) {
3039 dwc2_hc_start_transfer(hsotg, chan);
3042 retval = dwc2_hc_continue_transfer(hsotg, chan);
3050 * Processes periodic channels for the next frame and queues transactions for
3051 * these channels to the DWC_otg controller. After queueing transactions, the
3052 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3053 * to queue as Periodic Tx FIFO or request queue space becomes available.
3054 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3056 * Must be called with interrupt disabled and spinlock held
3058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3060 struct list_head *qh_ptr;
3066 bool no_queue_space = false;
3067 bool no_fifo_space = false;
3070 /* If empty list then just adjust interrupt enables */
3071 if (list_empty(&hsotg->periodic_sched_assigned))
3075 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3077 tx_status = dwc2_readl(hsotg, HPTXSTS);
3078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3079 TXSTS_QSPCAVAIL_SHIFT;
3080 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3081 TXSTS_FSPCAVAIL_SHIFT;
3084 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3086 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3090 qh_ptr = hsotg->periodic_sched_assigned.next;
3091 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3092 tx_status = dwc2_readl(hsotg, HPTXSTS);
3093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3094 TXSTS_QSPCAVAIL_SHIFT;
3095 if (qspcavail == 0) {
3096 no_queue_space = true;
3100 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3102 qh_ptr = qh_ptr->next;
3106 /* Make sure EP's TT buffer is clean before queueing qtds */
3107 if (qh->tt_buffer_dirty) {
3108 qh_ptr = qh_ptr->next;
3113 * Set a flag if we're queuing high-bandwidth in slave mode.
3114 * The flag prevents any halts to get into the request queue in
3115 * the middle of multiple high-bandwidth packets getting queued.
3117 if (!hsotg->params.host_dma &&
3118 qh->channel->multi_count > 1)
3119 hsotg->queuing_high_bandwidth = 1;
3121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122 TXSTS_FSPCAVAIL_SHIFT;
3123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3125 no_fifo_space = true;
3130 * In Slave mode, stay on the current transfer until there is
3131 * nothing more to do or the high-bandwidth request count is
3132 * reached. In DMA mode, only need to queue one request. The
3133 * controller automatically handles multiple packets for
3134 * high-bandwidth transfers.
3136 if (hsotg->params.host_dma || status == 0 ||
3137 qh->channel->requests == qh->channel->multi_count) {
3138 qh_ptr = qh_ptr->next;
3140 * Move the QH from the periodic assigned schedule to
3141 * the periodic queued schedule
3143 list_move_tail(&qh->qh_list_entry,
3144 &hsotg->periodic_sched_queued);
3146 /* done queuing high bandwidth */
3147 hsotg->queuing_high_bandwidth = 0;
3152 if (no_queue_space || no_fifo_space ||
3153 (!hsotg->params.host_dma &&
3154 !list_empty(&hsotg->periodic_sched_assigned))) {
3156 * May need to queue more transactions as the request
3157 * queue or Tx FIFO empties. Enable the periodic Tx
3158 * FIFO empty interrupt. (Always use the half-empty
3159 * level to ensure that new requests are loaded as
3160 * soon as possible.)
3162 gintmsk = dwc2_readl(hsotg, GINTMSK);
3163 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3164 gintmsk |= GINTSTS_PTXFEMP;
3165 dwc2_writel(hsotg, gintmsk, GINTMSK);
3169 * Disable the Tx FIFO empty interrupt since there are
3170 * no more transactions that need to be queued right
3171 * now. This function is called from interrupt
3172 * handlers to queue more transactions as transfer
3175 gintmsk = dwc2_readl(hsotg, GINTMSK);
3176 if (gintmsk & GINTSTS_PTXFEMP) {
3177 gintmsk &= ~GINTSTS_PTXFEMP;
3178 dwc2_writel(hsotg, gintmsk, GINTMSK);
3184 * Processes active non-periodic channels and queues transactions for these
3185 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3186 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3187 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3188 * FIFO Empty interrupt is disabled.
3190 * Must be called with interrupt disabled and spinlock held
3192 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3194 struct list_head *orig_qh_ptr;
3201 int no_queue_space = 0;
3202 int no_fifo_space = 0;
3205 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3207 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3208 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3209 TXSTS_QSPCAVAIL_SHIFT;
3210 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3211 TXSTS_FSPCAVAIL_SHIFT;
3212 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3214 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3218 * Keep track of the starting point. Skip over the start-of-list
3221 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3222 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3223 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3226 * Process once through the active list or until no more space is
3227 * available in the request queue or the Tx FIFO
3230 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3231 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3232 TXSTS_QSPCAVAIL_SHIFT;
3233 if (!hsotg->params.host_dma && qspcavail == 0) {
3238 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3243 /* Make sure EP's TT buffer is clean before queueing qtds */
3244 if (qh->tt_buffer_dirty)
3247 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3248 TXSTS_FSPCAVAIL_SHIFT;
3249 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3253 } else if (status < 0) {
3258 /* Advance to next QH, skipping start-of-list entry */
3259 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3260 if (hsotg->non_periodic_qh_ptr ==
3261 &hsotg->non_periodic_sched_active)
3262 hsotg->non_periodic_qh_ptr =
3263 hsotg->non_periodic_qh_ptr->next;
3264 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3266 if (!hsotg->params.host_dma) {
3267 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3268 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3269 TXSTS_QSPCAVAIL_SHIFT;
3270 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3271 TXSTS_FSPCAVAIL_SHIFT;
3272 dev_vdbg(hsotg->dev,
3273 " NP Tx Req Queue Space Avail (after queue): %d\n",
3275 dev_vdbg(hsotg->dev,
3276 " NP Tx FIFO Space Avail (after queue): %d\n",
3279 if (more_to_do || no_queue_space || no_fifo_space) {
3281 * May need to queue more transactions as the request
3282 * queue or Tx FIFO empties. Enable the non-periodic
3283 * Tx FIFO empty interrupt. (Always use the half-empty
3284 * level to ensure that new requests are loaded as
3285 * soon as possible.)
3287 gintmsk = dwc2_readl(hsotg, GINTMSK);
3288 gintmsk |= GINTSTS_NPTXFEMP;
3289 dwc2_writel(hsotg, gintmsk, GINTMSK);
3292 * Disable the Tx FIFO empty interrupt since there are
3293 * no more transactions that need to be queued right
3294 * now. This function is called from interrupt
3295 * handlers to queue more transactions as transfer
3298 gintmsk = dwc2_readl(hsotg, GINTMSK);
3299 gintmsk &= ~GINTSTS_NPTXFEMP;
3300 dwc2_writel(hsotg, gintmsk, GINTMSK);
3306 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3307 * and queues transactions for these channels to the DWC_otg controller. Called
3308 * from the HCD interrupt handler functions.
3310 * @hsotg: The HCD state structure
3311 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3314 * Must be called with interrupt disabled and spinlock held
3316 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3317 enum dwc2_transaction_type tr_type)
3319 #ifdef DWC2_DEBUG_SOF
3320 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3322 /* Process host channels associated with periodic transfers */
3323 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3324 tr_type == DWC2_TRANSACTION_ALL)
3325 dwc2_process_periodic_channels(hsotg);
3327 /* Process host channels associated with non-periodic transfers */
3328 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3329 tr_type == DWC2_TRANSACTION_ALL) {
3330 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3331 dwc2_process_non_periodic_channels(hsotg);
3334 * Ensure NP Tx FIFO empty interrupt is disabled when
3335 * there are no non-periodic transfers to process
3337 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3339 gintmsk &= ~GINTSTS_NPTXFEMP;
3340 dwc2_writel(hsotg, gintmsk, GINTMSK);
3345 static void dwc2_conn_id_status_change(struct work_struct *work)
3347 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3351 unsigned long flags;
3353 dev_dbg(hsotg->dev, "%s()\n", __func__);
3355 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3356 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3357 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3358 !!(gotgctl & GOTGCTL_CONID_B));
3360 /* B-Device connector (Device Mode) */
3361 if (gotgctl & GOTGCTL_CONID_B) {
3362 dwc2_vbus_supply_exit(hsotg);
3363 /* Wait for switch to device mode */
3364 dev_dbg(hsotg->dev, "connId B\n");
3365 if (hsotg->bus_suspended) {
3366 dev_info(hsotg->dev,
3367 "Do port resume before switching to device mode\n");
3368 dwc2_port_resume(hsotg);
3370 while (!dwc2_is_device_mode(hsotg)) {
3371 dev_info(hsotg->dev,
3372 "Waiting for Peripheral Mode, Mode=%s\n",
3373 dwc2_is_host_mode(hsotg) ? "Host" :
3377 * Sometimes the initial GOTGCTRL read is wrong, so
3378 * check it again and jump to host mode if that was
3381 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3382 if (!(gotgctl & GOTGCTL_CONID_B))
3389 "Connection id status change timed out\n");
3390 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3391 dwc2_core_init(hsotg, false);
3392 dwc2_enable_global_interrupts(hsotg);
3393 spin_lock_irqsave(&hsotg->lock, flags);
3394 dwc2_hsotg_core_init_disconnected(hsotg, false);
3395 spin_unlock_irqrestore(&hsotg->lock, flags);
3396 /* Enable ACG feature in device mode,if supported */
3397 dwc2_enable_acg(hsotg);
3398 dwc2_hsotg_core_connect(hsotg);
3401 /* A-Device connector (Host Mode) */
3402 dev_dbg(hsotg->dev, "connId A\n");
3403 while (!dwc2_is_host_mode(hsotg)) {
3404 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3405 dwc2_is_host_mode(hsotg) ?
3406 "Host" : "Peripheral");
3413 "Connection id status change timed out\n");
3415 spin_lock_irqsave(&hsotg->lock, flags);
3416 dwc2_hsotg_disconnect(hsotg);
3417 spin_unlock_irqrestore(&hsotg->lock, flags);
3419 hsotg->op_state = OTG_STATE_A_HOST;
3420 /* Initialize the Core for Host mode */
3421 dwc2_core_init(hsotg, false);
3422 dwc2_enable_global_interrupts(hsotg);
3423 dwc2_hcd_start(hsotg);
3427 static void dwc2_wakeup_detected(struct timer_list *t)
3429 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3432 dev_dbg(hsotg->dev, "%s()\n", __func__);
3435 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3436 * so that OPT tests pass with all PHYs.)
3438 hprt0 = dwc2_read_hprt0(hsotg);
3439 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3440 hprt0 &= ~HPRT0_RES;
3441 dwc2_writel(hsotg, hprt0, HPRT0);
3442 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3443 dwc2_readl(hsotg, HPRT0));
3445 dwc2_hcd_rem_wakeup(hsotg);
3446 hsotg->bus_suspended = false;
3448 /* Change to L0 state */
3449 hsotg->lx_state = DWC2_L0;
3452 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3454 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3456 return hcd->self.b_hnp_enable;
3459 /* Must NOT be called with interrupt disabled or spinlock held */
3460 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3462 unsigned long flags;
3467 dev_dbg(hsotg->dev, "%s()\n", __func__);
3469 spin_lock_irqsave(&hsotg->lock, flags);
3471 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3472 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3473 gotgctl |= GOTGCTL_HSTSETHNPEN;
3474 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3475 hsotg->op_state = OTG_STATE_A_SUSPEND;
3478 hprt0 = dwc2_read_hprt0(hsotg);
3479 hprt0 |= HPRT0_SUSP;
3480 dwc2_writel(hsotg, hprt0, HPRT0);
3482 hsotg->bus_suspended = true;
3485 * If power_down is supported, Phy clock will be suspended
3486 * after registers are backuped.
3488 if (!hsotg->params.power_down) {
3489 /* Suspend the Phy Clock */
3490 pcgctl = dwc2_readl(hsotg, PCGCTL);
3491 pcgctl |= PCGCTL_STOPPCLK;
3492 dwc2_writel(hsotg, pcgctl, PCGCTL);
3496 /* For HNP the bus must be suspended for at least 200ms */
3497 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3498 pcgctl = dwc2_readl(hsotg, PCGCTL);
3499 pcgctl &= ~PCGCTL_STOPPCLK;
3500 dwc2_writel(hsotg, pcgctl, PCGCTL);
3502 spin_unlock_irqrestore(&hsotg->lock, flags);
3506 spin_unlock_irqrestore(&hsotg->lock, flags);
3510 /* Must NOT be called with interrupt disabled or spinlock held */
3511 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3513 unsigned long flags;
3517 spin_lock_irqsave(&hsotg->lock, flags);
3520 * If power_down is supported, Phy clock is already resumed
3521 * after registers restore.
3523 if (!hsotg->params.power_down) {
3524 pcgctl = dwc2_readl(hsotg, PCGCTL);
3525 pcgctl &= ~PCGCTL_STOPPCLK;
3526 dwc2_writel(hsotg, pcgctl, PCGCTL);
3527 spin_unlock_irqrestore(&hsotg->lock, flags);
3529 spin_lock_irqsave(&hsotg->lock, flags);
3532 hprt0 = dwc2_read_hprt0(hsotg);
3534 hprt0 &= ~HPRT0_SUSP;
3535 dwc2_writel(hsotg, hprt0, HPRT0);
3536 spin_unlock_irqrestore(&hsotg->lock, flags);
3538 msleep(USB_RESUME_TIMEOUT);
3540 spin_lock_irqsave(&hsotg->lock, flags);
3541 hprt0 = dwc2_read_hprt0(hsotg);
3542 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3543 dwc2_writel(hsotg, hprt0, HPRT0);
3544 hsotg->bus_suspended = false;
3545 spin_unlock_irqrestore(&hsotg->lock, flags);
3548 /* Handles hub class-specific requests */
3549 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3550 u16 wvalue, u16 windex, char *buf, u16 wlength)
3552 struct usb_hub_descriptor *hub_desc;
3561 case ClearHubFeature:
3562 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3565 case C_HUB_LOCAL_POWER:
3566 case C_HUB_OVER_CURRENT:
3567 /* Nothing required here */
3573 "ClearHubFeature request %1xh unknown\n",
3578 case ClearPortFeature:
3579 if (wvalue != USB_PORT_FEAT_L1)
3580 if (!windex || windex > 1)
3583 case USB_PORT_FEAT_ENABLE:
3585 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3586 hprt0 = dwc2_read_hprt0(hsotg);
3588 dwc2_writel(hsotg, hprt0, HPRT0);
3591 case USB_PORT_FEAT_SUSPEND:
3593 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3595 if (hsotg->bus_suspended) {
3596 if (hsotg->hibernated)
3597 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3599 dwc2_port_resume(hsotg);
3603 case USB_PORT_FEAT_POWER:
3605 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3606 hprt0 = dwc2_read_hprt0(hsotg);
3607 pwr = hprt0 & HPRT0_PWR;
3608 hprt0 &= ~HPRT0_PWR;
3609 dwc2_writel(hsotg, hprt0, HPRT0);
3611 dwc2_vbus_supply_exit(hsotg);
3614 case USB_PORT_FEAT_INDICATOR:
3616 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3617 /* Port indicator not supported */
3620 case USB_PORT_FEAT_C_CONNECTION:
3622 * Clears driver's internal Connect Status Change flag
3625 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3626 hsotg->flags.b.port_connect_status_change = 0;
3629 case USB_PORT_FEAT_C_RESET:
3630 /* Clears driver's internal Port Reset Change flag */
3632 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3633 hsotg->flags.b.port_reset_change = 0;
3636 case USB_PORT_FEAT_C_ENABLE:
3638 * Clears the driver's internal Port Enable/Disable
3642 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3643 hsotg->flags.b.port_enable_change = 0;
3646 case USB_PORT_FEAT_C_SUSPEND:
3648 * Clears the driver's internal Port Suspend Change
3649 * flag, which is set when resume signaling on the host
3653 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3654 hsotg->flags.b.port_suspend_change = 0;
3657 case USB_PORT_FEAT_C_PORT_L1:
3659 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3660 hsotg->flags.b.port_l1_change = 0;
3663 case USB_PORT_FEAT_C_OVER_CURRENT:
3665 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3666 hsotg->flags.b.port_over_current_change = 0;
3672 "ClearPortFeature request %1xh unknown or unsupported\n",
3677 case GetHubDescriptor:
3678 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3679 hub_desc = (struct usb_hub_descriptor *)buf;
3680 hub_desc->bDescLength = 9;
3681 hub_desc->bDescriptorType = USB_DT_HUB;
3682 hub_desc->bNbrPorts = 1;
3683 hub_desc->wHubCharacteristics =
3684 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3685 HUB_CHAR_INDV_PORT_OCPM);
3686 hub_desc->bPwrOn2PwrGood = 1;
3687 hub_desc->bHubContrCurrent = 0;
3688 hub_desc->u.hs.DeviceRemovable[0] = 0;
3689 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3693 dev_dbg(hsotg->dev, "GetHubStatus\n");
3698 dev_vdbg(hsotg->dev,
3699 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3701 if (!windex || windex > 1)
3705 if (hsotg->flags.b.port_connect_status_change)
3706 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3707 if (hsotg->flags.b.port_enable_change)
3708 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3709 if (hsotg->flags.b.port_suspend_change)
3710 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3711 if (hsotg->flags.b.port_l1_change)
3712 port_status |= USB_PORT_STAT_C_L1 << 16;
3713 if (hsotg->flags.b.port_reset_change)
3714 port_status |= USB_PORT_STAT_C_RESET << 16;
3715 if (hsotg->flags.b.port_over_current_change) {
3716 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3717 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3720 if (!hsotg->flags.b.port_connect_status) {
3722 * The port is disconnected, which means the core is
3723 * either in device mode or it soon will be. Just
3724 * return 0's for the remainder of the port status
3725 * since the port register can't be read if the core
3726 * is in device mode.
3728 *(__le32 *)buf = cpu_to_le32(port_status);
3732 hprt0 = dwc2_readl(hsotg, HPRT0);
3733 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3735 if (hprt0 & HPRT0_CONNSTS)
3736 port_status |= USB_PORT_STAT_CONNECTION;
3737 if (hprt0 & HPRT0_ENA)
3738 port_status |= USB_PORT_STAT_ENABLE;
3739 if (hprt0 & HPRT0_SUSP)
3740 port_status |= USB_PORT_STAT_SUSPEND;
3741 if (hprt0 & HPRT0_OVRCURRACT)
3742 port_status |= USB_PORT_STAT_OVERCURRENT;
3743 if (hprt0 & HPRT0_RST)
3744 port_status |= USB_PORT_STAT_RESET;
3745 if (hprt0 & HPRT0_PWR)
3746 port_status |= USB_PORT_STAT_POWER;
3748 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3749 if (speed == HPRT0_SPD_HIGH_SPEED)
3750 port_status |= USB_PORT_STAT_HIGH_SPEED;
3751 else if (speed == HPRT0_SPD_LOW_SPEED)
3752 port_status |= USB_PORT_STAT_LOW_SPEED;
3754 if (hprt0 & HPRT0_TSTCTL_MASK)
3755 port_status |= USB_PORT_STAT_TEST;
3756 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3758 if (hsotg->params.dma_desc_fs_enable) {
3760 * Enable descriptor DMA only if a full speed
3761 * device is connected.
3763 if (hsotg->new_connection &&
3765 (USB_PORT_STAT_CONNECTION |
3766 USB_PORT_STAT_HIGH_SPEED |
3767 USB_PORT_STAT_LOW_SPEED)) ==
3768 USB_PORT_STAT_CONNECTION)) {
3771 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3772 hsotg->params.dma_desc_enable = true;
3773 hcfg = dwc2_readl(hsotg, HCFG);
3774 hcfg |= HCFG_DESCDMA;
3775 dwc2_writel(hsotg, hcfg, HCFG);
3776 hsotg->new_connection = false;
3780 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3781 *(__le32 *)buf = cpu_to_le32(port_status);
3785 dev_dbg(hsotg->dev, "SetHubFeature\n");
3786 /* No HUB features supported */
3789 case SetPortFeature:
3790 dev_dbg(hsotg->dev, "SetPortFeature\n");
3791 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3794 if (!hsotg->flags.b.port_connect_status) {
3796 * The port is disconnected, which means the core is
3797 * either in device mode or it soon will be. Just
3798 * return without doing anything since the port
3799 * register can't be written if the core is in device
3806 case USB_PORT_FEAT_SUSPEND:
3808 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3809 if (windex != hsotg->otg_port)
3811 if (hsotg->params.power_down == 2)
3812 dwc2_enter_hibernation(hsotg, 1);
3814 dwc2_port_suspend(hsotg, windex);
3817 case USB_PORT_FEAT_POWER:
3819 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3820 hprt0 = dwc2_read_hprt0(hsotg);
3821 pwr = hprt0 & HPRT0_PWR;
3823 dwc2_writel(hsotg, hprt0, HPRT0);
3825 dwc2_vbus_supply_init(hsotg);
3828 case USB_PORT_FEAT_RESET:
3829 if (hsotg->params.power_down == 2 &&
3831 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3832 hprt0 = dwc2_read_hprt0(hsotg);
3834 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3835 pcgctl = dwc2_readl(hsotg, PCGCTL);
3836 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3837 dwc2_writel(hsotg, pcgctl, PCGCTL);
3838 /* ??? Original driver does this */
3839 dwc2_writel(hsotg, 0, PCGCTL);
3841 hprt0 = dwc2_read_hprt0(hsotg);
3842 pwr = hprt0 & HPRT0_PWR;
3843 /* Clear suspend bit if resetting from suspend state */
3844 hprt0 &= ~HPRT0_SUSP;
3847 * When B-Host the Port reset bit is set in the Start
3848 * HCD Callback function, so that the reset is started
3849 * within 1ms of the HNP success interrupt
3851 if (!dwc2_hcd_is_b_host(hsotg)) {
3852 hprt0 |= HPRT0_PWR | HPRT0_RST;
3854 "In host mode, hprt0=%08x\n", hprt0);
3855 dwc2_writel(hsotg, hprt0, HPRT0);
3857 dwc2_vbus_supply_init(hsotg);
3860 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3862 hprt0 &= ~HPRT0_RST;
3863 dwc2_writel(hsotg, hprt0, HPRT0);
3864 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3867 case USB_PORT_FEAT_INDICATOR:
3869 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3873 case USB_PORT_FEAT_TEST:
3874 hprt0 = dwc2_read_hprt0(hsotg);
3876 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3877 hprt0 &= ~HPRT0_TSTCTL_MASK;
3878 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3879 dwc2_writel(hsotg, hprt0, HPRT0);
3885 "SetPortFeature %1xh unknown or unsupported\n",
3895 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3896 typereq, windex, wvalue);
3903 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3910 retval = (hsotg->flags.b.port_connect_status_change ||
3911 hsotg->flags.b.port_reset_change ||
3912 hsotg->flags.b.port_enable_change ||
3913 hsotg->flags.b.port_suspend_change ||
3914 hsotg->flags.b.port_over_current_change);
3918 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3919 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3920 hsotg->flags.b.port_connect_status_change);
3921 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3922 hsotg->flags.b.port_reset_change);
3923 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3924 hsotg->flags.b.port_enable_change);
3925 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3926 hsotg->flags.b.port_suspend_change);
3927 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3928 hsotg->flags.b.port_over_current_change);
3934 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3936 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3938 #ifdef DWC2_DEBUG_SOF
3939 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3940 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3942 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3945 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3947 u32 hprt = dwc2_readl(hsotg, HPRT0);
3948 u32 hfir = dwc2_readl(hsotg, HFIR);
3949 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3950 unsigned int us_per_frame;
3951 unsigned int frame_number;
3952 unsigned int remaining;
3953 unsigned int interval;
3954 unsigned int phy_clks;
3956 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3957 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3959 /* Extract fields */
3960 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3961 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3962 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3965 * Number of phy clocks since the last tick of the frame number after
3968 phy_clks = (interval - remaining) +
3969 DIV_ROUND_UP(interval * us, us_per_frame);
3971 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3974 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3976 return hsotg->op_state == OTG_STATE_B_HOST;
3979 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3983 struct dwc2_hcd_urb *urb;
3985 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
3987 urb->packet_count = iso_desc_count;
3991 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3992 struct dwc2_hcd_urb *urb, u8 dev_addr,
3993 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3996 ep_type == USB_ENDPOINT_XFER_BULK ||
3997 ep_type == USB_ENDPOINT_XFER_CONTROL)
3998 dev_vdbg(hsotg->dev,
3999 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
4000 dev_addr, ep_num, ep_dir, ep_type, mps);
4001 urb->pipe_info.dev_addr = dev_addr;
4002 urb->pipe_info.ep_num = ep_num;
4003 urb->pipe_info.pipe_type = ep_type;
4004 urb->pipe_info.pipe_dir = ep_dir;
4005 urb->pipe_info.mps = mps;
4009 * NOTE: This function will be removed once the peripheral controller code
4010 * is integrated and the driver is stable
4012 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4015 struct dwc2_host_chan *chan;
4016 struct dwc2_hcd_urb *urb;
4017 struct dwc2_qtd *qtd;
4023 num_channels = hsotg->params.host_channels;
4024 dev_dbg(hsotg->dev, "\n");
4026 "************************************************************\n");
4027 dev_dbg(hsotg->dev, "HCD State:\n");
4028 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
4030 for (i = 0; i < num_channels; i++) {
4031 chan = hsotg->hc_ptr_array[i];
4032 dev_dbg(hsotg->dev, " Channel %d:\n", i);
4034 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
4035 chan->dev_addr, chan->ep_num, chan->ep_is_in);
4036 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
4037 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
4038 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
4039 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
4040 chan->data_pid_start);
4041 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
4042 dev_dbg(hsotg->dev, " xfer_started: %d\n",
4043 chan->xfer_started);
4044 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
4045 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
4046 (unsigned long)chan->xfer_dma);
4047 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
4048 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
4049 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
4050 chan->halt_on_queue);
4051 dev_dbg(hsotg->dev, " halt_pending: %d\n",
4052 chan->halt_pending);
4053 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
4054 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
4055 dev_dbg(hsotg->dev, " complete_split: %d\n",
4056 chan->complete_split);
4057 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
4058 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
4059 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
4060 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
4061 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
4063 if (chan->xfer_started) {
4064 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4066 hfnum = dwc2_readl(hsotg, HFNUM);
4067 hcchar = dwc2_readl(hsotg, HCCHAR(i));
4068 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
4069 hcint = dwc2_readl(hsotg, HCINT(i));
4070 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
4071 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4072 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4073 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4074 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4075 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4078 if (!(chan->xfer_started && chan->qh))
4081 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4082 if (!qtd->in_process)
4085 dev_dbg(hsotg->dev, " URB Info:\n");
4086 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4090 " Dev: %d, EP: %d %s\n",
4091 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4092 dwc2_hcd_get_ep_num(&urb->pipe_info),
4093 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4096 " Max packet size: %d\n",
4097 dwc2_hcd_get_mps(&urb->pipe_info));
4099 " transfer_buffer: %p\n",
4102 " transfer_dma: %08lx\n",
4103 (unsigned long)urb->dma);
4105 " transfer_buffer_length: %d\n",
4107 dev_dbg(hsotg->dev, " actual_length: %d\n",
4108 urb->actual_length);
4113 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4114 hsotg->non_periodic_channels);
4115 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4116 hsotg->periodic_channels);
4117 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4118 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
4119 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4120 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4121 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4122 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4123 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
4124 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4125 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4126 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4127 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4128 dwc2_dump_global_registers(hsotg);
4129 dwc2_dump_host_registers(hsotg);
4131 "************************************************************\n");
4132 dev_dbg(hsotg->dev, "\n");
4136 struct wrapper_priv_data {
4137 struct dwc2_hsotg *hsotg;
4140 /* Gets the dwc2_hsotg from a usb_hcd */
4141 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4143 struct wrapper_priv_data *p;
4145 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4150 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4152 * This will get the dwc2_tt structure (and ttport) associated with the given
4153 * context (which is really just a struct urb pointer).
4155 * The first time this is called for a given TT we allocate memory for our
4156 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4157 * then the refcount for the structure will go to 0 and we'll free it.
4159 * @hsotg: The HCD state structure for the DWC OTG controller.
4160 * @context: The priv pointer from a struct dwc2_hcd_urb.
4161 * @mem_flags: Flags for allocating memory.
4162 * @ttport: We'll return this device's port number here. That's used to
4163 * reference into the bitmap if we're on a multi_tt hub.
4165 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4166 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4169 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4170 gfp_t mem_flags, int *ttport)
4172 struct urb *urb = context;
4173 struct dwc2_tt *dwc_tt = NULL;
4176 *ttport = urb->dev->ttport;
4178 dwc_tt = urb->dev->tt->hcpriv;
4183 * For single_tt we need one schedule. For multi_tt
4184 * we need one per port.
4186 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4187 sizeof(dwc_tt->periodic_bitmaps[0]);
4188 if (urb->dev->tt->multi)
4189 bitmap_size *= urb->dev->tt->hub->maxchild;
4191 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4196 dwc_tt->usb_tt = urb->dev->tt;
4197 dwc_tt->usb_tt->hcpriv = dwc_tt;
4207 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4209 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4210 * of the structure are done.
4212 * It's OK to call this with NULL.
4214 * @hsotg: The HCD state structure for the DWC OTG controller.
4215 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4217 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4219 /* Model kfree and make put of NULL a no-op */
4223 WARN_ON(dwc_tt->refcount < 1);
4226 if (!dwc_tt->refcount) {
4227 dwc_tt->usb_tt->hcpriv = NULL;
4232 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4234 struct urb *urb = context;
4236 return urb->dev->speed;
4239 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4242 struct usb_bus *bus = hcd_to_bus(hcd);
4245 bus->bandwidth_allocated += bw / urb->interval;
4246 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4247 bus->bandwidth_isoc_reqs++;
4249 bus->bandwidth_int_reqs++;
4252 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4255 struct usb_bus *bus = hcd_to_bus(hcd);
4258 bus->bandwidth_allocated -= bw / urb->interval;
4259 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4260 bus->bandwidth_isoc_reqs--;
4262 bus->bandwidth_int_reqs--;
4266 * Sets the final status of an URB and returns it to the upper layer. Any
4267 * required cleanup of the URB is performed.
4269 * Must be called with interrupt disabled and spinlock held
4271 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4278 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4283 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4287 urb = qtd->urb->priv;
4289 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4293 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4296 dev_vdbg(hsotg->dev,
4297 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4298 __func__, urb, usb_pipedevice(urb->pipe),
4299 usb_pipeendpoint(urb->pipe),
4300 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4301 urb->actual_length);
4303 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4304 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4305 for (i = 0; i < urb->number_of_packets; ++i) {
4306 urb->iso_frame_desc[i].actual_length =
4307 dwc2_hcd_urb_get_iso_desc_actual_length(
4309 urb->iso_frame_desc[i].status =
4310 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4314 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4315 for (i = 0; i < urb->number_of_packets; i++)
4316 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4317 i, urb->iso_frame_desc[i].status);
4320 urb->status = status;
4322 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4323 urb->actual_length < urb->transfer_buffer_length)
4324 urb->status = -EREMOTEIO;
4327 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4328 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4329 struct usb_host_endpoint *ep = urb->ep;
4332 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4333 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4337 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4342 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4346 * Work queue function for starting the HCD when A-Cable is connected
4348 static void dwc2_hcd_start_func(struct work_struct *work)
4350 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4353 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4354 dwc2_host_start(hsotg);
4358 * Reset work queue function
4360 static void dwc2_hcd_reset_func(struct work_struct *work)
4362 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4364 unsigned long flags;
4367 dev_dbg(hsotg->dev, "USB RESET function called\n");
4369 spin_lock_irqsave(&hsotg->lock, flags);
4371 hprt0 = dwc2_read_hprt0(hsotg);
4372 hprt0 &= ~HPRT0_RST;
4373 dwc2_writel(hsotg, hprt0, HPRT0);
4374 hsotg->flags.b.port_reset_change = 1;
4376 spin_unlock_irqrestore(&hsotg->lock, flags);
4380 * =========================================================================
4381 * Linux HC Driver Functions
4382 * =========================================================================
4386 * Initializes the DWC_otg controller and its root hub and prepares it for host
4387 * mode operation. Activates the root port. Returns 0 on success and a negative
4388 * error code on failure.
4390 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4392 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4393 struct usb_bus *bus = hcd_to_bus(hcd);
4394 unsigned long flags;
4398 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4400 spin_lock_irqsave(&hsotg->lock, flags);
4401 hsotg->lx_state = DWC2_L0;
4402 hcd->state = HC_STATE_RUNNING;
4403 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4405 if (dwc2_is_device_mode(hsotg)) {
4406 spin_unlock_irqrestore(&hsotg->lock, flags);
4407 return 0; /* why 0 ?? */
4410 dwc2_hcd_reinit(hsotg);
4412 hprt0 = dwc2_read_hprt0(hsotg);
4413 /* Has vbus power been turned on in dwc2_core_host_init ? */
4414 if (hprt0 & HPRT0_PWR) {
4415 /* Enable external vbus supply before resuming root hub */
4416 spin_unlock_irqrestore(&hsotg->lock, flags);
4417 ret = dwc2_vbus_supply_init(hsotg);
4420 spin_lock_irqsave(&hsotg->lock, flags);
4423 /* Initialize and connect root hub if one is not already attached */
4424 if (bus->root_hub) {
4425 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4426 /* Inform the HUB driver to resume */
4427 usb_hcd_resume_root_hub(hcd);
4430 spin_unlock_irqrestore(&hsotg->lock, flags);
4436 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4439 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4441 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4442 unsigned long flags;
4445 /* Turn off all host-specific interrupts */
4446 dwc2_disable_host_interrupts(hsotg);
4448 /* Wait for interrupt processing to finish */
4449 synchronize_irq(hcd->irq);
4451 spin_lock_irqsave(&hsotg->lock, flags);
4452 hprt0 = dwc2_read_hprt0(hsotg);
4453 /* Ensure hcd is disconnected */
4454 dwc2_hcd_disconnect(hsotg, true);
4455 dwc2_hcd_stop(hsotg);
4456 hsotg->lx_state = DWC2_L3;
4457 hcd->state = HC_STATE_HALT;
4458 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4459 spin_unlock_irqrestore(&hsotg->lock, flags);
4461 /* keep balanced supply init/exit by checking HPRT0_PWR */
4462 if (hprt0 & HPRT0_PWR)
4463 dwc2_vbus_supply_exit(hsotg);
4465 usleep_range(1000, 3000);
4468 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4470 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4471 unsigned long flags;
4475 spin_lock_irqsave(&hsotg->lock, flags);
4477 if (dwc2_is_device_mode(hsotg))
4480 if (hsotg->lx_state != DWC2_L0)
4483 if (!HCD_HW_ACCESSIBLE(hcd))
4486 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4489 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4490 goto skip_power_saving;
4493 * Drive USB suspend and disable port Power
4494 * if usb bus is not suspended.
4496 if (!hsotg->bus_suspended) {
4497 hprt0 = dwc2_read_hprt0(hsotg);
4498 hprt0 |= HPRT0_SUSP;
4499 hprt0 &= ~HPRT0_PWR;
4500 dwc2_writel(hsotg, hprt0, HPRT0);
4501 spin_unlock_irqrestore(&hsotg->lock, flags);
4502 dwc2_vbus_supply_exit(hsotg);
4503 spin_lock_irqsave(&hsotg->lock, flags);
4506 /* Enter partial_power_down */
4507 ret = dwc2_enter_partial_power_down(hsotg);
4509 if (ret != -ENOTSUPP)
4511 "enter partial_power_down failed\n");
4512 goto skip_power_saving;
4515 /* Ask phy to be suspended */
4516 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4517 spin_unlock_irqrestore(&hsotg->lock, flags);
4518 usb_phy_set_suspend(hsotg->uphy, true);
4519 spin_lock_irqsave(&hsotg->lock, flags);
4522 /* After entering partial_power_down, hardware is no more accessible */
4523 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4526 hsotg->lx_state = DWC2_L2;
4528 spin_unlock_irqrestore(&hsotg->lock, flags);
4533 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4535 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4536 unsigned long flags;
4539 spin_lock_irqsave(&hsotg->lock, flags);
4541 if (dwc2_is_device_mode(hsotg))
4544 if (hsotg->lx_state != DWC2_L2)
4547 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4548 hsotg->lx_state = DWC2_L0;
4553 * Set HW accessible bit before powering on the controller
4554 * since an interrupt may rise.
4556 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4559 * Enable power if not already done.
4560 * This must not be spinlocked since duration
4561 * of this call is unknown.
4563 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4564 spin_unlock_irqrestore(&hsotg->lock, flags);
4565 usb_phy_set_suspend(hsotg->uphy, false);
4566 spin_lock_irqsave(&hsotg->lock, flags);
4569 /* Exit partial_power_down */
4570 ret = dwc2_exit_partial_power_down(hsotg, true);
4571 if (ret && (ret != -ENOTSUPP))
4572 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4574 hsotg->lx_state = DWC2_L0;
4576 spin_unlock_irqrestore(&hsotg->lock, flags);
4578 if (hsotg->bus_suspended) {
4579 spin_lock_irqsave(&hsotg->lock, flags);
4580 hsotg->flags.b.port_suspend_change = 1;
4581 spin_unlock_irqrestore(&hsotg->lock, flags);
4582 dwc2_port_resume(hsotg);
4584 dwc2_vbus_supply_init(hsotg);
4586 /* Wait for controller to correctly update D+/D- level */
4587 usleep_range(3000, 5000);
4590 * Clear Port Enable and Port Status changes.
4591 * Enable Port Power.
4593 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4594 HPRT0_ENACHG, HPRT0);
4595 /* Wait for controller to detect Port Connect */
4596 usleep_range(5000, 7000);
4601 spin_unlock_irqrestore(&hsotg->lock, flags);
4606 /* Returns the current frame number */
4607 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4609 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4611 return dwc2_hcd_get_frame_number(hsotg);
4614 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4617 #ifdef VERBOSE_DEBUG
4618 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4619 char *pipetype = NULL;
4622 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4623 dev_vdbg(hsotg->dev, " Device address: %d\n",
4624 usb_pipedevice(urb->pipe));
4625 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4626 usb_pipeendpoint(urb->pipe),
4627 usb_pipein(urb->pipe) ? "IN" : "OUT");
4629 switch (usb_pipetype(urb->pipe)) {
4631 pipetype = "CONTROL";
4636 case PIPE_INTERRUPT:
4637 pipetype = "INTERRUPT";
4639 case PIPE_ISOCHRONOUS:
4640 pipetype = "ISOCHRONOUS";
4644 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4645 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4648 switch (urb->dev->speed) {
4649 case USB_SPEED_HIGH:
4652 case USB_SPEED_FULL:
4663 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4664 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4665 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4666 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4667 urb->transfer_buffer_length);
4668 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4669 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4670 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4671 urb->setup_packet, (unsigned long)urb->setup_dma);
4672 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4674 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4677 for (i = 0; i < urb->number_of_packets; i++) {
4678 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4679 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4680 urb->iso_frame_desc[i].offset,
4681 urb->iso_frame_desc[i].length);
4688 * Starts processing a USB transfer request specified by a USB Request Block
4689 * (URB). mem_flags indicates the type of memory allocation to use while
4690 * processing this URB.
4692 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4695 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4696 struct usb_host_endpoint *ep = urb->ep;
4697 struct dwc2_hcd_urb *dwc2_urb;
4700 int alloc_bandwidth = 0;
4704 unsigned long flags;
4706 bool qh_allocated = false;
4707 struct dwc2_qtd *qtd;
4710 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4711 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4717 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4718 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4719 spin_lock_irqsave(&hsotg->lock, flags);
4720 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4721 alloc_bandwidth = 1;
4722 spin_unlock_irqrestore(&hsotg->lock, flags);
4725 switch (usb_pipetype(urb->pipe)) {
4727 ep_type = USB_ENDPOINT_XFER_CONTROL;
4729 case PIPE_ISOCHRONOUS:
4730 ep_type = USB_ENDPOINT_XFER_ISOC;
4733 ep_type = USB_ENDPOINT_XFER_BULK;
4735 case PIPE_INTERRUPT:
4736 ep_type = USB_ENDPOINT_XFER_INT;
4740 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4745 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4746 usb_pipeendpoint(urb->pipe), ep_type,
4747 usb_pipein(urb->pipe),
4748 usb_maxpacket(urb->dev, urb->pipe,
4749 !(usb_pipein(urb->pipe))));
4751 buf = urb->transfer_buffer;
4753 if (hcd->self.uses_dma) {
4754 if (!buf && (urb->transfer_dma & 3)) {
4756 "%s: unaligned transfer with no transfer_buffer",
4763 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4764 tflags |= URB_GIVEBACK_ASAP;
4765 if (urb->transfer_flags & URB_ZERO_PACKET)
4766 tflags |= URB_SEND_ZERO_PACKET;
4768 dwc2_urb->priv = urb;
4769 dwc2_urb->buf = buf;
4770 dwc2_urb->dma = urb->transfer_dma;
4771 dwc2_urb->length = urb->transfer_buffer_length;
4772 dwc2_urb->setup_packet = urb->setup_packet;
4773 dwc2_urb->setup_dma = urb->setup_dma;
4774 dwc2_urb->flags = tflags;
4775 dwc2_urb->interval = urb->interval;
4776 dwc2_urb->status = -EINPROGRESS;
4778 for (i = 0; i < urb->number_of_packets; ++i)
4779 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4780 urb->iso_frame_desc[i].offset,
4781 urb->iso_frame_desc[i].length);
4783 urb->hcpriv = dwc2_urb;
4784 qh = (struct dwc2_qh *)ep->hcpriv;
4785 /* Create QH for the endpoint if it doesn't exist */
4787 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4793 qh_allocated = true;
4796 qtd = kzalloc(sizeof(*qtd), mem_flags);
4802 spin_lock_irqsave(&hsotg->lock, flags);
4803 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4807 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4811 if (alloc_bandwidth) {
4812 dwc2_allocate_bus_bandwidth(hcd,
4813 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4817 spin_unlock_irqrestore(&hsotg->lock, flags);
4822 dwc2_urb->priv = NULL;
4823 usb_hcd_unlink_urb_from_ep(hcd, urb);
4824 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4825 qh->channel->qh = NULL;
4827 spin_unlock_irqrestore(&hsotg->lock, flags);
4833 struct dwc2_qtd *qtd2, *qtd2_tmp;
4836 dwc2_hcd_qh_unlink(hsotg, qh);
4837 /* Free each QTD in the QH's QTD list */
4838 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4840 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4841 dwc2_hcd_qh_free(hsotg, qh);
4850 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4852 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4855 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4857 unsigned long flags;
4859 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4860 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4862 spin_lock_irqsave(&hsotg->lock, flags);
4864 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4869 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4873 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4875 usb_hcd_unlink_urb_from_ep(hcd, urb);
4880 /* Higher layer software sets URB status */
4881 spin_unlock(&hsotg->lock);
4882 usb_hcd_giveback_urb(hcd, urb, status);
4883 spin_lock(&hsotg->lock);
4885 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4886 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4888 spin_unlock_irqrestore(&hsotg->lock, flags);
4894 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4895 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4896 * must already be dequeued.
4898 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4899 struct usb_host_endpoint *ep)
4901 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4904 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4905 ep->desc.bEndpointAddress, ep->hcpriv);
4906 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4910 * Resets endpoint specific parameter values, in current version used to reset
4911 * the data toggle (as a WA). This function can be called from usb_clear_halt
4914 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4915 struct usb_host_endpoint *ep)
4917 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4918 unsigned long flags;
4921 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4922 ep->desc.bEndpointAddress);
4924 spin_lock_irqsave(&hsotg->lock, flags);
4925 dwc2_hcd_endpoint_reset(hsotg, ep);
4926 spin_unlock_irqrestore(&hsotg->lock, flags);
4930 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4931 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4934 * This function is called by the USB core when an interrupt occurs
4936 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4938 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4940 return dwc2_handle_hcd_intr(hsotg);
4944 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4945 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4946 * is the status change indicator for the single root port. Returns 1 if either
4947 * change indicator is 1, otherwise returns 0.
4949 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4951 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4953 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4957 /* Handles hub class-specific requests */
4958 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4959 u16 windex, char *buf, u16 wlength)
4961 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4962 wvalue, windex, buf, wlength);
4966 /* Handles hub TT buffer clear completions */
4967 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4968 struct usb_host_endpoint *ep)
4970 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4972 unsigned long flags;
4978 spin_lock_irqsave(&hsotg->lock, flags);
4979 qh->tt_buffer_dirty = 0;
4981 if (hsotg->flags.b.port_connect_status)
4982 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4984 spin_unlock_irqrestore(&hsotg->lock, flags);
4988 * HPRT0_SPD_HIGH_SPEED: high speed
4989 * HPRT0_SPD_FULL_SPEED: full speed
4991 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4993 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4995 if (hsotg->params.speed == speed)
4998 hsotg->params.speed = speed;
4999 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
5002 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
5004 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5006 if (!hsotg->params.change_speed_quirk)
5010 * On removal, set speed to default high-speed.
5012 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
5013 udev->parent->speed < USB_SPEED_HIGH) {
5014 dev_info(hsotg->dev, "Set speed to default high-speed\n");
5015 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5019 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5021 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5023 if (!hsotg->params.change_speed_quirk)
5026 if (udev->speed == USB_SPEED_HIGH) {
5027 dev_info(hsotg->dev, "Set speed to high-speed\n");
5028 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5029 } else if ((udev->speed == USB_SPEED_FULL ||
5030 udev->speed == USB_SPEED_LOW)) {
5032 * Change speed setting to full-speed if there's
5033 * a full-speed or low-speed device plugged in.
5035 dev_info(hsotg->dev, "Set speed to full-speed\n");
5036 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5042 static struct hc_driver dwc2_hc_driver = {
5043 .description = "dwc2_hsotg",
5044 .product_desc = "DWC OTG Controller",
5045 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5047 .irq = _dwc2_hcd_irq,
5048 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5050 .start = _dwc2_hcd_start,
5051 .stop = _dwc2_hcd_stop,
5052 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5053 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5054 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5055 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5056 .get_frame_number = _dwc2_hcd_get_frame_number,
5058 .hub_status_data = _dwc2_hcd_hub_status_data,
5059 .hub_control = _dwc2_hcd_hub_control,
5060 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5062 .bus_suspend = _dwc2_hcd_suspend,
5063 .bus_resume = _dwc2_hcd_resume,
5065 .map_urb_for_dma = dwc2_map_urb_for_dma,
5066 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5070 * Frees secondary storage associated with the dwc2_hsotg structure contained
5071 * in the struct usb_hcd field
5073 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5079 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5081 /* Free memory for QH/QTD lists */
5082 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5083 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5084 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5085 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5086 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5087 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5088 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5090 /* Free memory for the host channels */
5091 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5092 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5095 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5097 hsotg->hc_ptr_array[i] = NULL;
5102 if (hsotg->params.host_dma) {
5103 if (hsotg->status_buf) {
5104 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5106 hsotg->status_buf_dma);
5107 hsotg->status_buf = NULL;
5110 kfree(hsotg->status_buf);
5111 hsotg->status_buf = NULL;
5114 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5116 /* Disable all interrupts */
5117 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5118 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5119 dwc2_writel(hsotg, 0, GINTMSK);
5121 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5122 dctl = dwc2_readl(hsotg, DCTL);
5123 dctl |= DCTL_SFTDISCON;
5124 dwc2_writel(hsotg, dctl, DCTL);
5127 if (hsotg->wq_otg) {
5128 if (!cancel_work_sync(&hsotg->wf_otg))
5129 flush_workqueue(hsotg->wq_otg);
5130 destroy_workqueue(hsotg->wq_otg);
5133 del_timer(&hsotg->wkp_timer);
5136 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5138 /* Turn off all host-specific interrupts */
5139 dwc2_disable_host_interrupts(hsotg);
5141 dwc2_hcd_free(hsotg);
5145 * Initializes the HCD. This function allocates memory for and initializes the
5146 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5147 * USB bus with the core and calls the hc_driver->start() function. It returns
5148 * a negative error on failure.
5150 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5152 struct platform_device *pdev = to_platform_device(hsotg->dev);
5153 struct resource *res;
5154 struct usb_hcd *hcd;
5155 struct dwc2_host_chan *channel;
5157 int i, num_channels;
5163 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5167 hcfg = dwc2_readl(hsotg, HCFG);
5168 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5170 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5171 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5172 sizeof(*hsotg->frame_num_array),
5174 if (!hsotg->frame_num_array)
5176 hsotg->last_frame_num_array =
5177 kcalloc(FRAME_NUM_ARRAY_SIZE,
5178 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5179 if (!hsotg->last_frame_num_array)
5182 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5184 /* Check if the bus driver or platform code has setup a dma_mask */
5185 if (hsotg->params.host_dma &&
5186 !hsotg->dev->dma_mask) {
5187 dev_warn(hsotg->dev,
5188 "dma_mask not set, disabling DMA\n");
5189 hsotg->params.host_dma = false;
5190 hsotg->params.dma_desc_enable = false;
5193 /* Set device flags indicating whether the HCD supports DMA */
5194 if (hsotg->params.host_dma) {
5195 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5196 dev_warn(hsotg->dev, "can't set DMA mask\n");
5197 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5198 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5201 if (hsotg->params.change_speed_quirk) {
5202 dwc2_hc_driver.free_dev = dwc2_free_dev;
5203 dwc2_hc_driver.reset_device = dwc2_reset_device;
5206 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5210 if (!hsotg->params.host_dma)
5211 hcd->self.uses_dma = 0;
5215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5216 hcd->rsrc_start = res->start;
5217 hcd->rsrc_len = resource_size(res);
5219 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5223 * Disable the global interrupt until all the interrupt handlers are
5226 dwc2_disable_global_interrupts(hsotg);
5228 /* Initialize the DWC_otg core, and select the Phy type */
5229 retval = dwc2_core_init(hsotg, true);
5233 /* Create new workqueue and init work */
5235 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5236 if (!hsotg->wq_otg) {
5237 dev_err(hsotg->dev, "Failed to create workqueue\n");
5240 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5242 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5244 /* Initialize the non-periodic schedule */
5245 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5246 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5247 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5249 /* Initialize the periodic schedule */
5250 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5251 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5252 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5253 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5255 INIT_LIST_HEAD(&hsotg->split_order);
5258 * Create a host channel descriptor for each host channel implemented
5259 * in the controller. Initialize the channel descriptor array.
5261 INIT_LIST_HEAD(&hsotg->free_hc_list);
5262 num_channels = hsotg->params.host_channels;
5263 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5265 for (i = 0; i < num_channels; i++) {
5266 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5269 channel->hc_num = i;
5270 INIT_LIST_HEAD(&channel->split_order_list_entry);
5271 hsotg->hc_ptr_array[i] = channel;
5274 /* Initialize hsotg start work */
5275 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5277 /* Initialize port reset work */
5278 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5281 * Allocate space for storing data on status transactions. Normally no
5282 * data is sent, but this space acts as a bit bucket. This must be
5283 * done after usb_add_hcd since that function allocates the DMA buffer
5286 if (hsotg->params.host_dma)
5287 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5288 DWC2_HCD_STATUS_BUF_SIZE,
5289 &hsotg->status_buf_dma, GFP_KERNEL);
5291 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5294 if (!hsotg->status_buf)
5298 * Create kmem caches to handle descriptor buffers in descriptor
5300 * Alignment must be set to 512 bytes.
5302 if (hsotg->params.dma_desc_enable ||
5303 hsotg->params.dma_desc_fs_enable) {
5304 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5305 sizeof(struct dwc2_dma_desc) *
5306 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5308 if (!hsotg->desc_gen_cache) {
5310 "unable to create dwc2 generic desc cache\n");
5313 * Disable descriptor dma mode since it will not be
5316 hsotg->params.dma_desc_enable = false;
5317 hsotg->params.dma_desc_fs_enable = false;
5320 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5321 sizeof(struct dwc2_dma_desc) *
5322 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5323 if (!hsotg->desc_hsisoc_cache) {
5325 "unable to create dwc2 hs isoc desc cache\n");
5327 kmem_cache_destroy(hsotg->desc_gen_cache);
5330 * Disable descriptor dma mode since it will not be
5333 hsotg->params.dma_desc_enable = false;
5334 hsotg->params.dma_desc_fs_enable = false;
5338 if (hsotg->params.host_dma) {
5340 * Create kmem caches to handle non-aligned buffer
5341 * in Buffer DMA mode.
5343 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5344 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5345 SLAB_CACHE_DMA, NULL);
5346 if (!hsotg->unaligned_cache)
5348 "unable to create dwc2 unaligned cache\n");
5351 hsotg->otg_port = 1;
5352 hsotg->frame_list = NULL;
5353 hsotg->frame_list_dma = 0;
5354 hsotg->periodic_qh_count = 0;
5356 /* Initiate lx_state to L3 disconnected state */
5357 hsotg->lx_state = DWC2_L3;
5359 hcd->self.otg_port = hsotg->otg_port;
5361 /* Don't support SG list at this point */
5362 hcd->self.sg_tablesize = 0;
5364 if (!IS_ERR_OR_NULL(hsotg->uphy))
5365 otg_set_host(hsotg->uphy->otg, &hcd->self);
5368 * Finish generic HCD initialization and start the HCD. This function
5369 * allocates the DMA buffer pool, registers the USB bus, requests the
5370 * IRQ line, and calls hcd_start method.
5372 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5376 device_wakeup_enable(hcd->self.controller);
5378 dwc2_hcd_dump_state(hsotg);
5380 dwc2_enable_global_interrupts(hsotg);
5385 kmem_cache_destroy(hsotg->unaligned_cache);
5386 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5387 kmem_cache_destroy(hsotg->desc_gen_cache);
5389 dwc2_hcd_release(hsotg);
5394 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5395 kfree(hsotg->last_frame_num_array);
5396 kfree(hsotg->frame_num_array);
5399 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5405 * Frees memory and resources associated with the HCD and deregisters the bus.
5407 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5409 struct usb_hcd *hcd;
5411 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5413 hcd = dwc2_hsotg_to_hcd(hsotg);
5414 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5417 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5422 if (!IS_ERR_OR_NULL(hsotg->uphy))
5423 otg_set_host(hsotg->uphy->otg, NULL);
5425 usb_remove_hcd(hcd);
5428 kmem_cache_destroy(hsotg->unaligned_cache);
5429 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5430 kmem_cache_destroy(hsotg->desc_gen_cache);
5432 dwc2_hcd_release(hsotg);
5435 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5436 kfree(hsotg->last_frame_num_array);
5437 kfree(hsotg->frame_num_array);
5442 * dwc2_backup_host_registers() - Backup controller host registers.
5443 * When suspending usb bus, registers needs to be backuped
5444 * if controller power is disabled once suspended.
5446 * @hsotg: Programming view of the DWC_otg controller
5448 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5450 struct dwc2_hregs_backup *hr;
5453 dev_dbg(hsotg->dev, "%s\n", __func__);
5455 /* Backup Host regs */
5456 hr = &hsotg->hr_backup;
5457 hr->hcfg = dwc2_readl(hsotg, HCFG);
5458 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5459 for (i = 0; i < hsotg->params.host_channels; ++i)
5460 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5462 hr->hprt0 = dwc2_read_hprt0(hsotg);
5463 hr->hfir = dwc2_readl(hsotg, HFIR);
5464 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5471 * dwc2_restore_host_registers() - Restore controller host registers.
5472 * When resuming usb bus, device registers needs to be restored
5473 * if controller power were disabled.
5475 * @hsotg: Programming view of the DWC_otg controller
5477 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5479 struct dwc2_hregs_backup *hr;
5482 dev_dbg(hsotg->dev, "%s\n", __func__);
5484 /* Restore host regs */
5485 hr = &hsotg->hr_backup;
5487 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5493 dwc2_writel(hsotg, hr->hcfg, HCFG);
5494 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5496 for (i = 0; i < hsotg->params.host_channels; ++i)
5497 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5499 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5500 dwc2_writel(hsotg, hr->hfir, HFIR);
5501 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5502 hsotg->frame_number = 0;
5508 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5510 * @hsotg: Programming view of the DWC_otg controller
5512 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5514 unsigned long flags;
5521 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5522 ret = dwc2_backup_global_registers(hsotg);
5524 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5528 ret = dwc2_backup_host_registers(hsotg);
5530 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5535 /* Enter USB Suspend Mode */
5536 hprt0 = dwc2_readl(hsotg, HPRT0);
5537 hprt0 |= HPRT0_SUSP;
5538 hprt0 &= ~HPRT0_ENA;
5539 dwc2_writel(hsotg, hprt0, HPRT0);
5541 /* Wait for the HPRT0.PrtSusp register field to be set */
5542 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5543 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5546 * We need to disable interrupts to prevent servicing of any IRQ
5547 * during going to hibernation
5549 spin_lock_irqsave(&hsotg->lock, flags);
5550 hsotg->lx_state = DWC2_L2;
5552 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5553 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5554 /* ULPI interface */
5555 /* Suspend the Phy Clock */
5556 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5557 pcgcctl |= PCGCTL_STOPPCLK;
5558 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5561 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5562 gpwrdn |= GPWRDN_PMUACTV;
5563 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5566 /* UTMI+ Interface */
5567 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5568 gpwrdn |= GPWRDN_PMUACTV;
5569 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5572 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5573 pcgcctl |= PCGCTL_STOPPCLK;
5574 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5578 /* Enable interrupts from wake up logic */
5579 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5580 gpwrdn |= GPWRDN_PMUINTSEL;
5581 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5584 /* Unmask host mode interrupts in GPWRDN */
5585 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5586 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5587 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5588 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5589 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5592 /* Enable Power Down Clamp */
5593 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5594 gpwrdn |= GPWRDN_PWRDNCLMP;
5595 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5598 /* Switch off VDD */
5599 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5600 gpwrdn |= GPWRDN_PWRDNSWTCH;
5601 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5603 hsotg->hibernated = 1;
5604 hsotg->bus_suspended = 1;
5605 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5606 spin_unlock_irqrestore(&hsotg->lock, flags);
5611 * dwc2_host_exit_hibernation()
5613 * @hsotg: Programming view of the DWC_otg controller
5614 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5615 * @param reset: indicates whether resume is initiated by Reset.
5617 * Return: non-zero if failed to enter to hibernation.
5619 * This function is for exiting from Host mode hibernation by
5620 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5622 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5628 struct dwc2_gregs_backup *gr;
5629 struct dwc2_hregs_backup *hr;
5631 gr = &hsotg->gr_backup;
5632 hr = &hsotg->hr_backup;
5635 "%s: called with rem_wakeup = %d reset = %d\n",
5636 __func__, rem_wakeup, reset);
5638 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5639 hsotg->hibernated = 0;
5642 * This step is not described in functional spec but if not wait for
5643 * this delay, mismatch interrupts occurred because just after restore
5644 * core is in Device mode(gintsts.curmode == 0)
5648 /* Clear all pending interupts */
5649 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5651 /* De-assert Restore */
5652 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5653 gpwrdn &= ~GPWRDN_RESTORE;
5654 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5657 /* Restore GUSBCFG, HCFG */
5658 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5659 dwc2_writel(hsotg, hr->hcfg, HCFG);
5661 /* De-assert Wakeup Logic */
5662 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5663 gpwrdn &= ~GPWRDN_PMUACTV;
5664 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5669 hprt0 &= ~HPRT0_ENA;
5670 hprt0 &= ~HPRT0_SUSP;
5671 dwc2_writel(hsotg, hprt0, HPRT0);
5675 hprt0 &= ~HPRT0_ENA;
5676 hprt0 &= ~HPRT0_SUSP;
5680 dwc2_writel(hsotg, hprt0, HPRT0);
5682 /* Wait for Resume time and then program HPRT again */
5684 hprt0 &= ~HPRT0_RST;
5685 dwc2_writel(hsotg, hprt0, HPRT0);
5688 dwc2_writel(hsotg, hprt0, HPRT0);
5690 /* Wait for Resume time and then program HPRT again */
5692 hprt0 &= ~HPRT0_RES;
5693 dwc2_writel(hsotg, hprt0, HPRT0);
5695 /* Clear all interrupt status */
5696 hprt0 = dwc2_readl(hsotg, HPRT0);
5697 hprt0 |= HPRT0_CONNDET;
5698 hprt0 |= HPRT0_ENACHG;
5699 hprt0 &= ~HPRT0_ENA;
5700 dwc2_writel(hsotg, hprt0, HPRT0);
5702 hprt0 = dwc2_readl(hsotg, HPRT0);
5704 /* Clear all pending interupts */
5705 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5707 /* Restore global registers */
5708 ret = dwc2_restore_global_registers(hsotg);
5710 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5715 /* Restore host registers */
5716 ret = dwc2_restore_host_registers(hsotg);
5718 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5723 dwc2_hcd_rem_wakeup(hsotg);
5725 hsotg->hibernated = 0;
5726 hsotg->bus_suspended = 0;
5727 hsotg->lx_state = DWC2_L0;
5728 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");