1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
123 hs_ep->frame_overrun = false;
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
130 * @hs_ep: The endpoint.
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
137 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
150 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
155 new_gsintmsk = gsintmsk | ints;
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
168 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
173 new_gsintmsk = gsintmsk & ~ints;
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
186 * Set or clear the mask for an individual endpoint's interrupt
189 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
213 * @hsotg: Programming view of the DWC_otg controller
215 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
229 * @hsotg: Programming view of the DWC_otg controller
231 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
247 return tx_addr_max - addr;
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
253 * @hsotg: Programming view of the DWC_otg controller
256 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
263 gintsts2 &= gintmsk2;
265 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
266 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
267 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
268 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
273 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
276 * @hsotg: Programming view of the DWC_otg controller
278 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
283 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
285 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
288 return tx_fifo_depth;
290 return tx_fifo_depth / tx_fifo_count;
294 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
295 * @hsotg: The device instance.
297 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
304 u32 *txfsz = hsotg->params.g_tx_fifo_size;
306 /* Reset fifo map if not correctly cleared during previous session */
307 WARN_ON(hsotg->fifo_map);
310 /* set RX/NPTX FIFO sizes */
311 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
312 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
313 FIFOSIZE_STARTADDR_SHIFT) |
314 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
318 * arange all the rest of the TX FIFOs, as some versions of this
319 * block have overlapping default addresses. This also ensures
320 * that if the settings have been changed, then they are set to
324 /* start at the end of the GNPTXFSIZ, rounded up */
325 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
328 * Configure fifos sizes from provided configuration and assign
329 * them to endpoints dynamically according to maxpacket size value of
332 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
336 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
337 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
338 "insufficient fifo memory");
341 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
342 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
345 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
346 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
349 * according to p428 of the design guide, we need to ensure that
350 * all fifos are flushed before continuing
353 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
354 GRSTCTL_RXFFLSH, GRSTCTL);
356 /* wait until the fifos are both flushed */
359 val = dwc2_readl(hsotg, GRSTCTL);
361 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
364 if (--timeout == 0) {
366 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
374 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
378 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
379 * @ep: USB endpoint to allocate request for.
380 * @flags: Allocation flags
382 * Allocate a new USB request structure appropriate for the specified endpoint
384 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
387 struct dwc2_hsotg_req *req;
389 req = kzalloc(sizeof(*req), flags);
393 INIT_LIST_HEAD(&req->queue);
399 * is_ep_periodic - return true if the endpoint is in periodic mode.
400 * @hs_ep: The endpoint to query.
402 * Returns true if the endpoint is in periodic mode, meaning it is being
403 * used for an Interrupt or ISO transfer.
405 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
407 return hs_ep->periodic;
411 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
412 * @hsotg: The device state.
413 * @hs_ep: The endpoint for the request
414 * @hs_req: The request being processed.
416 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
417 * of a request to ensure the buffer is ready for access by the caller.
419 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
420 struct dwc2_hsotg_ep *hs_ep,
421 struct dwc2_hsotg_req *hs_req)
423 struct usb_request *req = &hs_req->req;
425 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
429 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
430 * for Control endpoint
431 * @hsotg: The device state.
433 * This function will allocate 4 descriptor chains for EP 0: 2 for
434 * Setup stage, per one for IN and OUT data/status transactions.
436 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
438 hsotg->setup_desc[0] =
439 dmam_alloc_coherent(hsotg->dev,
440 sizeof(struct dwc2_dma_desc),
441 &hsotg->setup_desc_dma[0],
443 if (!hsotg->setup_desc[0])
446 hsotg->setup_desc[1] =
447 dmam_alloc_coherent(hsotg->dev,
448 sizeof(struct dwc2_dma_desc),
449 &hsotg->setup_desc_dma[1],
451 if (!hsotg->setup_desc[1])
454 hsotg->ctrl_in_desc =
455 dmam_alloc_coherent(hsotg->dev,
456 sizeof(struct dwc2_dma_desc),
457 &hsotg->ctrl_in_desc_dma,
459 if (!hsotg->ctrl_in_desc)
462 hsotg->ctrl_out_desc =
463 dmam_alloc_coherent(hsotg->dev,
464 sizeof(struct dwc2_dma_desc),
465 &hsotg->ctrl_out_desc_dma,
467 if (!hsotg->ctrl_out_desc)
477 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
478 * @hsotg: The controller state.
479 * @hs_ep: The endpoint we're going to write for.
480 * @hs_req: The request to write data for.
482 * This is called when the TxFIFO has some space in it to hold a new
483 * transmission and we have something to give it. The actual setup of
484 * the data size is done elsewhere, so all we have to do is to actually
487 * The return value is zero if there is more space (or nothing was done)
488 * otherwise -ENOSPC is returned if the FIFO space was used up.
490 * This routine is only needed for PIO
492 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
493 struct dwc2_hsotg_ep *hs_ep,
494 struct dwc2_hsotg_req *hs_req)
496 bool periodic = is_ep_periodic(hs_ep);
497 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
498 int buf_pos = hs_req->req.actual;
499 int to_write = hs_ep->size_loaded;
505 to_write -= (buf_pos - hs_ep->last_load);
507 /* if there's nothing to write, get out early */
511 if (periodic && !hsotg->dedicated_fifos) {
512 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
517 * work out how much data was loaded so we can calculate
518 * how much data is left in the fifo.
521 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
524 * if shared fifo, we cannot write anything until the
525 * previous data has been completely sent.
527 if (hs_ep->fifo_load != 0) {
528 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
532 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
534 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
536 /* how much of the data has moved */
537 size_done = hs_ep->size_loaded - size_left;
539 /* how much data is left in the fifo */
540 can_write = hs_ep->fifo_load - size_done;
541 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
542 __func__, can_write);
544 can_write = hs_ep->fifo_size - can_write;
545 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
546 __func__, can_write);
548 if (can_write <= 0) {
549 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
552 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
553 can_write = dwc2_readl(hsotg,
554 DTXFSTS(hs_ep->fifo_index));
559 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
561 "%s: no queue slots available (0x%08x)\n",
564 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
568 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
569 can_write *= 4; /* fifo size is in 32bit quantities. */
572 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
574 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
575 __func__, gnptxsts, can_write, to_write, max_transfer);
578 * limit to 512 bytes of data, it seems at least on the non-periodic
579 * FIFO, requests of >512 cause the endpoint to get stuck with a
580 * fragment of the end of the transfer in it.
582 if (can_write > 512 && !periodic)
586 * limit the write to one max-packet size worth of data, but allow
587 * the transfer to return that it did not run out of fifo space
590 if (to_write > max_transfer) {
591 to_write = max_transfer;
593 /* it's needed only when we do not use dedicated fifos */
594 if (!hsotg->dedicated_fifos)
595 dwc2_hsotg_en_gsint(hsotg,
596 periodic ? GINTSTS_PTXFEMP :
600 /* see if we can write data */
602 if (to_write > can_write) {
603 to_write = can_write;
604 pkt_round = to_write % max_transfer;
607 * Round the write down to an
608 * exact number of packets.
610 * Note, we do not currently check to see if we can ever
611 * write a full packet or not to the FIFO.
615 to_write -= pkt_round;
618 * enable correct FIFO interrupt to alert us when there
622 /* it's needed only when we do not use dedicated fifos */
623 if (!hsotg->dedicated_fifos)
624 dwc2_hsotg_en_gsint(hsotg,
625 periodic ? GINTSTS_PTXFEMP :
629 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
630 to_write, hs_req->req.length, can_write, buf_pos);
635 hs_req->req.actual = buf_pos + to_write;
636 hs_ep->total_data += to_write;
639 hs_ep->fifo_load += to_write;
641 to_write = DIV_ROUND_UP(to_write, 4);
642 data = hs_req->req.buf + buf_pos;
644 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
646 return (to_write >= can_write) ? -ENOSPC : 0;
650 * get_ep_limit - get the maximum data legnth for this endpoint
651 * @hs_ep: The endpoint
653 * Return the maximum data that can be queued in one go on a given endpoint
654 * so that transfers that are too long can be split.
656 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
658 int index = hs_ep->index;
659 unsigned int maxsize;
663 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
664 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
668 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
673 /* we made the constant loading easier above by using +1 */
678 * constrain by packet count if maxpkts*pktsize is greater
679 * than the length register size.
682 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
683 maxsize = maxpkt * hs_ep->ep.maxpacket;
689 * dwc2_hsotg_read_frameno - read current frame number
690 * @hsotg: The device instance
692 * Return the current frame number
694 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
698 dsts = dwc2_readl(hsotg, DSTS);
699 dsts &= DSTS_SOFFN_MASK;
700 dsts >>= DSTS_SOFFN_SHIFT;
706 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
707 * DMA descriptor chain prepared for specific endpoint
708 * @hs_ep: The endpoint
710 * Return the maximum data that can be queued in one go on a given endpoint
711 * depending on its descriptor chain capacity so that transfers that
712 * are too long can be split.
714 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
716 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
717 int is_isoc = hs_ep->isochronous;
718 unsigned int maxsize;
719 u32 mps = hs_ep->ep.maxpacket;
720 int dir_in = hs_ep->dir_in;
723 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
724 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
725 MAX_DMA_DESC_NUM_HS_ISOC;
727 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
729 /* Interrupt OUT EP with mps not multiple of 4 */
731 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
732 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
738 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
739 * @hs_ep: The endpoint
740 * @mask: RX/TX bytes mask to be defined
742 * Returns maximum data payload for one descriptor after analyzing endpoint
744 * DMA descriptor transfer bytes limit depends on EP type:
746 * Isochronous - descriptor rx/tx bytes bitfield limit,
747 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
748 * have concatenations from various descriptors within one packet.
749 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
750 * to a single descriptor.
752 * Selects corresponding mask for RX/TX bytes as well.
754 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
756 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
757 u32 mps = hs_ep->ep.maxpacket;
758 int dir_in = hs_ep->dir_in;
761 if (!hs_ep->index && !dir_in) {
763 *mask = DEV_DMA_NBYTES_MASK;
764 } else if (hs_ep->isochronous) {
766 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
767 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
769 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
770 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
773 desc_size = DEV_DMA_NBYTES_LIMIT;
774 *mask = DEV_DMA_NBYTES_MASK;
776 /* Round down desc_size to be mps multiple */
777 desc_size -= desc_size % mps;
780 /* Interrupt OUT EP with mps not multiple of 4 */
782 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
784 *mask = DEV_DMA_NBYTES_MASK;
790 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
791 struct dwc2_dma_desc **desc,
796 int dir_in = hs_ep->dir_in;
797 u32 mps = hs_ep->ep.maxpacket;
803 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
805 hs_ep->desc_count = (len / maxsize) +
806 ((len % maxsize) ? 1 : 0);
808 hs_ep->desc_count = 1;
810 for (i = 0; i < hs_ep->desc_count; ++i) {
812 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
813 << DEV_DMA_BUFF_STS_SHIFT);
816 if (!hs_ep->index && !dir_in)
817 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
820 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
821 (*desc)->buf = dma_buff + offset;
827 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
831 ((hs_ep->send_zlp && true_last) ?
835 len << DEV_DMA_NBYTES_SHIFT & mask;
836 (*desc)->buf = dma_buff + offset;
839 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
840 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
841 << DEV_DMA_BUFF_STS_SHIFT);
847 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
848 * @hs_ep: The endpoint
849 * @ureq: Request to transfer
850 * @offset: offset in bytes
851 * @len: Length of the transfer
853 * This function will iterate over descriptor chain and fill its entries
854 * with corresponding information based on transfer data.
856 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
860 struct usb_request *ureq = NULL;
861 struct dwc2_dma_desc *desc = hs_ep->desc_list;
862 struct scatterlist *sg;
867 ureq = &hs_ep->req->req;
869 /* non-DMA sg buffer */
870 if (!ureq || !ureq->num_sgs) {
871 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
872 dma_buff, len, true);
877 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
878 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
879 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
881 desc_count += hs_ep->desc_count;
884 hs_ep->desc_count = desc_count;
888 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
889 * @hs_ep: The isochronous endpoint.
890 * @dma_buff: usb requests dma buffer.
891 * @len: usb request transfer length.
893 * Fills next free descriptor with the data of the arrived usb request,
894 * frame info, sets Last and IOC bits increments next_desc. If filled
895 * descriptor is not the first one, removes L bit from the previous descriptor
898 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
899 dma_addr_t dma_buff, unsigned int len)
901 struct dwc2_dma_desc *desc;
902 struct dwc2_hsotg *hsotg = hs_ep->parent;
907 dwc2_gadget_get_desc_params(hs_ep, &mask);
909 index = hs_ep->next_desc;
910 desc = &hs_ep->desc_list[index];
912 /* Check if descriptor chain full */
913 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
914 DEV_DMA_BUFF_STS_HREADY) {
915 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
919 /* Clear L bit of previous desc if more than one entries in the chain */
920 if (hs_ep->next_desc)
921 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
923 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
924 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
927 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
929 desc->buf = dma_buff;
930 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
931 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
935 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
938 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
939 DEV_DMA_ISOC_PID_MASK) |
940 ((len % hs_ep->ep.maxpacket) ?
942 ((hs_ep->target_frame <<
943 DEV_DMA_ISOC_FRNUM_SHIFT) &
944 DEV_DMA_ISOC_FRNUM_MASK);
947 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
948 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
950 /* Increment frame number by interval for IN */
952 dwc2_gadget_incr_frame_num(hs_ep);
954 /* Update index of last configured entry in the chain */
956 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
957 hs_ep->next_desc = 0;
963 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
964 * @hs_ep: The isochronous endpoint.
966 * Prepare descriptor chain for isochronous endpoints. Afterwards
967 * write DMA address to HW and enable the endpoint.
969 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
971 struct dwc2_hsotg *hsotg = hs_ep->parent;
972 struct dwc2_hsotg_req *hs_req, *treq;
973 int index = hs_ep->index;
979 struct dwc2_dma_desc *desc;
981 if (list_empty(&hs_ep->queue)) {
982 hs_ep->target_frame = TARGET_FRAME_INITIAL;
983 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
987 /* Initialize descriptor chain by Host Busy status */
988 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
989 desc = &hs_ep->desc_list[i];
991 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
992 << DEV_DMA_BUFF_STS_SHIFT);
995 hs_ep->next_desc = 0;
996 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
997 dma_addr_t dma_addr = hs_req->req.dma;
999 if (hs_req->req.num_sgs) {
1000 WARN_ON(hs_req->req.num_sgs > 1);
1001 dma_addr = sg_dma_address(hs_req->req.sg);
1003 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1004 hs_req->req.length);
1009 hs_ep->compl_desc = 0;
1010 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1011 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1013 /* write descriptor chain address to control register */
1014 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1016 ctrl = dwc2_readl(hsotg, depctl);
1017 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1018 dwc2_writel(hsotg, ctrl, depctl);
1022 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1023 * @hsotg: The controller state.
1024 * @hs_ep: The endpoint to process a request for
1025 * @hs_req: The request to start.
1026 * @continuing: True if we are doing more for the current request.
1028 * Start the given request running by setting the endpoint registers
1029 * appropriately, and writing any data to the FIFOs.
1031 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1032 struct dwc2_hsotg_ep *hs_ep,
1033 struct dwc2_hsotg_req *hs_req,
1036 struct usb_request *ureq = &hs_req->req;
1037 int index = hs_ep->index;
1038 int dir_in = hs_ep->dir_in;
1043 unsigned int length;
1044 unsigned int packets;
1045 unsigned int maxreq;
1046 unsigned int dma_reg;
1049 if (hs_ep->req && !continuing) {
1050 dev_err(hsotg->dev, "%s: active request\n", __func__);
1053 } else if (hs_ep->req != hs_req && continuing) {
1055 "%s: continue different req\n", __func__);
1061 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1063 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1065 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1066 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1067 hs_ep->dir_in ? "in" : "out");
1069 /* If endpoint is stalled, we will restart request later */
1070 ctrl = dwc2_readl(hsotg, epctrl_reg);
1072 if (index && ctrl & DXEPCTL_STALL) {
1073 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1077 length = ureq->length - ureq->actual;
1078 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1079 ureq->length, ureq->actual);
1081 if (!using_desc_dma(hsotg))
1082 maxreq = get_ep_limit(hs_ep);
1084 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1086 if (length > maxreq) {
1087 int round = maxreq % hs_ep->ep.maxpacket;
1089 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1090 __func__, length, maxreq, round);
1092 /* round down to multiple of packets */
1100 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1102 packets = 1; /* send one packet if length is zero. */
1104 if (dir_in && index != 0)
1105 if (hs_ep->isochronous)
1106 epsize = DXEPTSIZ_MC(packets);
1108 epsize = DXEPTSIZ_MC(1);
1113 * zero length packet should be programmed on its own and should not
1114 * be counted in DIEPTSIZ.PktCnt with other packets.
1116 if (dir_in && ureq->zero && !continuing) {
1117 /* Test if zlp is actually required. */
1118 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1119 !(ureq->length % hs_ep->ep.maxpacket))
1120 hs_ep->send_zlp = 1;
1123 epsize |= DXEPTSIZ_PKTCNT(packets);
1124 epsize |= DXEPTSIZ_XFERSIZE(length);
1126 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1127 __func__, packets, length, ureq->length, epsize, epsize_reg);
1129 /* store the request as the current one we're doing */
1130 hs_ep->req = hs_req;
1132 if (using_desc_dma(hsotg)) {
1134 u32 mps = hs_ep->ep.maxpacket;
1136 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1140 else if (length % mps)
1141 length += (mps - (length % mps));
1145 offset = ureq->actual;
1147 /* Fill DDMA chain entries */
1148 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1151 /* write descriptor chain address to control register */
1152 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1154 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1155 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1157 /* write size / packets */
1158 dwc2_writel(hsotg, epsize, epsize_reg);
1160 if (using_dma(hsotg) && !continuing && (length != 0)) {
1162 * write DMA address to control register, buffer
1163 * already synced by dwc2_hsotg_ep_queue().
1166 dwc2_writel(hsotg, ureq->dma, dma_reg);
1168 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1169 __func__, &ureq->dma, dma_reg);
1173 if (hs_ep->isochronous && hs_ep->interval == 1) {
1174 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1175 dwc2_gadget_incr_frame_num(hs_ep);
1177 if (hs_ep->target_frame & 0x1)
1178 ctrl |= DXEPCTL_SETODDFR;
1180 ctrl |= DXEPCTL_SETEVENFR;
1183 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1185 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1187 /* For Setup request do not clear NAK */
1188 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1189 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1191 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1192 dwc2_writel(hsotg, ctrl, epctrl_reg);
1195 * set these, it seems that DMA support increments past the end
1196 * of the packet buffer so we need to calculate the length from
1199 hs_ep->size_loaded = length;
1200 hs_ep->last_load = ureq->actual;
1202 if (dir_in && !using_dma(hsotg)) {
1203 /* set these anyway, we may need them for non-periodic in */
1204 hs_ep->fifo_load = 0;
1206 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1210 * Note, trying to clear the NAK here causes problems with transmit
1211 * on the S3C6400 ending up with the TXFIFO becoming full.
1214 /* check ep is enabled */
1215 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1217 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1218 index, dwc2_readl(hsotg, epctrl_reg));
1220 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1221 __func__, dwc2_readl(hsotg, epctrl_reg));
1223 /* enable ep interrupts */
1224 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1228 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1229 * @hsotg: The device state.
1230 * @hs_ep: The endpoint the request is on.
1231 * @req: The request being processed.
1233 * We've been asked to queue a request, so ensure that the memory buffer
1234 * is correctly setup for DMA. If we've been passed an extant DMA address
1235 * then ensure the buffer has been synced to memory. If our buffer has no
1236 * DMA memory, then we map the memory and mark our request to allow us to
1237 * cleanup on completion.
1239 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1240 struct dwc2_hsotg_ep *hs_ep,
1241 struct usb_request *req)
1245 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1252 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1253 __func__, req->buf, req->length);
1258 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1259 struct dwc2_hsotg_ep *hs_ep,
1260 struct dwc2_hsotg_req *hs_req)
1262 void *req_buf = hs_req->req.buf;
1264 /* If dma is not being used or buffer is aligned */
1265 if (!using_dma(hsotg) || !((long)req_buf & 3))
1268 WARN_ON(hs_req->saved_req_buf);
1270 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1271 hs_ep->ep.name, req_buf, hs_req->req.length);
1273 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1274 if (!hs_req->req.buf) {
1275 hs_req->req.buf = req_buf;
1277 "%s: unable to allocate memory for bounce buffer\n",
1282 /* Save actual buffer */
1283 hs_req->saved_req_buf = req_buf;
1286 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1291 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1292 struct dwc2_hsotg_ep *hs_ep,
1293 struct dwc2_hsotg_req *hs_req)
1295 /* If dma is not being used or buffer was aligned */
1296 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1299 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1300 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1302 /* Copy data from bounce buffer on successful out transfer */
1303 if (!hs_ep->dir_in && !hs_req->req.status)
1304 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1305 hs_req->req.actual);
1307 /* Free bounce buffer */
1308 kfree(hs_req->req.buf);
1310 hs_req->req.buf = hs_req->saved_req_buf;
1311 hs_req->saved_req_buf = NULL;
1315 * dwc2_gadget_target_frame_elapsed - Checks target frame
1316 * @hs_ep: The driver endpoint to check
1318 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1319 * corresponding transfer.
1321 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1323 struct dwc2_hsotg *hsotg = hs_ep->parent;
1324 u32 target_frame = hs_ep->target_frame;
1325 u32 current_frame = hsotg->frame_number;
1326 bool frame_overrun = hs_ep->frame_overrun;
1328 if (!frame_overrun && current_frame >= target_frame)
1331 if (frame_overrun && current_frame >= target_frame &&
1332 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1339 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1340 * @hsotg: The driver state
1341 * @hs_ep: the ep descriptor chain is for
1343 * Called to update EP0 structure's pointers depend on stage of
1346 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1347 struct dwc2_hsotg_ep *hs_ep)
1349 switch (hsotg->ep0_state) {
1350 case DWC2_EP0_SETUP:
1351 case DWC2_EP0_STATUS_OUT:
1352 hs_ep->desc_list = hsotg->setup_desc[0];
1353 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1355 case DWC2_EP0_DATA_IN:
1356 case DWC2_EP0_STATUS_IN:
1357 hs_ep->desc_list = hsotg->ctrl_in_desc;
1358 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1360 case DWC2_EP0_DATA_OUT:
1361 hs_ep->desc_list = hsotg->ctrl_out_desc;
1362 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1365 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1373 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1376 struct dwc2_hsotg_req *hs_req = our_req(req);
1377 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1378 struct dwc2_hsotg *hs = hs_ep->parent;
1385 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1386 ep->name, req, req->length, req->buf, req->no_interrupt,
1387 req->zero, req->short_not_ok);
1389 /* Prevent new request submission when controller is suspended */
1390 if (hs->lx_state != DWC2_L0) {
1391 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1396 /* initialise status of the request */
1397 INIT_LIST_HEAD(&hs_req->queue);
1399 req->status = -EINPROGRESS;
1401 /* Don't queue ISOC request if length greater than mps*mc */
1402 if (hs_ep->isochronous &&
1403 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1404 dev_err(hs->dev, "req length > maxpacket*mc\n");
1408 /* In DDMA mode for ISOC's don't queue request if length greater
1409 * than descriptor limits.
1411 if (using_desc_dma(hs) && hs_ep->isochronous) {
1412 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1413 if (hs_ep->dir_in && req->length > maxsize) {
1414 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1415 req->length, maxsize);
1419 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1420 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1421 req->length, hs_ep->ep.maxpacket);
1426 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1430 /* if we're using DMA, sync the buffers as necessary */
1431 if (using_dma(hs)) {
1432 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1436 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1437 if (using_desc_dma(hs) && !hs_ep->index) {
1438 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1443 first = list_empty(&hs_ep->queue);
1444 list_add_tail(&hs_req->queue, &hs_ep->queue);
1447 * Handle DDMA isochronous transfers separately - just add new entry
1448 * to the descriptor chain.
1449 * Transfer will be started once SW gets either one of NAK or
1450 * OutTknEpDis interrupts.
1452 if (using_desc_dma(hs) && hs_ep->isochronous) {
1453 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1454 dma_addr_t dma_addr = hs_req->req.dma;
1456 if (hs_req->req.num_sgs) {
1457 WARN_ON(hs_req->req.num_sgs > 1);
1458 dma_addr = sg_dma_address(hs_req->req.sg);
1460 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1461 hs_req->req.length);
1466 /* Change EP direction if status phase request is after data out */
1467 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1468 hs->ep0_state == DWC2_EP0_DATA_OUT)
1472 if (!hs_ep->isochronous) {
1473 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1477 /* Update current frame number value. */
1478 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1479 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1480 dwc2_gadget_incr_frame_num(hs_ep);
1481 /* Update current frame number value once more as it
1484 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1487 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1488 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1493 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1496 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1497 struct dwc2_hsotg *hs = hs_ep->parent;
1498 unsigned long flags = 0;
1501 spin_lock_irqsave(&hs->lock, flags);
1502 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1503 spin_unlock_irqrestore(&hs->lock, flags);
1508 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1509 struct usb_request *req)
1511 struct dwc2_hsotg_req *hs_req = our_req(req);
1517 * dwc2_hsotg_complete_oursetup - setup completion callback
1518 * @ep: The endpoint the request was on.
1519 * @req: The request completed.
1521 * Called on completion of any requests the driver itself
1522 * submitted that need cleaning up.
1524 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1525 struct usb_request *req)
1527 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1528 struct dwc2_hsotg *hsotg = hs_ep->parent;
1530 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1532 dwc2_hsotg_ep_free_request(ep, req);
1536 * ep_from_windex - convert control wIndex value to endpoint
1537 * @hsotg: The driver state.
1538 * @windex: The control request wIndex field (in host order).
1540 * Convert the given wIndex into a pointer to an driver endpoint
1541 * structure, or return NULL if it is not a valid endpoint.
1543 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1546 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1547 int idx = windex & 0x7F;
1549 if (windex >= 0x100)
1552 if (idx > hsotg->num_of_eps)
1555 return index_to_ep(hsotg, idx, dir);
1559 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1560 * @hsotg: The driver state.
1561 * @testmode: requested usb test mode
1562 * Enable usb Test Mode requested by the Host.
1564 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1566 int dctl = dwc2_readl(hsotg, DCTL);
1568 dctl &= ~DCTL_TSTCTL_MASK;
1572 case USB_TEST_SE0_NAK:
1573 case USB_TEST_PACKET:
1574 case USB_TEST_FORCE_ENABLE:
1575 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1580 dwc2_writel(hsotg, dctl, DCTL);
1585 * dwc2_hsotg_send_reply - send reply to control request
1586 * @hsotg: The device state
1588 * @buff: Buffer for request
1589 * @length: Length of reply.
1591 * Create a request and queue it on the given endpoint. This is useful as
1592 * an internal method of sending replies to certain control requests, etc.
1594 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1595 struct dwc2_hsotg_ep *ep,
1599 struct usb_request *req;
1602 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1604 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1605 hsotg->ep0_reply = req;
1607 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1611 req->buf = hsotg->ep0_buff;
1612 req->length = length;
1614 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1618 req->complete = dwc2_hsotg_complete_oursetup;
1621 memcpy(req->buf, buff, length);
1623 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1625 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1633 * dwc2_hsotg_process_req_status - process request GET_STATUS
1634 * @hsotg: The device state
1635 * @ctrl: USB control request
1637 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1638 struct usb_ctrlrequest *ctrl)
1640 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1641 struct dwc2_hsotg_ep *ep;
1646 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1649 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1653 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1654 case USB_RECIP_DEVICE:
1655 status = hsotg->gadget.is_selfpowered <<
1656 USB_DEVICE_SELF_POWERED;
1657 status |= hsotg->remote_wakeup_allowed <<
1658 USB_DEVICE_REMOTE_WAKEUP;
1659 reply = cpu_to_le16(status);
1662 case USB_RECIP_INTERFACE:
1663 /* currently, the data result should be zero */
1664 reply = cpu_to_le16(0);
1667 case USB_RECIP_ENDPOINT:
1668 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1672 reply = cpu_to_le16(ep->halted ? 1 : 0);
1679 if (le16_to_cpu(ctrl->wLength) != 2)
1682 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1684 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1691 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1694 * get_ep_head - return the first request on the endpoint
1695 * @hs_ep: The controller endpoint to get
1697 * Get the first request on the endpoint.
1699 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1701 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1706 * dwc2_gadget_start_next_request - Starts next request from ep queue
1707 * @hs_ep: Endpoint structure
1709 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1710 * in its handler. Hence we need to unmask it here to be able to do
1711 * resynchronization.
1713 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1716 struct dwc2_hsotg *hsotg = hs_ep->parent;
1717 int dir_in = hs_ep->dir_in;
1718 struct dwc2_hsotg_req *hs_req;
1719 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1721 if (!list_empty(&hs_ep->queue)) {
1722 hs_req = get_ep_head(hs_ep);
1723 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1726 if (!hs_ep->isochronous)
1730 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1733 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1735 mask = dwc2_readl(hsotg, epmsk_reg);
1736 mask |= DOEPMSK_OUTTKNEPDISMSK;
1737 dwc2_writel(hsotg, mask, epmsk_reg);
1742 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1743 * @hsotg: The device state
1744 * @ctrl: USB control request
1746 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1747 struct usb_ctrlrequest *ctrl)
1749 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1750 struct dwc2_hsotg_req *hs_req;
1751 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1752 struct dwc2_hsotg_ep *ep;
1759 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1760 __func__, set ? "SET" : "CLEAR");
1762 wValue = le16_to_cpu(ctrl->wValue);
1763 wIndex = le16_to_cpu(ctrl->wIndex);
1764 recip = ctrl->bRequestType & USB_RECIP_MASK;
1767 case USB_RECIP_DEVICE:
1769 case USB_DEVICE_REMOTE_WAKEUP:
1771 hsotg->remote_wakeup_allowed = 1;
1773 hsotg->remote_wakeup_allowed = 0;
1776 case USB_DEVICE_TEST_MODE:
1777 if ((wIndex & 0xff) != 0)
1782 hsotg->test_mode = wIndex >> 8;
1788 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1791 "%s: failed to send reply\n", __func__);
1796 case USB_RECIP_ENDPOINT:
1797 ep = ep_from_windex(hsotg, wIndex);
1799 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1805 case USB_ENDPOINT_HALT:
1806 halted = ep->halted;
1808 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1810 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1813 "%s: failed to send reply\n", __func__);
1818 * we have to complete all requests for ep if it was
1819 * halted, and the halt was cleared by CLEAR_FEATURE
1822 if (!set && halted) {
1824 * If we have request in progress,
1830 list_del_init(&hs_req->queue);
1831 if (hs_req->req.complete) {
1832 spin_unlock(&hsotg->lock);
1833 usb_gadget_giveback_request(
1834 &ep->ep, &hs_req->req);
1835 spin_lock(&hsotg->lock);
1839 /* If we have pending request, then start it */
1841 dwc2_gadget_start_next_request(ep);
1856 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1859 * dwc2_hsotg_stall_ep0 - stall ep0
1860 * @hsotg: The device state
1862 * Set stall for ep0 as response for setup request.
1864 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1866 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1870 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1871 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1874 * DxEPCTL_Stall will be cleared by EP once it has
1875 * taken effect, so no need to clear later.
1878 ctrl = dwc2_readl(hsotg, reg);
1879 ctrl |= DXEPCTL_STALL;
1880 ctrl |= DXEPCTL_CNAK;
1881 dwc2_writel(hsotg, ctrl, reg);
1884 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1885 ctrl, reg, dwc2_readl(hsotg, reg));
1888 * complete won't be called, so we enqueue
1889 * setup request here
1891 dwc2_hsotg_enqueue_setup(hsotg);
1895 * dwc2_hsotg_process_control - process a control request
1896 * @hsotg: The device state
1897 * @ctrl: The control request received
1899 * The controller has received the SETUP phase of a control request, and
1900 * needs to work out what to do next (and whether to pass it on to the
1903 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1904 struct usb_ctrlrequest *ctrl)
1906 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1911 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1912 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1913 ctrl->wIndex, ctrl->wLength);
1915 if (ctrl->wLength == 0) {
1917 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1918 } else if (ctrl->bRequestType & USB_DIR_IN) {
1920 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1923 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1926 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1927 switch (ctrl->bRequest) {
1928 case USB_REQ_SET_ADDRESS:
1929 hsotg->connected = 1;
1930 dcfg = dwc2_readl(hsotg, DCFG);
1931 dcfg &= ~DCFG_DEVADDR_MASK;
1932 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1933 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1934 dwc2_writel(hsotg, dcfg, DCFG);
1936 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1938 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1941 case USB_REQ_GET_STATUS:
1942 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1945 case USB_REQ_CLEAR_FEATURE:
1946 case USB_REQ_SET_FEATURE:
1947 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1952 /* as a fallback, try delivering it to the driver to deal with */
1954 if (ret == 0 && hsotg->driver) {
1955 spin_unlock(&hsotg->lock);
1956 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1957 spin_lock(&hsotg->lock);
1959 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1962 hsotg->delayed_status = false;
1963 if (ret == USB_GADGET_DELAYED_STATUS)
1964 hsotg->delayed_status = true;
1967 * the request is either unhandlable, or is not formatted correctly
1968 * so respond with a STALL for the status stage to indicate failure.
1972 dwc2_hsotg_stall_ep0(hsotg);
1976 * dwc2_hsotg_complete_setup - completion of a setup transfer
1977 * @ep: The endpoint the request was on.
1978 * @req: The request completed.
1980 * Called on completion of any requests the driver itself submitted for
1983 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1984 struct usb_request *req)
1986 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1987 struct dwc2_hsotg *hsotg = hs_ep->parent;
1989 if (req->status < 0) {
1990 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1994 spin_lock(&hsotg->lock);
1995 if (req->actual == 0)
1996 dwc2_hsotg_enqueue_setup(hsotg);
1998 dwc2_hsotg_process_control(hsotg, req->buf);
1999 spin_unlock(&hsotg->lock);
2003 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2004 * @hsotg: The device state.
2006 * Enqueue a request on EP0 if necessary to received any SETUP packets
2007 * received from the host.
2009 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2011 struct usb_request *req = hsotg->ctrl_req;
2012 struct dwc2_hsotg_req *hs_req = our_req(req);
2015 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2019 req->buf = hsotg->ctrl_buff;
2020 req->complete = dwc2_hsotg_complete_setup;
2022 if (!list_empty(&hs_req->queue)) {
2023 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2027 hsotg->eps_out[0]->dir_in = 0;
2028 hsotg->eps_out[0]->send_zlp = 0;
2029 hsotg->ep0_state = DWC2_EP0_SETUP;
2031 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2033 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2035 * Don't think there's much we can do other than watch the
2041 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2042 struct dwc2_hsotg_ep *hs_ep)
2045 u8 index = hs_ep->index;
2046 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2047 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2050 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2053 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2055 if (using_desc_dma(hsotg)) {
2056 /* Not specific buffer needed for ep0 ZLP */
2057 dma_addr_t dma = hs_ep->desc_list_dma;
2060 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2062 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2064 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2065 DXEPTSIZ_XFERSIZE(0),
2069 ctrl = dwc2_readl(hsotg, epctl_reg);
2070 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2071 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2072 ctrl |= DXEPCTL_USBACTEP;
2073 dwc2_writel(hsotg, ctrl, epctl_reg);
2077 * dwc2_hsotg_complete_request - complete a request given to us
2078 * @hsotg: The device state.
2079 * @hs_ep: The endpoint the request was on.
2080 * @hs_req: The request to complete.
2081 * @result: The result code (0 => Ok, otherwise errno)
2083 * The given request has finished, so call the necessary completion
2084 * if it has one and then look to see if we can start a new request
2087 * Note, expects the ep to already be locked as appropriate.
2089 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2090 struct dwc2_hsotg_ep *hs_ep,
2091 struct dwc2_hsotg_req *hs_req,
2095 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2099 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2100 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2103 * only replace the status if we've not already set an error
2104 * from a previous transaction
2107 if (hs_req->req.status == -EINPROGRESS)
2108 hs_req->req.status = result;
2110 if (using_dma(hsotg))
2111 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2113 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2116 list_del_init(&hs_req->queue);
2119 * call the complete request with the locks off, just in case the
2120 * request tries to queue more work for this endpoint.
2123 if (hs_req->req.complete) {
2124 spin_unlock(&hsotg->lock);
2125 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2126 spin_lock(&hsotg->lock);
2129 /* In DDMA don't need to proceed to starting of next ISOC request */
2130 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2134 * Look to see if there is anything else to do. Note, the completion
2135 * of the previous request may have caused a new request to be started
2136 * so be careful when doing this.
2139 if (!hs_ep->req && result >= 0)
2140 dwc2_gadget_start_next_request(hs_ep);
2144 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2145 * @hs_ep: The endpoint the request was on.
2147 * Get first request from the ep queue, determine descriptor on which complete
2148 * happened. SW discovers which descriptor currently in use by HW, adjusts
2149 * dma_address and calculates index of completed descriptor based on the value
2150 * of DEPDMA register. Update actual length of request, giveback to gadget.
2152 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2154 struct dwc2_hsotg *hsotg = hs_ep->parent;
2155 struct dwc2_hsotg_req *hs_req;
2156 struct usb_request *ureq;
2160 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2162 /* Process only descriptors with buffer status set to DMA done */
2163 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2164 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2166 hs_req = get_ep_head(hs_ep);
2168 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2171 ureq = &hs_req->req;
2173 /* Check completion status */
2174 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2176 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2177 DEV_DMA_ISOC_RX_NBYTES_MASK;
2178 ureq->actual = ureq->length - ((desc_sts & mask) >>
2179 DEV_DMA_ISOC_NBYTES_SHIFT);
2181 /* Adjust actual len for ISOC Out if len is
2184 if (!hs_ep->dir_in && ureq->length & 0x3)
2185 ureq->actual += 4 - (ureq->length & 0x3);
2187 /* Set actual frame number for completed transfers */
2188 ureq->frame_number =
2189 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2190 DEV_DMA_ISOC_FRNUM_SHIFT;
2193 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2195 hs_ep->compl_desc++;
2196 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2197 hs_ep->compl_desc = 0;
2198 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2203 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2204 * @hs_ep: The isochronous endpoint.
2206 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2207 * interrupt. Reset target frame and next_desc to allow to start
2208 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2209 * interrupt for OUT direction.
2211 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2213 struct dwc2_hsotg *hsotg = hs_ep->parent;
2216 dwc2_flush_rx_fifo(hsotg);
2217 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2219 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2220 hs_ep->next_desc = 0;
2221 hs_ep->compl_desc = 0;
2225 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2226 * @hsotg: The device state.
2227 * @ep_idx: The endpoint index for the data
2228 * @size: The size of data in the fifo, in bytes
2230 * The FIFO status shows there is data to read from the FIFO for a given
2231 * endpoint, so sort out whether we need to read the data into a request
2232 * that has been made for that endpoint.
2234 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2236 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2237 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2243 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2247 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2248 __func__, size, ep_idx, epctl);
2250 /* dump the data from the FIFO, we've nothing we can do */
2251 for (ptr = 0; ptr < size; ptr += 4)
2252 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2258 read_ptr = hs_req->req.actual;
2259 max_req = hs_req->req.length - read_ptr;
2261 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2262 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2264 if (to_read > max_req) {
2266 * more data appeared than we where willing
2267 * to deal with in this request.
2270 /* currently we don't deal this */
2274 hs_ep->total_data += to_read;
2275 hs_req->req.actual += to_read;
2276 to_read = DIV_ROUND_UP(to_read, 4);
2279 * note, we might over-write the buffer end by 3 bytes depending on
2280 * alignment of the data.
2282 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2283 hs_req->req.buf + read_ptr, to_read);
2287 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2288 * @hsotg: The device instance
2289 * @dir_in: If IN zlp
2291 * Generate a zero-length IN packet request for terminating a SETUP
2294 * Note, since we don't write any data to the TxFIFO, then it is
2295 * currently believed that we do not need to wait for any space in
2298 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2300 /* eps_out[0] is used in both directions */
2301 hsotg->eps_out[0]->dir_in = dir_in;
2302 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2304 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2307 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2312 ctrl = dwc2_readl(hsotg, epctl_reg);
2313 if (ctrl & DXEPCTL_EOFRNUM)
2314 ctrl |= DXEPCTL_SETEVENFR;
2316 ctrl |= DXEPCTL_SETODDFR;
2317 dwc2_writel(hsotg, ctrl, epctl_reg);
2321 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2322 * @hs_ep - The endpoint on which transfer went
2324 * Iterate over endpoints descriptor chain and get info on bytes remained
2325 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2327 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2329 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2330 struct dwc2_hsotg *hsotg = hs_ep->parent;
2331 unsigned int bytes_rem = 0;
2332 unsigned int bytes_rem_correction = 0;
2333 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2336 u32 mps = hs_ep->ep.maxpacket;
2337 int dir_in = hs_ep->dir_in;
2342 /* Interrupt OUT EP with mps not multiple of 4 */
2344 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2345 bytes_rem_correction = 4 - (mps % 4);
2347 for (i = 0; i < hs_ep->desc_count; ++i) {
2348 status = desc->status;
2349 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2350 bytes_rem -= bytes_rem_correction;
2352 if (status & DEV_DMA_STS_MASK)
2353 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2354 i, status & DEV_DMA_STS_MASK);
2356 if (status & DEV_DMA_L)
2366 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2367 * @hsotg: The device instance
2368 * @epnum: The endpoint received from
2370 * The RXFIFO has delivered an OutDone event, which means that the data
2371 * transfer for an OUT endpoint has been completed, either by a short
2372 * packet or by the finish of a transfer.
2374 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2376 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2377 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2378 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2379 struct usb_request *req = &hs_req->req;
2380 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2384 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2388 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2389 dev_dbg(hsotg->dev, "zlp packet received\n");
2390 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2391 dwc2_hsotg_enqueue_setup(hsotg);
2395 if (using_desc_dma(hsotg))
2396 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2398 if (using_dma(hsotg)) {
2399 unsigned int size_done;
2402 * Calculate the size of the transfer by checking how much
2403 * is left in the endpoint size register and then working it
2404 * out from the amount we loaded for the transfer.
2406 * We need to do this as DMA pointers are always 32bit aligned
2407 * so may overshoot/undershoot the transfer.
2410 size_done = hs_ep->size_loaded - size_left;
2411 size_done += hs_ep->last_load;
2413 req->actual = size_done;
2416 /* if there is more request to do, schedule new transfer */
2417 if (req->actual < req->length && size_left == 0) {
2418 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2422 if (req->actual < req->length && req->short_not_ok) {
2423 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2424 __func__, req->actual, req->length);
2427 * todo - what should we return here? there's no one else
2428 * even bothering to check the status.
2432 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2433 if (!using_desc_dma(hsotg) && epnum == 0 &&
2434 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2435 /* Move to STATUS IN */
2436 if (!hsotg->delayed_status)
2437 dwc2_hsotg_ep0_zlp(hsotg, true);
2441 * Slave mode OUT transfers do not go through XferComplete so
2442 * adjust the ISOC parity here.
2444 if (!using_dma(hsotg)) {
2445 if (hs_ep->isochronous && hs_ep->interval == 1)
2446 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2447 else if (hs_ep->isochronous && hs_ep->interval > 1)
2448 dwc2_gadget_incr_frame_num(hs_ep);
2451 /* Set actual frame number for completed transfers */
2452 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2453 req->frame_number = hsotg->frame_number;
2455 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2459 * dwc2_hsotg_handle_rx - RX FIFO has data
2460 * @hsotg: The device instance
2462 * The IRQ handler has detected that the RX FIFO has some data in it
2463 * that requires processing, so find out what is in there and do the
2466 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2467 * chunks, so if you have x packets received on an endpoint you'll get x
2468 * FIFO events delivered, each with a packet's worth of data in it.
2470 * When using DMA, we should not be processing events from the RXFIFO
2471 * as the actual data should be sent to the memory directly and we turn
2472 * on the completion interrupts to get notifications of transfer completion.
2474 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2476 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2477 u32 epnum, status, size;
2479 WARN_ON(using_dma(hsotg));
2481 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2482 status = grxstsr & GRXSTS_PKTSTS_MASK;
2484 size = grxstsr & GRXSTS_BYTECNT_MASK;
2485 size >>= GRXSTS_BYTECNT_SHIFT;
2487 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2488 __func__, grxstsr, size, epnum);
2490 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2491 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2492 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2495 case GRXSTS_PKTSTS_OUTDONE:
2496 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2497 dwc2_hsotg_read_frameno(hsotg));
2499 if (!using_dma(hsotg))
2500 dwc2_hsotg_handle_outdone(hsotg, epnum);
2503 case GRXSTS_PKTSTS_SETUPDONE:
2505 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2506 dwc2_hsotg_read_frameno(hsotg),
2507 dwc2_readl(hsotg, DOEPCTL(0)));
2509 * Call dwc2_hsotg_handle_outdone here if it was not called from
2510 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2511 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2513 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2514 dwc2_hsotg_handle_outdone(hsotg, epnum);
2517 case GRXSTS_PKTSTS_OUTRX:
2518 dwc2_hsotg_rx_data(hsotg, epnum, size);
2521 case GRXSTS_PKTSTS_SETUPRX:
2523 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2524 dwc2_hsotg_read_frameno(hsotg),
2525 dwc2_readl(hsotg, DOEPCTL(0)));
2527 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2529 dwc2_hsotg_rx_data(hsotg, epnum, size);
2533 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2536 dwc2_hsotg_dump(hsotg);
2542 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2543 * @mps: The maximum packet size in bytes.
2545 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2549 return D0EPCTL_MPS_64;
2551 return D0EPCTL_MPS_32;
2553 return D0EPCTL_MPS_16;
2555 return D0EPCTL_MPS_8;
2558 /* bad max packet size, warn and return invalid result */
2564 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2565 * @hsotg: The driver state.
2566 * @ep: The index number of the endpoint
2567 * @mps: The maximum packet size in bytes
2568 * @mc: The multicount value
2569 * @dir_in: True if direction is in.
2571 * Configure the maximum packet size for the given endpoint, updating
2572 * the hardware control registers to reflect this.
2574 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2575 unsigned int ep, unsigned int mps,
2576 unsigned int mc, unsigned int dir_in)
2578 struct dwc2_hsotg_ep *hs_ep;
2581 hs_ep = index_to_ep(hsotg, ep, dir_in);
2586 u32 mps_bytes = mps;
2588 /* EP0 is a special case */
2589 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2592 hs_ep->ep.maxpacket = mps_bytes;
2600 hs_ep->ep.maxpacket = mps;
2604 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2605 reg &= ~DXEPCTL_MPS_MASK;
2607 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2609 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2610 reg &= ~DXEPCTL_MPS_MASK;
2612 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2618 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2622 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2623 * @hsotg: The driver state
2624 * @idx: The index for the endpoint (0..15)
2626 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2628 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2631 /* wait until the fifo is flushed */
2632 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2633 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2638 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2639 * @hsotg: The driver state
2640 * @hs_ep: The driver endpoint to check.
2642 * Check to see if there is a request that has data to send, and if so
2643 * make an attempt to write data into the FIFO.
2645 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2646 struct dwc2_hsotg_ep *hs_ep)
2648 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2650 if (!hs_ep->dir_in || !hs_req) {
2652 * if request is not enqueued, we disable interrupts
2653 * for endpoints, excepting ep0
2655 if (hs_ep->index != 0)
2656 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2661 if (hs_req->req.actual < hs_req->req.length) {
2662 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2664 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2671 * dwc2_hsotg_complete_in - complete IN transfer
2672 * @hsotg: The device state.
2673 * @hs_ep: The endpoint that has just completed.
2675 * An IN transfer has been completed, update the transfer's state and then
2676 * call the relevant completion routines.
2678 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2679 struct dwc2_hsotg_ep *hs_ep)
2681 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2682 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2683 int size_left, size_done;
2686 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2690 /* Finish ZLP handling for IN EP0 transactions */
2691 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2692 dev_dbg(hsotg->dev, "zlp packet sent\n");
2695 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2696 * changed to IN. Change back to complete OUT transfer request
2700 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2701 if (hsotg->test_mode) {
2704 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2706 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2708 dwc2_hsotg_stall_ep0(hsotg);
2712 dwc2_hsotg_enqueue_setup(hsotg);
2717 * Calculate the size of the transfer by checking how much is left
2718 * in the endpoint size register and then working it out from
2719 * the amount we loaded for the transfer.
2721 * We do this even for DMA, as the transfer may have incremented
2722 * past the end of the buffer (DMA transfers are always 32bit
2725 if (using_desc_dma(hsotg)) {
2726 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2728 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2731 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2734 size_done = hs_ep->size_loaded - size_left;
2735 size_done += hs_ep->last_load;
2737 if (hs_req->req.actual != size_done)
2738 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2739 __func__, hs_req->req.actual, size_done);
2741 hs_req->req.actual = size_done;
2742 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2743 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2745 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2746 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2747 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2751 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2752 if (hs_ep->send_zlp) {
2753 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2754 hs_ep->send_zlp = 0;
2755 /* transfer will be completed on next complete interrupt */
2759 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2760 /* Move to STATUS OUT */
2761 dwc2_hsotg_ep0_zlp(hsotg, false);
2765 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2769 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2770 * @hsotg: The device state.
2771 * @idx: Index of ep.
2772 * @dir_in: Endpoint direction 1-in 0-out.
2774 * Reads for endpoint with given index and direction, by masking
2775 * epint_reg with coresponding mask.
2777 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2778 unsigned int idx, int dir_in)
2780 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2781 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2786 mask = dwc2_readl(hsotg, epmsk_reg);
2787 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2788 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2789 mask |= DXEPINT_SETUP_RCVD;
2791 ints = dwc2_readl(hsotg, epint_reg);
2797 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2798 * @hs_ep: The endpoint on which interrupt is asserted.
2800 * This interrupt indicates that the endpoint has been disabled per the
2801 * application's request.
2803 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2804 * in case of ISOC completes current request.
2806 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2807 * request starts it.
2809 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2811 struct dwc2_hsotg *hsotg = hs_ep->parent;
2812 struct dwc2_hsotg_req *hs_req;
2813 unsigned char idx = hs_ep->index;
2814 int dir_in = hs_ep->dir_in;
2815 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2816 int dctl = dwc2_readl(hsotg, DCTL);
2818 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2821 int epctl = dwc2_readl(hsotg, epctl_reg);
2823 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2825 if (hs_ep->isochronous) {
2826 dwc2_hsotg_complete_in(hsotg, hs_ep);
2830 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2831 int dctl = dwc2_readl(hsotg, DCTL);
2833 dctl |= DCTL_CGNPINNAK;
2834 dwc2_writel(hsotg, dctl, DCTL);
2839 if (dctl & DCTL_GOUTNAKSTS) {
2840 dctl |= DCTL_CGOUTNAK;
2841 dwc2_writel(hsotg, dctl, DCTL);
2844 if (!hs_ep->isochronous)
2847 if (list_empty(&hs_ep->queue)) {
2848 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2854 hs_req = get_ep_head(hs_ep);
2856 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2858 dwc2_gadget_incr_frame_num(hs_ep);
2859 /* Update current frame number value. */
2860 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2861 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2863 dwc2_gadget_start_next_request(hs_ep);
2867 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2868 * @ep: The endpoint on which interrupt is asserted.
2870 * This is starting point for ISOC-OUT transfer, synchronization done with
2871 * first out token received from host while corresponding EP is disabled.
2873 * Device does not know initial frame in which out token will come. For this
2874 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2875 * getting this interrupt SW starts calculation for next transfer frame.
2877 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2879 struct dwc2_hsotg *hsotg = ep->parent;
2880 int dir_in = ep->dir_in;
2883 if (dir_in || !ep->isochronous)
2886 if (using_desc_dma(hsotg)) {
2887 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2888 /* Start first ISO Out */
2889 ep->target_frame = hsotg->frame_number;
2890 dwc2_gadget_start_isoc_ddma(ep);
2895 if (ep->interval > 1 &&
2896 ep->target_frame == TARGET_FRAME_INITIAL) {
2899 ep->target_frame = hsotg->frame_number;
2900 dwc2_gadget_incr_frame_num(ep);
2902 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2903 if (ep->target_frame & 0x1)
2904 ctrl |= DXEPCTL_SETODDFR;
2906 ctrl |= DXEPCTL_SETEVENFR;
2908 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2911 dwc2_gadget_start_next_request(ep);
2912 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2913 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2914 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2918 * dwc2_gadget_handle_nak - handle NAK interrupt
2919 * @hs_ep: The endpoint on which interrupt is asserted.
2921 * This is starting point for ISOC-IN transfer, synchronization done with
2922 * first IN token received from host while corresponding EP is disabled.
2924 * Device does not know when first one token will arrive from host. On first
2925 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2926 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2927 * sent in response to that as there was no data in FIFO. SW is basing on this
2928 * interrupt to obtain frame in which token has come and then based on the
2929 * interval calculates next frame for transfer.
2931 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2933 struct dwc2_hsotg *hsotg = hs_ep->parent;
2934 int dir_in = hs_ep->dir_in;
2936 if (!dir_in || !hs_ep->isochronous)
2939 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2941 if (using_desc_dma(hsotg)) {
2942 hs_ep->target_frame = hsotg->frame_number;
2943 dwc2_gadget_incr_frame_num(hs_ep);
2945 /* In service interval mode target_frame must
2946 * be set to last (u)frame of the service interval.
2948 if (hsotg->params.service_interval) {
2949 /* Set target_frame to the first (u)frame of
2950 * the service interval
2952 hs_ep->target_frame &= ~hs_ep->interval + 1;
2954 /* Set target_frame to the last (u)frame of
2955 * the service interval
2957 dwc2_gadget_incr_frame_num(hs_ep);
2958 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2961 dwc2_gadget_start_isoc_ddma(hs_ep);
2965 hs_ep->target_frame = hsotg->frame_number;
2966 if (hs_ep->interval > 1) {
2967 u32 ctrl = dwc2_readl(hsotg,
2968 DIEPCTL(hs_ep->index));
2969 if (hs_ep->target_frame & 0x1)
2970 ctrl |= DXEPCTL_SETODDFR;
2972 ctrl |= DXEPCTL_SETEVENFR;
2974 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2977 dwc2_hsotg_complete_request(hsotg, hs_ep,
2978 get_ep_head(hs_ep), 0);
2981 if (!using_desc_dma(hsotg))
2982 dwc2_gadget_incr_frame_num(hs_ep);
2986 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2987 * @hsotg: The driver state
2988 * @idx: The index for the endpoint (0..15)
2989 * @dir_in: Set if this is an IN endpoint
2991 * Process and clear any interrupt pending for an individual endpoint
2993 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2996 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2997 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2998 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2999 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3002 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3004 /* Clear endpoint interrupts */
3005 dwc2_writel(hsotg, ints, epint_reg);
3008 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3009 __func__, idx, dir_in ? "in" : "out");
3013 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3014 __func__, idx, dir_in ? "in" : "out", ints);
3016 /* Don't process XferCompl interrupt if it is a setup packet */
3017 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3018 ints &= ~DXEPINT_XFERCOMPL;
3021 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3022 * stage and xfercomplete was generated without SETUP phase done
3023 * interrupt. SW should parse received setup packet only after host's
3024 * exit from setup phase of control transfer.
3026 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3027 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3028 ints &= ~DXEPINT_XFERCOMPL;
3030 if (ints & DXEPINT_XFERCOMPL) {
3032 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3033 __func__, dwc2_readl(hsotg, epctl_reg),
3034 dwc2_readl(hsotg, epsiz_reg));
3036 /* In DDMA handle isochronous requests separately */
3037 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3038 /* XferCompl set along with BNA */
3039 if (!(ints & DXEPINT_BNAINTR))
3040 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3041 } else if (dir_in) {
3043 * We get OutDone from the FIFO, so we only
3044 * need to look at completing IN requests here
3045 * if operating slave mode
3047 if (hs_ep->isochronous && hs_ep->interval > 1)
3048 dwc2_gadget_incr_frame_num(hs_ep);
3050 dwc2_hsotg_complete_in(hsotg, hs_ep);
3051 if (ints & DXEPINT_NAKINTRPT)
3052 ints &= ~DXEPINT_NAKINTRPT;
3054 if (idx == 0 && !hs_ep->req)
3055 dwc2_hsotg_enqueue_setup(hsotg);
3056 } else if (using_dma(hsotg)) {
3058 * We're using DMA, we need to fire an OutDone here
3059 * as we ignore the RXFIFO.
3061 if (hs_ep->isochronous && hs_ep->interval > 1)
3062 dwc2_gadget_incr_frame_num(hs_ep);
3064 dwc2_hsotg_handle_outdone(hsotg, idx);
3068 if (ints & DXEPINT_EPDISBLD)
3069 dwc2_gadget_handle_ep_disabled(hs_ep);
3071 if (ints & DXEPINT_OUTTKNEPDIS)
3072 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3074 if (ints & DXEPINT_NAKINTRPT)
3075 dwc2_gadget_handle_nak(hs_ep);
3077 if (ints & DXEPINT_AHBERR)
3078 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3080 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3081 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3083 if (using_dma(hsotg) && idx == 0) {
3085 * this is the notification we've received a
3086 * setup packet. In non-DMA mode we'd get this
3087 * from the RXFIFO, instead we need to process
3094 dwc2_hsotg_handle_outdone(hsotg, 0);
3098 if (ints & DXEPINT_STSPHSERCVD) {
3099 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3101 /* Safety check EP0 state when STSPHSERCVD asserted */
3102 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3103 /* Move to STATUS IN for DDMA */
3104 if (using_desc_dma(hsotg)) {
3105 if (!hsotg->delayed_status)
3106 dwc2_hsotg_ep0_zlp(hsotg, true);
3108 /* In case of 3 stage Control Write with delayed
3109 * status, when Status IN transfer started
3110 * before STSPHSERCVD asserted, NAKSTS bit not
3111 * cleared by CNAK in dwc2_hsotg_start_req()
3112 * function. Clear now NAKSTS to allow complete
3115 dwc2_set_bit(hsotg, DIEPCTL(0),
3122 if (ints & DXEPINT_BACK2BACKSETUP)
3123 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3125 if (ints & DXEPINT_BNAINTR) {
3126 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3127 if (hs_ep->isochronous)
3128 dwc2_gadget_handle_isoc_bna(hs_ep);
3131 if (dir_in && !hs_ep->isochronous) {
3132 /* not sure if this is important, but we'll clear it anyway */
3133 if (ints & DXEPINT_INTKNTXFEMP) {
3134 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3138 /* this probably means something bad is happening */
3139 if (ints & DXEPINT_INTKNEPMIS) {
3140 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3144 /* FIFO has space or is empty (see GAHBCFG) */
3145 if (hsotg->dedicated_fifos &&
3146 ints & DXEPINT_TXFEMP) {
3147 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3149 if (!using_dma(hsotg))
3150 dwc2_hsotg_trytx(hsotg, hs_ep);
3156 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3157 * @hsotg: The device state.
3159 * Handle updating the device settings after the enumeration phase has
3162 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3164 u32 dsts = dwc2_readl(hsotg, DSTS);
3165 int ep0_mps = 0, ep_mps = 8;
3168 * This should signal the finish of the enumeration phase
3169 * of the USB handshaking, so we should now know what rate
3173 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3176 * note, since we're limited by the size of transfer on EP0, and
3177 * it seems IN transfers must be a even number of packets we do
3178 * not advertise a 64byte MPS on EP0.
3181 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3182 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3183 case DSTS_ENUMSPD_FS:
3184 case DSTS_ENUMSPD_FS48:
3185 hsotg->gadget.speed = USB_SPEED_FULL;
3186 ep0_mps = EP0_MPS_LIMIT;
3190 case DSTS_ENUMSPD_HS:
3191 hsotg->gadget.speed = USB_SPEED_HIGH;
3192 ep0_mps = EP0_MPS_LIMIT;
3196 case DSTS_ENUMSPD_LS:
3197 hsotg->gadget.speed = USB_SPEED_LOW;
3201 * note, we don't actually support LS in this driver at the
3202 * moment, and the documentation seems to imply that it isn't
3203 * supported by the PHYs on some of the devices.
3207 dev_info(hsotg->dev, "new device is %s\n",
3208 usb_speed_string(hsotg->gadget.speed));
3211 * we should now know the maximum packet size for an
3212 * endpoint, so set the endpoints to a default value.
3217 /* Initialize ep0 for both in and out directions */
3218 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3219 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3220 for (i = 1; i < hsotg->num_of_eps; i++) {
3221 if (hsotg->eps_in[i])
3222 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3224 if (hsotg->eps_out[i])
3225 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3230 /* ensure after enumeration our EP0 is active */
3232 dwc2_hsotg_enqueue_setup(hsotg);
3234 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3235 dwc2_readl(hsotg, DIEPCTL0),
3236 dwc2_readl(hsotg, DOEPCTL0));
3240 * kill_all_requests - remove all requests from the endpoint's queue
3241 * @hsotg: The device state.
3242 * @ep: The endpoint the requests may be on.
3243 * @result: The result code to use.
3245 * Go through the requests on the given endpoint and mark them
3246 * completed with the given result code.
3248 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3249 struct dwc2_hsotg_ep *ep,
3256 while (!list_empty(&ep->queue)) {
3257 struct dwc2_hsotg_req *req = get_ep_head(ep);
3259 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3262 if (!hsotg->dedicated_fifos)
3264 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3265 if (size < ep->fifo_size)
3266 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3270 * dwc2_hsotg_disconnect - disconnect service
3271 * @hsotg: The device state.
3273 * The device has been disconnected. Remove all current
3274 * transactions and signal the gadget driver that this
3277 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3281 if (!hsotg->connected)
3284 hsotg->connected = 0;
3285 hsotg->test_mode = 0;
3287 /* all endpoints should be shutdown */
3288 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3289 if (hsotg->eps_in[ep])
3290 kill_all_requests(hsotg, hsotg->eps_in[ep],
3292 if (hsotg->eps_out[ep])
3293 kill_all_requests(hsotg, hsotg->eps_out[ep],
3297 call_gadget(hsotg, disconnect);
3298 hsotg->lx_state = DWC2_L3;
3300 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3304 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3305 * @hsotg: The device state:
3306 * @periodic: True if this is a periodic FIFO interrupt
3308 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3310 struct dwc2_hsotg_ep *ep;
3313 /* look through for any more data to transmit */
3314 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3315 ep = index_to_ep(hsotg, epno, 1);
3323 if ((periodic && !ep->periodic) ||
3324 (!periodic && ep->periodic))
3327 ret = dwc2_hsotg_trytx(hsotg, ep);
3333 /* IRQ flags which will trigger a retry around the IRQ loop */
3334 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3338 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3340 * dwc2_hsotg_core_init - issue softreset to the core
3341 * @hsotg: The device state
3342 * @is_usb_reset: Usb resetting flag
3344 * Issue a soft reset to the core, and await the core finishing it.
3346 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3355 /* Kill any ep0 requests as controller will be reinitialized */
3356 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3358 if (!is_usb_reset) {
3359 if (dwc2_core_reset(hsotg, true))
3362 /* all endpoints should be shutdown */
3363 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3364 if (hsotg->eps_in[ep])
3365 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3366 if (hsotg->eps_out[ep])
3367 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3372 * we must now enable ep0 ready for host detection and then
3373 * set configuration.
3376 /* keep other bits untouched (so e.g. forced modes are not lost) */
3377 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3378 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3379 usbcfg |= GUSBCFG_TOUTCAL(7);
3381 /* remove the HNP/SRP and set the PHY */
3382 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3383 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3385 dwc2_phy_init(hsotg, true);
3387 dwc2_hsotg_init_fifo(hsotg);
3390 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3392 dcfg |= DCFG_EPMISCNT(1);
3394 switch (hsotg->params.speed) {
3395 case DWC2_SPEED_PARAM_LOW:
3396 dcfg |= DCFG_DEVSPD_LS;
3398 case DWC2_SPEED_PARAM_FULL:
3399 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3400 dcfg |= DCFG_DEVSPD_FS48;
3402 dcfg |= DCFG_DEVSPD_FS;
3405 dcfg |= DCFG_DEVSPD_HS;
3408 if (hsotg->params.ipg_isoc_en)
3409 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3411 dwc2_writel(hsotg, dcfg, DCFG);
3413 /* Clear any pending OTG interrupts */
3414 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3416 /* Clear any pending interrupts */
3417 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3418 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3419 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3420 GINTSTS_USBRST | GINTSTS_RESETDET |
3421 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3422 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3423 GINTSTS_LPMTRANRCVD;
3425 if (!using_desc_dma(hsotg))
3426 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3428 if (!hsotg->params.external_id_pin_ctl)
3429 intmsk |= GINTSTS_CONIDSTSCHNG;
3431 dwc2_writel(hsotg, intmsk, GINTMSK);
3433 if (using_dma(hsotg)) {
3434 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3435 hsotg->params.ahbcfg,
3438 /* Set DDMA mode support in the core if needed */
3439 if (using_desc_dma(hsotg))
3440 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3443 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3444 (GAHBCFG_NP_TXF_EMP_LVL |
3445 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3446 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3450 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3451 * when we have no data to transfer. Otherwise we get being flooded by
3455 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3456 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3457 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3458 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3462 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3463 * DMA mode we may need this and StsPhseRcvd.
3465 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3466 DOEPMSK_STSPHSERCVDMSK) : 0) |
3467 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3471 /* Enable BNA interrupt for DDMA */
3472 if (using_desc_dma(hsotg)) {
3473 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3474 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3477 /* Enable Service Interval mode if supported */
3478 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3479 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3481 dwc2_writel(hsotg, 0, DAINTMSK);
3483 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3484 dwc2_readl(hsotg, DIEPCTL0),
3485 dwc2_readl(hsotg, DOEPCTL0));
3487 /* enable in and out endpoint interrupts */
3488 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3491 * Enable the RXFIFO when in slave mode, as this is how we collect
3492 * the data. In DMA mode, we get events from the FIFO but also
3493 * things we cannot process, so do not use it.
3495 if (!using_dma(hsotg))
3496 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3498 /* Enable interrupts for EP0 in and out */
3499 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3500 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3502 if (!is_usb_reset) {
3503 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3504 udelay(10); /* see openiboot */
3505 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3508 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3511 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3512 * writing to the EPCTL register..
3515 /* set to read 1 8byte packet */
3516 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3517 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3519 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3520 DXEPCTL_CNAK | DXEPCTL_EPENA |
3524 /* enable, but don't activate EP0in */
3525 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3526 DXEPCTL_USBACTEP, DIEPCTL0);
3528 /* clear global NAKs */
3529 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3531 val |= DCTL_SFTDISCON;
3532 dwc2_set_bit(hsotg, DCTL, val);
3534 /* configure the core to support LPM */
3535 dwc2_gadget_init_lpm(hsotg);
3537 /* program GREFCLK register if needed */
3538 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3539 dwc2_gadget_program_ref_clk(hsotg);
3541 /* must be at-least 3ms to allow bus to see disconnect */
3544 hsotg->lx_state = DWC2_L0;
3546 dwc2_hsotg_enqueue_setup(hsotg);
3548 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3549 dwc2_readl(hsotg, DIEPCTL0),
3550 dwc2_readl(hsotg, DOEPCTL0));
3553 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3555 /* set the soft-disconnect bit */
3556 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3559 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3561 /* remove the soft-disconnect and let's go */
3562 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3566 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3567 * @hsotg: The device state:
3569 * This interrupt indicates one of the following conditions occurred while
3570 * transmitting an ISOC transaction.
3571 * - Corrupted IN Token for ISOC EP.
3572 * - Packet not complete in FIFO.
3574 * The following actions will be taken:
3575 * - Determine the EP
3576 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3578 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3580 struct dwc2_hsotg_ep *hs_ep;
3585 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3587 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3589 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3590 hs_ep = hsotg->eps_in[idx];
3591 /* Proceed only unmasked ISOC EPs */
3592 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3595 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3596 if ((epctrl & DXEPCTL_EPENA) &&
3597 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3598 epctrl |= DXEPCTL_SNAK;
3599 epctrl |= DXEPCTL_EPDIS;
3600 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3604 /* Clear interrupt */
3605 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3609 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3610 * @hsotg: The device state:
3612 * This interrupt indicates one of the following conditions occurred while
3613 * transmitting an ISOC transaction.
3614 * - Corrupted OUT Token for ISOC EP.
3615 * - Packet not complete in FIFO.
3617 * The following actions will be taken:
3618 * - Determine the EP
3619 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3621 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3627 struct dwc2_hsotg_ep *hs_ep;
3630 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3632 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3633 daintmsk >>= DAINT_OUTEP_SHIFT;
3635 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3636 hs_ep = hsotg->eps_out[idx];
3637 /* Proceed only unmasked ISOC EPs */
3638 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3641 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3642 if ((epctrl & DXEPCTL_EPENA) &&
3643 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3644 /* Unmask GOUTNAKEFF interrupt */
3645 gintmsk = dwc2_readl(hsotg, GINTMSK);
3646 gintmsk |= GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(hsotg, gintmsk, GINTMSK);
3649 gintsts = dwc2_readl(hsotg, GINTSTS);
3650 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3651 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3657 /* Clear interrupt */
3658 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3662 * dwc2_hsotg_irq - handle device interrupt
3663 * @irq: The IRQ number triggered
3664 * @pw: The pw value when registered the handler.
3666 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3668 struct dwc2_hsotg *hsotg = pw;
3669 int retry_count = 8;
3673 if (!dwc2_is_device_mode(hsotg))
3676 spin_lock(&hsotg->lock);
3678 gintsts = dwc2_readl(hsotg, GINTSTS);
3679 gintmsk = dwc2_readl(hsotg, GINTMSK);
3681 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3682 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3686 if (gintsts & GINTSTS_RESETDET) {
3687 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3689 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3691 /* This event must be used only if controller is suspended */
3692 if (hsotg->lx_state == DWC2_L2) {
3693 dwc2_exit_partial_power_down(hsotg, true);
3694 hsotg->lx_state = DWC2_L0;
3698 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3699 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3700 u32 connected = hsotg->connected;
3702 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3703 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3704 dwc2_readl(hsotg, GNPTXSTS));
3706 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3708 /* Report disconnection if it is not already done. */
3709 dwc2_hsotg_disconnect(hsotg);
3711 /* Reset device address to zero */
3712 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3714 if (usb_status & GOTGCTL_BSESVLD && connected)
3715 dwc2_hsotg_core_init_disconnected(hsotg, true);
3718 if (gintsts & GINTSTS_ENUMDONE) {
3719 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3721 dwc2_hsotg_irq_enumdone(hsotg);
3724 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3725 u32 daint = dwc2_readl(hsotg, DAINT);
3726 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3727 u32 daint_out, daint_in;
3731 daint_out = daint >> DAINT_OUTEP_SHIFT;
3732 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3734 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3736 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3737 ep++, daint_out >>= 1) {
3739 dwc2_hsotg_epint(hsotg, ep, 0);
3742 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3743 ep++, daint_in >>= 1) {
3745 dwc2_hsotg_epint(hsotg, ep, 1);
3749 /* check both FIFOs */
3751 if (gintsts & GINTSTS_NPTXFEMP) {
3752 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3755 * Disable the interrupt to stop it happening again
3756 * unless one of these endpoint routines decides that
3757 * it needs re-enabling
3760 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3761 dwc2_hsotg_irq_fifoempty(hsotg, false);
3764 if (gintsts & GINTSTS_PTXFEMP) {
3765 dev_dbg(hsotg->dev, "PTxFEmp\n");
3767 /* See note in GINTSTS_NPTxFEmp */
3769 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3770 dwc2_hsotg_irq_fifoempty(hsotg, true);
3773 if (gintsts & GINTSTS_RXFLVL) {
3775 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3776 * we need to retry dwc2_hsotg_handle_rx if this is still
3780 dwc2_hsotg_handle_rx(hsotg);
3783 if (gintsts & GINTSTS_ERLYSUSP) {
3784 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3785 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3789 * these next two seem to crop-up occasionally causing the core
3790 * to shutdown the USB transfer, so try clearing them and logging
3794 if (gintsts & GINTSTS_GOUTNAKEFF) {
3799 struct dwc2_hsotg_ep *hs_ep;
3801 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3802 daintmsk >>= DAINT_OUTEP_SHIFT;
3803 /* Mask this interrupt */
3804 gintmsk = dwc2_readl(hsotg, GINTMSK);
3805 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3806 dwc2_writel(hsotg, gintmsk, GINTMSK);
3808 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3809 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3810 hs_ep = hsotg->eps_out[idx];
3811 /* Proceed only unmasked ISOC EPs */
3812 if (BIT(idx) & ~daintmsk)
3815 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3818 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3819 epctrl |= DXEPCTL_SNAK;
3820 epctrl |= DXEPCTL_EPDIS;
3821 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3826 if (hs_ep->halted) {
3827 if (!(epctrl & DXEPCTL_EPENA))
3828 epctrl |= DXEPCTL_EPENA;
3829 epctrl |= DXEPCTL_EPDIS;
3830 epctrl |= DXEPCTL_STALL;
3831 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3835 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3838 if (gintsts & GINTSTS_GINNAKEFF) {
3839 dev_info(hsotg->dev, "GINNakEff triggered\n");
3841 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3843 dwc2_hsotg_dump(hsotg);
3846 if (gintsts & GINTSTS_INCOMPL_SOIN)
3847 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3849 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3850 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3853 * if we've had fifo events, we should try and go around the
3854 * loop again to see if there's any point in returning yet.
3857 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3860 /* Check WKUP_ALERT interrupt*/
3861 if (hsotg->params.service_interval)
3862 dwc2_gadget_wkup_alert_handler(hsotg);
3864 spin_unlock(&hsotg->lock);
3869 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3870 struct dwc2_hsotg_ep *hs_ep)
3875 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3876 DOEPCTL(hs_ep->index);
3877 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3878 DOEPINT(hs_ep->index);
3880 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3883 if (hs_ep->dir_in) {
3884 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3885 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3886 /* Wait for Nak effect */
3887 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3888 DXEPINT_INEPNAKEFF, 100))
3889 dev_warn(hsotg->dev,
3890 "%s: timeout DIEPINT.NAKEFF\n",
3893 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3894 /* Wait for Nak effect */
3895 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3896 GINTSTS_GINNAKEFF, 100))
3897 dev_warn(hsotg->dev,
3898 "%s: timeout GINTSTS.GINNAKEFF\n",
3902 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3903 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3905 /* Wait for global nak to take effect */
3906 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3907 GINTSTS_GOUTNAKEFF, 100))
3908 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3913 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3915 /* Wait for ep to be disabled */
3916 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3917 dev_warn(hsotg->dev,
3918 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3920 /* Clear EPDISBLD interrupt */
3921 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3923 if (hs_ep->dir_in) {
3924 unsigned short fifo_index;
3926 if (hsotg->dedicated_fifos || hs_ep->periodic)
3927 fifo_index = hs_ep->fifo_index;
3932 dwc2_flush_tx_fifo(hsotg, fifo_index);
3934 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3935 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3936 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3939 /* Remove global NAKs */
3940 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3945 * dwc2_hsotg_ep_enable - enable the given endpoint
3946 * @ep: The USB endpint to configure
3947 * @desc: The USB endpoint descriptor to configure with.
3949 * This is called from the USB gadget code's usb_ep_enable().
3951 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3952 const struct usb_endpoint_descriptor *desc)
3954 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3955 struct dwc2_hsotg *hsotg = hs_ep->parent;
3956 unsigned long flags;
3957 unsigned int index = hs_ep->index;
3963 unsigned int dir_in;
3964 unsigned int i, val, size;
3966 unsigned char ep_type;
3970 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3971 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3972 desc->wMaxPacketSize, desc->bInterval);
3974 /* not to be called for EP0 */
3976 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3980 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3981 if (dir_in != hs_ep->dir_in) {
3982 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3986 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3987 mps = usb_endpoint_maxp(desc);
3988 mc = usb_endpoint_maxp_mult(desc);
3990 /* ISOC IN in DDMA supported bInterval up to 10 */
3991 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3992 dir_in && desc->bInterval > 10) {
3994 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3998 /* High bandwidth ISOC OUT in DDMA not supported */
3999 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4000 !dir_in && mc > 1) {
4002 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4006 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4008 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4009 epctrl = dwc2_readl(hsotg, epctrl_reg);
4011 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4012 __func__, epctrl, epctrl_reg);
4014 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4015 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4017 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4019 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4020 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4021 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4022 desc_num * sizeof(struct dwc2_dma_desc),
4023 &hs_ep->desc_list_dma, GFP_ATOMIC);
4024 if (!hs_ep->desc_list) {
4030 spin_lock_irqsave(&hsotg->lock, flags);
4032 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4033 epctrl |= DXEPCTL_MPS(mps);
4036 * mark the endpoint as active, otherwise the core may ignore
4037 * transactions entirely for this endpoint
4039 epctrl |= DXEPCTL_USBACTEP;
4041 /* update the endpoint state */
4042 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4044 /* default, set to non-periodic */
4045 hs_ep->isochronous = 0;
4046 hs_ep->periodic = 0;
4048 hs_ep->interval = desc->bInterval;
4051 case USB_ENDPOINT_XFER_ISOC:
4052 epctrl |= DXEPCTL_EPTYPE_ISO;
4053 epctrl |= DXEPCTL_SETEVENFR;
4054 hs_ep->isochronous = 1;
4055 hs_ep->interval = 1 << (desc->bInterval - 1);
4056 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4057 hs_ep->next_desc = 0;
4058 hs_ep->compl_desc = 0;
4060 hs_ep->periodic = 1;
4061 mask = dwc2_readl(hsotg, DIEPMSK);
4062 mask |= DIEPMSK_NAKMSK;
4063 dwc2_writel(hsotg, mask, DIEPMSK);
4065 mask = dwc2_readl(hsotg, DOEPMSK);
4066 mask |= DOEPMSK_OUTTKNEPDISMSK;
4067 dwc2_writel(hsotg, mask, DOEPMSK);
4071 case USB_ENDPOINT_XFER_BULK:
4072 epctrl |= DXEPCTL_EPTYPE_BULK;
4075 case USB_ENDPOINT_XFER_INT:
4077 hs_ep->periodic = 1;
4079 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4080 hs_ep->interval = 1 << (desc->bInterval - 1);
4082 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4085 case USB_ENDPOINT_XFER_CONTROL:
4086 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4091 * if the hardware has dedicated fifos, we must give each IN EP
4092 * a unique tx-fifo even if it is non-periodic.
4094 if (dir_in && hsotg->dedicated_fifos) {
4095 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4097 u32 fifo_size = UINT_MAX;
4099 size = hs_ep->ep.maxpacket * hs_ep->mc;
4100 for (i = 1; i <= fifo_count; ++i) {
4101 if (hsotg->fifo_map & (1 << i))
4103 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4104 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4107 /* Search for smallest acceptable fifo */
4108 if (val < fifo_size) {
4115 "%s: No suitable fifo found\n", __func__);
4119 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4120 hsotg->fifo_map |= 1 << fifo_index;
4121 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4122 hs_ep->fifo_index = fifo_index;
4123 hs_ep->fifo_size = fifo_size;
4126 /* for non control endpoints, set PID to D0 */
4127 if (index && !hs_ep->isochronous)
4128 epctrl |= DXEPCTL_SETD0PID;
4130 /* WA for Full speed ISOC IN in DDMA mode.
4131 * By Clear NAK status of EP, core will send ZLP
4132 * to IN token and assert NAK interrupt relying
4133 * on TxFIFO status only
4136 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4137 hs_ep->isochronous && dir_in) {
4138 /* The WA applies only to core versions from 2.72a
4139 * to 4.00a (including both). Also for FS_IOT_1.00a
4142 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4144 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4145 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4146 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4147 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4148 epctrl |= DXEPCTL_CNAK;
4151 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4154 dwc2_writel(hsotg, epctrl, epctrl_reg);
4155 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4156 __func__, dwc2_readl(hsotg, epctrl_reg));
4158 /* enable the endpoint interrupt */
4159 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4162 spin_unlock_irqrestore(&hsotg->lock, flags);
4165 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4166 dmam_free_coherent(hsotg->dev, desc_num *
4167 sizeof(struct dwc2_dma_desc),
4168 hs_ep->desc_list, hs_ep->desc_list_dma);
4169 hs_ep->desc_list = NULL;
4176 * dwc2_hsotg_ep_disable - disable given endpoint
4177 * @ep: The endpoint to disable.
4179 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4181 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4182 struct dwc2_hsotg *hsotg = hs_ep->parent;
4183 int dir_in = hs_ep->dir_in;
4184 int index = hs_ep->index;
4188 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4190 if (ep == &hsotg->eps_out[0]->ep) {
4191 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4195 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4196 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4200 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4202 ctrl = dwc2_readl(hsotg, epctrl_reg);
4204 if (ctrl & DXEPCTL_EPENA)
4205 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4207 ctrl &= ~DXEPCTL_EPENA;
4208 ctrl &= ~DXEPCTL_USBACTEP;
4209 ctrl |= DXEPCTL_SNAK;
4211 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4212 dwc2_writel(hsotg, ctrl, epctrl_reg);
4214 /* disable endpoint interrupts */
4215 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4217 /* terminate all requests with shutdown */
4218 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4220 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4221 hs_ep->fifo_index = 0;
4222 hs_ep->fifo_size = 0;
4227 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4229 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4230 struct dwc2_hsotg *hsotg = hs_ep->parent;
4231 unsigned long flags;
4234 spin_lock_irqsave(&hsotg->lock, flags);
4235 ret = dwc2_hsotg_ep_disable(ep);
4236 spin_unlock_irqrestore(&hsotg->lock, flags);
4241 * on_list - check request is on the given endpoint
4242 * @ep: The endpoint to check.
4243 * @test: The request to test if it is on the endpoint.
4245 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4247 struct dwc2_hsotg_req *req, *treq;
4249 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4258 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4259 * @ep: The endpoint to dequeue.
4260 * @req: The request to be removed from a queue.
4262 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4264 struct dwc2_hsotg_req *hs_req = our_req(req);
4265 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4266 struct dwc2_hsotg *hs = hs_ep->parent;
4267 unsigned long flags;
4269 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4271 spin_lock_irqsave(&hs->lock, flags);
4273 if (!on_list(hs_ep, hs_req)) {
4274 spin_unlock_irqrestore(&hs->lock, flags);
4278 /* Dequeue already started request */
4279 if (req == &hs_ep->req->req)
4280 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4282 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4283 spin_unlock_irqrestore(&hs->lock, flags);
4289 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4290 * @ep: The endpoint to set halt.
4291 * @value: Set or unset the halt.
4292 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4293 * the endpoint is busy processing requests.
4295 * We need to stall the endpoint immediately if request comes from set_feature
4296 * protocol command handler.
4298 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4300 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4301 struct dwc2_hsotg *hs = hs_ep->parent;
4302 int index = hs_ep->index;
4307 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4311 dwc2_hsotg_stall_ep0(hs);
4314 "%s: can't clear halt on ep0\n", __func__);
4318 if (hs_ep->isochronous) {
4319 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4323 if (!now && value && !list_empty(&hs_ep->queue)) {
4324 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4329 if (hs_ep->dir_in) {
4330 epreg = DIEPCTL(index);
4331 epctl = dwc2_readl(hs, epreg);
4334 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4335 if (epctl & DXEPCTL_EPENA)
4336 epctl |= DXEPCTL_EPDIS;
4338 epctl &= ~DXEPCTL_STALL;
4339 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4340 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4341 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4342 epctl |= DXEPCTL_SETD0PID;
4344 dwc2_writel(hs, epctl, epreg);
4346 epreg = DOEPCTL(index);
4347 epctl = dwc2_readl(hs, epreg);
4350 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4351 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4352 // STALL bit will be set in GOUTNAKEFF interrupt handler
4354 epctl &= ~DXEPCTL_STALL;
4355 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4356 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4357 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4358 epctl |= DXEPCTL_SETD0PID;
4359 dwc2_writel(hs, epctl, epreg);
4363 hs_ep->halted = value;
4368 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4369 * @ep: The endpoint to set halt.
4370 * @value: Set or unset the halt.
4372 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4374 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4375 struct dwc2_hsotg *hs = hs_ep->parent;
4376 unsigned long flags = 0;
4379 spin_lock_irqsave(&hs->lock, flags);
4380 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4381 spin_unlock_irqrestore(&hs->lock, flags);
4386 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4387 .enable = dwc2_hsotg_ep_enable,
4388 .disable = dwc2_hsotg_ep_disable_lock,
4389 .alloc_request = dwc2_hsotg_ep_alloc_request,
4390 .free_request = dwc2_hsotg_ep_free_request,
4391 .queue = dwc2_hsotg_ep_queue_lock,
4392 .dequeue = dwc2_hsotg_ep_dequeue,
4393 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4394 /* note, don't believe we have any call for the fifo routines */
4398 * dwc2_hsotg_init - initialize the usb core
4399 * @hsotg: The driver state
4401 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4403 /* unmask subset of endpoint interrupts */
4405 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4406 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4409 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4410 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4413 dwc2_writel(hsotg, 0, DAINTMSK);
4415 /* Be in disconnected state until gadget is registered */
4416 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4420 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4421 dwc2_readl(hsotg, GRXFSIZ),
4422 dwc2_readl(hsotg, GNPTXFSIZ));
4424 dwc2_hsotg_init_fifo(hsotg);
4426 if (using_dma(hsotg))
4427 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4431 * dwc2_hsotg_udc_start - prepare the udc for work
4432 * @gadget: The usb gadget state
4433 * @driver: The usb gadget driver
4435 * Perform initialization to prepare udc device and driver
4438 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4439 struct usb_gadget_driver *driver)
4441 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4442 unsigned long flags;
4446 pr_err("%s: called with no device\n", __func__);
4451 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4455 if (driver->max_speed < USB_SPEED_FULL)
4456 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4458 if (!driver->setup) {
4459 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4463 WARN_ON(hsotg->driver);
4465 driver->driver.bus = NULL;
4466 hsotg->driver = driver;
4467 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4468 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4470 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4471 ret = dwc2_lowlevel_hw_enable(hsotg);
4476 if (!IS_ERR_OR_NULL(hsotg->uphy))
4477 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4479 spin_lock_irqsave(&hsotg->lock, flags);
4480 if (dwc2_hw_is_device(hsotg)) {
4481 dwc2_hsotg_init(hsotg);
4482 dwc2_hsotg_core_init_disconnected(hsotg, false);
4486 spin_unlock_irqrestore(&hsotg->lock, flags);
4488 gadget->sg_supported = using_desc_dma(hsotg);
4489 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4494 hsotg->driver = NULL;
4499 * dwc2_hsotg_udc_stop - stop the udc
4500 * @gadget: The usb gadget state
4502 * Stop udc hw block and stay tunned for future transmissions
4504 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4506 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4507 unsigned long flags = 0;
4513 /* all endpoints should be shutdown */
4514 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4515 if (hsotg->eps_in[ep])
4516 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4517 if (hsotg->eps_out[ep])
4518 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4521 spin_lock_irqsave(&hsotg->lock, flags);
4523 hsotg->driver = NULL;
4524 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4527 spin_unlock_irqrestore(&hsotg->lock, flags);
4529 if (!IS_ERR_OR_NULL(hsotg->uphy))
4530 otg_set_peripheral(hsotg->uphy->otg, NULL);
4532 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4533 dwc2_lowlevel_hw_disable(hsotg);
4539 * dwc2_hsotg_gadget_getframe - read the frame number
4540 * @gadget: The usb gadget state
4542 * Read the {micro} frame number
4544 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4546 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4550 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4551 * @gadget: The usb gadget state
4552 * @is_selfpowered: Whether the device is self-powered
4554 * Set if the device is self or bus powered.
4556 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4559 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4560 unsigned long flags;
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 gadget->is_selfpowered = !!is_selfpowered;
4564 spin_unlock_irqrestore(&hsotg->lock, flags);
4570 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4571 * @gadget: The usb gadget state
4572 * @is_on: Current state of the USB PHY
4574 * Connect/Disconnect the USB PHY pullup
4576 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4578 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4579 unsigned long flags = 0;
4581 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4584 /* Don't modify pullup state while in host mode */
4585 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4586 hsotg->enabled = is_on;
4590 spin_lock_irqsave(&hsotg->lock, flags);
4593 dwc2_hsotg_core_init_disconnected(hsotg, false);
4594 /* Enable ACG feature in device mode,if supported */
4595 dwc2_enable_acg(hsotg);
4596 dwc2_hsotg_core_connect(hsotg);
4598 dwc2_hsotg_core_disconnect(hsotg);
4599 dwc2_hsotg_disconnect(hsotg);
4603 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4604 spin_unlock_irqrestore(&hsotg->lock, flags);
4609 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4611 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4612 unsigned long flags;
4614 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4615 spin_lock_irqsave(&hsotg->lock, flags);
4618 * If controller is hibernated, it must exit from power_down
4619 * before being initialized / de-initialized
4621 if (hsotg->lx_state == DWC2_L2)
4622 dwc2_exit_partial_power_down(hsotg, false);
4625 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4627 dwc2_hsotg_core_init_disconnected(hsotg, false);
4628 if (hsotg->enabled) {
4629 /* Enable ACG feature in device mode,if supported */
4630 dwc2_enable_acg(hsotg);
4631 dwc2_hsotg_core_connect(hsotg);
4634 dwc2_hsotg_core_disconnect(hsotg);
4635 dwc2_hsotg_disconnect(hsotg);
4638 spin_unlock_irqrestore(&hsotg->lock, flags);
4643 * dwc2_hsotg_vbus_draw - report bMaxPower field
4644 * @gadget: The usb gadget state
4645 * @mA: Amount of current
4647 * Report how much power the device may consume to the phy.
4649 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4651 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4653 if (IS_ERR_OR_NULL(hsotg->uphy))
4655 return usb_phy_set_power(hsotg->uphy, mA);
4658 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4659 .get_frame = dwc2_hsotg_gadget_getframe,
4660 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4661 .udc_start = dwc2_hsotg_udc_start,
4662 .udc_stop = dwc2_hsotg_udc_stop,
4663 .pullup = dwc2_hsotg_pullup,
4664 .vbus_session = dwc2_hsotg_vbus_session,
4665 .vbus_draw = dwc2_hsotg_vbus_draw,
4669 * dwc2_hsotg_initep - initialise a single endpoint
4670 * @hsotg: The device state.
4671 * @hs_ep: The endpoint to be initialised.
4672 * @epnum: The endpoint number
4673 * @dir_in: True if direction is in.
4675 * Initialise the given endpoint (as part of the probe and device state
4676 * creation) to give to the gadget driver. Setup the endpoint name, any
4677 * direction information and other state that may be required.
4679 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4680 struct dwc2_hsotg_ep *hs_ep,
4693 hs_ep->dir_in = dir_in;
4694 hs_ep->index = epnum;
4696 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4698 INIT_LIST_HEAD(&hs_ep->queue);
4699 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4701 /* add to the list of endpoints known by the gadget driver */
4703 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4705 hs_ep->parent = hsotg;
4706 hs_ep->ep.name = hs_ep->name;
4708 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4709 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4711 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4712 epnum ? 1024 : EP0_MPS_LIMIT);
4713 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4716 hs_ep->ep.caps.type_control = true;
4718 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4719 hs_ep->ep.caps.type_iso = true;
4720 hs_ep->ep.caps.type_bulk = true;
4722 hs_ep->ep.caps.type_int = true;
4726 hs_ep->ep.caps.dir_in = true;
4728 hs_ep->ep.caps.dir_out = true;
4731 * if we're using dma, we need to set the next-endpoint pointer
4732 * to be something valid.
4735 if (using_dma(hsotg)) {
4736 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4739 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4741 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4746 * dwc2_hsotg_hw_cfg - read HW configuration registers
4747 * @hsotg: Programming view of the DWC_otg controller
4749 * Read the USB core HW configuration registers
4751 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4757 /* check hardware configuration */
4759 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4762 hsotg->num_of_eps++;
4764 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4765 sizeof(struct dwc2_hsotg_ep),
4767 if (!hsotg->eps_in[0])
4769 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4770 hsotg->eps_out[0] = hsotg->eps_in[0];
4772 cfg = hsotg->hw_params.dev_ep_dirs;
4773 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4775 /* Direction in or both */
4776 if (!(ep_type & 2)) {
4777 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4778 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4779 if (!hsotg->eps_in[i])
4782 /* Direction out or both */
4783 if (!(ep_type & 1)) {
4784 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4785 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4786 if (!hsotg->eps_out[i])
4791 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4792 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4794 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4796 hsotg->dedicated_fifos ? "dedicated" : "shared",
4802 * dwc2_hsotg_dump - dump state of the udc
4803 * @hsotg: Programming view of the DWC_otg controller
4806 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4809 struct device *dev = hsotg->dev;
4813 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4814 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4815 dwc2_readl(hsotg, DIEPMSK));
4817 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4818 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4820 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4821 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4823 /* show periodic fifo settings */
4825 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4826 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4827 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4828 val >> FIFOSIZE_DEPTH_SHIFT,
4829 val & FIFOSIZE_STARTADDR_MASK);
4832 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4834 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4835 dwc2_readl(hsotg, DIEPCTL(idx)),
4836 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4837 dwc2_readl(hsotg, DIEPDMA(idx)));
4839 val = dwc2_readl(hsotg, DOEPCTL(idx));
4841 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4842 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4843 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4844 dwc2_readl(hsotg, DOEPDMA(idx)));
4847 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4848 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4853 * dwc2_gadget_init - init function for gadget
4854 * @hsotg: Programming view of the DWC_otg controller
4857 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4859 struct device *dev = hsotg->dev;
4863 /* Dump fifo information */
4864 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4865 hsotg->params.g_np_tx_fifo_size);
4866 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4868 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4869 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4870 hsotg->gadget.name = dev_name(dev);
4871 hsotg->remote_wakeup_allowed = 0;
4873 if (hsotg->params.lpm)
4874 hsotg->gadget.lpm_capable = true;
4876 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4877 hsotg->gadget.is_otg = 1;
4878 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4879 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4881 ret = dwc2_hsotg_hw_cfg(hsotg);
4883 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4887 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4888 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4889 if (!hsotg->ctrl_buff)
4892 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4893 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4894 if (!hsotg->ep0_buff)
4897 if (using_desc_dma(hsotg)) {
4898 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4903 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4904 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4906 dev_err(dev, "cannot claim IRQ for gadget\n");
4910 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4912 if (hsotg->num_of_eps == 0) {
4913 dev_err(dev, "wrong number of EPs (zero)\n");
4917 /* setup endpoint information */
4919 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4920 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4922 /* allocate EP0 request */
4924 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4926 if (!hsotg->ctrl_req) {
4927 dev_err(dev, "failed to allocate ctrl req\n");
4931 /* initialise the endpoints now the core has been initialised */
4932 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4933 if (hsotg->eps_in[epnum])
4934 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4936 if (hsotg->eps_out[epnum])
4937 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4941 dwc2_hsotg_dump(hsotg);
4947 * dwc2_hsotg_remove - remove function for hsotg driver
4948 * @hsotg: Programming view of the DWC_otg controller
4951 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4953 usb_del_gadget_udc(&hsotg->gadget);
4954 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4959 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4961 unsigned long flags;
4963 if (hsotg->lx_state != DWC2_L0)
4966 if (hsotg->driver) {
4969 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4970 hsotg->driver->driver.name);
4972 spin_lock_irqsave(&hsotg->lock, flags);
4974 dwc2_hsotg_core_disconnect(hsotg);
4975 dwc2_hsotg_disconnect(hsotg);
4976 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4977 spin_unlock_irqrestore(&hsotg->lock, flags);
4979 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4980 if (hsotg->eps_in[ep])
4981 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4982 if (hsotg->eps_out[ep])
4983 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4990 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4992 unsigned long flags;
4994 if (hsotg->lx_state == DWC2_L2)
4997 if (hsotg->driver) {
4998 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4999 hsotg->driver->driver.name);
5001 spin_lock_irqsave(&hsotg->lock, flags);
5002 dwc2_hsotg_core_init_disconnected(hsotg, false);
5003 if (hsotg->enabled) {
5004 /* Enable ACG feature in device mode,if supported */
5005 dwc2_enable_acg(hsotg);
5006 dwc2_hsotg_core_connect(hsotg);
5008 spin_unlock_irqrestore(&hsotg->lock, flags);
5015 * dwc2_backup_device_registers() - Backup controller device registers.
5016 * When suspending usb bus, registers needs to be backuped
5017 * if controller power is disabled once suspended.
5019 * @hsotg: Programming view of the DWC_otg controller
5021 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5023 struct dwc2_dregs_backup *dr;
5026 dev_dbg(hsotg->dev, "%s\n", __func__);
5028 /* Backup dev regs */
5029 dr = &hsotg->dr_backup;
5031 dr->dcfg = dwc2_readl(hsotg, DCFG);
5032 dr->dctl = dwc2_readl(hsotg, DCTL);
5033 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5034 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5035 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5037 for (i = 0; i < hsotg->num_of_eps; i++) {
5039 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5041 /* Ensure DATA PID is correctly configured */
5042 if (dr->diepctl[i] & DXEPCTL_DPID)
5043 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5045 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5047 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5048 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5050 /* Backup OUT EPs */
5051 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5053 /* Ensure DATA PID is correctly configured */
5054 if (dr->doepctl[i] & DXEPCTL_DPID)
5055 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5057 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5059 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5060 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5061 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5068 * dwc2_restore_device_registers() - Restore controller device registers.
5069 * When resuming usb bus, device registers needs to be restored
5070 * if controller power were disabled.
5072 * @hsotg: Programming view of the DWC_otg controller
5073 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5075 * Return: 0 if successful, negative error code otherwise
5077 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5079 struct dwc2_dregs_backup *dr;
5082 dev_dbg(hsotg->dev, "%s\n", __func__);
5084 /* Restore dev regs */
5085 dr = &hsotg->dr_backup;
5087 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5094 dwc2_writel(hsotg, dr->dctl, DCTL);
5096 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5097 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5098 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5100 for (i = 0; i < hsotg->num_of_eps; i++) {
5101 /* Restore IN EPs */
5102 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5103 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5104 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5105 /** WA for enabled EPx's IN in DDMA mode. On entering to
5106 * hibernation wrong value read and saved from DIEPDMAx,
5107 * as result BNA interrupt asserted on hibernation exit
5108 * by restoring from saved area.
5110 if (hsotg->params.g_dma_desc &&
5111 (dr->diepctl[i] & DXEPCTL_EPENA))
5112 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5113 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5114 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5115 /* Restore OUT EPs */
5116 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5117 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5118 * hibernation wrong value read and saved from DOEPDMAx,
5119 * as result BNA interrupt asserted on hibernation exit
5120 * by restoring from saved area.
5122 if (hsotg->params.g_dma_desc &&
5123 (dr->doepctl[i] & DXEPCTL_EPENA))
5124 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5125 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5126 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5133 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5135 * @hsotg: Programming view of DWC_otg controller
5138 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5142 if (!hsotg->params.lpm)
5145 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5146 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5147 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5148 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5149 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5150 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5151 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5152 dwc2_writel(hsotg, val, GLPMCFG);
5153 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5155 /* Unmask WKUP_ALERT Interrupt */
5156 if (hsotg->params.service_interval)
5157 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5161 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5163 * @hsotg: Programming view of DWC_otg controller
5166 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5170 val |= GREFCLK_REF_CLK_MODE;
5171 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5172 val |= hsotg->params.sof_cnt_wkup_alert <<
5173 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5175 dwc2_writel(hsotg, val, GREFCLK);
5176 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5180 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5182 * @hsotg: Programming view of the DWC_otg controller
5184 * Return non-zero if failed to enter to hibernation.
5186 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5191 /* Change to L2(suspend) state */
5192 hsotg->lx_state = DWC2_L2;
5193 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5194 ret = dwc2_backup_global_registers(hsotg);
5196 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5200 ret = dwc2_backup_device_registers(hsotg);
5202 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5207 gpwrdn = GPWRDN_PWRDNRSTN;
5208 gpwrdn |= GPWRDN_PMUACTV;
5209 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5212 /* Set flag to indicate that we are in hibernation */
5213 hsotg->hibernated = 1;
5215 /* Enable interrupts from wake up logic */
5216 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5217 gpwrdn |= GPWRDN_PMUINTSEL;
5218 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5221 /* Unmask device mode interrupts in GPWRDN */
5222 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5223 gpwrdn |= GPWRDN_RST_DET_MSK;
5224 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5225 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5226 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5229 /* Enable Power Down Clamp */
5230 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5231 gpwrdn |= GPWRDN_PWRDNCLMP;
5232 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5235 /* Switch off VDD */
5236 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5237 gpwrdn |= GPWRDN_PWRDNSWTCH;
5238 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5241 /* Save gpwrdn register for further usage if stschng interrupt */
5242 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5243 dev_dbg(hsotg->dev, "Hibernation completed\n");
5249 * dwc2_gadget_exit_hibernation()
5250 * This function is for exiting from Device mode hibernation by host initiated
5251 * resume/reset and device initiated remote-wakeup.
5253 * @hsotg: Programming view of the DWC_otg controller
5254 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5255 * @reset: indicates whether resume is initiated by Reset.
5257 * Return non-zero if failed to exit from hibernation.
5259 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5260 int rem_wakeup, int reset)
5266 struct dwc2_gregs_backup *gr;
5267 struct dwc2_dregs_backup *dr;
5269 gr = &hsotg->gr_backup;
5270 dr = &hsotg->dr_backup;
5272 if (!hsotg->hibernated) {
5273 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5277 "%s: called with rem_wakeup = %d reset = %d\n",
5278 __func__, rem_wakeup, reset);
5280 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5283 /* Clear all pending interupts */
5284 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5287 /* De-assert Restore */
5288 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5289 gpwrdn &= ~GPWRDN_RESTORE;
5290 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5294 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5295 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5296 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5299 /* Restore GUSBCFG, DCFG and DCTL */
5300 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5301 dwc2_writel(hsotg, dr->dcfg, DCFG);
5302 dwc2_writel(hsotg, dr->dctl, DCTL);
5304 /* De-assert Wakeup Logic */
5305 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5306 gpwrdn &= ~GPWRDN_PMUACTV;
5307 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5311 /* Start Remote Wakeup Signaling */
5312 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5315 /* Set Device programming done bit */
5316 dctl = dwc2_readl(hsotg, DCTL);
5317 dctl |= DCTL_PWRONPRGDONE;
5318 dwc2_writel(hsotg, dctl, DCTL);
5320 /* Wait for interrupts which must be cleared */
5322 /* Clear all pending interupts */
5323 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5325 /* Restore global registers */
5326 ret = dwc2_restore_global_registers(hsotg);
5328 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5333 /* Restore device registers */
5334 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5336 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5343 dctl = dwc2_readl(hsotg, DCTL);
5344 dctl &= ~DCTL_RMTWKUPSIG;
5345 dwc2_writel(hsotg, dctl, DCTL);
5348 hsotg->hibernated = 0;
5349 hsotg->lx_state = DWC2_L0;
5350 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");