1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
123 hs_ep->frame_overrun = false;
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
130 * @hs_ep: The endpoint.
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
137 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
150 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
155 new_gsintmsk = gsintmsk | ints;
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
168 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
173 new_gsintmsk = gsintmsk & ~ints;
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
186 * Set or clear the mask for an individual endpoint's interrupt
189 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
213 * @hsotg: Programming view of the DWC_otg controller
215 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
229 * @hsotg: Programming view of the DWC_otg controller
231 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
247 return tx_addr_max - addr;
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
253 * @hsotg: Programming view of the DWC_otg controller
256 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
264 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
265 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
266 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
267 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
272 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
275 * @hsotg: Programming view of the DWC_otg controller
277 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
282 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
284 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
287 return tx_fifo_depth;
289 return tx_fifo_depth / tx_fifo_count;
293 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
294 * @hsotg: The device instance.
296 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
303 u32 *txfsz = hsotg->params.g_tx_fifo_size;
305 /* Reset fifo map if not correctly cleared during previous session */
306 WARN_ON(hsotg->fifo_map);
309 /* set RX/NPTX FIFO sizes */
310 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
311 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
312 FIFOSIZE_STARTADDR_SHIFT) |
313 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
317 * arange all the rest of the TX FIFOs, as some versions of this
318 * block have overlapping default addresses. This also ensures
319 * that if the settings have been changed, then they are set to
323 /* start at the end of the GNPTXFSIZ, rounded up */
324 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
327 * Configure fifos sizes from provided configuration and assign
328 * them to endpoints dynamically according to maxpacket size value of
331 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
335 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
336 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
337 "insufficient fifo memory");
340 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
341 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
344 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
345 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
348 * according to p428 of the design guide, we need to ensure that
349 * all fifos are flushed before continuing
352 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
353 GRSTCTL_RXFFLSH, GRSTCTL);
355 /* wait until the fifos are both flushed */
358 val = dwc2_readl(hsotg, GRSTCTL);
360 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
363 if (--timeout == 0) {
365 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
373 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
377 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
378 * @ep: USB endpoint to allocate request for.
379 * @flags: Allocation flags
381 * Allocate a new USB request structure appropriate for the specified endpoint
383 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
386 struct dwc2_hsotg_req *req;
388 req = kzalloc(sizeof(*req), flags);
392 INIT_LIST_HEAD(&req->queue);
398 * is_ep_periodic - return true if the endpoint is in periodic mode.
399 * @hs_ep: The endpoint to query.
401 * Returns true if the endpoint is in periodic mode, meaning it is being
402 * used for an Interrupt or ISO transfer.
404 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
406 return hs_ep->periodic;
410 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
411 * @hsotg: The device state.
412 * @hs_ep: The endpoint for the request
413 * @hs_req: The request being processed.
415 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
416 * of a request to ensure the buffer is ready for access by the caller.
418 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
419 struct dwc2_hsotg_ep *hs_ep,
420 struct dwc2_hsotg_req *hs_req)
422 struct usb_request *req = &hs_req->req;
424 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
428 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
429 * for Control endpoint
430 * @hsotg: The device state.
432 * This function will allocate 4 descriptor chains for EP 0: 2 for
433 * Setup stage, per one for IN and OUT data/status transactions.
435 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
437 hsotg->setup_desc[0] =
438 dmam_alloc_coherent(hsotg->dev,
439 sizeof(struct dwc2_dma_desc),
440 &hsotg->setup_desc_dma[0],
442 if (!hsotg->setup_desc[0])
445 hsotg->setup_desc[1] =
446 dmam_alloc_coherent(hsotg->dev,
447 sizeof(struct dwc2_dma_desc),
448 &hsotg->setup_desc_dma[1],
450 if (!hsotg->setup_desc[1])
453 hsotg->ctrl_in_desc =
454 dmam_alloc_coherent(hsotg->dev,
455 sizeof(struct dwc2_dma_desc),
456 &hsotg->ctrl_in_desc_dma,
458 if (!hsotg->ctrl_in_desc)
461 hsotg->ctrl_out_desc =
462 dmam_alloc_coherent(hsotg->dev,
463 sizeof(struct dwc2_dma_desc),
464 &hsotg->ctrl_out_desc_dma,
466 if (!hsotg->ctrl_out_desc)
476 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
477 * @hsotg: The controller state.
478 * @hs_ep: The endpoint we're going to write for.
479 * @hs_req: The request to write data for.
481 * This is called when the TxFIFO has some space in it to hold a new
482 * transmission and we have something to give it. The actual setup of
483 * the data size is done elsewhere, so all we have to do is to actually
486 * The return value is zero if there is more space (or nothing was done)
487 * otherwise -ENOSPC is returned if the FIFO space was used up.
489 * This routine is only needed for PIO
491 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
492 struct dwc2_hsotg_ep *hs_ep,
493 struct dwc2_hsotg_req *hs_req)
495 bool periodic = is_ep_periodic(hs_ep);
496 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
497 int buf_pos = hs_req->req.actual;
498 int to_write = hs_ep->size_loaded;
504 to_write -= (buf_pos - hs_ep->last_load);
506 /* if there's nothing to write, get out early */
510 if (periodic && !hsotg->dedicated_fifos) {
511 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
516 * work out how much data was loaded so we can calculate
517 * how much data is left in the fifo.
520 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
523 * if shared fifo, we cannot write anything until the
524 * previous data has been completely sent.
526 if (hs_ep->fifo_load != 0) {
527 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
531 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
533 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
535 /* how much of the data has moved */
536 size_done = hs_ep->size_loaded - size_left;
538 /* how much data is left in the fifo */
539 can_write = hs_ep->fifo_load - size_done;
540 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
541 __func__, can_write);
543 can_write = hs_ep->fifo_size - can_write;
544 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
545 __func__, can_write);
547 if (can_write <= 0) {
548 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
551 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
552 can_write = dwc2_readl(hsotg,
553 DTXFSTS(hs_ep->fifo_index));
558 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
560 "%s: no queue slots available (0x%08x)\n",
563 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
567 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
568 can_write *= 4; /* fifo size is in 32bit quantities. */
571 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
573 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
574 __func__, gnptxsts, can_write, to_write, max_transfer);
577 * limit to 512 bytes of data, it seems at least on the non-periodic
578 * FIFO, requests of >512 cause the endpoint to get stuck with a
579 * fragment of the end of the transfer in it.
581 if (can_write > 512 && !periodic)
585 * limit the write to one max-packet size worth of data, but allow
586 * the transfer to return that it did not run out of fifo space
589 if (to_write > max_transfer) {
590 to_write = max_transfer;
592 /* it's needed only when we do not use dedicated fifos */
593 if (!hsotg->dedicated_fifos)
594 dwc2_hsotg_en_gsint(hsotg,
595 periodic ? GINTSTS_PTXFEMP :
599 /* see if we can write data */
601 if (to_write > can_write) {
602 to_write = can_write;
603 pkt_round = to_write % max_transfer;
606 * Round the write down to an
607 * exact number of packets.
609 * Note, we do not currently check to see if we can ever
610 * write a full packet or not to the FIFO.
614 to_write -= pkt_round;
617 * enable correct FIFO interrupt to alert us when there
621 /* it's needed only when we do not use dedicated fifos */
622 if (!hsotg->dedicated_fifos)
623 dwc2_hsotg_en_gsint(hsotg,
624 periodic ? GINTSTS_PTXFEMP :
628 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
629 to_write, hs_req->req.length, can_write, buf_pos);
634 hs_req->req.actual = buf_pos + to_write;
635 hs_ep->total_data += to_write;
638 hs_ep->fifo_load += to_write;
640 to_write = DIV_ROUND_UP(to_write, 4);
641 data = hs_req->req.buf + buf_pos;
643 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
645 return (to_write >= can_write) ? -ENOSPC : 0;
649 * get_ep_limit - get the maximum data legnth for this endpoint
650 * @hs_ep: The endpoint
652 * Return the maximum data that can be queued in one go on a given endpoint
653 * so that transfers that are too long can be split.
655 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
657 int index = hs_ep->index;
658 unsigned int maxsize;
662 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
663 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
667 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
672 /* we made the constant loading easier above by using +1 */
677 * constrain by packet count if maxpkts*pktsize is greater
678 * than the length register size.
681 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
682 maxsize = maxpkt * hs_ep->ep.maxpacket;
688 * dwc2_hsotg_read_frameno - read current frame number
689 * @hsotg: The device instance
691 * Return the current frame number
693 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
697 dsts = dwc2_readl(hsotg, DSTS);
698 dsts &= DSTS_SOFFN_MASK;
699 dsts >>= DSTS_SOFFN_SHIFT;
705 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
706 * DMA descriptor chain prepared for specific endpoint
707 * @hs_ep: The endpoint
709 * Return the maximum data that can be queued in one go on a given endpoint
710 * depending on its descriptor chain capacity so that transfers that
711 * are too long can be split.
713 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
715 int is_isoc = hs_ep->isochronous;
716 unsigned int maxsize;
719 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
720 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
721 MAX_DMA_DESC_NUM_HS_ISOC;
723 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
729 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
730 * @hs_ep: The endpoint
731 * @mask: RX/TX bytes mask to be defined
733 * Returns maximum data payload for one descriptor after analyzing endpoint
735 * DMA descriptor transfer bytes limit depends on EP type:
737 * Isochronous - descriptor rx/tx bytes bitfield limit,
738 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
739 * have concatenations from various descriptors within one packet.
741 * Selects corresponding mask for RX/TX bytes as well.
743 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
745 u32 mps = hs_ep->ep.maxpacket;
746 int dir_in = hs_ep->dir_in;
749 if (!hs_ep->index && !dir_in) {
751 *mask = DEV_DMA_NBYTES_MASK;
752 } else if (hs_ep->isochronous) {
754 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
755 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
757 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
758 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
761 desc_size = DEV_DMA_NBYTES_LIMIT;
762 *mask = DEV_DMA_NBYTES_MASK;
764 /* Round down desc_size to be mps multiple */
765 desc_size -= desc_size % mps;
771 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
772 struct dwc2_dma_desc **desc,
777 int dir_in = hs_ep->dir_in;
778 u32 mps = hs_ep->ep.maxpacket;
784 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
786 hs_ep->desc_count = (len / maxsize) +
787 ((len % maxsize) ? 1 : 0);
789 hs_ep->desc_count = 1;
791 for (i = 0; i < hs_ep->desc_count; ++i) {
793 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
794 << DEV_DMA_BUFF_STS_SHIFT);
797 if (!hs_ep->index && !dir_in)
798 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
801 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
802 (*desc)->buf = dma_buff + offset;
808 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
811 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
812 ((hs_ep->send_zlp && true_last) ?
816 len << DEV_DMA_NBYTES_SHIFT & mask;
817 (*desc)->buf = dma_buff + offset;
820 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
821 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
822 << DEV_DMA_BUFF_STS_SHIFT);
828 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
829 * @hs_ep: The endpoint
830 * @ureq: Request to transfer
831 * @offset: offset in bytes
832 * @len: Length of the transfer
834 * This function will iterate over descriptor chain and fill its entries
835 * with corresponding information based on transfer data.
837 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
841 struct usb_request *ureq = NULL;
842 struct dwc2_dma_desc *desc = hs_ep->desc_list;
843 struct scatterlist *sg;
848 ureq = &hs_ep->req->req;
850 /* non-DMA sg buffer */
851 if (!ureq || !ureq->num_sgs) {
852 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
853 dma_buff, len, true);
858 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
859 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
860 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
862 desc_count += hs_ep->desc_count;
865 hs_ep->desc_count = desc_count;
869 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
870 * @hs_ep: The isochronous endpoint.
871 * @dma_buff: usb requests dma buffer.
872 * @len: usb request transfer length.
874 * Fills next free descriptor with the data of the arrived usb request,
875 * frame info, sets Last and IOC bits increments next_desc. If filled
876 * descriptor is not the first one, removes L bit from the previous descriptor
879 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
880 dma_addr_t dma_buff, unsigned int len)
882 struct dwc2_dma_desc *desc;
883 struct dwc2_hsotg *hsotg = hs_ep->parent;
889 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
891 index = hs_ep->next_desc;
892 desc = &hs_ep->desc_list[index];
894 /* Check if descriptor chain full */
895 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
896 DEV_DMA_BUFF_STS_HREADY) {
897 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
901 /* Clear L bit of previous desc if more than one entries in the chain */
902 if (hs_ep->next_desc)
903 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
905 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
906 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
909 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
911 desc->buf = dma_buff;
912 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
913 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
917 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
920 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
921 DEV_DMA_ISOC_PID_MASK) |
922 ((len % hs_ep->ep.maxpacket) ?
924 ((hs_ep->target_frame <<
925 DEV_DMA_ISOC_FRNUM_SHIFT) &
926 DEV_DMA_ISOC_FRNUM_MASK);
929 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
930 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
932 /* Increment frame number by interval for IN */
934 dwc2_gadget_incr_frame_num(hs_ep);
936 /* Update index of last configured entry in the chain */
938 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
939 hs_ep->next_desc = 0;
945 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
946 * @hs_ep: The isochronous endpoint.
948 * Prepare descriptor chain for isochronous endpoints. Afterwards
949 * write DMA address to HW and enable the endpoint.
951 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
953 struct dwc2_hsotg *hsotg = hs_ep->parent;
954 struct dwc2_hsotg_req *hs_req, *treq;
955 int index = hs_ep->index;
961 struct dwc2_dma_desc *desc;
963 if (list_empty(&hs_ep->queue)) {
964 hs_ep->target_frame = TARGET_FRAME_INITIAL;
965 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
969 /* Initialize descriptor chain by Host Busy status */
970 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
971 desc = &hs_ep->desc_list[i];
973 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
974 << DEV_DMA_BUFF_STS_SHIFT);
977 hs_ep->next_desc = 0;
978 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
979 dma_addr_t dma_addr = hs_req->req.dma;
981 if (hs_req->req.num_sgs) {
982 WARN_ON(hs_req->req.num_sgs > 1);
983 dma_addr = sg_dma_address(hs_req->req.sg);
985 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
991 hs_ep->compl_desc = 0;
992 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
993 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
995 /* write descriptor chain address to control register */
996 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
998 ctrl = dwc2_readl(hsotg, depctl);
999 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1000 dwc2_writel(hsotg, ctrl, depctl);
1004 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1005 * @hsotg: The controller state.
1006 * @hs_ep: The endpoint to process a request for
1007 * @hs_req: The request to start.
1008 * @continuing: True if we are doing more for the current request.
1010 * Start the given request running by setting the endpoint registers
1011 * appropriately, and writing any data to the FIFOs.
1013 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1014 struct dwc2_hsotg_ep *hs_ep,
1015 struct dwc2_hsotg_req *hs_req,
1018 struct usb_request *ureq = &hs_req->req;
1019 int index = hs_ep->index;
1020 int dir_in = hs_ep->dir_in;
1025 unsigned int length;
1026 unsigned int packets;
1027 unsigned int maxreq;
1028 unsigned int dma_reg;
1031 if (hs_ep->req && !continuing) {
1032 dev_err(hsotg->dev, "%s: active request\n", __func__);
1035 } else if (hs_ep->req != hs_req && continuing) {
1037 "%s: continue different req\n", __func__);
1043 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1044 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1045 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1047 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1048 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1049 hs_ep->dir_in ? "in" : "out");
1051 /* If endpoint is stalled, we will restart request later */
1052 ctrl = dwc2_readl(hsotg, epctrl_reg);
1054 if (index && ctrl & DXEPCTL_STALL) {
1055 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1059 length = ureq->length - ureq->actual;
1060 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1061 ureq->length, ureq->actual);
1063 if (!using_desc_dma(hsotg))
1064 maxreq = get_ep_limit(hs_ep);
1066 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1068 if (length > maxreq) {
1069 int round = maxreq % hs_ep->ep.maxpacket;
1071 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1072 __func__, length, maxreq, round);
1074 /* round down to multiple of packets */
1082 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1084 packets = 1; /* send one packet if length is zero. */
1086 if (dir_in && index != 0)
1087 if (hs_ep->isochronous)
1088 epsize = DXEPTSIZ_MC(packets);
1090 epsize = DXEPTSIZ_MC(1);
1095 * zero length packet should be programmed on its own and should not
1096 * be counted in DIEPTSIZ.PktCnt with other packets.
1098 if (dir_in && ureq->zero && !continuing) {
1099 /* Test if zlp is actually required. */
1100 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1101 !(ureq->length % hs_ep->ep.maxpacket))
1102 hs_ep->send_zlp = 1;
1105 epsize |= DXEPTSIZ_PKTCNT(packets);
1106 epsize |= DXEPTSIZ_XFERSIZE(length);
1108 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1109 __func__, packets, length, ureq->length, epsize, epsize_reg);
1111 /* store the request as the current one we're doing */
1112 hs_ep->req = hs_req;
1114 if (using_desc_dma(hsotg)) {
1116 u32 mps = hs_ep->ep.maxpacket;
1118 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1122 else if (length % mps)
1123 length += (mps - (length % mps));
1127 * If more data to send, adjust DMA for EP0 out data stage.
1128 * ureq->dma stays unchanged, hence increment it by already
1129 * passed passed data count before starting new transaction.
1131 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1133 offset = ureq->actual;
1135 /* Fill DDMA chain entries */
1136 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1139 /* write descriptor chain address to control register */
1140 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1142 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1143 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1145 /* write size / packets */
1146 dwc2_writel(hsotg, epsize, epsize_reg);
1148 if (using_dma(hsotg) && !continuing && (length != 0)) {
1150 * write DMA address to control register, buffer
1151 * already synced by dwc2_hsotg_ep_queue().
1154 dwc2_writel(hsotg, ureq->dma, dma_reg);
1156 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1157 __func__, &ureq->dma, dma_reg);
1161 if (hs_ep->isochronous && hs_ep->interval == 1) {
1162 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1163 dwc2_gadget_incr_frame_num(hs_ep);
1165 if (hs_ep->target_frame & 0x1)
1166 ctrl |= DXEPCTL_SETODDFR;
1168 ctrl |= DXEPCTL_SETEVENFR;
1171 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1173 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1175 /* For Setup request do not clear NAK */
1176 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1177 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1179 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1180 dwc2_writel(hsotg, ctrl, epctrl_reg);
1183 * set these, it seems that DMA support increments past the end
1184 * of the packet buffer so we need to calculate the length from
1187 hs_ep->size_loaded = length;
1188 hs_ep->last_load = ureq->actual;
1190 if (dir_in && !using_dma(hsotg)) {
1191 /* set these anyway, we may need them for non-periodic in */
1192 hs_ep->fifo_load = 0;
1194 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1198 * Note, trying to clear the NAK here causes problems with transmit
1199 * on the S3C6400 ending up with the TXFIFO becoming full.
1202 /* check ep is enabled */
1203 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1205 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1206 index, dwc2_readl(hsotg, epctrl_reg));
1208 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1209 __func__, dwc2_readl(hsotg, epctrl_reg));
1211 /* enable ep interrupts */
1212 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1216 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1217 * @hsotg: The device state.
1218 * @hs_ep: The endpoint the request is on.
1219 * @req: The request being processed.
1221 * We've been asked to queue a request, so ensure that the memory buffer
1222 * is correctly setup for DMA. If we've been passed an extant DMA address
1223 * then ensure the buffer has been synced to memory. If our buffer has no
1224 * DMA memory, then we map the memory and mark our request to allow us to
1225 * cleanup on completion.
1227 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1228 struct dwc2_hsotg_ep *hs_ep,
1229 struct usb_request *req)
1233 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1240 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1241 __func__, req->buf, req->length);
1246 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1247 struct dwc2_hsotg_ep *hs_ep,
1248 struct dwc2_hsotg_req *hs_req)
1250 void *req_buf = hs_req->req.buf;
1252 /* If dma is not being used or buffer is aligned */
1253 if (!using_dma(hsotg) || !((long)req_buf & 3))
1256 WARN_ON(hs_req->saved_req_buf);
1258 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1259 hs_ep->ep.name, req_buf, hs_req->req.length);
1261 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1262 if (!hs_req->req.buf) {
1263 hs_req->req.buf = req_buf;
1265 "%s: unable to allocate memory for bounce buffer\n",
1270 /* Save actual buffer */
1271 hs_req->saved_req_buf = req_buf;
1274 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1279 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1280 struct dwc2_hsotg_ep *hs_ep,
1281 struct dwc2_hsotg_req *hs_req)
1283 /* If dma is not being used or buffer was aligned */
1284 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1287 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1288 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1290 /* Copy data from bounce buffer on successful out transfer */
1291 if (!hs_ep->dir_in && !hs_req->req.status)
1292 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1293 hs_req->req.actual);
1295 /* Free bounce buffer */
1296 kfree(hs_req->req.buf);
1298 hs_req->req.buf = hs_req->saved_req_buf;
1299 hs_req->saved_req_buf = NULL;
1303 * dwc2_gadget_target_frame_elapsed - Checks target frame
1304 * @hs_ep: The driver endpoint to check
1306 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1307 * corresponding transfer.
1309 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1311 struct dwc2_hsotg *hsotg = hs_ep->parent;
1312 u32 target_frame = hs_ep->target_frame;
1313 u32 current_frame = hsotg->frame_number;
1314 bool frame_overrun = hs_ep->frame_overrun;
1316 if (!frame_overrun && current_frame >= target_frame)
1319 if (frame_overrun && current_frame >= target_frame &&
1320 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1327 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1328 * @hsotg: The driver state
1329 * @hs_ep: the ep descriptor chain is for
1331 * Called to update EP0 structure's pointers depend on stage of
1334 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1335 struct dwc2_hsotg_ep *hs_ep)
1337 switch (hsotg->ep0_state) {
1338 case DWC2_EP0_SETUP:
1339 case DWC2_EP0_STATUS_OUT:
1340 hs_ep->desc_list = hsotg->setup_desc[0];
1341 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1343 case DWC2_EP0_DATA_IN:
1344 case DWC2_EP0_STATUS_IN:
1345 hs_ep->desc_list = hsotg->ctrl_in_desc;
1346 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1348 case DWC2_EP0_DATA_OUT:
1349 hs_ep->desc_list = hsotg->ctrl_out_desc;
1350 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1353 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1361 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1364 struct dwc2_hsotg_req *hs_req = our_req(req);
1365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1366 struct dwc2_hsotg *hs = hs_ep->parent;
1373 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1374 ep->name, req, req->length, req->buf, req->no_interrupt,
1375 req->zero, req->short_not_ok);
1377 /* Prevent new request submission when controller is suspended */
1378 if (hs->lx_state != DWC2_L0) {
1379 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1384 /* initialise status of the request */
1385 INIT_LIST_HEAD(&hs_req->queue);
1387 req->status = -EINPROGRESS;
1389 /* Don't queue ISOC request if length greater than mps*mc */
1390 if (hs_ep->isochronous &&
1391 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1392 dev_err(hs->dev, "req length > maxpacket*mc\n");
1396 /* In DDMA mode for ISOC's don't queue request if length greater
1397 * than descriptor limits.
1399 if (using_desc_dma(hs) && hs_ep->isochronous) {
1400 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1401 if (hs_ep->dir_in && req->length > maxsize) {
1402 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1403 req->length, maxsize);
1407 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1408 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1409 req->length, hs_ep->ep.maxpacket);
1414 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1418 /* if we're using DMA, sync the buffers as necessary */
1419 if (using_dma(hs)) {
1420 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1424 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1425 if (using_desc_dma(hs) && !hs_ep->index) {
1426 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1431 first = list_empty(&hs_ep->queue);
1432 list_add_tail(&hs_req->queue, &hs_ep->queue);
1435 * Handle DDMA isochronous transfers separately - just add new entry
1436 * to the descriptor chain.
1437 * Transfer will be started once SW gets either one of NAK or
1438 * OutTknEpDis interrupts.
1440 if (using_desc_dma(hs) && hs_ep->isochronous) {
1441 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1442 dma_addr_t dma_addr = hs_req->req.dma;
1444 if (hs_req->req.num_sgs) {
1445 WARN_ON(hs_req->req.num_sgs > 1);
1446 dma_addr = sg_dma_address(hs_req->req.sg);
1448 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1449 hs_req->req.length);
1454 /* Change EP direction if status phase request is after data out */
1455 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1456 hs->ep0_state == DWC2_EP0_DATA_OUT)
1460 if (!hs_ep->isochronous) {
1461 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1465 /* Update current frame number value. */
1466 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1467 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1468 dwc2_gadget_incr_frame_num(hs_ep);
1469 /* Update current frame number value once more as it
1472 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1475 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1476 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1481 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1484 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1485 struct dwc2_hsotg *hs = hs_ep->parent;
1486 unsigned long flags = 0;
1489 spin_lock_irqsave(&hs->lock, flags);
1490 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1491 spin_unlock_irqrestore(&hs->lock, flags);
1496 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1497 struct usb_request *req)
1499 struct dwc2_hsotg_req *hs_req = our_req(req);
1505 * dwc2_hsotg_complete_oursetup - setup completion callback
1506 * @ep: The endpoint the request was on.
1507 * @req: The request completed.
1509 * Called on completion of any requests the driver itself
1510 * submitted that need cleaning up.
1512 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1513 struct usb_request *req)
1515 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1516 struct dwc2_hsotg *hsotg = hs_ep->parent;
1518 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1520 dwc2_hsotg_ep_free_request(ep, req);
1524 * ep_from_windex - convert control wIndex value to endpoint
1525 * @hsotg: The driver state.
1526 * @windex: The control request wIndex field (in host order).
1528 * Convert the given wIndex into a pointer to an driver endpoint
1529 * structure, or return NULL if it is not a valid endpoint.
1531 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1534 struct dwc2_hsotg_ep *ep;
1535 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1536 int idx = windex & 0x7F;
1538 if (windex >= 0x100)
1541 if (idx > hsotg->num_of_eps)
1544 ep = index_to_ep(hsotg, idx, dir);
1546 if (idx && ep->dir_in != dir)
1553 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1554 * @hsotg: The driver state.
1555 * @testmode: requested usb test mode
1556 * Enable usb Test Mode requested by the Host.
1558 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1560 int dctl = dwc2_readl(hsotg, DCTL);
1562 dctl &= ~DCTL_TSTCTL_MASK;
1569 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1574 dwc2_writel(hsotg, dctl, DCTL);
1579 * dwc2_hsotg_send_reply - send reply to control request
1580 * @hsotg: The device state
1582 * @buff: Buffer for request
1583 * @length: Length of reply.
1585 * Create a request and queue it on the given endpoint. This is useful as
1586 * an internal method of sending replies to certain control requests, etc.
1588 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1589 struct dwc2_hsotg_ep *ep,
1593 struct usb_request *req;
1596 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1598 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1599 hsotg->ep0_reply = req;
1601 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1605 req->buf = hsotg->ep0_buff;
1606 req->length = length;
1608 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1612 req->complete = dwc2_hsotg_complete_oursetup;
1615 memcpy(req->buf, buff, length);
1617 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1619 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1627 * dwc2_hsotg_process_req_status - process request GET_STATUS
1628 * @hsotg: The device state
1629 * @ctrl: USB control request
1631 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1632 struct usb_ctrlrequest *ctrl)
1634 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1635 struct dwc2_hsotg_ep *ep;
1640 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1643 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1647 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1648 case USB_RECIP_DEVICE:
1649 status = hsotg->gadget.is_selfpowered <<
1650 USB_DEVICE_SELF_POWERED;
1651 status |= hsotg->remote_wakeup_allowed <<
1652 USB_DEVICE_REMOTE_WAKEUP;
1653 reply = cpu_to_le16(status);
1656 case USB_RECIP_INTERFACE:
1657 /* currently, the data result should be zero */
1658 reply = cpu_to_le16(0);
1661 case USB_RECIP_ENDPOINT:
1662 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1666 reply = cpu_to_le16(ep->halted ? 1 : 0);
1673 if (le16_to_cpu(ctrl->wLength) != 2)
1676 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1678 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1685 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1688 * get_ep_head - return the first request on the endpoint
1689 * @hs_ep: The controller endpoint to get
1691 * Get the first request on the endpoint.
1693 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1695 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1700 * dwc2_gadget_start_next_request - Starts next request from ep queue
1701 * @hs_ep: Endpoint structure
1703 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1704 * in its handler. Hence we need to unmask it here to be able to do
1705 * resynchronization.
1707 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1710 struct dwc2_hsotg *hsotg = hs_ep->parent;
1711 int dir_in = hs_ep->dir_in;
1712 struct dwc2_hsotg_req *hs_req;
1713 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1715 if (!list_empty(&hs_ep->queue)) {
1716 hs_req = get_ep_head(hs_ep);
1717 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1720 if (!hs_ep->isochronous)
1724 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1727 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1729 mask = dwc2_readl(hsotg, epmsk_reg);
1730 mask |= DOEPMSK_OUTTKNEPDISMSK;
1731 dwc2_writel(hsotg, mask, epmsk_reg);
1736 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1737 * @hsotg: The device state
1738 * @ctrl: USB control request
1740 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1741 struct usb_ctrlrequest *ctrl)
1743 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1744 struct dwc2_hsotg_req *hs_req;
1745 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1746 struct dwc2_hsotg_ep *ep;
1753 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1754 __func__, set ? "SET" : "CLEAR");
1756 wValue = le16_to_cpu(ctrl->wValue);
1757 wIndex = le16_to_cpu(ctrl->wIndex);
1758 recip = ctrl->bRequestType & USB_RECIP_MASK;
1761 case USB_RECIP_DEVICE:
1763 case USB_DEVICE_REMOTE_WAKEUP:
1765 hsotg->remote_wakeup_allowed = 1;
1767 hsotg->remote_wakeup_allowed = 0;
1770 case USB_DEVICE_TEST_MODE:
1771 if ((wIndex & 0xff) != 0)
1776 hsotg->test_mode = wIndex >> 8;
1782 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1785 "%s: failed to send reply\n", __func__);
1790 case USB_RECIP_ENDPOINT:
1791 ep = ep_from_windex(hsotg, wIndex);
1793 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1799 case USB_ENDPOINT_HALT:
1800 halted = ep->halted;
1802 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1804 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1807 "%s: failed to send reply\n", __func__);
1812 * we have to complete all requests for ep if it was
1813 * halted, and the halt was cleared by CLEAR_FEATURE
1816 if (!set && halted) {
1818 * If we have request in progress,
1824 list_del_init(&hs_req->queue);
1825 if (hs_req->req.complete) {
1826 spin_unlock(&hsotg->lock);
1827 usb_gadget_giveback_request(
1828 &ep->ep, &hs_req->req);
1829 spin_lock(&hsotg->lock);
1833 /* If we have pending request, then start it */
1835 dwc2_gadget_start_next_request(ep);
1850 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1853 * dwc2_hsotg_stall_ep0 - stall ep0
1854 * @hsotg: The device state
1856 * Set stall for ep0 as response for setup request.
1858 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1860 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1864 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1865 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1868 * DxEPCTL_Stall will be cleared by EP once it has
1869 * taken effect, so no need to clear later.
1872 ctrl = dwc2_readl(hsotg, reg);
1873 ctrl |= DXEPCTL_STALL;
1874 ctrl |= DXEPCTL_CNAK;
1875 dwc2_writel(hsotg, ctrl, reg);
1878 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1879 ctrl, reg, dwc2_readl(hsotg, reg));
1882 * complete won't be called, so we enqueue
1883 * setup request here
1885 dwc2_hsotg_enqueue_setup(hsotg);
1889 * dwc2_hsotg_process_control - process a control request
1890 * @hsotg: The device state
1891 * @ctrl: The control request received
1893 * The controller has received the SETUP phase of a control request, and
1894 * needs to work out what to do next (and whether to pass it on to the
1897 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1898 struct usb_ctrlrequest *ctrl)
1900 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1905 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1906 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1907 ctrl->wIndex, ctrl->wLength);
1909 if (ctrl->wLength == 0) {
1911 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1912 } else if (ctrl->bRequestType & USB_DIR_IN) {
1914 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1917 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1920 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1921 switch (ctrl->bRequest) {
1922 case USB_REQ_SET_ADDRESS:
1923 hsotg->connected = 1;
1924 dcfg = dwc2_readl(hsotg, DCFG);
1925 dcfg &= ~DCFG_DEVADDR_MASK;
1926 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1927 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1928 dwc2_writel(hsotg, dcfg, DCFG);
1930 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1932 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1935 case USB_REQ_GET_STATUS:
1936 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1939 case USB_REQ_CLEAR_FEATURE:
1940 case USB_REQ_SET_FEATURE:
1941 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1946 /* as a fallback, try delivering it to the driver to deal with */
1948 if (ret == 0 && hsotg->driver) {
1949 spin_unlock(&hsotg->lock);
1950 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1951 spin_lock(&hsotg->lock);
1953 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1956 hsotg->delayed_status = false;
1957 if (ret == USB_GADGET_DELAYED_STATUS)
1958 hsotg->delayed_status = true;
1961 * the request is either unhandlable, or is not formatted correctly
1962 * so respond with a STALL for the status stage to indicate failure.
1966 dwc2_hsotg_stall_ep0(hsotg);
1970 * dwc2_hsotg_complete_setup - completion of a setup transfer
1971 * @ep: The endpoint the request was on.
1972 * @req: The request completed.
1974 * Called on completion of any requests the driver itself submitted for
1977 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1978 struct usb_request *req)
1980 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1981 struct dwc2_hsotg *hsotg = hs_ep->parent;
1983 if (req->status < 0) {
1984 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1988 spin_lock(&hsotg->lock);
1989 if (req->actual == 0)
1990 dwc2_hsotg_enqueue_setup(hsotg);
1992 dwc2_hsotg_process_control(hsotg, req->buf);
1993 spin_unlock(&hsotg->lock);
1997 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1998 * @hsotg: The device state.
2000 * Enqueue a request on EP0 if necessary to received any SETUP packets
2001 * received from the host.
2003 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2005 struct usb_request *req = hsotg->ctrl_req;
2006 struct dwc2_hsotg_req *hs_req = our_req(req);
2009 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2013 req->buf = hsotg->ctrl_buff;
2014 req->complete = dwc2_hsotg_complete_setup;
2016 if (!list_empty(&hs_req->queue)) {
2017 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2021 hsotg->eps_out[0]->dir_in = 0;
2022 hsotg->eps_out[0]->send_zlp = 0;
2023 hsotg->ep0_state = DWC2_EP0_SETUP;
2025 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2027 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2029 * Don't think there's much we can do other than watch the
2035 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2036 struct dwc2_hsotg_ep *hs_ep)
2039 u8 index = hs_ep->index;
2040 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2041 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2044 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2047 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2049 if (using_desc_dma(hsotg)) {
2050 /* Not specific buffer needed for ep0 ZLP */
2051 dma_addr_t dma = hs_ep->desc_list_dma;
2054 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2056 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2058 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2059 DXEPTSIZ_XFERSIZE(0),
2063 ctrl = dwc2_readl(hsotg, epctl_reg);
2064 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2065 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2066 ctrl |= DXEPCTL_USBACTEP;
2067 dwc2_writel(hsotg, ctrl, epctl_reg);
2071 * dwc2_hsotg_complete_request - complete a request given to us
2072 * @hsotg: The device state.
2073 * @hs_ep: The endpoint the request was on.
2074 * @hs_req: The request to complete.
2075 * @result: The result code (0 => Ok, otherwise errno)
2077 * The given request has finished, so call the necessary completion
2078 * if it has one and then look to see if we can start a new request
2081 * Note, expects the ep to already be locked as appropriate.
2083 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2084 struct dwc2_hsotg_ep *hs_ep,
2085 struct dwc2_hsotg_req *hs_req,
2089 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2093 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2094 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2097 * only replace the status if we've not already set an error
2098 * from a previous transaction
2101 if (hs_req->req.status == -EINPROGRESS)
2102 hs_req->req.status = result;
2104 if (using_dma(hsotg))
2105 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2107 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2110 list_del_init(&hs_req->queue);
2113 * call the complete request with the locks off, just in case the
2114 * request tries to queue more work for this endpoint.
2117 if (hs_req->req.complete) {
2118 spin_unlock(&hsotg->lock);
2119 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2120 spin_lock(&hsotg->lock);
2123 /* In DDMA don't need to proceed to starting of next ISOC request */
2124 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2128 * Look to see if there is anything else to do. Note, the completion
2129 * of the previous request may have caused a new request to be started
2130 * so be careful when doing this.
2133 if (!hs_ep->req && result >= 0)
2134 dwc2_gadget_start_next_request(hs_ep);
2138 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2139 * @hs_ep: The endpoint the request was on.
2141 * Get first request from the ep queue, determine descriptor on which complete
2142 * happened. SW discovers which descriptor currently in use by HW, adjusts
2143 * dma_address and calculates index of completed descriptor based on the value
2144 * of DEPDMA register. Update actual length of request, giveback to gadget.
2146 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2148 struct dwc2_hsotg *hsotg = hs_ep->parent;
2149 struct dwc2_hsotg_req *hs_req;
2150 struct usb_request *ureq;
2154 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2156 /* Process only descriptors with buffer status set to DMA done */
2157 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2158 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2160 hs_req = get_ep_head(hs_ep);
2162 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2165 ureq = &hs_req->req;
2167 /* Check completion status */
2168 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2170 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2171 DEV_DMA_ISOC_RX_NBYTES_MASK;
2172 ureq->actual = ureq->length - ((desc_sts & mask) >>
2173 DEV_DMA_ISOC_NBYTES_SHIFT);
2175 /* Adjust actual len for ISOC Out if len is
2178 if (!hs_ep->dir_in && ureq->length & 0x3)
2179 ureq->actual += 4 - (ureq->length & 0x3);
2181 /* Set actual frame number for completed transfers */
2182 ureq->frame_number =
2183 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2184 DEV_DMA_ISOC_FRNUM_SHIFT;
2187 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2189 hs_ep->compl_desc++;
2190 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2191 hs_ep->compl_desc = 0;
2192 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2197 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2198 * @hs_ep: The isochronous endpoint.
2200 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2201 * interrupt. Reset target frame and next_desc to allow to start
2202 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2203 * interrupt for OUT direction.
2205 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2207 struct dwc2_hsotg *hsotg = hs_ep->parent;
2210 dwc2_flush_rx_fifo(hsotg);
2211 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2213 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2214 hs_ep->next_desc = 0;
2215 hs_ep->compl_desc = 0;
2219 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2220 * @hsotg: The device state.
2221 * @ep_idx: The endpoint index for the data
2222 * @size: The size of data in the fifo, in bytes
2224 * The FIFO status shows there is data to read from the FIFO for a given
2225 * endpoint, so sort out whether we need to read the data into a request
2226 * that has been made for that endpoint.
2228 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2230 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2231 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2237 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2241 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2242 __func__, size, ep_idx, epctl);
2244 /* dump the data from the FIFO, we've nothing we can do */
2245 for (ptr = 0; ptr < size; ptr += 4)
2246 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2252 read_ptr = hs_req->req.actual;
2253 max_req = hs_req->req.length - read_ptr;
2255 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2256 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2258 if (to_read > max_req) {
2260 * more data appeared than we where willing
2261 * to deal with in this request.
2264 /* currently we don't deal this */
2268 hs_ep->total_data += to_read;
2269 hs_req->req.actual += to_read;
2270 to_read = DIV_ROUND_UP(to_read, 4);
2273 * note, we might over-write the buffer end by 3 bytes depending on
2274 * alignment of the data.
2276 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2277 hs_req->req.buf + read_ptr, to_read);
2281 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2282 * @hsotg: The device instance
2283 * @dir_in: If IN zlp
2285 * Generate a zero-length IN packet request for terminating a SETUP
2288 * Note, since we don't write any data to the TxFIFO, then it is
2289 * currently believed that we do not need to wait for any space in
2292 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2294 /* eps_out[0] is used in both directions */
2295 hsotg->eps_out[0]->dir_in = dir_in;
2296 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2298 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2301 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2306 ctrl = dwc2_readl(hsotg, epctl_reg);
2307 if (ctrl & DXEPCTL_EOFRNUM)
2308 ctrl |= DXEPCTL_SETEVENFR;
2310 ctrl |= DXEPCTL_SETODDFR;
2311 dwc2_writel(hsotg, ctrl, epctl_reg);
2315 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2316 * @hs_ep - The endpoint on which transfer went
2318 * Iterate over endpoints descriptor chain and get info on bytes remained
2319 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2321 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2323 struct dwc2_hsotg *hsotg = hs_ep->parent;
2324 unsigned int bytes_rem = 0;
2325 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2332 for (i = 0; i < hs_ep->desc_count; ++i) {
2333 status = desc->status;
2334 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2336 if (status & DEV_DMA_STS_MASK)
2337 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2338 i, status & DEV_DMA_STS_MASK);
2346 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2347 * @hsotg: The device instance
2348 * @epnum: The endpoint received from
2350 * The RXFIFO has delivered an OutDone event, which means that the data
2351 * transfer for an OUT endpoint has been completed, either by a short
2352 * packet or by the finish of a transfer.
2354 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2356 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2357 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2358 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2359 struct usb_request *req = &hs_req->req;
2360 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2364 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2368 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2369 dev_dbg(hsotg->dev, "zlp packet received\n");
2370 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2371 dwc2_hsotg_enqueue_setup(hsotg);
2375 if (using_desc_dma(hsotg))
2376 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2378 if (using_dma(hsotg)) {
2379 unsigned int size_done;
2382 * Calculate the size of the transfer by checking how much
2383 * is left in the endpoint size register and then working it
2384 * out from the amount we loaded for the transfer.
2386 * We need to do this as DMA pointers are always 32bit aligned
2387 * so may overshoot/undershoot the transfer.
2390 size_done = hs_ep->size_loaded - size_left;
2391 size_done += hs_ep->last_load;
2393 req->actual = size_done;
2396 /* if there is more request to do, schedule new transfer */
2397 if (req->actual < req->length && size_left == 0) {
2398 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2402 if (req->actual < req->length && req->short_not_ok) {
2403 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2404 __func__, req->actual, req->length);
2407 * todo - what should we return here? there's no one else
2408 * even bothering to check the status.
2412 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2413 if (!using_desc_dma(hsotg) && epnum == 0 &&
2414 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2415 /* Move to STATUS IN */
2416 if (!hsotg->delayed_status)
2417 dwc2_hsotg_ep0_zlp(hsotg, true);
2421 * Slave mode OUT transfers do not go through XferComplete so
2422 * adjust the ISOC parity here.
2424 if (!using_dma(hsotg)) {
2425 if (hs_ep->isochronous && hs_ep->interval == 1)
2426 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2427 else if (hs_ep->isochronous && hs_ep->interval > 1)
2428 dwc2_gadget_incr_frame_num(hs_ep);
2431 /* Set actual frame number for completed transfers */
2432 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2433 req->frame_number = hsotg->frame_number;
2435 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2439 * dwc2_hsotg_handle_rx - RX FIFO has data
2440 * @hsotg: The device instance
2442 * The IRQ handler has detected that the RX FIFO has some data in it
2443 * that requires processing, so find out what is in there and do the
2446 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2447 * chunks, so if you have x packets received on an endpoint you'll get x
2448 * FIFO events delivered, each with a packet's worth of data in it.
2450 * When using DMA, we should not be processing events from the RXFIFO
2451 * as the actual data should be sent to the memory directly and we turn
2452 * on the completion interrupts to get notifications of transfer completion.
2454 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2456 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2457 u32 epnum, status, size;
2459 WARN_ON(using_dma(hsotg));
2461 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2462 status = grxstsr & GRXSTS_PKTSTS_MASK;
2464 size = grxstsr & GRXSTS_BYTECNT_MASK;
2465 size >>= GRXSTS_BYTECNT_SHIFT;
2467 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2468 __func__, grxstsr, size, epnum);
2470 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2471 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2472 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2475 case GRXSTS_PKTSTS_OUTDONE:
2476 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2477 dwc2_hsotg_read_frameno(hsotg));
2479 if (!using_dma(hsotg))
2480 dwc2_hsotg_handle_outdone(hsotg, epnum);
2483 case GRXSTS_PKTSTS_SETUPDONE:
2485 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2486 dwc2_hsotg_read_frameno(hsotg),
2487 dwc2_readl(hsotg, DOEPCTL(0)));
2489 * Call dwc2_hsotg_handle_outdone here if it was not called from
2490 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2491 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2493 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2494 dwc2_hsotg_handle_outdone(hsotg, epnum);
2497 case GRXSTS_PKTSTS_OUTRX:
2498 dwc2_hsotg_rx_data(hsotg, epnum, size);
2501 case GRXSTS_PKTSTS_SETUPRX:
2503 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2504 dwc2_hsotg_read_frameno(hsotg),
2505 dwc2_readl(hsotg, DOEPCTL(0)));
2507 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2509 dwc2_hsotg_rx_data(hsotg, epnum, size);
2513 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2516 dwc2_hsotg_dump(hsotg);
2522 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2523 * @mps: The maximum packet size in bytes.
2525 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2529 return D0EPCTL_MPS_64;
2531 return D0EPCTL_MPS_32;
2533 return D0EPCTL_MPS_16;
2535 return D0EPCTL_MPS_8;
2538 /* bad max packet size, warn and return invalid result */
2544 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2545 * @hsotg: The driver state.
2546 * @ep: The index number of the endpoint
2547 * @mps: The maximum packet size in bytes
2548 * @mc: The multicount value
2549 * @dir_in: True if direction is in.
2551 * Configure the maximum packet size for the given endpoint, updating
2552 * the hardware control registers to reflect this.
2554 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2555 unsigned int ep, unsigned int mps,
2556 unsigned int mc, unsigned int dir_in)
2558 struct dwc2_hsotg_ep *hs_ep;
2561 hs_ep = index_to_ep(hsotg, ep, dir_in);
2566 u32 mps_bytes = mps;
2568 /* EP0 is a special case */
2569 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2572 hs_ep->ep.maxpacket = mps_bytes;
2580 hs_ep->ep.maxpacket = mps;
2584 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2585 reg &= ~DXEPCTL_MPS_MASK;
2587 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2589 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2590 reg &= ~DXEPCTL_MPS_MASK;
2592 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2598 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2602 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2603 * @hsotg: The driver state
2604 * @idx: The index for the endpoint (0..15)
2606 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2608 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2611 /* wait until the fifo is flushed */
2612 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2613 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2618 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2619 * @hsotg: The driver state
2620 * @hs_ep: The driver endpoint to check.
2622 * Check to see if there is a request that has data to send, and if so
2623 * make an attempt to write data into the FIFO.
2625 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2626 struct dwc2_hsotg_ep *hs_ep)
2628 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2630 if (!hs_ep->dir_in || !hs_req) {
2632 * if request is not enqueued, we disable interrupts
2633 * for endpoints, excepting ep0
2635 if (hs_ep->index != 0)
2636 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2641 if (hs_req->req.actual < hs_req->req.length) {
2642 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2644 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2651 * dwc2_hsotg_complete_in - complete IN transfer
2652 * @hsotg: The device state.
2653 * @hs_ep: The endpoint that has just completed.
2655 * An IN transfer has been completed, update the transfer's state and then
2656 * call the relevant completion routines.
2658 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2659 struct dwc2_hsotg_ep *hs_ep)
2661 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2662 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2663 int size_left, size_done;
2666 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2670 /* Finish ZLP handling for IN EP0 transactions */
2671 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2672 dev_dbg(hsotg->dev, "zlp packet sent\n");
2675 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2676 * changed to IN. Change back to complete OUT transfer request
2680 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2681 if (hsotg->test_mode) {
2684 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2686 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2688 dwc2_hsotg_stall_ep0(hsotg);
2692 dwc2_hsotg_enqueue_setup(hsotg);
2697 * Calculate the size of the transfer by checking how much is left
2698 * in the endpoint size register and then working it out from
2699 * the amount we loaded for the transfer.
2701 * We do this even for DMA, as the transfer may have incremented
2702 * past the end of the buffer (DMA transfers are always 32bit
2705 if (using_desc_dma(hsotg)) {
2706 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2708 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2711 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2714 size_done = hs_ep->size_loaded - size_left;
2715 size_done += hs_ep->last_load;
2717 if (hs_req->req.actual != size_done)
2718 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2719 __func__, hs_req->req.actual, size_done);
2721 hs_req->req.actual = size_done;
2722 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2723 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2725 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2726 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2727 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2731 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2732 if (hs_ep->send_zlp) {
2733 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2734 hs_ep->send_zlp = 0;
2735 /* transfer will be completed on next complete interrupt */
2739 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2740 /* Move to STATUS OUT */
2741 dwc2_hsotg_ep0_zlp(hsotg, false);
2745 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2749 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2750 * @hsotg: The device state.
2751 * @idx: Index of ep.
2752 * @dir_in: Endpoint direction 1-in 0-out.
2754 * Reads for endpoint with given index and direction, by masking
2755 * epint_reg with coresponding mask.
2757 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2758 unsigned int idx, int dir_in)
2760 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2761 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2766 mask = dwc2_readl(hsotg, epmsk_reg);
2767 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2768 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2769 mask |= DXEPINT_SETUP_RCVD;
2771 ints = dwc2_readl(hsotg, epint_reg);
2777 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2778 * @hs_ep: The endpoint on which interrupt is asserted.
2780 * This interrupt indicates that the endpoint has been disabled per the
2781 * application's request.
2783 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2784 * in case of ISOC completes current request.
2786 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2787 * request starts it.
2789 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2791 struct dwc2_hsotg *hsotg = hs_ep->parent;
2792 struct dwc2_hsotg_req *hs_req;
2793 unsigned char idx = hs_ep->index;
2794 int dir_in = hs_ep->dir_in;
2795 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2796 int dctl = dwc2_readl(hsotg, DCTL);
2798 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2801 int epctl = dwc2_readl(hsotg, epctl_reg);
2803 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2805 if (hs_ep->isochronous) {
2806 dwc2_hsotg_complete_in(hsotg, hs_ep);
2810 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2811 int dctl = dwc2_readl(hsotg, DCTL);
2813 dctl |= DCTL_CGNPINNAK;
2814 dwc2_writel(hsotg, dctl, DCTL);
2819 if (dctl & DCTL_GOUTNAKSTS) {
2820 dctl |= DCTL_CGOUTNAK;
2821 dwc2_writel(hsotg, dctl, DCTL);
2824 if (!hs_ep->isochronous)
2827 if (list_empty(&hs_ep->queue)) {
2828 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2834 hs_req = get_ep_head(hs_ep);
2836 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2838 dwc2_gadget_incr_frame_num(hs_ep);
2839 /* Update current frame number value. */
2840 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2841 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2843 dwc2_gadget_start_next_request(hs_ep);
2847 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2848 * @ep: The endpoint on which interrupt is asserted.
2850 * This is starting point for ISOC-OUT transfer, synchronization done with
2851 * first out token received from host while corresponding EP is disabled.
2853 * Device does not know initial frame in which out token will come. For this
2854 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2855 * getting this interrupt SW starts calculation for next transfer frame.
2857 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2859 struct dwc2_hsotg *hsotg = ep->parent;
2860 int dir_in = ep->dir_in;
2863 if (dir_in || !ep->isochronous)
2866 if (using_desc_dma(hsotg)) {
2867 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2868 /* Start first ISO Out */
2869 ep->target_frame = hsotg->frame_number;
2870 dwc2_gadget_start_isoc_ddma(ep);
2875 if (ep->interval > 1 &&
2876 ep->target_frame == TARGET_FRAME_INITIAL) {
2879 ep->target_frame = hsotg->frame_number;
2880 dwc2_gadget_incr_frame_num(ep);
2882 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2883 if (ep->target_frame & 0x1)
2884 ctrl |= DXEPCTL_SETODDFR;
2886 ctrl |= DXEPCTL_SETEVENFR;
2888 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2891 dwc2_gadget_start_next_request(ep);
2892 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2893 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2894 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2898 * dwc2_gadget_handle_nak - handle NAK interrupt
2899 * @hs_ep: The endpoint on which interrupt is asserted.
2901 * This is starting point for ISOC-IN transfer, synchronization done with
2902 * first IN token received from host while corresponding EP is disabled.
2904 * Device does not know when first one token will arrive from host. On first
2905 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2906 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2907 * sent in response to that as there was no data in FIFO. SW is basing on this
2908 * interrupt to obtain frame in which token has come and then based on the
2909 * interval calculates next frame for transfer.
2911 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2913 struct dwc2_hsotg *hsotg = hs_ep->parent;
2914 int dir_in = hs_ep->dir_in;
2916 if (!dir_in || !hs_ep->isochronous)
2919 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2921 if (using_desc_dma(hsotg)) {
2922 hs_ep->target_frame = hsotg->frame_number;
2923 dwc2_gadget_incr_frame_num(hs_ep);
2925 /* In service interval mode target_frame must
2926 * be set to last (u)frame of the service interval.
2928 if (hsotg->params.service_interval) {
2929 /* Set target_frame to the first (u)frame of
2930 * the service interval
2932 hs_ep->target_frame &= ~hs_ep->interval + 1;
2934 /* Set target_frame to the last (u)frame of
2935 * the service interval
2937 dwc2_gadget_incr_frame_num(hs_ep);
2938 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2941 dwc2_gadget_start_isoc_ddma(hs_ep);
2945 hs_ep->target_frame = hsotg->frame_number;
2946 if (hs_ep->interval > 1) {
2947 u32 ctrl = dwc2_readl(hsotg,
2948 DIEPCTL(hs_ep->index));
2949 if (hs_ep->target_frame & 0x1)
2950 ctrl |= DXEPCTL_SETODDFR;
2952 ctrl |= DXEPCTL_SETEVENFR;
2954 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2957 dwc2_hsotg_complete_request(hsotg, hs_ep,
2958 get_ep_head(hs_ep), 0);
2961 if (!using_desc_dma(hsotg))
2962 dwc2_gadget_incr_frame_num(hs_ep);
2966 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2967 * @hsotg: The driver state
2968 * @idx: The index for the endpoint (0..15)
2969 * @dir_in: Set if this is an IN endpoint
2971 * Process and clear any interrupt pending for an individual endpoint
2973 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2976 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2977 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2978 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2979 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2983 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2984 ctrl = dwc2_readl(hsotg, epctl_reg);
2986 /* Clear endpoint interrupts */
2987 dwc2_writel(hsotg, ints, epint_reg);
2990 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2991 __func__, idx, dir_in ? "in" : "out");
2995 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2996 __func__, idx, dir_in ? "in" : "out", ints);
2998 /* Don't process XferCompl interrupt if it is a setup packet */
2999 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3000 ints &= ~DXEPINT_XFERCOMPL;
3003 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3004 * stage and xfercomplete was generated without SETUP phase done
3005 * interrupt. SW should parse received setup packet only after host's
3006 * exit from setup phase of control transfer.
3008 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3009 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3010 ints &= ~DXEPINT_XFERCOMPL;
3012 if (ints & DXEPINT_XFERCOMPL) {
3014 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3015 __func__, dwc2_readl(hsotg, epctl_reg),
3016 dwc2_readl(hsotg, epsiz_reg));
3018 /* In DDMA handle isochronous requests separately */
3019 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3020 /* XferCompl set along with BNA */
3021 if (!(ints & DXEPINT_BNAINTR))
3022 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3023 } else if (dir_in) {
3025 * We get OutDone from the FIFO, so we only
3026 * need to look at completing IN requests here
3027 * if operating slave mode
3029 if (hs_ep->isochronous && hs_ep->interval > 1)
3030 dwc2_gadget_incr_frame_num(hs_ep);
3032 dwc2_hsotg_complete_in(hsotg, hs_ep);
3033 if (ints & DXEPINT_NAKINTRPT)
3034 ints &= ~DXEPINT_NAKINTRPT;
3036 if (idx == 0 && !hs_ep->req)
3037 dwc2_hsotg_enqueue_setup(hsotg);
3038 } else if (using_dma(hsotg)) {
3040 * We're using DMA, we need to fire an OutDone here
3041 * as we ignore the RXFIFO.
3043 if (hs_ep->isochronous && hs_ep->interval > 1)
3044 dwc2_gadget_incr_frame_num(hs_ep);
3046 dwc2_hsotg_handle_outdone(hsotg, idx);
3050 if (ints & DXEPINT_EPDISBLD)
3051 dwc2_gadget_handle_ep_disabled(hs_ep);
3053 if (ints & DXEPINT_OUTTKNEPDIS)
3054 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3056 if (ints & DXEPINT_NAKINTRPT)
3057 dwc2_gadget_handle_nak(hs_ep);
3059 if (ints & DXEPINT_AHBERR)
3060 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3062 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3063 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3065 if (using_dma(hsotg) && idx == 0) {
3067 * this is the notification we've received a
3068 * setup packet. In non-DMA mode we'd get this
3069 * from the RXFIFO, instead we need to process
3076 dwc2_hsotg_handle_outdone(hsotg, 0);
3080 if (ints & DXEPINT_STSPHSERCVD) {
3081 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3083 /* Safety check EP0 state when STSPHSERCVD asserted */
3084 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3085 /* Move to STATUS IN for DDMA */
3086 if (using_desc_dma(hsotg)) {
3087 if (!hsotg->delayed_status)
3088 dwc2_hsotg_ep0_zlp(hsotg, true);
3090 /* In case of 3 stage Control Write with delayed
3091 * status, when Status IN transfer started
3092 * before STSPHSERCVD asserted, NAKSTS bit not
3093 * cleared by CNAK in dwc2_hsotg_start_req()
3094 * function. Clear now NAKSTS to allow complete
3097 dwc2_set_bit(hsotg, DIEPCTL(0),
3104 if (ints & DXEPINT_BACK2BACKSETUP)
3105 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3107 if (ints & DXEPINT_BNAINTR) {
3108 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3109 if (hs_ep->isochronous)
3110 dwc2_gadget_handle_isoc_bna(hs_ep);
3113 if (dir_in && !hs_ep->isochronous) {
3114 /* not sure if this is important, but we'll clear it anyway */
3115 if (ints & DXEPINT_INTKNTXFEMP) {
3116 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3120 /* this probably means something bad is happening */
3121 if (ints & DXEPINT_INTKNEPMIS) {
3122 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3126 /* FIFO has space or is empty (see GAHBCFG) */
3127 if (hsotg->dedicated_fifos &&
3128 ints & DXEPINT_TXFEMP) {
3129 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3131 if (!using_dma(hsotg))
3132 dwc2_hsotg_trytx(hsotg, hs_ep);
3138 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3139 * @hsotg: The device state.
3141 * Handle updating the device settings after the enumeration phase has
3144 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3146 u32 dsts = dwc2_readl(hsotg, DSTS);
3147 int ep0_mps = 0, ep_mps = 8;
3150 * This should signal the finish of the enumeration phase
3151 * of the USB handshaking, so we should now know what rate
3155 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3158 * note, since we're limited by the size of transfer on EP0, and
3159 * it seems IN transfers must be a even number of packets we do
3160 * not advertise a 64byte MPS on EP0.
3163 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3164 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3165 case DSTS_ENUMSPD_FS:
3166 case DSTS_ENUMSPD_FS48:
3167 hsotg->gadget.speed = USB_SPEED_FULL;
3168 ep0_mps = EP0_MPS_LIMIT;
3172 case DSTS_ENUMSPD_HS:
3173 hsotg->gadget.speed = USB_SPEED_HIGH;
3174 ep0_mps = EP0_MPS_LIMIT;
3178 case DSTS_ENUMSPD_LS:
3179 hsotg->gadget.speed = USB_SPEED_LOW;
3183 * note, we don't actually support LS in this driver at the
3184 * moment, and the documentation seems to imply that it isn't
3185 * supported by the PHYs on some of the devices.
3189 dev_info(hsotg->dev, "new device is %s\n",
3190 usb_speed_string(hsotg->gadget.speed));
3193 * we should now know the maximum packet size for an
3194 * endpoint, so set the endpoints to a default value.
3199 /* Initialize ep0 for both in and out directions */
3200 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3201 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3202 for (i = 1; i < hsotg->num_of_eps; i++) {
3203 if (hsotg->eps_in[i])
3204 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3206 if (hsotg->eps_out[i])
3207 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3212 /* ensure after enumeration our EP0 is active */
3214 dwc2_hsotg_enqueue_setup(hsotg);
3216 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3217 dwc2_readl(hsotg, DIEPCTL0),
3218 dwc2_readl(hsotg, DOEPCTL0));
3222 * kill_all_requests - remove all requests from the endpoint's queue
3223 * @hsotg: The device state.
3224 * @ep: The endpoint the requests may be on.
3225 * @result: The result code to use.
3227 * Go through the requests on the given endpoint and mark them
3228 * completed with the given result code.
3230 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3231 struct dwc2_hsotg_ep *ep,
3238 while (!list_empty(&ep->queue)) {
3239 struct dwc2_hsotg_req *req = get_ep_head(ep);
3241 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3244 if (!hsotg->dedicated_fifos)
3246 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3247 if (size < ep->fifo_size)
3248 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3252 * dwc2_hsotg_disconnect - disconnect service
3253 * @hsotg: The device state.
3255 * The device has been disconnected. Remove all current
3256 * transactions and signal the gadget driver that this
3259 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3263 if (!hsotg->connected)
3266 hsotg->connected = 0;
3267 hsotg->test_mode = 0;
3269 /* all endpoints should be shutdown */
3270 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3271 if (hsotg->eps_in[ep])
3272 kill_all_requests(hsotg, hsotg->eps_in[ep],
3274 if (hsotg->eps_out[ep])
3275 kill_all_requests(hsotg, hsotg->eps_out[ep],
3279 call_gadget(hsotg, disconnect);
3280 hsotg->lx_state = DWC2_L3;
3282 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3286 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3287 * @hsotg: The device state:
3288 * @periodic: True if this is a periodic FIFO interrupt
3290 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3292 struct dwc2_hsotg_ep *ep;
3295 /* look through for any more data to transmit */
3296 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3297 ep = index_to_ep(hsotg, epno, 1);
3305 if ((periodic && !ep->periodic) ||
3306 (!periodic && ep->periodic))
3309 ret = dwc2_hsotg_trytx(hsotg, ep);
3315 /* IRQ flags which will trigger a retry around the IRQ loop */
3316 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3320 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3322 * dwc2_hsotg_core_init - issue softreset to the core
3323 * @hsotg: The device state
3324 * @is_usb_reset: Usb resetting flag
3326 * Issue a soft reset to the core, and await the core finishing it.
3328 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3337 /* Kill any ep0 requests as controller will be reinitialized */
3338 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3340 if (!is_usb_reset) {
3341 if (dwc2_core_reset(hsotg, true))
3344 /* all endpoints should be shutdown */
3345 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3346 if (hsotg->eps_in[ep])
3347 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3348 if (hsotg->eps_out[ep])
3349 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3354 * we must now enable ep0 ready for host detection and then
3355 * set configuration.
3358 /* keep other bits untouched (so e.g. forced modes are not lost) */
3359 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3360 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3361 usbcfg |= GUSBCFG_TOUTCAL(7);
3363 /* remove the HNP/SRP and set the PHY */
3364 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3365 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3367 dwc2_phy_init(hsotg, true);
3369 dwc2_hsotg_init_fifo(hsotg);
3372 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3374 dcfg |= DCFG_EPMISCNT(1);
3376 switch (hsotg->params.speed) {
3377 case DWC2_SPEED_PARAM_LOW:
3378 dcfg |= DCFG_DEVSPD_LS;
3380 case DWC2_SPEED_PARAM_FULL:
3381 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3382 dcfg |= DCFG_DEVSPD_FS48;
3384 dcfg |= DCFG_DEVSPD_FS;
3387 dcfg |= DCFG_DEVSPD_HS;
3390 if (hsotg->params.ipg_isoc_en)
3391 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3393 dwc2_writel(hsotg, dcfg, DCFG);
3395 /* Clear any pending OTG interrupts */
3396 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3398 /* Clear any pending interrupts */
3399 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3400 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3401 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3402 GINTSTS_USBRST | GINTSTS_RESETDET |
3403 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3404 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3405 GINTSTS_LPMTRANRCVD;
3407 if (!using_desc_dma(hsotg))
3408 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3410 if (!hsotg->params.external_id_pin_ctl)
3411 intmsk |= GINTSTS_CONIDSTSCHNG;
3413 dwc2_writel(hsotg, intmsk, GINTMSK);
3415 if (using_dma(hsotg)) {
3416 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3417 hsotg->params.ahbcfg,
3420 /* Set DDMA mode support in the core if needed */
3421 if (using_desc_dma(hsotg))
3422 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3425 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3426 (GAHBCFG_NP_TXF_EMP_LVL |
3427 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3428 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3432 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3433 * when we have no data to transfer. Otherwise we get being flooded by
3437 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3438 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3439 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3440 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3444 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3445 * DMA mode we may need this and StsPhseRcvd.
3447 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3448 DOEPMSK_STSPHSERCVDMSK) : 0) |
3449 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3453 /* Enable BNA interrupt for DDMA */
3454 if (using_desc_dma(hsotg)) {
3455 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3456 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3459 /* Enable Service Interval mode if supported */
3460 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3461 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3463 dwc2_writel(hsotg, 0, DAINTMSK);
3465 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3466 dwc2_readl(hsotg, DIEPCTL0),
3467 dwc2_readl(hsotg, DOEPCTL0));
3469 /* enable in and out endpoint interrupts */
3470 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3473 * Enable the RXFIFO when in slave mode, as this is how we collect
3474 * the data. In DMA mode, we get events from the FIFO but also
3475 * things we cannot process, so do not use it.
3477 if (!using_dma(hsotg))
3478 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3480 /* Enable interrupts for EP0 in and out */
3481 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3482 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3484 if (!is_usb_reset) {
3485 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3486 udelay(10); /* see openiboot */
3487 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3490 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3493 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3494 * writing to the EPCTL register..
3497 /* set to read 1 8byte packet */
3498 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3499 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3501 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3502 DXEPCTL_CNAK | DXEPCTL_EPENA |
3506 /* enable, but don't activate EP0in */
3507 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3508 DXEPCTL_USBACTEP, DIEPCTL0);
3510 /* clear global NAKs */
3511 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3513 val |= DCTL_SFTDISCON;
3514 dwc2_set_bit(hsotg, DCTL, val);
3516 /* configure the core to support LPM */
3517 dwc2_gadget_init_lpm(hsotg);
3519 /* program GREFCLK register if needed */
3520 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3521 dwc2_gadget_program_ref_clk(hsotg);
3523 /* must be at-least 3ms to allow bus to see disconnect */
3526 hsotg->lx_state = DWC2_L0;
3528 dwc2_hsotg_enqueue_setup(hsotg);
3530 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3531 dwc2_readl(hsotg, DIEPCTL0),
3532 dwc2_readl(hsotg, DOEPCTL0));
3535 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3537 /* set the soft-disconnect bit */
3538 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3541 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3543 /* remove the soft-disconnect and let's go */
3544 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3548 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3549 * @hsotg: The device state:
3551 * This interrupt indicates one of the following conditions occurred while
3552 * transmitting an ISOC transaction.
3553 * - Corrupted IN Token for ISOC EP.
3554 * - Packet not complete in FIFO.
3556 * The following actions will be taken:
3557 * - Determine the EP
3558 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3560 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3562 struct dwc2_hsotg_ep *hs_ep;
3567 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3569 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3571 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3572 hs_ep = hsotg->eps_in[idx];
3573 /* Proceed only unmasked ISOC EPs */
3574 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3577 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3578 if ((epctrl & DXEPCTL_EPENA) &&
3579 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3580 epctrl |= DXEPCTL_SNAK;
3581 epctrl |= DXEPCTL_EPDIS;
3582 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3586 /* Clear interrupt */
3587 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3591 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3592 * @hsotg: The device state:
3594 * This interrupt indicates one of the following conditions occurred while
3595 * transmitting an ISOC transaction.
3596 * - Corrupted OUT Token for ISOC EP.
3597 * - Packet not complete in FIFO.
3599 * The following actions will be taken:
3600 * - Determine the EP
3601 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3603 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3609 struct dwc2_hsotg_ep *hs_ep;
3612 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3614 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3615 daintmsk >>= DAINT_OUTEP_SHIFT;
3617 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3618 hs_ep = hsotg->eps_out[idx];
3619 /* Proceed only unmasked ISOC EPs */
3620 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3623 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3624 if ((epctrl & DXEPCTL_EPENA) &&
3625 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3626 /* Unmask GOUTNAKEFF interrupt */
3627 gintmsk = dwc2_readl(hsotg, GINTMSK);
3628 gintmsk |= GINTSTS_GOUTNAKEFF;
3629 dwc2_writel(hsotg, gintmsk, GINTMSK);
3631 gintsts = dwc2_readl(hsotg, GINTSTS);
3632 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3633 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3639 /* Clear interrupt */
3640 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3644 * dwc2_hsotg_irq - handle device interrupt
3645 * @irq: The IRQ number triggered
3646 * @pw: The pw value when registered the handler.
3648 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3650 struct dwc2_hsotg *hsotg = pw;
3651 int retry_count = 8;
3655 if (!dwc2_is_device_mode(hsotg))
3658 spin_lock(&hsotg->lock);
3660 gintsts = dwc2_readl(hsotg, GINTSTS);
3661 gintmsk = dwc2_readl(hsotg, GINTMSK);
3663 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3664 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3668 if (gintsts & GINTSTS_RESETDET) {
3669 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3671 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3673 /* This event must be used only if controller is suspended */
3674 if (hsotg->lx_state == DWC2_L2) {
3675 dwc2_exit_partial_power_down(hsotg, true);
3676 hsotg->lx_state = DWC2_L0;
3680 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3681 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3682 u32 connected = hsotg->connected;
3684 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3685 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3686 dwc2_readl(hsotg, GNPTXSTS));
3688 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3690 /* Report disconnection if it is not already done. */
3691 dwc2_hsotg_disconnect(hsotg);
3693 /* Reset device address to zero */
3694 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3696 if (usb_status & GOTGCTL_BSESVLD && connected)
3697 dwc2_hsotg_core_init_disconnected(hsotg, true);
3700 if (gintsts & GINTSTS_ENUMDONE) {
3701 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3703 dwc2_hsotg_irq_enumdone(hsotg);
3706 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3707 u32 daint = dwc2_readl(hsotg, DAINT);
3708 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3709 u32 daint_out, daint_in;
3713 daint_out = daint >> DAINT_OUTEP_SHIFT;
3714 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3716 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3718 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3719 ep++, daint_out >>= 1) {
3721 dwc2_hsotg_epint(hsotg, ep, 0);
3724 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3725 ep++, daint_in >>= 1) {
3727 dwc2_hsotg_epint(hsotg, ep, 1);
3731 /* check both FIFOs */
3733 if (gintsts & GINTSTS_NPTXFEMP) {
3734 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3737 * Disable the interrupt to stop it happening again
3738 * unless one of these endpoint routines decides that
3739 * it needs re-enabling
3742 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3743 dwc2_hsotg_irq_fifoempty(hsotg, false);
3746 if (gintsts & GINTSTS_PTXFEMP) {
3747 dev_dbg(hsotg->dev, "PTxFEmp\n");
3749 /* See note in GINTSTS_NPTxFEmp */
3751 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3752 dwc2_hsotg_irq_fifoempty(hsotg, true);
3755 if (gintsts & GINTSTS_RXFLVL) {
3757 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3758 * we need to retry dwc2_hsotg_handle_rx if this is still
3762 dwc2_hsotg_handle_rx(hsotg);
3765 if (gintsts & GINTSTS_ERLYSUSP) {
3766 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3767 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3771 * these next two seem to crop-up occasionally causing the core
3772 * to shutdown the USB transfer, so try clearing them and logging
3776 if (gintsts & GINTSTS_GOUTNAKEFF) {
3781 struct dwc2_hsotg_ep *hs_ep;
3783 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3784 daintmsk >>= DAINT_OUTEP_SHIFT;
3785 /* Mask this interrupt */
3786 gintmsk = dwc2_readl(hsotg, GINTMSK);
3787 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3788 dwc2_writel(hsotg, gintmsk, GINTMSK);
3790 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3791 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3792 hs_ep = hsotg->eps_out[idx];
3793 /* Proceed only unmasked ISOC EPs */
3794 if (BIT(idx) & ~daintmsk)
3797 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3800 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3801 epctrl |= DXEPCTL_SNAK;
3802 epctrl |= DXEPCTL_EPDIS;
3803 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3808 if (hs_ep->halted) {
3809 if (!(epctrl & DXEPCTL_EPENA))
3810 epctrl |= DXEPCTL_EPENA;
3811 epctrl |= DXEPCTL_EPDIS;
3812 epctrl |= DXEPCTL_STALL;
3813 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3817 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3820 if (gintsts & GINTSTS_GINNAKEFF) {
3821 dev_info(hsotg->dev, "GINNakEff triggered\n");
3823 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3825 dwc2_hsotg_dump(hsotg);
3828 if (gintsts & GINTSTS_INCOMPL_SOIN)
3829 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3831 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3832 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3835 * if we've had fifo events, we should try and go around the
3836 * loop again to see if there's any point in returning yet.
3839 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3842 /* Check WKUP_ALERT interrupt*/
3843 if (hsotg->params.service_interval)
3844 dwc2_gadget_wkup_alert_handler(hsotg);
3846 spin_unlock(&hsotg->lock);
3851 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3852 struct dwc2_hsotg_ep *hs_ep)
3857 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3858 DOEPCTL(hs_ep->index);
3859 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3860 DOEPINT(hs_ep->index);
3862 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3865 if (hs_ep->dir_in) {
3866 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3867 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3868 /* Wait for Nak effect */
3869 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3870 DXEPINT_INEPNAKEFF, 100))
3871 dev_warn(hsotg->dev,
3872 "%s: timeout DIEPINT.NAKEFF\n",
3875 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3876 /* Wait for Nak effect */
3877 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3878 GINTSTS_GINNAKEFF, 100))
3879 dev_warn(hsotg->dev,
3880 "%s: timeout GINTSTS.GINNAKEFF\n",
3884 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3885 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3887 /* Wait for global nak to take effect */
3888 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3889 GINTSTS_GOUTNAKEFF, 100))
3890 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3895 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3897 /* Wait for ep to be disabled */
3898 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3899 dev_warn(hsotg->dev,
3900 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3902 /* Clear EPDISBLD interrupt */
3903 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3905 if (hs_ep->dir_in) {
3906 unsigned short fifo_index;
3908 if (hsotg->dedicated_fifos || hs_ep->periodic)
3909 fifo_index = hs_ep->fifo_index;
3914 dwc2_flush_tx_fifo(hsotg, fifo_index);
3916 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3917 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3918 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3921 /* Remove global NAKs */
3922 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3927 * dwc2_hsotg_ep_enable - enable the given endpoint
3928 * @ep: The USB endpint to configure
3929 * @desc: The USB endpoint descriptor to configure with.
3931 * This is called from the USB gadget code's usb_ep_enable().
3933 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3934 const struct usb_endpoint_descriptor *desc)
3936 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3937 struct dwc2_hsotg *hsotg = hs_ep->parent;
3938 unsigned long flags;
3939 unsigned int index = hs_ep->index;
3945 unsigned int dir_in;
3946 unsigned int i, val, size;
3948 unsigned char ep_type;
3952 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3953 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3954 desc->wMaxPacketSize, desc->bInterval);
3956 /* not to be called for EP0 */
3958 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3962 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3963 if (dir_in != hs_ep->dir_in) {
3964 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3968 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3969 mps = usb_endpoint_maxp(desc);
3970 mc = usb_endpoint_maxp_mult(desc);
3972 /* ISOC IN in DDMA supported bInterval up to 10 */
3973 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3974 dir_in && desc->bInterval > 10) {
3976 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3980 /* High bandwidth ISOC OUT in DDMA not supported */
3981 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3982 !dir_in && mc > 1) {
3984 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3988 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3990 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3991 epctrl = dwc2_readl(hsotg, epctrl_reg);
3993 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3994 __func__, epctrl, epctrl_reg);
3996 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
3997 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
3999 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4001 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4002 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4003 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4004 desc_num * sizeof(struct dwc2_dma_desc),
4005 &hs_ep->desc_list_dma, GFP_ATOMIC);
4006 if (!hs_ep->desc_list) {
4012 spin_lock_irqsave(&hsotg->lock, flags);
4014 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4015 epctrl |= DXEPCTL_MPS(mps);
4018 * mark the endpoint as active, otherwise the core may ignore
4019 * transactions entirely for this endpoint
4021 epctrl |= DXEPCTL_USBACTEP;
4023 /* update the endpoint state */
4024 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4026 /* default, set to non-periodic */
4027 hs_ep->isochronous = 0;
4028 hs_ep->periodic = 0;
4030 hs_ep->interval = desc->bInterval;
4033 case USB_ENDPOINT_XFER_ISOC:
4034 epctrl |= DXEPCTL_EPTYPE_ISO;
4035 epctrl |= DXEPCTL_SETEVENFR;
4036 hs_ep->isochronous = 1;
4037 hs_ep->interval = 1 << (desc->bInterval - 1);
4038 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4039 hs_ep->next_desc = 0;
4040 hs_ep->compl_desc = 0;
4042 hs_ep->periodic = 1;
4043 mask = dwc2_readl(hsotg, DIEPMSK);
4044 mask |= DIEPMSK_NAKMSK;
4045 dwc2_writel(hsotg, mask, DIEPMSK);
4047 mask = dwc2_readl(hsotg, DOEPMSK);
4048 mask |= DOEPMSK_OUTTKNEPDISMSK;
4049 dwc2_writel(hsotg, mask, DOEPMSK);
4053 case USB_ENDPOINT_XFER_BULK:
4054 epctrl |= DXEPCTL_EPTYPE_BULK;
4057 case USB_ENDPOINT_XFER_INT:
4059 hs_ep->periodic = 1;
4061 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4062 hs_ep->interval = 1 << (desc->bInterval - 1);
4064 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4067 case USB_ENDPOINT_XFER_CONTROL:
4068 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4073 * if the hardware has dedicated fifos, we must give each IN EP
4074 * a unique tx-fifo even if it is non-periodic.
4076 if (dir_in && hsotg->dedicated_fifos) {
4077 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4079 u32 fifo_size = UINT_MAX;
4081 size = hs_ep->ep.maxpacket * hs_ep->mc;
4082 for (i = 1; i <= fifo_count; ++i) {
4083 if (hsotg->fifo_map & (1 << i))
4085 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4086 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4089 /* Search for smallest acceptable fifo */
4090 if (val < fifo_size) {
4097 "%s: No suitable fifo found\n", __func__);
4101 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4102 hsotg->fifo_map |= 1 << fifo_index;
4103 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4104 hs_ep->fifo_index = fifo_index;
4105 hs_ep->fifo_size = fifo_size;
4108 /* for non control endpoints, set PID to D0 */
4109 if (index && !hs_ep->isochronous)
4110 epctrl |= DXEPCTL_SETD0PID;
4112 /* WA for Full speed ISOC IN in DDMA mode.
4113 * By Clear NAK status of EP, core will send ZLP
4114 * to IN token and assert NAK interrupt relying
4115 * on TxFIFO status only
4118 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4119 hs_ep->isochronous && dir_in) {
4120 /* The WA applies only to core versions from 2.72a
4121 * to 4.00a (including both). Also for FS_IOT_1.00a
4124 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4126 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4127 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4128 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4129 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4130 epctrl |= DXEPCTL_CNAK;
4133 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4136 dwc2_writel(hsotg, epctrl, epctrl_reg);
4137 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4138 __func__, dwc2_readl(hsotg, epctrl_reg));
4140 /* enable the endpoint interrupt */
4141 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4144 spin_unlock_irqrestore(&hsotg->lock, flags);
4147 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4148 dmam_free_coherent(hsotg->dev, desc_num *
4149 sizeof(struct dwc2_dma_desc),
4150 hs_ep->desc_list, hs_ep->desc_list_dma);
4151 hs_ep->desc_list = NULL;
4158 * dwc2_hsotg_ep_disable - disable given endpoint
4159 * @ep: The endpoint to disable.
4161 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4163 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4164 struct dwc2_hsotg *hsotg = hs_ep->parent;
4165 int dir_in = hs_ep->dir_in;
4166 int index = hs_ep->index;
4170 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4172 if (ep == &hsotg->eps_out[0]->ep) {
4173 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4177 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4178 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4182 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4184 ctrl = dwc2_readl(hsotg, epctrl_reg);
4186 if (ctrl & DXEPCTL_EPENA)
4187 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4189 ctrl &= ~DXEPCTL_EPENA;
4190 ctrl &= ~DXEPCTL_USBACTEP;
4191 ctrl |= DXEPCTL_SNAK;
4193 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4194 dwc2_writel(hsotg, ctrl, epctrl_reg);
4196 /* disable endpoint interrupts */
4197 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4199 /* terminate all requests with shutdown */
4200 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4202 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4203 hs_ep->fifo_index = 0;
4204 hs_ep->fifo_size = 0;
4209 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4211 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4212 struct dwc2_hsotg *hsotg = hs_ep->parent;
4213 unsigned long flags;
4216 spin_lock_irqsave(&hsotg->lock, flags);
4217 ret = dwc2_hsotg_ep_disable(ep);
4218 spin_unlock_irqrestore(&hsotg->lock, flags);
4223 * on_list - check request is on the given endpoint
4224 * @ep: The endpoint to check.
4225 * @test: The request to test if it is on the endpoint.
4227 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4229 struct dwc2_hsotg_req *req, *treq;
4231 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4240 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4241 * @ep: The endpoint to dequeue.
4242 * @req: The request to be removed from a queue.
4244 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4246 struct dwc2_hsotg_req *hs_req = our_req(req);
4247 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4248 struct dwc2_hsotg *hs = hs_ep->parent;
4249 unsigned long flags;
4251 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4253 spin_lock_irqsave(&hs->lock, flags);
4255 if (!on_list(hs_ep, hs_req)) {
4256 spin_unlock_irqrestore(&hs->lock, flags);
4260 /* Dequeue already started request */
4261 if (req == &hs_ep->req->req)
4262 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4264 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4265 spin_unlock_irqrestore(&hs->lock, flags);
4271 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4272 * @ep: The endpoint to set halt.
4273 * @value: Set or unset the halt.
4274 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4275 * the endpoint is busy processing requests.
4277 * We need to stall the endpoint immediately if request comes from set_feature
4278 * protocol command handler.
4280 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4282 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4283 struct dwc2_hsotg *hs = hs_ep->parent;
4284 int index = hs_ep->index;
4289 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4293 dwc2_hsotg_stall_ep0(hs);
4296 "%s: can't clear halt on ep0\n", __func__);
4300 if (hs_ep->isochronous) {
4301 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4305 if (!now && value && !list_empty(&hs_ep->queue)) {
4306 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4311 if (hs_ep->dir_in) {
4312 epreg = DIEPCTL(index);
4313 epctl = dwc2_readl(hs, epreg);
4316 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4317 if (epctl & DXEPCTL_EPENA)
4318 epctl |= DXEPCTL_EPDIS;
4320 epctl &= ~DXEPCTL_STALL;
4321 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4322 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4323 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4324 epctl |= DXEPCTL_SETD0PID;
4326 dwc2_writel(hs, epctl, epreg);
4328 epreg = DOEPCTL(index);
4329 epctl = dwc2_readl(hs, epreg);
4332 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4333 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4334 // STALL bit will be set in GOUTNAKEFF interrupt handler
4336 epctl &= ~DXEPCTL_STALL;
4337 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4338 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4339 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4340 epctl |= DXEPCTL_SETD0PID;
4341 dwc2_writel(hs, epctl, epreg);
4345 hs_ep->halted = value;
4350 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4351 * @ep: The endpoint to set halt.
4352 * @value: Set or unset the halt.
4354 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4356 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4357 struct dwc2_hsotg *hs = hs_ep->parent;
4358 unsigned long flags = 0;
4361 spin_lock_irqsave(&hs->lock, flags);
4362 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4363 spin_unlock_irqrestore(&hs->lock, flags);
4368 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4369 .enable = dwc2_hsotg_ep_enable,
4370 .disable = dwc2_hsotg_ep_disable_lock,
4371 .alloc_request = dwc2_hsotg_ep_alloc_request,
4372 .free_request = dwc2_hsotg_ep_free_request,
4373 .queue = dwc2_hsotg_ep_queue_lock,
4374 .dequeue = dwc2_hsotg_ep_dequeue,
4375 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4376 /* note, don't believe we have any call for the fifo routines */
4380 * dwc2_hsotg_init - initialize the usb core
4381 * @hsotg: The driver state
4383 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4385 /* unmask subset of endpoint interrupts */
4387 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4388 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4391 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4392 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4395 dwc2_writel(hsotg, 0, DAINTMSK);
4397 /* Be in disconnected state until gadget is registered */
4398 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4402 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4403 dwc2_readl(hsotg, GRXFSIZ),
4404 dwc2_readl(hsotg, GNPTXFSIZ));
4406 dwc2_hsotg_init_fifo(hsotg);
4408 if (using_dma(hsotg))
4409 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4413 * dwc2_hsotg_udc_start - prepare the udc for work
4414 * @gadget: The usb gadget state
4415 * @driver: The usb gadget driver
4417 * Perform initialization to prepare udc device and driver
4420 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4421 struct usb_gadget_driver *driver)
4423 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4424 unsigned long flags;
4428 pr_err("%s: called with no device\n", __func__);
4433 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4437 if (driver->max_speed < USB_SPEED_FULL)
4438 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4440 if (!driver->setup) {
4441 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4445 WARN_ON(hsotg->driver);
4447 driver->driver.bus = NULL;
4448 hsotg->driver = driver;
4449 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4450 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4452 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4453 ret = dwc2_lowlevel_hw_enable(hsotg);
4458 if (!IS_ERR_OR_NULL(hsotg->uphy))
4459 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4461 spin_lock_irqsave(&hsotg->lock, flags);
4462 if (dwc2_hw_is_device(hsotg)) {
4463 dwc2_hsotg_init(hsotg);
4464 dwc2_hsotg_core_init_disconnected(hsotg, false);
4468 spin_unlock_irqrestore(&hsotg->lock, flags);
4470 gadget->sg_supported = using_desc_dma(hsotg);
4471 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4476 hsotg->driver = NULL;
4481 * dwc2_hsotg_udc_stop - stop the udc
4482 * @gadget: The usb gadget state
4484 * Stop udc hw block and stay tunned for future transmissions
4486 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4488 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4489 unsigned long flags = 0;
4495 /* all endpoints should be shutdown */
4496 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4497 if (hsotg->eps_in[ep])
4498 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4499 if (hsotg->eps_out[ep])
4500 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4503 spin_lock_irqsave(&hsotg->lock, flags);
4505 hsotg->driver = NULL;
4506 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4509 spin_unlock_irqrestore(&hsotg->lock, flags);
4511 if (!IS_ERR_OR_NULL(hsotg->uphy))
4512 otg_set_peripheral(hsotg->uphy->otg, NULL);
4514 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4515 dwc2_lowlevel_hw_disable(hsotg);
4521 * dwc2_hsotg_gadget_getframe - read the frame number
4522 * @gadget: The usb gadget state
4524 * Read the {micro} frame number
4526 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4528 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4532 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4533 * @gadget: The usb gadget state
4534 * @is_selfpowered: Whether the device is self-powered
4536 * Set if the device is self or bus powered.
4538 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4541 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4542 unsigned long flags;
4544 spin_lock_irqsave(&hsotg->lock, flags);
4545 gadget->is_selfpowered = !!is_selfpowered;
4546 spin_unlock_irqrestore(&hsotg->lock, flags);
4552 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4553 * @gadget: The usb gadget state
4554 * @is_on: Current state of the USB PHY
4556 * Connect/Disconnect the USB PHY pullup
4558 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4560 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4561 unsigned long flags = 0;
4563 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4566 /* Don't modify pullup state while in host mode */
4567 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4568 hsotg->enabled = is_on;
4572 spin_lock_irqsave(&hsotg->lock, flags);
4575 dwc2_hsotg_core_init_disconnected(hsotg, false);
4576 /* Enable ACG feature in device mode,if supported */
4577 dwc2_enable_acg(hsotg);
4578 dwc2_hsotg_core_connect(hsotg);
4580 dwc2_hsotg_core_disconnect(hsotg);
4581 dwc2_hsotg_disconnect(hsotg);
4585 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4586 spin_unlock_irqrestore(&hsotg->lock, flags);
4591 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4593 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4594 unsigned long flags;
4596 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4597 spin_lock_irqsave(&hsotg->lock, flags);
4600 * If controller is hibernated, it must exit from power_down
4601 * before being initialized / de-initialized
4603 if (hsotg->lx_state == DWC2_L2)
4604 dwc2_exit_partial_power_down(hsotg, false);
4607 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4609 dwc2_hsotg_core_init_disconnected(hsotg, false);
4610 if (hsotg->enabled) {
4611 /* Enable ACG feature in device mode,if supported */
4612 dwc2_enable_acg(hsotg);
4613 dwc2_hsotg_core_connect(hsotg);
4616 dwc2_hsotg_core_disconnect(hsotg);
4617 dwc2_hsotg_disconnect(hsotg);
4620 spin_unlock_irqrestore(&hsotg->lock, flags);
4625 * dwc2_hsotg_vbus_draw - report bMaxPower field
4626 * @gadget: The usb gadget state
4627 * @mA: Amount of current
4629 * Report how much power the device may consume to the phy.
4631 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4633 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4635 if (IS_ERR_OR_NULL(hsotg->uphy))
4637 return usb_phy_set_power(hsotg->uphy, mA);
4640 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4641 .get_frame = dwc2_hsotg_gadget_getframe,
4642 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4643 .udc_start = dwc2_hsotg_udc_start,
4644 .udc_stop = dwc2_hsotg_udc_stop,
4645 .pullup = dwc2_hsotg_pullup,
4646 .vbus_session = dwc2_hsotg_vbus_session,
4647 .vbus_draw = dwc2_hsotg_vbus_draw,
4651 * dwc2_hsotg_initep - initialise a single endpoint
4652 * @hsotg: The device state.
4653 * @hs_ep: The endpoint to be initialised.
4654 * @epnum: The endpoint number
4655 * @dir_in: True if direction is in.
4657 * Initialise the given endpoint (as part of the probe and device state
4658 * creation) to give to the gadget driver. Setup the endpoint name, any
4659 * direction information and other state that may be required.
4661 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4662 struct dwc2_hsotg_ep *hs_ep,
4675 hs_ep->dir_in = dir_in;
4676 hs_ep->index = epnum;
4678 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4680 INIT_LIST_HEAD(&hs_ep->queue);
4681 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4683 /* add to the list of endpoints known by the gadget driver */
4685 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4687 hs_ep->parent = hsotg;
4688 hs_ep->ep.name = hs_ep->name;
4690 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4691 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4693 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4694 epnum ? 1024 : EP0_MPS_LIMIT);
4695 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4698 hs_ep->ep.caps.type_control = true;
4700 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4701 hs_ep->ep.caps.type_iso = true;
4702 hs_ep->ep.caps.type_bulk = true;
4704 hs_ep->ep.caps.type_int = true;
4708 hs_ep->ep.caps.dir_in = true;
4710 hs_ep->ep.caps.dir_out = true;
4713 * if we're using dma, we need to set the next-endpoint pointer
4714 * to be something valid.
4717 if (using_dma(hsotg)) {
4718 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4721 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4723 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4728 * dwc2_hsotg_hw_cfg - read HW configuration registers
4729 * @hsotg: Programming view of the DWC_otg controller
4731 * Read the USB core HW configuration registers
4733 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4739 /* check hardware configuration */
4741 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4744 hsotg->num_of_eps++;
4746 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4747 sizeof(struct dwc2_hsotg_ep),
4749 if (!hsotg->eps_in[0])
4751 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4752 hsotg->eps_out[0] = hsotg->eps_in[0];
4754 cfg = hsotg->hw_params.dev_ep_dirs;
4755 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4757 /* Direction in or both */
4758 if (!(ep_type & 2)) {
4759 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4760 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4761 if (!hsotg->eps_in[i])
4764 /* Direction out or both */
4765 if (!(ep_type & 1)) {
4766 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4767 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4768 if (!hsotg->eps_out[i])
4773 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4774 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4776 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4778 hsotg->dedicated_fifos ? "dedicated" : "shared",
4784 * dwc2_hsotg_dump - dump state of the udc
4785 * @hsotg: Programming view of the DWC_otg controller
4788 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4791 struct device *dev = hsotg->dev;
4795 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4796 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4797 dwc2_readl(hsotg, DIEPMSK));
4799 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4800 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4802 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4803 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4805 /* show periodic fifo settings */
4807 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4808 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4809 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4810 val >> FIFOSIZE_DEPTH_SHIFT,
4811 val & FIFOSIZE_STARTADDR_MASK);
4814 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4816 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4817 dwc2_readl(hsotg, DIEPCTL(idx)),
4818 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4819 dwc2_readl(hsotg, DIEPDMA(idx)));
4821 val = dwc2_readl(hsotg, DOEPCTL(idx));
4823 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4824 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4825 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4826 dwc2_readl(hsotg, DOEPDMA(idx)));
4829 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4830 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4835 * dwc2_gadget_init - init function for gadget
4836 * @hsotg: Programming view of the DWC_otg controller
4839 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4841 struct device *dev = hsotg->dev;
4845 /* Dump fifo information */
4846 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4847 hsotg->params.g_np_tx_fifo_size);
4848 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4850 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4851 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4852 hsotg->gadget.name = dev_name(dev);
4853 hsotg->remote_wakeup_allowed = 0;
4855 if (hsotg->params.lpm)
4856 hsotg->gadget.lpm_capable = true;
4858 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4859 hsotg->gadget.is_otg = 1;
4860 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4861 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4863 ret = dwc2_hsotg_hw_cfg(hsotg);
4865 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4869 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4870 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4871 if (!hsotg->ctrl_buff)
4874 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4875 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4876 if (!hsotg->ep0_buff)
4879 if (using_desc_dma(hsotg)) {
4880 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4885 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4886 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4888 dev_err(dev, "cannot claim IRQ for gadget\n");
4892 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4894 if (hsotg->num_of_eps == 0) {
4895 dev_err(dev, "wrong number of EPs (zero)\n");
4899 /* setup endpoint information */
4901 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4902 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4904 /* allocate EP0 request */
4906 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4908 if (!hsotg->ctrl_req) {
4909 dev_err(dev, "failed to allocate ctrl req\n");
4913 /* initialise the endpoints now the core has been initialised */
4914 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4915 if (hsotg->eps_in[epnum])
4916 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4918 if (hsotg->eps_out[epnum])
4919 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4923 dwc2_hsotg_dump(hsotg);
4929 * dwc2_hsotg_remove - remove function for hsotg driver
4930 * @hsotg: Programming view of the DWC_otg controller
4933 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4935 usb_del_gadget_udc(&hsotg->gadget);
4936 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4941 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4943 unsigned long flags;
4945 if (hsotg->lx_state != DWC2_L0)
4948 if (hsotg->driver) {
4951 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4952 hsotg->driver->driver.name);
4954 spin_lock_irqsave(&hsotg->lock, flags);
4956 dwc2_hsotg_core_disconnect(hsotg);
4957 dwc2_hsotg_disconnect(hsotg);
4958 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4959 spin_unlock_irqrestore(&hsotg->lock, flags);
4961 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4962 if (hsotg->eps_in[ep])
4963 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4964 if (hsotg->eps_out[ep])
4965 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4972 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4974 unsigned long flags;
4976 if (hsotg->lx_state == DWC2_L2)
4979 if (hsotg->driver) {
4980 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4981 hsotg->driver->driver.name);
4983 spin_lock_irqsave(&hsotg->lock, flags);
4984 dwc2_hsotg_core_init_disconnected(hsotg, false);
4985 if (hsotg->enabled) {
4986 /* Enable ACG feature in device mode,if supported */
4987 dwc2_enable_acg(hsotg);
4988 dwc2_hsotg_core_connect(hsotg);
4990 spin_unlock_irqrestore(&hsotg->lock, flags);
4997 * dwc2_backup_device_registers() - Backup controller device registers.
4998 * When suspending usb bus, registers needs to be backuped
4999 * if controller power is disabled once suspended.
5001 * @hsotg: Programming view of the DWC_otg controller
5003 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5005 struct dwc2_dregs_backup *dr;
5008 dev_dbg(hsotg->dev, "%s\n", __func__);
5010 /* Backup dev regs */
5011 dr = &hsotg->dr_backup;
5013 dr->dcfg = dwc2_readl(hsotg, DCFG);
5014 dr->dctl = dwc2_readl(hsotg, DCTL);
5015 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5016 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5017 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5019 for (i = 0; i < hsotg->num_of_eps; i++) {
5021 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5023 /* Ensure DATA PID is correctly configured */
5024 if (dr->diepctl[i] & DXEPCTL_DPID)
5025 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5027 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5029 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5030 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5032 /* Backup OUT EPs */
5033 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5035 /* Ensure DATA PID is correctly configured */
5036 if (dr->doepctl[i] & DXEPCTL_DPID)
5037 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5039 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5041 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5042 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5043 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5050 * dwc2_restore_device_registers() - Restore controller device registers.
5051 * When resuming usb bus, device registers needs to be restored
5052 * if controller power were disabled.
5054 * @hsotg: Programming view of the DWC_otg controller
5055 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5057 * Return: 0 if successful, negative error code otherwise
5059 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5061 struct dwc2_dregs_backup *dr;
5064 dev_dbg(hsotg->dev, "%s\n", __func__);
5066 /* Restore dev regs */
5067 dr = &hsotg->dr_backup;
5069 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5076 dwc2_writel(hsotg, dr->dctl, DCTL);
5078 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5079 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5080 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5082 for (i = 0; i < hsotg->num_of_eps; i++) {
5083 /* Restore IN EPs */
5084 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5085 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5086 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5087 /** WA for enabled EPx's IN in DDMA mode. On entering to
5088 * hibernation wrong value read and saved from DIEPDMAx,
5089 * as result BNA interrupt asserted on hibernation exit
5090 * by restoring from saved area.
5092 if (hsotg->params.g_dma_desc &&
5093 (dr->diepctl[i] & DXEPCTL_EPENA))
5094 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5095 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5096 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5097 /* Restore OUT EPs */
5098 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5099 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5100 * hibernation wrong value read and saved from DOEPDMAx,
5101 * as result BNA interrupt asserted on hibernation exit
5102 * by restoring from saved area.
5104 if (hsotg->params.g_dma_desc &&
5105 (dr->doepctl[i] & DXEPCTL_EPENA))
5106 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5107 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5108 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5115 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5117 * @hsotg: Programming view of DWC_otg controller
5120 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5124 if (!hsotg->params.lpm)
5127 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5128 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5129 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5130 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5131 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5132 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5133 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5134 dwc2_writel(hsotg, val, GLPMCFG);
5135 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5137 /* Unmask WKUP_ALERT Interrupt */
5138 if (hsotg->params.service_interval)
5139 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5143 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5145 * @hsotg: Programming view of DWC_otg controller
5148 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5152 val |= GREFCLK_REF_CLK_MODE;
5153 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5154 val |= hsotg->params.sof_cnt_wkup_alert <<
5155 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5157 dwc2_writel(hsotg, val, GREFCLK);
5158 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5162 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5164 * @hsotg: Programming view of the DWC_otg controller
5166 * Return non-zero if failed to enter to hibernation.
5168 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5173 /* Change to L2(suspend) state */
5174 hsotg->lx_state = DWC2_L2;
5175 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5176 ret = dwc2_backup_global_registers(hsotg);
5178 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5182 ret = dwc2_backup_device_registers(hsotg);
5184 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5189 gpwrdn = GPWRDN_PWRDNRSTN;
5190 gpwrdn |= GPWRDN_PMUACTV;
5191 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5194 /* Set flag to indicate that we are in hibernation */
5195 hsotg->hibernated = 1;
5197 /* Enable interrupts from wake up logic */
5198 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5199 gpwrdn |= GPWRDN_PMUINTSEL;
5200 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5203 /* Unmask device mode interrupts in GPWRDN */
5204 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5205 gpwrdn |= GPWRDN_RST_DET_MSK;
5206 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5207 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5208 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5211 /* Enable Power Down Clamp */
5212 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5213 gpwrdn |= GPWRDN_PWRDNCLMP;
5214 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5217 /* Switch off VDD */
5218 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5219 gpwrdn |= GPWRDN_PWRDNSWTCH;
5220 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5223 /* Save gpwrdn register for further usage if stschng interrupt */
5224 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5225 dev_dbg(hsotg->dev, "Hibernation completed\n");
5231 * dwc2_gadget_exit_hibernation()
5232 * This function is for exiting from Device mode hibernation by host initiated
5233 * resume/reset and device initiated remote-wakeup.
5235 * @hsotg: Programming view of the DWC_otg controller
5236 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5237 * @reset: indicates whether resume is initiated by Reset.
5239 * Return non-zero if failed to exit from hibernation.
5241 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5242 int rem_wakeup, int reset)
5248 struct dwc2_gregs_backup *gr;
5249 struct dwc2_dregs_backup *dr;
5251 gr = &hsotg->gr_backup;
5252 dr = &hsotg->dr_backup;
5254 if (!hsotg->hibernated) {
5255 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5259 "%s: called with rem_wakeup = %d reset = %d\n",
5260 __func__, rem_wakeup, reset);
5262 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5265 /* Clear all pending interupts */
5266 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5269 /* De-assert Restore */
5270 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5271 gpwrdn &= ~GPWRDN_RESTORE;
5272 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5276 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5277 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5278 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5281 /* Restore GUSBCFG, DCFG and DCTL */
5282 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5283 dwc2_writel(hsotg, dr->dcfg, DCFG);
5284 dwc2_writel(hsotg, dr->dctl, DCTL);
5286 /* De-assert Wakeup Logic */
5287 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5288 gpwrdn &= ~GPWRDN_PMUACTV;
5289 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5293 /* Start Remote Wakeup Signaling */
5294 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5297 /* Set Device programming done bit */
5298 dctl = dwc2_readl(hsotg, DCTL);
5299 dctl |= DCTL_PWRONPRGDONE;
5300 dwc2_writel(hsotg, dctl, DCTL);
5302 /* Wait for interrupts which must be cleared */
5304 /* Clear all pending interupts */
5305 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5307 /* Restore global registers */
5308 ret = dwc2_restore_global_registers(hsotg);
5310 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5315 /* Restore device registers */
5316 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5318 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5325 dctl = dwc2_readl(hsotg, DCTL);
5326 dctl &= ~DCTL_RMTWKUPSIG;
5327 dwc2_writel(hsotg, dctl, DCTL);
5330 hsotg->hibernated = 0;
5331 hsotg->lx_state = DWC2_L0;
5332 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");