1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
123 hs_ep->frame_overrun = false;
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
130 * @hs_ep: The endpoint.
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
137 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
150 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
155 new_gsintmsk = gsintmsk | ints;
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
168 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
173 new_gsintmsk = gsintmsk & ~ints;
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
186 * Set or clear the mask for an individual endpoint's interrupt
189 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
213 * @hsotg: Programming view of the DWC_otg controller
215 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
229 * @hsotg: Programming view of the DWC_otg controller
231 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
247 return tx_addr_max - addr;
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
253 * @hsotg: Programming view of the DWC_otg controller
256 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
264 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
265 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
266 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
267 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
272 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
275 * @hsotg: Programming view of the DWC_otg controller
277 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
282 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
284 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
287 return tx_fifo_depth;
289 return tx_fifo_depth / tx_fifo_count;
293 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
294 * @hsotg: The device instance.
296 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
303 u32 *txfsz = hsotg->params.g_tx_fifo_size;
305 /* Reset fifo map if not correctly cleared during previous session */
306 WARN_ON(hsotg->fifo_map);
309 /* set RX/NPTX FIFO sizes */
310 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
311 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
312 FIFOSIZE_STARTADDR_SHIFT) |
313 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
317 * arange all the rest of the TX FIFOs, as some versions of this
318 * block have overlapping default addresses. This also ensures
319 * that if the settings have been changed, then they are set to
323 /* start at the end of the GNPTXFSIZ, rounded up */
324 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
327 * Configure fifos sizes from provided configuration and assign
328 * them to endpoints dynamically according to maxpacket size value of
331 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
335 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
336 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
337 "insufficient fifo memory");
340 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
341 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
344 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
345 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
348 * according to p428 of the design guide, we need to ensure that
349 * all fifos are flushed before continuing
352 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
353 GRSTCTL_RXFFLSH, GRSTCTL);
355 /* wait until the fifos are both flushed */
358 val = dwc2_readl(hsotg, GRSTCTL);
360 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
363 if (--timeout == 0) {
365 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
373 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
377 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
378 * @ep: USB endpoint to allocate request for.
379 * @flags: Allocation flags
381 * Allocate a new USB request structure appropriate for the specified endpoint
383 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
386 struct dwc2_hsotg_req *req;
388 req = kzalloc(sizeof(*req), flags);
392 INIT_LIST_HEAD(&req->queue);
398 * is_ep_periodic - return true if the endpoint is in periodic mode.
399 * @hs_ep: The endpoint to query.
401 * Returns true if the endpoint is in periodic mode, meaning it is being
402 * used for an Interrupt or ISO transfer.
404 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
406 return hs_ep->periodic;
410 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
411 * @hsotg: The device state.
412 * @hs_ep: The endpoint for the request
413 * @hs_req: The request being processed.
415 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
416 * of a request to ensure the buffer is ready for access by the caller.
418 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
419 struct dwc2_hsotg_ep *hs_ep,
420 struct dwc2_hsotg_req *hs_req)
422 struct usb_request *req = &hs_req->req;
424 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
428 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
429 * for Control endpoint
430 * @hsotg: The device state.
432 * This function will allocate 4 descriptor chains for EP 0: 2 for
433 * Setup stage, per one for IN and OUT data/status transactions.
435 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
437 hsotg->setup_desc[0] =
438 dmam_alloc_coherent(hsotg->dev,
439 sizeof(struct dwc2_dma_desc),
440 &hsotg->setup_desc_dma[0],
442 if (!hsotg->setup_desc[0])
445 hsotg->setup_desc[1] =
446 dmam_alloc_coherent(hsotg->dev,
447 sizeof(struct dwc2_dma_desc),
448 &hsotg->setup_desc_dma[1],
450 if (!hsotg->setup_desc[1])
453 hsotg->ctrl_in_desc =
454 dmam_alloc_coherent(hsotg->dev,
455 sizeof(struct dwc2_dma_desc),
456 &hsotg->ctrl_in_desc_dma,
458 if (!hsotg->ctrl_in_desc)
461 hsotg->ctrl_out_desc =
462 dmam_alloc_coherent(hsotg->dev,
463 sizeof(struct dwc2_dma_desc),
464 &hsotg->ctrl_out_desc_dma,
466 if (!hsotg->ctrl_out_desc)
476 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
477 * @hsotg: The controller state.
478 * @hs_ep: The endpoint we're going to write for.
479 * @hs_req: The request to write data for.
481 * This is called when the TxFIFO has some space in it to hold a new
482 * transmission and we have something to give it. The actual setup of
483 * the data size is done elsewhere, so all we have to do is to actually
486 * The return value is zero if there is more space (or nothing was done)
487 * otherwise -ENOSPC is returned if the FIFO space was used up.
489 * This routine is only needed for PIO
491 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
492 struct dwc2_hsotg_ep *hs_ep,
493 struct dwc2_hsotg_req *hs_req)
495 bool periodic = is_ep_periodic(hs_ep);
496 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
497 int buf_pos = hs_req->req.actual;
498 int to_write = hs_ep->size_loaded;
504 to_write -= (buf_pos - hs_ep->last_load);
506 /* if there's nothing to write, get out early */
510 if (periodic && !hsotg->dedicated_fifos) {
511 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
516 * work out how much data was loaded so we can calculate
517 * how much data is left in the fifo.
520 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
523 * if shared fifo, we cannot write anything until the
524 * previous data has been completely sent.
526 if (hs_ep->fifo_load != 0) {
527 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
531 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
533 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
535 /* how much of the data has moved */
536 size_done = hs_ep->size_loaded - size_left;
538 /* how much data is left in the fifo */
539 can_write = hs_ep->fifo_load - size_done;
540 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
541 __func__, can_write);
543 can_write = hs_ep->fifo_size - can_write;
544 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
545 __func__, can_write);
547 if (can_write <= 0) {
548 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
551 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
552 can_write = dwc2_readl(hsotg,
553 DTXFSTS(hs_ep->fifo_index));
558 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
560 "%s: no queue slots available (0x%08x)\n",
563 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
567 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
568 can_write *= 4; /* fifo size is in 32bit quantities. */
571 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
573 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
574 __func__, gnptxsts, can_write, to_write, max_transfer);
577 * limit to 512 bytes of data, it seems at least on the non-periodic
578 * FIFO, requests of >512 cause the endpoint to get stuck with a
579 * fragment of the end of the transfer in it.
581 if (can_write > 512 && !periodic)
585 * limit the write to one max-packet size worth of data, but allow
586 * the transfer to return that it did not run out of fifo space
589 if (to_write > max_transfer) {
590 to_write = max_transfer;
592 /* it's needed only when we do not use dedicated fifos */
593 if (!hsotg->dedicated_fifos)
594 dwc2_hsotg_en_gsint(hsotg,
595 periodic ? GINTSTS_PTXFEMP :
599 /* see if we can write data */
601 if (to_write > can_write) {
602 to_write = can_write;
603 pkt_round = to_write % max_transfer;
606 * Round the write down to an
607 * exact number of packets.
609 * Note, we do not currently check to see if we can ever
610 * write a full packet or not to the FIFO.
614 to_write -= pkt_round;
617 * enable correct FIFO interrupt to alert us when there
621 /* it's needed only when we do not use dedicated fifos */
622 if (!hsotg->dedicated_fifos)
623 dwc2_hsotg_en_gsint(hsotg,
624 periodic ? GINTSTS_PTXFEMP :
628 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
629 to_write, hs_req->req.length, can_write, buf_pos);
634 hs_req->req.actual = buf_pos + to_write;
635 hs_ep->total_data += to_write;
638 hs_ep->fifo_load += to_write;
640 to_write = DIV_ROUND_UP(to_write, 4);
641 data = hs_req->req.buf + buf_pos;
643 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
645 return (to_write >= can_write) ? -ENOSPC : 0;
649 * get_ep_limit - get the maximum data legnth for this endpoint
650 * @hs_ep: The endpoint
652 * Return the maximum data that can be queued in one go on a given endpoint
653 * so that transfers that are too long can be split.
655 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
657 int index = hs_ep->index;
658 unsigned int maxsize;
662 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
663 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
667 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
672 /* we made the constant loading easier above by using +1 */
677 * constrain by packet count if maxpkts*pktsize is greater
678 * than the length register size.
681 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
682 maxsize = maxpkt * hs_ep->ep.maxpacket;
688 * dwc2_hsotg_read_frameno - read current frame number
689 * @hsotg: The device instance
691 * Return the current frame number
693 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
697 dsts = dwc2_readl(hsotg, DSTS);
698 dsts &= DSTS_SOFFN_MASK;
699 dsts >>= DSTS_SOFFN_SHIFT;
705 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
706 * DMA descriptor chain prepared for specific endpoint
707 * @hs_ep: The endpoint
709 * Return the maximum data that can be queued in one go on a given endpoint
710 * depending on its descriptor chain capacity so that transfers that
711 * are too long can be split.
713 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
715 int is_isoc = hs_ep->isochronous;
716 unsigned int maxsize;
719 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
720 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
721 MAX_DMA_DESC_NUM_HS_ISOC;
723 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
729 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
730 * @hs_ep: The endpoint
731 * @mask: RX/TX bytes mask to be defined
733 * Returns maximum data payload for one descriptor after analyzing endpoint
735 * DMA descriptor transfer bytes limit depends on EP type:
737 * Isochronous - descriptor rx/tx bytes bitfield limit,
738 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
739 * have concatenations from various descriptors within one packet.
741 * Selects corresponding mask for RX/TX bytes as well.
743 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
745 u32 mps = hs_ep->ep.maxpacket;
746 int dir_in = hs_ep->dir_in;
749 if (!hs_ep->index && !dir_in) {
751 *mask = DEV_DMA_NBYTES_MASK;
752 } else if (hs_ep->isochronous) {
754 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
755 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
757 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
758 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
761 desc_size = DEV_DMA_NBYTES_LIMIT;
762 *mask = DEV_DMA_NBYTES_MASK;
764 /* Round down desc_size to be mps multiple */
765 desc_size -= desc_size % mps;
771 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
772 struct dwc2_dma_desc **desc,
777 int dir_in = hs_ep->dir_in;
778 u32 mps = hs_ep->ep.maxpacket;
784 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
786 hs_ep->desc_count = (len / maxsize) +
787 ((len % maxsize) ? 1 : 0);
789 hs_ep->desc_count = 1;
791 for (i = 0; i < hs_ep->desc_count; ++i) {
793 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
794 << DEV_DMA_BUFF_STS_SHIFT);
797 if (!hs_ep->index && !dir_in)
798 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
801 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
802 (*desc)->buf = dma_buff + offset;
808 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
811 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
812 ((hs_ep->send_zlp && true_last) ?
816 len << DEV_DMA_NBYTES_SHIFT & mask;
817 (*desc)->buf = dma_buff + offset;
820 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
821 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
822 << DEV_DMA_BUFF_STS_SHIFT);
828 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
829 * @hs_ep: The endpoint
830 * @ureq: Request to transfer
831 * @offset: offset in bytes
832 * @len: Length of the transfer
834 * This function will iterate over descriptor chain and fill its entries
835 * with corresponding information based on transfer data.
837 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
838 struct usb_request *ureq,
842 struct dwc2_dma_desc *desc = hs_ep->desc_list;
843 struct scatterlist *sg;
847 /* non-DMA sg buffer */
848 if (!ureq->num_sgs) {
849 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
850 ureq->dma + offset, len, true);
855 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
856 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
857 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
859 desc_count += hs_ep->desc_count;
862 hs_ep->desc_count = desc_count;
866 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
867 * @hs_ep: The isochronous endpoint.
868 * @dma_buff: usb requests dma buffer.
869 * @len: usb request transfer length.
871 * Fills next free descriptor with the data of the arrived usb request,
872 * frame info, sets Last and IOC bits increments next_desc. If filled
873 * descriptor is not the first one, removes L bit from the previous descriptor
876 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
877 dma_addr_t dma_buff, unsigned int len)
879 struct dwc2_dma_desc *desc;
880 struct dwc2_hsotg *hsotg = hs_ep->parent;
886 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
888 index = hs_ep->next_desc;
889 desc = &hs_ep->desc_list[index];
891 /* Check if descriptor chain full */
892 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
893 DEV_DMA_BUFF_STS_HREADY) {
894 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
898 /* Clear L bit of previous desc if more than one entries in the chain */
899 if (hs_ep->next_desc)
900 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
902 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
903 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
906 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
908 desc->buf = dma_buff;
909 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
910 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
914 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
917 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
918 DEV_DMA_ISOC_PID_MASK) |
919 ((len % hs_ep->ep.maxpacket) ?
921 ((hs_ep->target_frame <<
922 DEV_DMA_ISOC_FRNUM_SHIFT) &
923 DEV_DMA_ISOC_FRNUM_MASK);
926 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
927 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
929 /* Increment frame number by interval for IN */
931 dwc2_gadget_incr_frame_num(hs_ep);
933 /* Update index of last configured entry in the chain */
935 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
936 hs_ep->next_desc = 0;
942 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
943 * @hs_ep: The isochronous endpoint.
945 * Prepare descriptor chain for isochronous endpoints. Afterwards
946 * write DMA address to HW and enable the endpoint.
948 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
950 struct dwc2_hsotg *hsotg = hs_ep->parent;
951 struct dwc2_hsotg_req *hs_req, *treq;
952 int index = hs_ep->index;
958 struct dwc2_dma_desc *desc;
960 if (list_empty(&hs_ep->queue)) {
961 hs_ep->target_frame = TARGET_FRAME_INITIAL;
962 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
966 /* Initialize descriptor chain by Host Busy status */
967 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
968 desc = &hs_ep->desc_list[i];
970 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
971 << DEV_DMA_BUFF_STS_SHIFT);
974 hs_ep->next_desc = 0;
975 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
976 dma_addr_t dma_addr = hs_req->req.dma;
978 if (hs_req->req.num_sgs) {
979 WARN_ON(hs_req->req.num_sgs > 1);
980 dma_addr = sg_dma_address(hs_req->req.sg);
982 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
988 hs_ep->compl_desc = 0;
989 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
990 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
992 /* write descriptor chain address to control register */
993 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
995 ctrl = dwc2_readl(hsotg, depctl);
996 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
997 dwc2_writel(hsotg, ctrl, depctl);
1001 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1002 * @hsotg: The controller state.
1003 * @hs_ep: The endpoint to process a request for
1004 * @hs_req: The request to start.
1005 * @continuing: True if we are doing more for the current request.
1007 * Start the given request running by setting the endpoint registers
1008 * appropriately, and writing any data to the FIFOs.
1010 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1011 struct dwc2_hsotg_ep *hs_ep,
1012 struct dwc2_hsotg_req *hs_req,
1015 struct usb_request *ureq = &hs_req->req;
1016 int index = hs_ep->index;
1017 int dir_in = hs_ep->dir_in;
1022 unsigned int length;
1023 unsigned int packets;
1024 unsigned int maxreq;
1025 unsigned int dma_reg;
1028 if (hs_ep->req && !continuing) {
1029 dev_err(hsotg->dev, "%s: active request\n", __func__);
1032 } else if (hs_ep->req != hs_req && continuing) {
1034 "%s: continue different req\n", __func__);
1040 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1041 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1042 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1044 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1045 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1046 hs_ep->dir_in ? "in" : "out");
1048 /* If endpoint is stalled, we will restart request later */
1049 ctrl = dwc2_readl(hsotg, epctrl_reg);
1051 if (index && ctrl & DXEPCTL_STALL) {
1052 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1056 length = ureq->length - ureq->actual;
1057 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1058 ureq->length, ureq->actual);
1060 if (!using_desc_dma(hsotg))
1061 maxreq = get_ep_limit(hs_ep);
1063 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1065 if (length > maxreq) {
1066 int round = maxreq % hs_ep->ep.maxpacket;
1068 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1069 __func__, length, maxreq, round);
1071 /* round down to multiple of packets */
1079 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1081 packets = 1; /* send one packet if length is zero. */
1083 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1084 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1088 if (dir_in && index != 0)
1089 if (hs_ep->isochronous)
1090 epsize = DXEPTSIZ_MC(packets);
1092 epsize = DXEPTSIZ_MC(1);
1097 * zero length packet should be programmed on its own and should not
1098 * be counted in DIEPTSIZ.PktCnt with other packets.
1100 if (dir_in && ureq->zero && !continuing) {
1101 /* Test if zlp is actually required. */
1102 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1103 !(ureq->length % hs_ep->ep.maxpacket))
1104 hs_ep->send_zlp = 1;
1107 epsize |= DXEPTSIZ_PKTCNT(packets);
1108 epsize |= DXEPTSIZ_XFERSIZE(length);
1110 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1111 __func__, packets, length, ureq->length, epsize, epsize_reg);
1113 /* store the request as the current one we're doing */
1114 hs_ep->req = hs_req;
1116 if (using_desc_dma(hsotg)) {
1118 u32 mps = hs_ep->ep.maxpacket;
1120 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1124 else if (length % mps)
1125 length += (mps - (length % mps));
1129 * If more data to send, adjust DMA for EP0 out data stage.
1130 * ureq->dma stays unchanged, hence increment it by already
1131 * passed passed data count before starting new transaction.
1133 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1135 offset = ureq->actual;
1137 /* Fill DDMA chain entries */
1138 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq, offset,
1141 /* write descriptor chain address to control register */
1142 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1144 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1145 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1147 /* write size / packets */
1148 dwc2_writel(hsotg, epsize, epsize_reg);
1150 if (using_dma(hsotg) && !continuing && (length != 0)) {
1152 * write DMA address to control register, buffer
1153 * already synced by dwc2_hsotg_ep_queue().
1156 dwc2_writel(hsotg, ureq->dma, dma_reg);
1158 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1159 __func__, &ureq->dma, dma_reg);
1163 if (hs_ep->isochronous && hs_ep->interval == 1) {
1164 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1165 dwc2_gadget_incr_frame_num(hs_ep);
1167 if (hs_ep->target_frame & 0x1)
1168 ctrl |= DXEPCTL_SETODDFR;
1170 ctrl |= DXEPCTL_SETEVENFR;
1173 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1175 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1177 /* For Setup request do not clear NAK */
1178 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1179 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1181 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1182 dwc2_writel(hsotg, ctrl, epctrl_reg);
1185 * set these, it seems that DMA support increments past the end
1186 * of the packet buffer so we need to calculate the length from
1189 hs_ep->size_loaded = length;
1190 hs_ep->last_load = ureq->actual;
1192 if (dir_in && !using_dma(hsotg)) {
1193 /* set these anyway, we may need them for non-periodic in */
1194 hs_ep->fifo_load = 0;
1196 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1200 * Note, trying to clear the NAK here causes problems with transmit
1201 * on the S3C6400 ending up with the TXFIFO becoming full.
1204 /* check ep is enabled */
1205 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1207 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1208 index, dwc2_readl(hsotg, epctrl_reg));
1210 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1211 __func__, dwc2_readl(hsotg, epctrl_reg));
1213 /* enable ep interrupts */
1214 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1218 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1219 * @hsotg: The device state.
1220 * @hs_ep: The endpoint the request is on.
1221 * @req: The request being processed.
1223 * We've been asked to queue a request, so ensure that the memory buffer
1224 * is correctly setup for DMA. If we've been passed an extant DMA address
1225 * then ensure the buffer has been synced to memory. If our buffer has no
1226 * DMA memory, then we map the memory and mark our request to allow us to
1227 * cleanup on completion.
1229 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1230 struct dwc2_hsotg_ep *hs_ep,
1231 struct usb_request *req)
1235 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1242 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1243 __func__, req->buf, req->length);
1248 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1249 struct dwc2_hsotg_ep *hs_ep,
1250 struct dwc2_hsotg_req *hs_req)
1252 void *req_buf = hs_req->req.buf;
1254 /* If dma is not being used or buffer is aligned */
1255 if (!using_dma(hsotg) || !((long)req_buf & 3))
1258 WARN_ON(hs_req->saved_req_buf);
1260 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1261 hs_ep->ep.name, req_buf, hs_req->req.length);
1263 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1264 if (!hs_req->req.buf) {
1265 hs_req->req.buf = req_buf;
1267 "%s: unable to allocate memory for bounce buffer\n",
1272 /* Save actual buffer */
1273 hs_req->saved_req_buf = req_buf;
1276 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1281 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1282 struct dwc2_hsotg_ep *hs_ep,
1283 struct dwc2_hsotg_req *hs_req)
1285 /* If dma is not being used or buffer was aligned */
1286 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1289 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1290 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1292 /* Copy data from bounce buffer on successful out transfer */
1293 if (!hs_ep->dir_in && !hs_req->req.status)
1294 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1295 hs_req->req.actual);
1297 /* Free bounce buffer */
1298 kfree(hs_req->req.buf);
1300 hs_req->req.buf = hs_req->saved_req_buf;
1301 hs_req->saved_req_buf = NULL;
1305 * dwc2_gadget_target_frame_elapsed - Checks target frame
1306 * @hs_ep: The driver endpoint to check
1308 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1309 * corresponding transfer.
1311 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1313 struct dwc2_hsotg *hsotg = hs_ep->parent;
1314 u32 target_frame = hs_ep->target_frame;
1315 u32 current_frame = hsotg->frame_number;
1316 bool frame_overrun = hs_ep->frame_overrun;
1318 if (!frame_overrun && current_frame >= target_frame)
1321 if (frame_overrun && current_frame >= target_frame &&
1322 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1329 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1330 * @hsotg: The driver state
1331 * @hs_ep: the ep descriptor chain is for
1333 * Called to update EP0 structure's pointers depend on stage of
1336 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1337 struct dwc2_hsotg_ep *hs_ep)
1339 switch (hsotg->ep0_state) {
1340 case DWC2_EP0_SETUP:
1341 case DWC2_EP0_STATUS_OUT:
1342 hs_ep->desc_list = hsotg->setup_desc[0];
1343 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1345 case DWC2_EP0_DATA_IN:
1346 case DWC2_EP0_STATUS_IN:
1347 hs_ep->desc_list = hsotg->ctrl_in_desc;
1348 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1350 case DWC2_EP0_DATA_OUT:
1351 hs_ep->desc_list = hsotg->ctrl_out_desc;
1352 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1355 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1363 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1366 struct dwc2_hsotg_req *hs_req = our_req(req);
1367 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1368 struct dwc2_hsotg *hs = hs_ep->parent;
1375 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1376 ep->name, req, req->length, req->buf, req->no_interrupt,
1377 req->zero, req->short_not_ok);
1379 /* Prevent new request submission when controller is suspended */
1380 if (hs->lx_state != DWC2_L0) {
1381 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1386 /* initialise status of the request */
1387 INIT_LIST_HEAD(&hs_req->queue);
1389 req->status = -EINPROGRESS;
1391 /* In DDMA mode for ISOC's don't queue request if length greater
1392 * than descriptor limits.
1394 if (using_desc_dma(hs) && hs_ep->isochronous) {
1395 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1396 if (hs_ep->dir_in && req->length > maxsize) {
1397 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1398 req->length, maxsize);
1402 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1403 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1404 req->length, hs_ep->ep.maxpacket);
1409 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1413 /* if we're using DMA, sync the buffers as necessary */
1414 if (using_dma(hs)) {
1415 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1419 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1420 if (using_desc_dma(hs) && !hs_ep->index) {
1421 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1426 first = list_empty(&hs_ep->queue);
1427 list_add_tail(&hs_req->queue, &hs_ep->queue);
1430 * Handle DDMA isochronous transfers separately - just add new entry
1431 * to the descriptor chain.
1432 * Transfer will be started once SW gets either one of NAK or
1433 * OutTknEpDis interrupts.
1435 if (using_desc_dma(hs) && hs_ep->isochronous) {
1436 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1437 dma_addr_t dma_addr = hs_req->req.dma;
1439 if (hs_req->req.num_sgs) {
1440 WARN_ON(hs_req->req.num_sgs > 1);
1441 dma_addr = sg_dma_address(hs_req->req.sg);
1443 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1444 hs_req->req.length);
1449 /* Change EP direction if status phase request is after data out */
1450 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1451 hs->ep0_state == DWC2_EP0_DATA_OUT)
1455 if (!hs_ep->isochronous) {
1456 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1460 /* Update current frame number value. */
1461 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1462 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1463 dwc2_gadget_incr_frame_num(hs_ep);
1464 /* Update current frame number value once more as it
1467 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1470 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1471 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1476 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1479 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1480 struct dwc2_hsotg *hs = hs_ep->parent;
1481 unsigned long flags = 0;
1484 spin_lock_irqsave(&hs->lock, flags);
1485 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1486 spin_unlock_irqrestore(&hs->lock, flags);
1491 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1492 struct usb_request *req)
1494 struct dwc2_hsotg_req *hs_req = our_req(req);
1500 * dwc2_hsotg_complete_oursetup - setup completion callback
1501 * @ep: The endpoint the request was on.
1502 * @req: The request completed.
1504 * Called on completion of any requests the driver itself
1505 * submitted that need cleaning up.
1507 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1508 struct usb_request *req)
1510 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1511 struct dwc2_hsotg *hsotg = hs_ep->parent;
1513 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1515 dwc2_hsotg_ep_free_request(ep, req);
1519 * ep_from_windex - convert control wIndex value to endpoint
1520 * @hsotg: The driver state.
1521 * @windex: The control request wIndex field (in host order).
1523 * Convert the given wIndex into a pointer to an driver endpoint
1524 * structure, or return NULL if it is not a valid endpoint.
1526 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1529 struct dwc2_hsotg_ep *ep;
1530 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1531 int idx = windex & 0x7F;
1533 if (windex >= 0x100)
1536 if (idx > hsotg->num_of_eps)
1539 ep = index_to_ep(hsotg, idx, dir);
1541 if (idx && ep->dir_in != dir)
1548 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1549 * @hsotg: The driver state.
1550 * @testmode: requested usb test mode
1551 * Enable usb Test Mode requested by the Host.
1553 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1555 int dctl = dwc2_readl(hsotg, DCTL);
1557 dctl &= ~DCTL_TSTCTL_MASK;
1564 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1569 dwc2_writel(hsotg, dctl, DCTL);
1574 * dwc2_hsotg_send_reply - send reply to control request
1575 * @hsotg: The device state
1577 * @buff: Buffer for request
1578 * @length: Length of reply.
1580 * Create a request and queue it on the given endpoint. This is useful as
1581 * an internal method of sending replies to certain control requests, etc.
1583 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1584 struct dwc2_hsotg_ep *ep,
1588 struct usb_request *req;
1591 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1593 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1594 hsotg->ep0_reply = req;
1596 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1600 req->buf = hsotg->ep0_buff;
1601 req->length = length;
1603 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1607 req->complete = dwc2_hsotg_complete_oursetup;
1610 memcpy(req->buf, buff, length);
1612 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1614 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1622 * dwc2_hsotg_process_req_status - process request GET_STATUS
1623 * @hsotg: The device state
1624 * @ctrl: USB control request
1626 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1627 struct usb_ctrlrequest *ctrl)
1629 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1630 struct dwc2_hsotg_ep *ep;
1634 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1637 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1641 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1642 case USB_RECIP_DEVICE:
1644 * bit 0 => self powered
1645 * bit 1 => remote wakeup
1647 reply = cpu_to_le16(0);
1650 case USB_RECIP_INTERFACE:
1651 /* currently, the data result should be zero */
1652 reply = cpu_to_le16(0);
1655 case USB_RECIP_ENDPOINT:
1656 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1660 reply = cpu_to_le16(ep->halted ? 1 : 0);
1667 if (le16_to_cpu(ctrl->wLength) != 2)
1670 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1672 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1679 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1682 * get_ep_head - return the first request on the endpoint
1683 * @hs_ep: The controller endpoint to get
1685 * Get the first request on the endpoint.
1687 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1689 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1694 * dwc2_gadget_start_next_request - Starts next request from ep queue
1695 * @hs_ep: Endpoint structure
1697 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1698 * in its handler. Hence we need to unmask it here to be able to do
1699 * resynchronization.
1701 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1704 struct dwc2_hsotg *hsotg = hs_ep->parent;
1705 int dir_in = hs_ep->dir_in;
1706 struct dwc2_hsotg_req *hs_req;
1707 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1709 if (!list_empty(&hs_ep->queue)) {
1710 hs_req = get_ep_head(hs_ep);
1711 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1714 if (!hs_ep->isochronous)
1718 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1721 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1723 mask = dwc2_readl(hsotg, epmsk_reg);
1724 mask |= DOEPMSK_OUTTKNEPDISMSK;
1725 dwc2_writel(hsotg, mask, epmsk_reg);
1730 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1731 * @hsotg: The device state
1732 * @ctrl: USB control request
1734 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1735 struct usb_ctrlrequest *ctrl)
1737 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1738 struct dwc2_hsotg_req *hs_req;
1739 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1740 struct dwc2_hsotg_ep *ep;
1747 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1748 __func__, set ? "SET" : "CLEAR");
1750 wValue = le16_to_cpu(ctrl->wValue);
1751 wIndex = le16_to_cpu(ctrl->wIndex);
1752 recip = ctrl->bRequestType & USB_RECIP_MASK;
1755 case USB_RECIP_DEVICE:
1757 case USB_DEVICE_REMOTE_WAKEUP:
1758 hsotg->remote_wakeup_allowed = 1;
1761 case USB_DEVICE_TEST_MODE:
1762 if ((wIndex & 0xff) != 0)
1767 hsotg->test_mode = wIndex >> 8;
1768 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1771 "%s: failed to send reply\n", __func__);
1780 case USB_RECIP_ENDPOINT:
1781 ep = ep_from_windex(hsotg, wIndex);
1783 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1789 case USB_ENDPOINT_HALT:
1790 halted = ep->halted;
1792 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1794 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1797 "%s: failed to send reply\n", __func__);
1802 * we have to complete all requests for ep if it was
1803 * halted, and the halt was cleared by CLEAR_FEATURE
1806 if (!set && halted) {
1808 * If we have request in progress,
1814 list_del_init(&hs_req->queue);
1815 if (hs_req->req.complete) {
1816 spin_unlock(&hsotg->lock);
1817 usb_gadget_giveback_request(
1818 &ep->ep, &hs_req->req);
1819 spin_lock(&hsotg->lock);
1823 /* If we have pending request, then start it */
1825 dwc2_gadget_start_next_request(ep);
1840 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1843 * dwc2_hsotg_stall_ep0 - stall ep0
1844 * @hsotg: The device state
1846 * Set stall for ep0 as response for setup request.
1848 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1850 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1854 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1855 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1858 * DxEPCTL_Stall will be cleared by EP once it has
1859 * taken effect, so no need to clear later.
1862 ctrl = dwc2_readl(hsotg, reg);
1863 ctrl |= DXEPCTL_STALL;
1864 ctrl |= DXEPCTL_CNAK;
1865 dwc2_writel(hsotg, ctrl, reg);
1868 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1869 ctrl, reg, dwc2_readl(hsotg, reg));
1872 * complete won't be called, so we enqueue
1873 * setup request here
1875 dwc2_hsotg_enqueue_setup(hsotg);
1879 * dwc2_hsotg_process_control - process a control request
1880 * @hsotg: The device state
1881 * @ctrl: The control request received
1883 * The controller has received the SETUP phase of a control request, and
1884 * needs to work out what to do next (and whether to pass it on to the
1887 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1888 struct usb_ctrlrequest *ctrl)
1890 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1895 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1896 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1897 ctrl->wIndex, ctrl->wLength);
1899 if (ctrl->wLength == 0) {
1901 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1902 } else if (ctrl->bRequestType & USB_DIR_IN) {
1904 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1907 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1910 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1911 switch (ctrl->bRequest) {
1912 case USB_REQ_SET_ADDRESS:
1913 hsotg->connected = 1;
1914 dcfg = dwc2_readl(hsotg, DCFG);
1915 dcfg &= ~DCFG_DEVADDR_MASK;
1916 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1917 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1918 dwc2_writel(hsotg, dcfg, DCFG);
1920 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1922 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1925 case USB_REQ_GET_STATUS:
1926 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1929 case USB_REQ_CLEAR_FEATURE:
1930 case USB_REQ_SET_FEATURE:
1931 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1936 /* as a fallback, try delivering it to the driver to deal with */
1938 if (ret == 0 && hsotg->driver) {
1939 spin_unlock(&hsotg->lock);
1940 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1941 spin_lock(&hsotg->lock);
1943 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1946 hsotg->delayed_status = false;
1947 if (ret == USB_GADGET_DELAYED_STATUS)
1948 hsotg->delayed_status = true;
1951 * the request is either unhandlable, or is not formatted correctly
1952 * so respond with a STALL for the status stage to indicate failure.
1956 dwc2_hsotg_stall_ep0(hsotg);
1960 * dwc2_hsotg_complete_setup - completion of a setup transfer
1961 * @ep: The endpoint the request was on.
1962 * @req: The request completed.
1964 * Called on completion of any requests the driver itself submitted for
1967 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1968 struct usb_request *req)
1970 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1971 struct dwc2_hsotg *hsotg = hs_ep->parent;
1973 if (req->status < 0) {
1974 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1978 spin_lock(&hsotg->lock);
1979 if (req->actual == 0)
1980 dwc2_hsotg_enqueue_setup(hsotg);
1982 dwc2_hsotg_process_control(hsotg, req->buf);
1983 spin_unlock(&hsotg->lock);
1987 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1988 * @hsotg: The device state.
1990 * Enqueue a request on EP0 if necessary to received any SETUP packets
1991 * received from the host.
1993 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1995 struct usb_request *req = hsotg->ctrl_req;
1996 struct dwc2_hsotg_req *hs_req = our_req(req);
1999 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2003 req->buf = hsotg->ctrl_buff;
2004 req->complete = dwc2_hsotg_complete_setup;
2006 if (!list_empty(&hs_req->queue)) {
2007 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2011 hsotg->eps_out[0]->dir_in = 0;
2012 hsotg->eps_out[0]->send_zlp = 0;
2013 hsotg->ep0_state = DWC2_EP0_SETUP;
2015 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2017 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2019 * Don't think there's much we can do other than watch the
2025 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2026 struct dwc2_hsotg_ep *hs_ep)
2029 u8 index = hs_ep->index;
2030 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2031 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2034 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2037 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2039 if (using_desc_dma(hsotg)) {
2041 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2043 /* Not specific buffer needed for ep0 ZLP */
2044 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &hs_ep->desc_list,
2045 hs_ep->desc_list_dma, 0, true);
2047 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2048 DXEPTSIZ_XFERSIZE(0),
2052 ctrl = dwc2_readl(hsotg, epctl_reg);
2053 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2054 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2055 ctrl |= DXEPCTL_USBACTEP;
2056 dwc2_writel(hsotg, ctrl, epctl_reg);
2060 * dwc2_hsotg_complete_request - complete a request given to us
2061 * @hsotg: The device state.
2062 * @hs_ep: The endpoint the request was on.
2063 * @hs_req: The request to complete.
2064 * @result: The result code (0 => Ok, otherwise errno)
2066 * The given request has finished, so call the necessary completion
2067 * if it has one and then look to see if we can start a new request
2070 * Note, expects the ep to already be locked as appropriate.
2072 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2073 struct dwc2_hsotg_ep *hs_ep,
2074 struct dwc2_hsotg_req *hs_req,
2078 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2082 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2083 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2086 * only replace the status if we've not already set an error
2087 * from a previous transaction
2090 if (hs_req->req.status == -EINPROGRESS)
2091 hs_req->req.status = result;
2093 if (using_dma(hsotg))
2094 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2096 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2099 list_del_init(&hs_req->queue);
2102 * call the complete request with the locks off, just in case the
2103 * request tries to queue more work for this endpoint.
2106 if (hs_req->req.complete) {
2107 spin_unlock(&hsotg->lock);
2108 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2109 spin_lock(&hsotg->lock);
2112 /* In DDMA don't need to proceed to starting of next ISOC request */
2113 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2117 * Look to see if there is anything else to do. Note, the completion
2118 * of the previous request may have caused a new request to be started
2119 * so be careful when doing this.
2122 if (!hs_ep->req && result >= 0)
2123 dwc2_gadget_start_next_request(hs_ep);
2127 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2128 * @hs_ep: The endpoint the request was on.
2130 * Get first request from the ep queue, determine descriptor on which complete
2131 * happened. SW discovers which descriptor currently in use by HW, adjusts
2132 * dma_address and calculates index of completed descriptor based on the value
2133 * of DEPDMA register. Update actual length of request, giveback to gadget.
2135 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2137 struct dwc2_hsotg *hsotg = hs_ep->parent;
2138 struct dwc2_hsotg_req *hs_req;
2139 struct usb_request *ureq;
2143 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2145 /* Process only descriptors with buffer status set to DMA done */
2146 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2147 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2149 hs_req = get_ep_head(hs_ep);
2151 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2154 ureq = &hs_req->req;
2156 /* Check completion status */
2157 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2159 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2160 DEV_DMA_ISOC_RX_NBYTES_MASK;
2161 ureq->actual = ureq->length - ((desc_sts & mask) >>
2162 DEV_DMA_ISOC_NBYTES_SHIFT);
2164 /* Adjust actual len for ISOC Out if len is
2167 if (!hs_ep->dir_in && ureq->length & 0x3)
2168 ureq->actual += 4 - (ureq->length & 0x3);
2170 /* Set actual frame number for completed transfers */
2171 ureq->frame_number =
2172 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2173 DEV_DMA_ISOC_FRNUM_SHIFT;
2176 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2178 hs_ep->compl_desc++;
2179 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2180 hs_ep->compl_desc = 0;
2181 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2186 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2187 * @hs_ep: The isochronous endpoint.
2189 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2190 * interrupt. Reset target frame and next_desc to allow to start
2191 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2192 * interrupt for OUT direction.
2194 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2196 struct dwc2_hsotg *hsotg = hs_ep->parent;
2199 dwc2_flush_rx_fifo(hsotg);
2200 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2202 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2203 hs_ep->next_desc = 0;
2204 hs_ep->compl_desc = 0;
2208 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2209 * @hsotg: The device state.
2210 * @ep_idx: The endpoint index for the data
2211 * @size: The size of data in the fifo, in bytes
2213 * The FIFO status shows there is data to read from the FIFO for a given
2214 * endpoint, so sort out whether we need to read the data into a request
2215 * that has been made for that endpoint.
2217 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2219 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2220 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2226 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2230 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2231 __func__, size, ep_idx, epctl);
2233 /* dump the data from the FIFO, we've nothing we can do */
2234 for (ptr = 0; ptr < size; ptr += 4)
2235 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2241 read_ptr = hs_req->req.actual;
2242 max_req = hs_req->req.length - read_ptr;
2244 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2245 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2247 if (to_read > max_req) {
2249 * more data appeared than we where willing
2250 * to deal with in this request.
2253 /* currently we don't deal this */
2257 hs_ep->total_data += to_read;
2258 hs_req->req.actual += to_read;
2259 to_read = DIV_ROUND_UP(to_read, 4);
2262 * note, we might over-write the buffer end by 3 bytes depending on
2263 * alignment of the data.
2265 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2266 hs_req->req.buf + read_ptr, to_read);
2270 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2271 * @hsotg: The device instance
2272 * @dir_in: If IN zlp
2274 * Generate a zero-length IN packet request for terminating a SETUP
2277 * Note, since we don't write any data to the TxFIFO, then it is
2278 * currently believed that we do not need to wait for any space in
2281 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2283 /* eps_out[0] is used in both directions */
2284 hsotg->eps_out[0]->dir_in = dir_in;
2285 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2287 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2290 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2295 ctrl = dwc2_readl(hsotg, epctl_reg);
2296 if (ctrl & DXEPCTL_EOFRNUM)
2297 ctrl |= DXEPCTL_SETEVENFR;
2299 ctrl |= DXEPCTL_SETODDFR;
2300 dwc2_writel(hsotg, ctrl, epctl_reg);
2304 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2305 * @hs_ep - The endpoint on which transfer went
2307 * Iterate over endpoints descriptor chain and get info on bytes remained
2308 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2310 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2312 struct dwc2_hsotg *hsotg = hs_ep->parent;
2313 unsigned int bytes_rem = 0;
2314 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2321 for (i = 0; i < hs_ep->desc_count; ++i) {
2322 status = desc->status;
2323 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2325 if (status & DEV_DMA_STS_MASK)
2326 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2327 i, status & DEV_DMA_STS_MASK);
2335 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2336 * @hsotg: The device instance
2337 * @epnum: The endpoint received from
2339 * The RXFIFO has delivered an OutDone event, which means that the data
2340 * transfer for an OUT endpoint has been completed, either by a short
2341 * packet or by the finish of a transfer.
2343 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2345 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2346 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2347 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2348 struct usb_request *req = &hs_req->req;
2349 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2353 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2357 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2358 dev_dbg(hsotg->dev, "zlp packet received\n");
2359 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2360 dwc2_hsotg_enqueue_setup(hsotg);
2364 if (using_desc_dma(hsotg))
2365 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2367 if (using_dma(hsotg)) {
2368 unsigned int size_done;
2371 * Calculate the size of the transfer by checking how much
2372 * is left in the endpoint size register and then working it
2373 * out from the amount we loaded for the transfer.
2375 * We need to do this as DMA pointers are always 32bit aligned
2376 * so may overshoot/undershoot the transfer.
2379 size_done = hs_ep->size_loaded - size_left;
2380 size_done += hs_ep->last_load;
2382 req->actual = size_done;
2385 /* if there is more request to do, schedule new transfer */
2386 if (req->actual < req->length && size_left == 0) {
2387 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2391 if (req->actual < req->length && req->short_not_ok) {
2392 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2393 __func__, req->actual, req->length);
2396 * todo - what should we return here? there's no one else
2397 * even bothering to check the status.
2401 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2402 if (!using_desc_dma(hsotg) && epnum == 0 &&
2403 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2404 /* Move to STATUS IN */
2405 if (!hsotg->delayed_status)
2406 dwc2_hsotg_ep0_zlp(hsotg, true);
2410 * Slave mode OUT transfers do not go through XferComplete so
2411 * adjust the ISOC parity here.
2413 if (!using_dma(hsotg)) {
2414 if (hs_ep->isochronous && hs_ep->interval == 1)
2415 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2416 else if (hs_ep->isochronous && hs_ep->interval > 1)
2417 dwc2_gadget_incr_frame_num(hs_ep);
2420 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2424 * dwc2_hsotg_handle_rx - RX FIFO has data
2425 * @hsotg: The device instance
2427 * The IRQ handler has detected that the RX FIFO has some data in it
2428 * that requires processing, so find out what is in there and do the
2431 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2432 * chunks, so if you have x packets received on an endpoint you'll get x
2433 * FIFO events delivered, each with a packet's worth of data in it.
2435 * When using DMA, we should not be processing events from the RXFIFO
2436 * as the actual data should be sent to the memory directly and we turn
2437 * on the completion interrupts to get notifications of transfer completion.
2439 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2441 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2442 u32 epnum, status, size;
2444 WARN_ON(using_dma(hsotg));
2446 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2447 status = grxstsr & GRXSTS_PKTSTS_MASK;
2449 size = grxstsr & GRXSTS_BYTECNT_MASK;
2450 size >>= GRXSTS_BYTECNT_SHIFT;
2452 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2453 __func__, grxstsr, size, epnum);
2455 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2456 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2457 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2460 case GRXSTS_PKTSTS_OUTDONE:
2461 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2462 dwc2_hsotg_read_frameno(hsotg));
2464 if (!using_dma(hsotg))
2465 dwc2_hsotg_handle_outdone(hsotg, epnum);
2468 case GRXSTS_PKTSTS_SETUPDONE:
2470 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2471 dwc2_hsotg_read_frameno(hsotg),
2472 dwc2_readl(hsotg, DOEPCTL(0)));
2474 * Call dwc2_hsotg_handle_outdone here if it was not called from
2475 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2476 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2478 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2479 dwc2_hsotg_handle_outdone(hsotg, epnum);
2482 case GRXSTS_PKTSTS_OUTRX:
2483 dwc2_hsotg_rx_data(hsotg, epnum, size);
2486 case GRXSTS_PKTSTS_SETUPRX:
2488 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2489 dwc2_hsotg_read_frameno(hsotg),
2490 dwc2_readl(hsotg, DOEPCTL(0)));
2492 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2494 dwc2_hsotg_rx_data(hsotg, epnum, size);
2498 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2501 dwc2_hsotg_dump(hsotg);
2507 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2508 * @mps: The maximum packet size in bytes.
2510 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2514 return D0EPCTL_MPS_64;
2516 return D0EPCTL_MPS_32;
2518 return D0EPCTL_MPS_16;
2520 return D0EPCTL_MPS_8;
2523 /* bad max packet size, warn and return invalid result */
2529 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2530 * @hsotg: The driver state.
2531 * @ep: The index number of the endpoint
2532 * @mps: The maximum packet size in bytes
2533 * @mc: The multicount value
2534 * @dir_in: True if direction is in.
2536 * Configure the maximum packet size for the given endpoint, updating
2537 * the hardware control registers to reflect this.
2539 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2540 unsigned int ep, unsigned int mps,
2541 unsigned int mc, unsigned int dir_in)
2543 struct dwc2_hsotg_ep *hs_ep;
2546 hs_ep = index_to_ep(hsotg, ep, dir_in);
2551 u32 mps_bytes = mps;
2553 /* EP0 is a special case */
2554 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2557 hs_ep->ep.maxpacket = mps_bytes;
2565 hs_ep->ep.maxpacket = mps;
2569 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2570 reg &= ~DXEPCTL_MPS_MASK;
2572 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2574 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2575 reg &= ~DXEPCTL_MPS_MASK;
2577 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2583 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2587 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2588 * @hsotg: The driver state
2589 * @idx: The index for the endpoint (0..15)
2591 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2593 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2596 /* wait until the fifo is flushed */
2597 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2598 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2603 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2604 * @hsotg: The driver state
2605 * @hs_ep: The driver endpoint to check.
2607 * Check to see if there is a request that has data to send, and if so
2608 * make an attempt to write data into the FIFO.
2610 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2611 struct dwc2_hsotg_ep *hs_ep)
2613 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2615 if (!hs_ep->dir_in || !hs_req) {
2617 * if request is not enqueued, we disable interrupts
2618 * for endpoints, excepting ep0
2620 if (hs_ep->index != 0)
2621 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2626 if (hs_req->req.actual < hs_req->req.length) {
2627 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2629 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2636 * dwc2_hsotg_complete_in - complete IN transfer
2637 * @hsotg: The device state.
2638 * @hs_ep: The endpoint that has just completed.
2640 * An IN transfer has been completed, update the transfer's state and then
2641 * call the relevant completion routines.
2643 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2644 struct dwc2_hsotg_ep *hs_ep)
2646 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2647 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2648 int size_left, size_done;
2651 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2655 /* Finish ZLP handling for IN EP0 transactions */
2656 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2657 dev_dbg(hsotg->dev, "zlp packet sent\n");
2660 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2661 * changed to IN. Change back to complete OUT transfer request
2665 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2666 if (hsotg->test_mode) {
2669 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2671 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2673 dwc2_hsotg_stall_ep0(hsotg);
2677 dwc2_hsotg_enqueue_setup(hsotg);
2682 * Calculate the size of the transfer by checking how much is left
2683 * in the endpoint size register and then working it out from
2684 * the amount we loaded for the transfer.
2686 * We do this even for DMA, as the transfer may have incremented
2687 * past the end of the buffer (DMA transfers are always 32bit
2690 if (using_desc_dma(hsotg)) {
2691 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2693 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2696 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2699 size_done = hs_ep->size_loaded - size_left;
2700 size_done += hs_ep->last_load;
2702 if (hs_req->req.actual != size_done)
2703 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2704 __func__, hs_req->req.actual, size_done);
2706 hs_req->req.actual = size_done;
2707 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2708 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2710 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2711 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2712 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2716 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2717 if (hs_ep->send_zlp) {
2718 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2719 hs_ep->send_zlp = 0;
2720 /* transfer will be completed on next complete interrupt */
2724 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2725 /* Move to STATUS OUT */
2726 dwc2_hsotg_ep0_zlp(hsotg, false);
2730 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2734 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2735 * @hsotg: The device state.
2736 * @idx: Index of ep.
2737 * @dir_in: Endpoint direction 1-in 0-out.
2739 * Reads for endpoint with given index and direction, by masking
2740 * epint_reg with coresponding mask.
2742 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2743 unsigned int idx, int dir_in)
2745 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2746 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2751 mask = dwc2_readl(hsotg, epmsk_reg);
2752 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2753 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2754 mask |= DXEPINT_SETUP_RCVD;
2756 ints = dwc2_readl(hsotg, epint_reg);
2762 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2763 * @hs_ep: The endpoint on which interrupt is asserted.
2765 * This interrupt indicates that the endpoint has been disabled per the
2766 * application's request.
2768 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2769 * in case of ISOC completes current request.
2771 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2772 * request starts it.
2774 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2776 struct dwc2_hsotg *hsotg = hs_ep->parent;
2777 struct dwc2_hsotg_req *hs_req;
2778 unsigned char idx = hs_ep->index;
2779 int dir_in = hs_ep->dir_in;
2780 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2781 int dctl = dwc2_readl(hsotg, DCTL);
2783 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2786 int epctl = dwc2_readl(hsotg, epctl_reg);
2788 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2790 if (hs_ep->isochronous) {
2791 dwc2_hsotg_complete_in(hsotg, hs_ep);
2795 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2796 int dctl = dwc2_readl(hsotg, DCTL);
2798 dctl |= DCTL_CGNPINNAK;
2799 dwc2_writel(hsotg, dctl, DCTL);
2804 if (dctl & DCTL_GOUTNAKSTS) {
2805 dctl |= DCTL_CGOUTNAK;
2806 dwc2_writel(hsotg, dctl, DCTL);
2809 if (!hs_ep->isochronous)
2812 if (list_empty(&hs_ep->queue)) {
2813 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2819 hs_req = get_ep_head(hs_ep);
2821 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2823 dwc2_gadget_incr_frame_num(hs_ep);
2824 /* Update current frame number value. */
2825 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2826 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2828 dwc2_gadget_start_next_request(hs_ep);
2832 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2833 * @ep: The endpoint on which interrupt is asserted.
2835 * This is starting point for ISOC-OUT transfer, synchronization done with
2836 * first out token received from host while corresponding EP is disabled.
2838 * Device does not know initial frame in which out token will come. For this
2839 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2840 * getting this interrupt SW starts calculation for next transfer frame.
2842 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2844 struct dwc2_hsotg *hsotg = ep->parent;
2845 int dir_in = ep->dir_in;
2848 if (dir_in || !ep->isochronous)
2851 if (using_desc_dma(hsotg)) {
2852 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2853 /* Start first ISO Out */
2854 ep->target_frame = hsotg->frame_number;
2855 dwc2_gadget_start_isoc_ddma(ep);
2860 if (ep->interval > 1 &&
2861 ep->target_frame == TARGET_FRAME_INITIAL) {
2864 ep->target_frame = hsotg->frame_number;
2865 dwc2_gadget_incr_frame_num(ep);
2867 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2868 if (ep->target_frame & 0x1)
2869 ctrl |= DXEPCTL_SETODDFR;
2871 ctrl |= DXEPCTL_SETEVENFR;
2873 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2876 dwc2_gadget_start_next_request(ep);
2877 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2878 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2879 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2883 * dwc2_gadget_handle_nak - handle NAK interrupt
2884 * @hs_ep: The endpoint on which interrupt is asserted.
2886 * This is starting point for ISOC-IN transfer, synchronization done with
2887 * first IN token received from host while corresponding EP is disabled.
2889 * Device does not know when first one token will arrive from host. On first
2890 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2891 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2892 * sent in response to that as there was no data in FIFO. SW is basing on this
2893 * interrupt to obtain frame in which token has come and then based on the
2894 * interval calculates next frame for transfer.
2896 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2898 struct dwc2_hsotg *hsotg = hs_ep->parent;
2899 int dir_in = hs_ep->dir_in;
2901 if (!dir_in || !hs_ep->isochronous)
2904 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2906 if (using_desc_dma(hsotg)) {
2907 hs_ep->target_frame = hsotg->frame_number;
2908 dwc2_gadget_incr_frame_num(hs_ep);
2910 /* In service interval mode target_frame must
2911 * be set to last (u)frame of the service interval.
2913 if (hsotg->params.service_interval) {
2914 /* Set target_frame to the first (u)frame of
2915 * the service interval
2917 hs_ep->target_frame &= ~hs_ep->interval + 1;
2919 /* Set target_frame to the last (u)frame of
2920 * the service interval
2922 dwc2_gadget_incr_frame_num(hs_ep);
2923 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2926 dwc2_gadget_start_isoc_ddma(hs_ep);
2930 hs_ep->target_frame = hsotg->frame_number;
2931 if (hs_ep->interval > 1) {
2932 u32 ctrl = dwc2_readl(hsotg,
2933 DIEPCTL(hs_ep->index));
2934 if (hs_ep->target_frame & 0x1)
2935 ctrl |= DXEPCTL_SETODDFR;
2937 ctrl |= DXEPCTL_SETEVENFR;
2939 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2942 dwc2_hsotg_complete_request(hsotg, hs_ep,
2943 get_ep_head(hs_ep), 0);
2946 if (!using_desc_dma(hsotg))
2947 dwc2_gadget_incr_frame_num(hs_ep);
2951 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2952 * @hsotg: The driver state
2953 * @idx: The index for the endpoint (0..15)
2954 * @dir_in: Set if this is an IN endpoint
2956 * Process and clear any interrupt pending for an individual endpoint
2958 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2961 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2962 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2963 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2964 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2968 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2969 ctrl = dwc2_readl(hsotg, epctl_reg);
2971 /* Clear endpoint interrupts */
2972 dwc2_writel(hsotg, ints, epint_reg);
2975 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2976 __func__, idx, dir_in ? "in" : "out");
2980 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2981 __func__, idx, dir_in ? "in" : "out", ints);
2983 /* Don't process XferCompl interrupt if it is a setup packet */
2984 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2985 ints &= ~DXEPINT_XFERCOMPL;
2988 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2989 * stage and xfercomplete was generated without SETUP phase done
2990 * interrupt. SW should parse received setup packet only after host's
2991 * exit from setup phase of control transfer.
2993 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2994 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2995 ints &= ~DXEPINT_XFERCOMPL;
2997 if (ints & DXEPINT_XFERCOMPL) {
2999 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3000 __func__, dwc2_readl(hsotg, epctl_reg),
3001 dwc2_readl(hsotg, epsiz_reg));
3003 /* In DDMA handle isochronous requests separately */
3004 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3005 /* XferCompl set along with BNA */
3006 if (!(ints & DXEPINT_BNAINTR))
3007 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3008 } else if (dir_in) {
3010 * We get OutDone from the FIFO, so we only
3011 * need to look at completing IN requests here
3012 * if operating slave mode
3014 if (hs_ep->isochronous && hs_ep->interval > 1)
3015 dwc2_gadget_incr_frame_num(hs_ep);
3017 dwc2_hsotg_complete_in(hsotg, hs_ep);
3018 if (ints & DXEPINT_NAKINTRPT)
3019 ints &= ~DXEPINT_NAKINTRPT;
3021 if (idx == 0 && !hs_ep->req)
3022 dwc2_hsotg_enqueue_setup(hsotg);
3023 } else if (using_dma(hsotg)) {
3025 * We're using DMA, we need to fire an OutDone here
3026 * as we ignore the RXFIFO.
3028 if (hs_ep->isochronous && hs_ep->interval > 1)
3029 dwc2_gadget_incr_frame_num(hs_ep);
3031 dwc2_hsotg_handle_outdone(hsotg, idx);
3035 if (ints & DXEPINT_EPDISBLD)
3036 dwc2_gadget_handle_ep_disabled(hs_ep);
3038 if (ints & DXEPINT_OUTTKNEPDIS)
3039 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3041 if (ints & DXEPINT_NAKINTRPT)
3042 dwc2_gadget_handle_nak(hs_ep);
3044 if (ints & DXEPINT_AHBERR)
3045 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3047 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3048 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3050 if (using_dma(hsotg) && idx == 0) {
3052 * this is the notification we've received a
3053 * setup packet. In non-DMA mode we'd get this
3054 * from the RXFIFO, instead we need to process
3061 dwc2_hsotg_handle_outdone(hsotg, 0);
3065 if (ints & DXEPINT_STSPHSERCVD) {
3066 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3068 /* Safety check EP0 state when STSPHSERCVD asserted */
3069 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3070 /* Move to STATUS IN for DDMA */
3071 if (using_desc_dma(hsotg)) {
3072 if (!hsotg->delayed_status)
3073 dwc2_hsotg_ep0_zlp(hsotg, true);
3075 /* In case of 3 stage Control Write with delayed
3076 * status, when Status IN transfer started
3077 * before STSPHSERCVD asserted, NAKSTS bit not
3078 * cleared by CNAK in dwc2_hsotg_start_req()
3079 * function. Clear now NAKSTS to allow complete
3082 dwc2_set_bit(hsotg, DIEPCTL(0),
3089 if (ints & DXEPINT_BACK2BACKSETUP)
3090 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3092 if (ints & DXEPINT_BNAINTR) {
3093 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3094 if (hs_ep->isochronous)
3095 dwc2_gadget_handle_isoc_bna(hs_ep);
3098 if (dir_in && !hs_ep->isochronous) {
3099 /* not sure if this is important, but we'll clear it anyway */
3100 if (ints & DXEPINT_INTKNTXFEMP) {
3101 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3105 /* this probably means something bad is happening */
3106 if (ints & DXEPINT_INTKNEPMIS) {
3107 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3111 /* FIFO has space or is empty (see GAHBCFG) */
3112 if (hsotg->dedicated_fifos &&
3113 ints & DXEPINT_TXFEMP) {
3114 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3116 if (!using_dma(hsotg))
3117 dwc2_hsotg_trytx(hsotg, hs_ep);
3123 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3124 * @hsotg: The device state.
3126 * Handle updating the device settings after the enumeration phase has
3129 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3131 u32 dsts = dwc2_readl(hsotg, DSTS);
3132 int ep0_mps = 0, ep_mps = 8;
3135 * This should signal the finish of the enumeration phase
3136 * of the USB handshaking, so we should now know what rate
3140 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3143 * note, since we're limited by the size of transfer on EP0, and
3144 * it seems IN transfers must be a even number of packets we do
3145 * not advertise a 64byte MPS on EP0.
3148 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3149 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3150 case DSTS_ENUMSPD_FS:
3151 case DSTS_ENUMSPD_FS48:
3152 hsotg->gadget.speed = USB_SPEED_FULL;
3153 ep0_mps = EP0_MPS_LIMIT;
3157 case DSTS_ENUMSPD_HS:
3158 hsotg->gadget.speed = USB_SPEED_HIGH;
3159 ep0_mps = EP0_MPS_LIMIT;
3163 case DSTS_ENUMSPD_LS:
3164 hsotg->gadget.speed = USB_SPEED_LOW;
3168 * note, we don't actually support LS in this driver at the
3169 * moment, and the documentation seems to imply that it isn't
3170 * supported by the PHYs on some of the devices.
3174 dev_info(hsotg->dev, "new device is %s\n",
3175 usb_speed_string(hsotg->gadget.speed));
3178 * we should now know the maximum packet size for an
3179 * endpoint, so set the endpoints to a default value.
3184 /* Initialize ep0 for both in and out directions */
3185 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3186 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3187 for (i = 1; i < hsotg->num_of_eps; i++) {
3188 if (hsotg->eps_in[i])
3189 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3191 if (hsotg->eps_out[i])
3192 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3197 /* ensure after enumeration our EP0 is active */
3199 dwc2_hsotg_enqueue_setup(hsotg);
3201 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3202 dwc2_readl(hsotg, DIEPCTL0),
3203 dwc2_readl(hsotg, DOEPCTL0));
3207 * kill_all_requests - remove all requests from the endpoint's queue
3208 * @hsotg: The device state.
3209 * @ep: The endpoint the requests may be on.
3210 * @result: The result code to use.
3212 * Go through the requests on the given endpoint and mark them
3213 * completed with the given result code.
3215 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3216 struct dwc2_hsotg_ep *ep,
3219 struct dwc2_hsotg_req *req, *treq;
3224 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3225 dwc2_hsotg_complete_request(hsotg, ep, req,
3228 if (!hsotg->dedicated_fifos)
3230 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3231 if (size < ep->fifo_size)
3232 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3236 * dwc2_hsotg_disconnect - disconnect service
3237 * @hsotg: The device state.
3239 * The device has been disconnected. Remove all current
3240 * transactions and signal the gadget driver that this
3243 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3247 if (!hsotg->connected)
3250 hsotg->connected = 0;
3251 hsotg->test_mode = 0;
3253 /* all endpoints should be shutdown */
3254 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3255 if (hsotg->eps_in[ep])
3256 kill_all_requests(hsotg, hsotg->eps_in[ep],
3258 if (hsotg->eps_out[ep])
3259 kill_all_requests(hsotg, hsotg->eps_out[ep],
3263 call_gadget(hsotg, disconnect);
3264 hsotg->lx_state = DWC2_L3;
3266 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3270 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3271 * @hsotg: The device state:
3272 * @periodic: True if this is a periodic FIFO interrupt
3274 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3276 struct dwc2_hsotg_ep *ep;
3279 /* look through for any more data to transmit */
3280 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3281 ep = index_to_ep(hsotg, epno, 1);
3289 if ((periodic && !ep->periodic) ||
3290 (!periodic && ep->periodic))
3293 ret = dwc2_hsotg_trytx(hsotg, ep);
3299 /* IRQ flags which will trigger a retry around the IRQ loop */
3300 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3304 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3306 * dwc2_hsotg_core_init - issue softreset to the core
3307 * @hsotg: The device state
3308 * @is_usb_reset: Usb resetting flag
3310 * Issue a soft reset to the core, and await the core finishing it.
3312 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3321 /* Kill any ep0 requests as controller will be reinitialized */
3322 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3324 if (!is_usb_reset) {
3325 if (dwc2_core_reset(hsotg, true))
3328 /* all endpoints should be shutdown */
3329 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3330 if (hsotg->eps_in[ep])
3331 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3332 if (hsotg->eps_out[ep])
3333 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3338 * we must now enable ep0 ready for host detection and then
3339 * set configuration.
3342 /* keep other bits untouched (so e.g. forced modes are not lost) */
3343 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3344 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3345 usbcfg |= GUSBCFG_TOUTCAL(7);
3347 /* remove the HNP/SRP and set the PHY */
3348 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3349 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3351 dwc2_phy_init(hsotg, true);
3353 dwc2_hsotg_init_fifo(hsotg);
3356 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3358 dcfg |= DCFG_EPMISCNT(1);
3360 switch (hsotg->params.speed) {
3361 case DWC2_SPEED_PARAM_LOW:
3362 dcfg |= DCFG_DEVSPD_LS;
3364 case DWC2_SPEED_PARAM_FULL:
3365 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3366 dcfg |= DCFG_DEVSPD_FS48;
3368 dcfg |= DCFG_DEVSPD_FS;
3371 dcfg |= DCFG_DEVSPD_HS;
3374 if (hsotg->params.ipg_isoc_en)
3375 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3377 dwc2_writel(hsotg, dcfg, DCFG);
3379 /* Clear any pending OTG interrupts */
3380 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3382 /* Clear any pending interrupts */
3383 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3384 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3385 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3386 GINTSTS_USBRST | GINTSTS_RESETDET |
3387 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3388 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3389 GINTSTS_LPMTRANRCVD;
3391 if (!using_desc_dma(hsotg))
3392 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3394 if (!hsotg->params.external_id_pin_ctl)
3395 intmsk |= GINTSTS_CONIDSTSCHNG;
3397 dwc2_writel(hsotg, intmsk, GINTMSK);
3399 if (using_dma(hsotg)) {
3400 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3401 hsotg->params.ahbcfg,
3404 /* Set DDMA mode support in the core if needed */
3405 if (using_desc_dma(hsotg))
3406 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3409 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3410 (GAHBCFG_NP_TXF_EMP_LVL |
3411 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3412 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3416 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3417 * when we have no data to transfer. Otherwise we get being flooded by
3421 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3422 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3423 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3424 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3428 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3429 * DMA mode we may need this and StsPhseRcvd.
3431 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3432 DOEPMSK_STSPHSERCVDMSK) : 0) |
3433 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3437 /* Enable BNA interrupt for DDMA */
3438 if (using_desc_dma(hsotg)) {
3439 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3440 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3443 /* Enable Service Interval mode if supported */
3444 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3445 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3447 dwc2_writel(hsotg, 0, DAINTMSK);
3449 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3450 dwc2_readl(hsotg, DIEPCTL0),
3451 dwc2_readl(hsotg, DOEPCTL0));
3453 /* enable in and out endpoint interrupts */
3454 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3457 * Enable the RXFIFO when in slave mode, as this is how we collect
3458 * the data. In DMA mode, we get events from the FIFO but also
3459 * things we cannot process, so do not use it.
3461 if (!using_dma(hsotg))
3462 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3464 /* Enable interrupts for EP0 in and out */
3465 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3466 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3468 if (!is_usb_reset) {
3469 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3470 udelay(10); /* see openiboot */
3471 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3474 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3477 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3478 * writing to the EPCTL register..
3481 /* set to read 1 8byte packet */
3482 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3483 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3485 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3486 DXEPCTL_CNAK | DXEPCTL_EPENA |
3490 /* enable, but don't activate EP0in */
3491 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3492 DXEPCTL_USBACTEP, DIEPCTL0);
3494 /* clear global NAKs */
3495 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3497 val |= DCTL_SFTDISCON;
3498 dwc2_set_bit(hsotg, DCTL, val);
3500 /* configure the core to support LPM */
3501 dwc2_gadget_init_lpm(hsotg);
3503 /* program GREFCLK register if needed */
3504 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3505 dwc2_gadget_program_ref_clk(hsotg);
3507 /* must be at-least 3ms to allow bus to see disconnect */
3510 hsotg->lx_state = DWC2_L0;
3512 dwc2_hsotg_enqueue_setup(hsotg);
3514 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3515 dwc2_readl(hsotg, DIEPCTL0),
3516 dwc2_readl(hsotg, DOEPCTL0));
3519 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3521 /* set the soft-disconnect bit */
3522 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3525 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3527 /* remove the soft-disconnect and let's go */
3528 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3532 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3533 * @hsotg: The device state:
3535 * This interrupt indicates one of the following conditions occurred while
3536 * transmitting an ISOC transaction.
3537 * - Corrupted IN Token for ISOC EP.
3538 * - Packet not complete in FIFO.
3540 * The following actions will be taken:
3541 * - Determine the EP
3542 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3544 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3546 struct dwc2_hsotg_ep *hs_ep;
3551 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3553 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3555 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3556 hs_ep = hsotg->eps_in[idx];
3557 /* Proceed only unmasked ISOC EPs */
3558 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3561 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3562 if ((epctrl & DXEPCTL_EPENA) &&
3563 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3564 epctrl |= DXEPCTL_SNAK;
3565 epctrl |= DXEPCTL_EPDIS;
3566 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3570 /* Clear interrupt */
3571 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3575 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3576 * @hsotg: The device state:
3578 * This interrupt indicates one of the following conditions occurred while
3579 * transmitting an ISOC transaction.
3580 * - Corrupted OUT Token for ISOC EP.
3581 * - Packet not complete in FIFO.
3583 * The following actions will be taken:
3584 * - Determine the EP
3585 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3587 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3593 struct dwc2_hsotg_ep *hs_ep;
3596 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3598 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3599 daintmsk >>= DAINT_OUTEP_SHIFT;
3601 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3602 hs_ep = hsotg->eps_out[idx];
3603 /* Proceed only unmasked ISOC EPs */
3604 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3607 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3608 if ((epctrl & DXEPCTL_EPENA) &&
3609 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3610 /* Unmask GOUTNAKEFF interrupt */
3611 gintmsk = dwc2_readl(hsotg, GINTMSK);
3612 gintmsk |= GINTSTS_GOUTNAKEFF;
3613 dwc2_writel(hsotg, gintmsk, GINTMSK);
3615 gintsts = dwc2_readl(hsotg, GINTSTS);
3616 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3617 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3623 /* Clear interrupt */
3624 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3628 * dwc2_hsotg_irq - handle device interrupt
3629 * @irq: The IRQ number triggered
3630 * @pw: The pw value when registered the handler.
3632 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3634 struct dwc2_hsotg *hsotg = pw;
3635 int retry_count = 8;
3639 if (!dwc2_is_device_mode(hsotg))
3642 spin_lock(&hsotg->lock);
3644 gintsts = dwc2_readl(hsotg, GINTSTS);
3645 gintmsk = dwc2_readl(hsotg, GINTMSK);
3647 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3648 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3652 if (gintsts & GINTSTS_RESETDET) {
3653 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3655 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3657 /* This event must be used only if controller is suspended */
3658 if (hsotg->lx_state == DWC2_L2) {
3659 dwc2_exit_partial_power_down(hsotg, true);
3660 hsotg->lx_state = DWC2_L0;
3664 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3665 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3666 u32 connected = hsotg->connected;
3668 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3669 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3670 dwc2_readl(hsotg, GNPTXSTS));
3672 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3674 /* Report disconnection if it is not already done. */
3675 dwc2_hsotg_disconnect(hsotg);
3677 /* Reset device address to zero */
3678 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3680 if (usb_status & GOTGCTL_BSESVLD && connected)
3681 dwc2_hsotg_core_init_disconnected(hsotg, true);
3684 if (gintsts & GINTSTS_ENUMDONE) {
3685 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3687 dwc2_hsotg_irq_enumdone(hsotg);
3690 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3691 u32 daint = dwc2_readl(hsotg, DAINT);
3692 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3693 u32 daint_out, daint_in;
3697 daint_out = daint >> DAINT_OUTEP_SHIFT;
3698 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3700 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3702 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3703 ep++, daint_out >>= 1) {
3705 dwc2_hsotg_epint(hsotg, ep, 0);
3708 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3709 ep++, daint_in >>= 1) {
3711 dwc2_hsotg_epint(hsotg, ep, 1);
3715 /* check both FIFOs */
3717 if (gintsts & GINTSTS_NPTXFEMP) {
3718 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3721 * Disable the interrupt to stop it happening again
3722 * unless one of these endpoint routines decides that
3723 * it needs re-enabling
3726 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3727 dwc2_hsotg_irq_fifoempty(hsotg, false);
3730 if (gintsts & GINTSTS_PTXFEMP) {
3731 dev_dbg(hsotg->dev, "PTxFEmp\n");
3733 /* See note in GINTSTS_NPTxFEmp */
3735 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3736 dwc2_hsotg_irq_fifoempty(hsotg, true);
3739 if (gintsts & GINTSTS_RXFLVL) {
3741 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3742 * we need to retry dwc2_hsotg_handle_rx if this is still
3746 dwc2_hsotg_handle_rx(hsotg);
3749 if (gintsts & GINTSTS_ERLYSUSP) {
3750 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3751 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3755 * these next two seem to crop-up occasionally causing the core
3756 * to shutdown the USB transfer, so try clearing them and logging
3760 if (gintsts & GINTSTS_GOUTNAKEFF) {
3765 struct dwc2_hsotg_ep *hs_ep;
3767 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3768 daintmsk >>= DAINT_OUTEP_SHIFT;
3769 /* Mask this interrupt */
3770 gintmsk = dwc2_readl(hsotg, GINTMSK);
3771 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3772 dwc2_writel(hsotg, gintmsk, GINTMSK);
3774 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3775 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3776 hs_ep = hsotg->eps_out[idx];
3777 /* Proceed only unmasked ISOC EPs */
3778 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3781 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3783 if (epctrl & DXEPCTL_EPENA) {
3784 epctrl |= DXEPCTL_SNAK;
3785 epctrl |= DXEPCTL_EPDIS;
3786 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3790 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3793 if (gintsts & GINTSTS_GINNAKEFF) {
3794 dev_info(hsotg->dev, "GINNakEff triggered\n");
3796 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3798 dwc2_hsotg_dump(hsotg);
3801 if (gintsts & GINTSTS_INCOMPL_SOIN)
3802 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3804 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3805 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3808 * if we've had fifo events, we should try and go around the
3809 * loop again to see if there's any point in returning yet.
3812 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3815 /* Check WKUP_ALERT interrupt*/
3816 if (hsotg->params.service_interval)
3817 dwc2_gadget_wkup_alert_handler(hsotg);
3819 spin_unlock(&hsotg->lock);
3824 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3825 struct dwc2_hsotg_ep *hs_ep)
3830 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3831 DOEPCTL(hs_ep->index);
3832 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3833 DOEPINT(hs_ep->index);
3835 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3838 if (hs_ep->dir_in) {
3839 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3840 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3841 /* Wait for Nak effect */
3842 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3843 DXEPINT_INEPNAKEFF, 100))
3844 dev_warn(hsotg->dev,
3845 "%s: timeout DIEPINT.NAKEFF\n",
3848 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3849 /* Wait for Nak effect */
3850 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3851 GINTSTS_GINNAKEFF, 100))
3852 dev_warn(hsotg->dev,
3853 "%s: timeout GINTSTS.GINNAKEFF\n",
3857 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3858 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3860 /* Wait for global nak to take effect */
3861 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3862 GINTSTS_GOUTNAKEFF, 100))
3863 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3868 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3870 /* Wait for ep to be disabled */
3871 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3872 dev_warn(hsotg->dev,
3873 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3875 /* Clear EPDISBLD interrupt */
3876 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3878 if (hs_ep->dir_in) {
3879 unsigned short fifo_index;
3881 if (hsotg->dedicated_fifos || hs_ep->periodic)
3882 fifo_index = hs_ep->fifo_index;
3887 dwc2_flush_tx_fifo(hsotg, fifo_index);
3889 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3890 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3891 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3894 /* Remove global NAKs */
3895 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3900 * dwc2_hsotg_ep_enable - enable the given endpoint
3901 * @ep: The USB endpint to configure
3902 * @desc: The USB endpoint descriptor to configure with.
3904 * This is called from the USB gadget code's usb_ep_enable().
3906 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3907 const struct usb_endpoint_descriptor *desc)
3909 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3910 struct dwc2_hsotg *hsotg = hs_ep->parent;
3911 unsigned long flags;
3912 unsigned int index = hs_ep->index;
3918 unsigned int dir_in;
3919 unsigned int i, val, size;
3921 unsigned char ep_type;
3925 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3926 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3927 desc->wMaxPacketSize, desc->bInterval);
3929 /* not to be called for EP0 */
3931 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3935 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3936 if (dir_in != hs_ep->dir_in) {
3937 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3941 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3942 mps = usb_endpoint_maxp(desc);
3943 mc = usb_endpoint_maxp_mult(desc);
3945 /* ISOC IN in DDMA supported bInterval up to 10 */
3946 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3947 dir_in && desc->bInterval > 10) {
3949 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3953 /* High bandwidth ISOC OUT in DDMA not supported */
3954 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3955 !dir_in && mc > 1) {
3957 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3961 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3963 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3964 epctrl = dwc2_readl(hsotg, epctrl_reg);
3966 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3967 __func__, epctrl, epctrl_reg);
3969 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
3970 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
3972 desc_num = MAX_DMA_DESC_NUM_GENERIC;
3974 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3975 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3976 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3977 desc_num * sizeof(struct dwc2_dma_desc),
3978 &hs_ep->desc_list_dma, GFP_ATOMIC);
3979 if (!hs_ep->desc_list) {
3985 spin_lock_irqsave(&hsotg->lock, flags);
3987 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3988 epctrl |= DXEPCTL_MPS(mps);
3991 * mark the endpoint as active, otherwise the core may ignore
3992 * transactions entirely for this endpoint
3994 epctrl |= DXEPCTL_USBACTEP;
3996 /* update the endpoint state */
3997 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3999 /* default, set to non-periodic */
4000 hs_ep->isochronous = 0;
4001 hs_ep->periodic = 0;
4003 hs_ep->interval = desc->bInterval;
4006 case USB_ENDPOINT_XFER_ISOC:
4007 epctrl |= DXEPCTL_EPTYPE_ISO;
4008 epctrl |= DXEPCTL_SETEVENFR;
4009 hs_ep->isochronous = 1;
4010 hs_ep->interval = 1 << (desc->bInterval - 1);
4011 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4012 hs_ep->next_desc = 0;
4013 hs_ep->compl_desc = 0;
4015 hs_ep->periodic = 1;
4016 mask = dwc2_readl(hsotg, DIEPMSK);
4017 mask |= DIEPMSK_NAKMSK;
4018 dwc2_writel(hsotg, mask, DIEPMSK);
4020 mask = dwc2_readl(hsotg, DOEPMSK);
4021 mask |= DOEPMSK_OUTTKNEPDISMSK;
4022 dwc2_writel(hsotg, mask, DOEPMSK);
4026 case USB_ENDPOINT_XFER_BULK:
4027 epctrl |= DXEPCTL_EPTYPE_BULK;
4030 case USB_ENDPOINT_XFER_INT:
4032 hs_ep->periodic = 1;
4034 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4035 hs_ep->interval = 1 << (desc->bInterval - 1);
4037 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4040 case USB_ENDPOINT_XFER_CONTROL:
4041 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4046 * if the hardware has dedicated fifos, we must give each IN EP
4047 * a unique tx-fifo even if it is non-periodic.
4049 if (dir_in && hsotg->dedicated_fifos) {
4051 u32 fifo_size = UINT_MAX;
4053 size = hs_ep->ep.maxpacket * hs_ep->mc;
4054 for (i = 1; i < hsotg->num_of_eps; ++i) {
4055 if (hsotg->fifo_map & (1 << i))
4057 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4058 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4061 /* Search for smallest acceptable fifo */
4062 if (val < fifo_size) {
4069 "%s: No suitable fifo found\n", __func__);
4073 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4074 hsotg->fifo_map |= 1 << fifo_index;
4075 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4076 hs_ep->fifo_index = fifo_index;
4077 hs_ep->fifo_size = fifo_size;
4080 /* for non control endpoints, set PID to D0 */
4081 if (index && !hs_ep->isochronous)
4082 epctrl |= DXEPCTL_SETD0PID;
4084 /* WA for Full speed ISOC IN in DDMA mode.
4085 * By Clear NAK status of EP, core will send ZLP
4086 * to IN token and assert NAK interrupt relying
4087 * on TxFIFO status only
4090 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4091 hs_ep->isochronous && dir_in) {
4092 /* The WA applies only to core versions from 2.72a
4093 * to 4.00a (including both). Also for FS_IOT_1.00a
4096 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4098 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4099 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4100 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4101 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4102 epctrl |= DXEPCTL_CNAK;
4105 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4108 dwc2_writel(hsotg, epctrl, epctrl_reg);
4109 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4110 __func__, dwc2_readl(hsotg, epctrl_reg));
4112 /* enable the endpoint interrupt */
4113 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4116 spin_unlock_irqrestore(&hsotg->lock, flags);
4119 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4120 dmam_free_coherent(hsotg->dev, desc_num *
4121 sizeof(struct dwc2_dma_desc),
4122 hs_ep->desc_list, hs_ep->desc_list_dma);
4123 hs_ep->desc_list = NULL;
4130 * dwc2_hsotg_ep_disable - disable given endpoint
4131 * @ep: The endpoint to disable.
4133 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4135 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4136 struct dwc2_hsotg *hsotg = hs_ep->parent;
4137 int dir_in = hs_ep->dir_in;
4138 int index = hs_ep->index;
4142 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4144 if (ep == &hsotg->eps_out[0]->ep) {
4145 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4149 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4150 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4154 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4156 ctrl = dwc2_readl(hsotg, epctrl_reg);
4158 if (ctrl & DXEPCTL_EPENA)
4159 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4161 ctrl &= ~DXEPCTL_EPENA;
4162 ctrl &= ~DXEPCTL_USBACTEP;
4163 ctrl |= DXEPCTL_SNAK;
4165 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4166 dwc2_writel(hsotg, ctrl, epctrl_reg);
4168 /* disable endpoint interrupts */
4169 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4171 /* terminate all requests with shutdown */
4172 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4174 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4175 hs_ep->fifo_index = 0;
4176 hs_ep->fifo_size = 0;
4181 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4183 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4184 struct dwc2_hsotg *hsotg = hs_ep->parent;
4185 unsigned long flags;
4188 spin_lock_irqsave(&hsotg->lock, flags);
4189 ret = dwc2_hsotg_ep_disable(ep);
4190 spin_unlock_irqrestore(&hsotg->lock, flags);
4195 * on_list - check request is on the given endpoint
4196 * @ep: The endpoint to check.
4197 * @test: The request to test if it is on the endpoint.
4199 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4201 struct dwc2_hsotg_req *req, *treq;
4203 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4212 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4213 * @ep: The endpoint to dequeue.
4214 * @req: The request to be removed from a queue.
4216 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4218 struct dwc2_hsotg_req *hs_req = our_req(req);
4219 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4220 struct dwc2_hsotg *hs = hs_ep->parent;
4221 unsigned long flags;
4223 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4225 spin_lock_irqsave(&hs->lock, flags);
4227 if (!on_list(hs_ep, hs_req)) {
4228 spin_unlock_irqrestore(&hs->lock, flags);
4232 /* Dequeue already started request */
4233 if (req == &hs_ep->req->req)
4234 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4236 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4237 spin_unlock_irqrestore(&hs->lock, flags);
4243 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4244 * @ep: The endpoint to set halt.
4245 * @value: Set or unset the halt.
4246 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4247 * the endpoint is busy processing requests.
4249 * We need to stall the endpoint immediately if request comes from set_feature
4250 * protocol command handler.
4252 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4254 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4255 struct dwc2_hsotg *hs = hs_ep->parent;
4256 int index = hs_ep->index;
4261 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4265 dwc2_hsotg_stall_ep0(hs);
4268 "%s: can't clear halt on ep0\n", __func__);
4272 if (hs_ep->isochronous) {
4273 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4277 if (!now && value && !list_empty(&hs_ep->queue)) {
4278 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4283 if (hs_ep->dir_in) {
4284 epreg = DIEPCTL(index);
4285 epctl = dwc2_readl(hs, epreg);
4288 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4289 if (epctl & DXEPCTL_EPENA)
4290 epctl |= DXEPCTL_EPDIS;
4292 epctl &= ~DXEPCTL_STALL;
4293 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4294 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4295 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4296 epctl |= DXEPCTL_SETD0PID;
4298 dwc2_writel(hs, epctl, epreg);
4300 epreg = DOEPCTL(index);
4301 epctl = dwc2_readl(hs, epreg);
4304 epctl |= DXEPCTL_STALL;
4306 epctl &= ~DXEPCTL_STALL;
4307 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4308 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4309 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4310 epctl |= DXEPCTL_SETD0PID;
4312 dwc2_writel(hs, epctl, epreg);
4315 hs_ep->halted = value;
4321 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4322 * @ep: The endpoint to set halt.
4323 * @value: Set or unset the halt.
4325 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4327 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4328 struct dwc2_hsotg *hs = hs_ep->parent;
4329 unsigned long flags = 0;
4332 spin_lock_irqsave(&hs->lock, flags);
4333 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4334 spin_unlock_irqrestore(&hs->lock, flags);
4339 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4340 .enable = dwc2_hsotg_ep_enable,
4341 .disable = dwc2_hsotg_ep_disable_lock,
4342 .alloc_request = dwc2_hsotg_ep_alloc_request,
4343 .free_request = dwc2_hsotg_ep_free_request,
4344 .queue = dwc2_hsotg_ep_queue_lock,
4345 .dequeue = dwc2_hsotg_ep_dequeue,
4346 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4347 /* note, don't believe we have any call for the fifo routines */
4351 * dwc2_hsotg_init - initialize the usb core
4352 * @hsotg: The driver state
4354 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4356 /* unmask subset of endpoint interrupts */
4358 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4359 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4362 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4363 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4366 dwc2_writel(hsotg, 0, DAINTMSK);
4368 /* Be in disconnected state until gadget is registered */
4369 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4373 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4374 dwc2_readl(hsotg, GRXFSIZ),
4375 dwc2_readl(hsotg, GNPTXFSIZ));
4377 dwc2_hsotg_init_fifo(hsotg);
4379 if (using_dma(hsotg))
4380 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4384 * dwc2_hsotg_udc_start - prepare the udc for work
4385 * @gadget: The usb gadget state
4386 * @driver: The usb gadget driver
4388 * Perform initialization to prepare udc device and driver
4391 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4392 struct usb_gadget_driver *driver)
4394 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4395 unsigned long flags;
4399 pr_err("%s: called with no device\n", __func__);
4404 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4408 if (driver->max_speed < USB_SPEED_FULL)
4409 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4411 if (!driver->setup) {
4412 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4416 WARN_ON(hsotg->driver);
4418 driver->driver.bus = NULL;
4419 hsotg->driver = driver;
4420 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4421 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4423 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4424 ret = dwc2_lowlevel_hw_enable(hsotg);
4429 if (!IS_ERR_OR_NULL(hsotg->uphy))
4430 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4432 spin_lock_irqsave(&hsotg->lock, flags);
4433 if (dwc2_hw_is_device(hsotg)) {
4434 dwc2_hsotg_init(hsotg);
4435 dwc2_hsotg_core_init_disconnected(hsotg, false);
4439 spin_unlock_irqrestore(&hsotg->lock, flags);
4441 gadget->sg_supported = using_desc_dma(hsotg);
4442 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4447 hsotg->driver = NULL;
4452 * dwc2_hsotg_udc_stop - stop the udc
4453 * @gadget: The usb gadget state
4455 * Stop udc hw block and stay tunned for future transmissions
4457 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4459 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4460 unsigned long flags = 0;
4466 /* all endpoints should be shutdown */
4467 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4468 if (hsotg->eps_in[ep])
4469 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4470 if (hsotg->eps_out[ep])
4471 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4474 spin_lock_irqsave(&hsotg->lock, flags);
4476 hsotg->driver = NULL;
4477 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4480 spin_unlock_irqrestore(&hsotg->lock, flags);
4482 if (!IS_ERR_OR_NULL(hsotg->uphy))
4483 otg_set_peripheral(hsotg->uphy->otg, NULL);
4485 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4486 dwc2_lowlevel_hw_disable(hsotg);
4492 * dwc2_hsotg_gadget_getframe - read the frame number
4493 * @gadget: The usb gadget state
4495 * Read the {micro} frame number
4497 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4499 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4503 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4504 * @gadget: The usb gadget state
4505 * @is_on: Current state of the USB PHY
4507 * Connect/Disconnect the USB PHY pullup
4509 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4511 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4512 unsigned long flags = 0;
4514 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4517 /* Don't modify pullup state while in host mode */
4518 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4519 hsotg->enabled = is_on;
4523 spin_lock_irqsave(&hsotg->lock, flags);
4526 dwc2_hsotg_core_init_disconnected(hsotg, false);
4527 /* Enable ACG feature in device mode,if supported */
4528 dwc2_enable_acg(hsotg);
4529 dwc2_hsotg_core_connect(hsotg);
4531 dwc2_hsotg_core_disconnect(hsotg);
4532 dwc2_hsotg_disconnect(hsotg);
4536 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4537 spin_unlock_irqrestore(&hsotg->lock, flags);
4542 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4544 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4545 unsigned long flags;
4547 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4548 spin_lock_irqsave(&hsotg->lock, flags);
4551 * If controller is hibernated, it must exit from power_down
4552 * before being initialized / de-initialized
4554 if (hsotg->lx_state == DWC2_L2)
4555 dwc2_exit_partial_power_down(hsotg, false);
4558 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4560 dwc2_hsotg_core_init_disconnected(hsotg, false);
4561 if (hsotg->enabled) {
4562 /* Enable ACG feature in device mode,if supported */
4563 dwc2_enable_acg(hsotg);
4564 dwc2_hsotg_core_connect(hsotg);
4567 dwc2_hsotg_core_disconnect(hsotg);
4568 dwc2_hsotg_disconnect(hsotg);
4571 spin_unlock_irqrestore(&hsotg->lock, flags);
4576 * dwc2_hsotg_vbus_draw - report bMaxPower field
4577 * @gadget: The usb gadget state
4578 * @mA: Amount of current
4580 * Report how much power the device may consume to the phy.
4582 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4584 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4586 if (IS_ERR_OR_NULL(hsotg->uphy))
4588 return usb_phy_set_power(hsotg->uphy, mA);
4591 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4592 .get_frame = dwc2_hsotg_gadget_getframe,
4593 .udc_start = dwc2_hsotg_udc_start,
4594 .udc_stop = dwc2_hsotg_udc_stop,
4595 .pullup = dwc2_hsotg_pullup,
4596 .vbus_session = dwc2_hsotg_vbus_session,
4597 .vbus_draw = dwc2_hsotg_vbus_draw,
4601 * dwc2_hsotg_initep - initialise a single endpoint
4602 * @hsotg: The device state.
4603 * @hs_ep: The endpoint to be initialised.
4604 * @epnum: The endpoint number
4605 * @dir_in: True if direction is in.
4607 * Initialise the given endpoint (as part of the probe and device state
4608 * creation) to give to the gadget driver. Setup the endpoint name, any
4609 * direction information and other state that may be required.
4611 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4612 struct dwc2_hsotg_ep *hs_ep,
4625 hs_ep->dir_in = dir_in;
4626 hs_ep->index = epnum;
4628 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4630 INIT_LIST_HEAD(&hs_ep->queue);
4631 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4633 /* add to the list of endpoints known by the gadget driver */
4635 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4637 hs_ep->parent = hsotg;
4638 hs_ep->ep.name = hs_ep->name;
4640 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4641 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4643 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4644 epnum ? 1024 : EP0_MPS_LIMIT);
4645 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4648 hs_ep->ep.caps.type_control = true;
4650 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4651 hs_ep->ep.caps.type_iso = true;
4652 hs_ep->ep.caps.type_bulk = true;
4654 hs_ep->ep.caps.type_int = true;
4658 hs_ep->ep.caps.dir_in = true;
4660 hs_ep->ep.caps.dir_out = true;
4663 * if we're using dma, we need to set the next-endpoint pointer
4664 * to be something valid.
4667 if (using_dma(hsotg)) {
4668 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4671 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4673 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4678 * dwc2_hsotg_hw_cfg - read HW configuration registers
4679 * @hsotg: Programming view of the DWC_otg controller
4681 * Read the USB core HW configuration registers
4683 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4689 /* check hardware configuration */
4691 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4694 hsotg->num_of_eps++;
4696 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4697 sizeof(struct dwc2_hsotg_ep),
4699 if (!hsotg->eps_in[0])
4701 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4702 hsotg->eps_out[0] = hsotg->eps_in[0];
4704 cfg = hsotg->hw_params.dev_ep_dirs;
4705 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4707 /* Direction in or both */
4708 if (!(ep_type & 2)) {
4709 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4710 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4711 if (!hsotg->eps_in[i])
4714 /* Direction out or both */
4715 if (!(ep_type & 1)) {
4716 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4717 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4718 if (!hsotg->eps_out[i])
4723 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4724 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4726 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4728 hsotg->dedicated_fifos ? "dedicated" : "shared",
4734 * dwc2_hsotg_dump - dump state of the udc
4735 * @hsotg: Programming view of the DWC_otg controller
4738 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4741 struct device *dev = hsotg->dev;
4745 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4746 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4747 dwc2_readl(hsotg, DIEPMSK));
4749 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4750 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4752 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4753 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4755 /* show periodic fifo settings */
4757 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4758 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4759 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4760 val >> FIFOSIZE_DEPTH_SHIFT,
4761 val & FIFOSIZE_STARTADDR_MASK);
4764 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4766 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4767 dwc2_readl(hsotg, DIEPCTL(idx)),
4768 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4769 dwc2_readl(hsotg, DIEPDMA(idx)));
4771 val = dwc2_readl(hsotg, DOEPCTL(idx));
4773 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4774 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4775 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4776 dwc2_readl(hsotg, DOEPDMA(idx)));
4779 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4780 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4785 * dwc2_gadget_init - init function for gadget
4786 * @hsotg: Programming view of the DWC_otg controller
4789 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4791 struct device *dev = hsotg->dev;
4795 /* Dump fifo information */
4796 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4797 hsotg->params.g_np_tx_fifo_size);
4798 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4800 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4801 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4802 hsotg->gadget.name = dev_name(dev);
4803 hsotg->remote_wakeup_allowed = 0;
4805 if (hsotg->params.lpm)
4806 hsotg->gadget.lpm_capable = true;
4808 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4809 hsotg->gadget.is_otg = 1;
4810 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4811 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4813 ret = dwc2_hsotg_hw_cfg(hsotg);
4815 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4819 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4820 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4821 if (!hsotg->ctrl_buff)
4824 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4825 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4826 if (!hsotg->ep0_buff)
4829 if (using_desc_dma(hsotg)) {
4830 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4835 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4836 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4838 dev_err(dev, "cannot claim IRQ for gadget\n");
4842 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4844 if (hsotg->num_of_eps == 0) {
4845 dev_err(dev, "wrong number of EPs (zero)\n");
4849 /* setup endpoint information */
4851 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4852 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4854 /* allocate EP0 request */
4856 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4858 if (!hsotg->ctrl_req) {
4859 dev_err(dev, "failed to allocate ctrl req\n");
4863 /* initialise the endpoints now the core has been initialised */
4864 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4865 if (hsotg->eps_in[epnum])
4866 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4868 if (hsotg->eps_out[epnum])
4869 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4873 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4875 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep,
4879 dwc2_hsotg_dump(hsotg);
4885 * dwc2_hsotg_remove - remove function for hsotg driver
4886 * @hsotg: Programming view of the DWC_otg controller
4889 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4891 usb_del_gadget_udc(&hsotg->gadget);
4892 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4897 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4899 unsigned long flags;
4901 if (hsotg->lx_state != DWC2_L0)
4904 if (hsotg->driver) {
4907 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4908 hsotg->driver->driver.name);
4910 spin_lock_irqsave(&hsotg->lock, flags);
4912 dwc2_hsotg_core_disconnect(hsotg);
4913 dwc2_hsotg_disconnect(hsotg);
4914 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4915 spin_unlock_irqrestore(&hsotg->lock, flags);
4917 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4918 if (hsotg->eps_in[ep])
4919 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4920 if (hsotg->eps_out[ep])
4921 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4928 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4930 unsigned long flags;
4932 if (hsotg->lx_state == DWC2_L2)
4935 if (hsotg->driver) {
4936 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4937 hsotg->driver->driver.name);
4939 spin_lock_irqsave(&hsotg->lock, flags);
4940 dwc2_hsotg_core_init_disconnected(hsotg, false);
4941 if (hsotg->enabled) {
4942 /* Enable ACG feature in device mode,if supported */
4943 dwc2_enable_acg(hsotg);
4944 dwc2_hsotg_core_connect(hsotg);
4946 spin_unlock_irqrestore(&hsotg->lock, flags);
4953 * dwc2_backup_device_registers() - Backup controller device registers.
4954 * When suspending usb bus, registers needs to be backuped
4955 * if controller power is disabled once suspended.
4957 * @hsotg: Programming view of the DWC_otg controller
4959 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4961 struct dwc2_dregs_backup *dr;
4964 dev_dbg(hsotg->dev, "%s\n", __func__);
4966 /* Backup dev regs */
4967 dr = &hsotg->dr_backup;
4969 dr->dcfg = dwc2_readl(hsotg, DCFG);
4970 dr->dctl = dwc2_readl(hsotg, DCTL);
4971 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
4972 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
4973 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
4975 for (i = 0; i < hsotg->num_of_eps; i++) {
4977 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
4979 /* Ensure DATA PID is correctly configured */
4980 if (dr->diepctl[i] & DXEPCTL_DPID)
4981 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4983 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4985 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
4986 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
4988 /* Backup OUT EPs */
4989 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
4991 /* Ensure DATA PID is correctly configured */
4992 if (dr->doepctl[i] & DXEPCTL_DPID)
4993 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4995 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4997 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
4998 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
4999 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5006 * dwc2_restore_device_registers() - Restore controller device registers.
5007 * When resuming usb bus, device registers needs to be restored
5008 * if controller power were disabled.
5010 * @hsotg: Programming view of the DWC_otg controller
5011 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5013 * Return: 0 if successful, negative error code otherwise
5015 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5017 struct dwc2_dregs_backup *dr;
5020 dev_dbg(hsotg->dev, "%s\n", __func__);
5022 /* Restore dev regs */
5023 dr = &hsotg->dr_backup;
5025 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5032 dwc2_writel(hsotg, dr->dctl, DCTL);
5034 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5035 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5036 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5038 for (i = 0; i < hsotg->num_of_eps; i++) {
5039 /* Restore IN EPs */
5040 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5041 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5042 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5043 /** WA for enabled EPx's IN in DDMA mode. On entering to
5044 * hibernation wrong value read and saved from DIEPDMAx,
5045 * as result BNA interrupt asserted on hibernation exit
5046 * by restoring from saved area.
5048 if (hsotg->params.g_dma_desc &&
5049 (dr->diepctl[i] & DXEPCTL_EPENA))
5050 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5051 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5052 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5053 /* Restore OUT EPs */
5054 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5055 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5056 * hibernation wrong value read and saved from DOEPDMAx,
5057 * as result BNA interrupt asserted on hibernation exit
5058 * by restoring from saved area.
5060 if (hsotg->params.g_dma_desc &&
5061 (dr->doepctl[i] & DXEPCTL_EPENA))
5062 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5063 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5064 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5071 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5073 * @hsotg: Programming view of DWC_otg controller
5076 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5080 if (!hsotg->params.lpm)
5083 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5084 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5085 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5086 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5087 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5088 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5089 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5090 dwc2_writel(hsotg, val, GLPMCFG);
5091 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5093 /* Unmask WKUP_ALERT Interrupt */
5094 if (hsotg->params.service_interval)
5095 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5099 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5101 * @hsotg: Programming view of DWC_otg controller
5104 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5108 val |= GREFCLK_REF_CLK_MODE;
5109 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5110 val |= hsotg->params.sof_cnt_wkup_alert <<
5111 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5113 dwc2_writel(hsotg, val, GREFCLK);
5114 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5118 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5120 * @hsotg: Programming view of the DWC_otg controller
5122 * Return non-zero if failed to enter to hibernation.
5124 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5129 /* Change to L2(suspend) state */
5130 hsotg->lx_state = DWC2_L2;
5131 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5132 ret = dwc2_backup_global_registers(hsotg);
5134 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5138 ret = dwc2_backup_device_registers(hsotg);
5140 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5145 gpwrdn = GPWRDN_PWRDNRSTN;
5146 gpwrdn |= GPWRDN_PMUACTV;
5147 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5150 /* Set flag to indicate that we are in hibernation */
5151 hsotg->hibernated = 1;
5153 /* Enable interrupts from wake up logic */
5154 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5155 gpwrdn |= GPWRDN_PMUINTSEL;
5156 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5159 /* Unmask device mode interrupts in GPWRDN */
5160 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5161 gpwrdn |= GPWRDN_RST_DET_MSK;
5162 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5163 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5164 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5167 /* Enable Power Down Clamp */
5168 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5169 gpwrdn |= GPWRDN_PWRDNCLMP;
5170 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5173 /* Switch off VDD */
5174 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5175 gpwrdn |= GPWRDN_PWRDNSWTCH;
5176 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5179 /* Save gpwrdn register for further usage if stschng interrupt */
5180 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5181 dev_dbg(hsotg->dev, "Hibernation completed\n");
5187 * dwc2_gadget_exit_hibernation()
5188 * This function is for exiting from Device mode hibernation by host initiated
5189 * resume/reset and device initiated remote-wakeup.
5191 * @hsotg: Programming view of the DWC_otg controller
5192 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5193 * @reset: indicates whether resume is initiated by Reset.
5195 * Return non-zero if failed to exit from hibernation.
5197 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5198 int rem_wakeup, int reset)
5204 struct dwc2_gregs_backup *gr;
5205 struct dwc2_dregs_backup *dr;
5207 gr = &hsotg->gr_backup;
5208 dr = &hsotg->dr_backup;
5210 if (!hsotg->hibernated) {
5211 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5215 "%s: called with rem_wakeup = %d reset = %d\n",
5216 __func__, rem_wakeup, reset);
5218 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5221 /* Clear all pending interupts */
5222 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5225 /* De-assert Restore */
5226 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5227 gpwrdn &= ~GPWRDN_RESTORE;
5228 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5232 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5233 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5234 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5237 /* Restore GUSBCFG, DCFG and DCTL */
5238 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5239 dwc2_writel(hsotg, dr->dcfg, DCFG);
5240 dwc2_writel(hsotg, dr->dctl, DCTL);
5242 /* De-assert Wakeup Logic */
5243 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5244 gpwrdn &= ~GPWRDN_PMUACTV;
5245 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5249 /* Start Remote Wakeup Signaling */
5250 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5253 /* Set Device programming done bit */
5254 dctl = dwc2_readl(hsotg, DCTL);
5255 dctl |= DCTL_PWRONPRGDONE;
5256 dwc2_writel(hsotg, dctl, DCTL);
5258 /* Wait for interrupts which must be cleared */
5260 /* Clear all pending interupts */
5261 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5263 /* Restore global registers */
5264 ret = dwc2_restore_global_registers(hsotg);
5266 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5271 /* Restore device registers */
5272 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5274 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5281 dctl = dwc2_readl(hsotg, DCTL);
5282 dctl &= ~DCTL_RMTWKUPSIG;
5283 dwc2_writel(hsotg, dctl, DCTL);
5286 hsotg->hibernated = 0;
5287 hsotg->lx_state = DWC2_L0;
5288 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");