1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, NVIDIA Corporation
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/reset.h>
12 #include <linux/usb.h>
13 #include <linux/usb/chipidea.h>
14 #include <linux/usb/hcd.h>
15 #include <linux/usb/of.h>
16 #include <linux/usb/phy.h>
18 #include "../host/ehci.h"
23 struct ci_hdrc_platform_data data;
24 struct platform_device *dev;
26 const struct tegra_usb_soc_info *soc;
30 bool needs_double_reset;
33 struct tegra_usb_soc_info {
35 unsigned int txfifothresh;
36 enum usb_dr_mode dr_mode;
39 static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
40 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
41 CI_HDRC_OVERRIDE_PHY_CONTROL |
42 CI_HDRC_SUPPORTS_RUNTIME_PM,
43 .dr_mode = USB_DR_MODE_HOST,
47 static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
48 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
49 CI_HDRC_OVERRIDE_PHY_CONTROL |
50 CI_HDRC_SUPPORTS_RUNTIME_PM,
51 .dr_mode = USB_DR_MODE_HOST,
55 static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
56 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
57 CI_HDRC_OVERRIDE_PHY_CONTROL |
58 CI_HDRC_SUPPORTS_RUNTIME_PM,
59 .dr_mode = USB_DR_MODE_UNKNOWN,
63 static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
64 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
65 CI_HDRC_OVERRIDE_PHY_CONTROL |
66 CI_HDRC_SUPPORTS_RUNTIME_PM,
67 .dr_mode = USB_DR_MODE_UNKNOWN,
71 static const struct of_device_id tegra_usb_of_match[] = {
73 .compatible = "nvidia,tegra20-ehci",
74 .data = &tegra20_ehci_soc_info,
76 .compatible = "nvidia,tegra30-ehci",
77 .data = &tegra30_ehci_soc_info,
79 .compatible = "nvidia,tegra20-udc",
80 .data = &tegra20_udc_soc_info,
82 .compatible = "nvidia,tegra30-udc",
83 .data = &tegra30_udc_soc_info,
85 .compatible = "nvidia,tegra114-udc",
86 .data = &tegra30_udc_soc_info,
88 .compatible = "nvidia,tegra124-udc",
89 .data = &tegra30_udc_soc_info,
94 MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
96 static int tegra_usb_reset_controller(struct device *dev)
98 struct reset_control *rst, *rst_utmi;
99 struct device_node *phy_np;
102 rst = devm_reset_control_get_shared(dev, "usb");
104 dev_err(dev, "can't get ehci reset: %pe\n", rst);
108 phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
113 * The 1st USB controller contains some UTMI pad registers that are
114 * global for all the controllers on the chip. Those registers are
115 * also cleared when reset is asserted to the 1st controller.
117 rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
118 if (IS_ERR(rst_utmi)) {
119 dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
120 dev_warn(dev, "continuing, but please update your DT\n");
123 * PHY driver performs UTMI-pads reset in a case of a
126 reset_control_put(rst_utmi);
131 /* reset control is shared, hence initialize it first */
132 err = reset_control_deassert(rst);
136 err = reset_control_assert(rst);
142 err = reset_control_deassert(rst);
149 static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
151 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
152 struct ehci_hcd *ehci;
155 case CI_HDRC_CONTROLLER_RESET_EVENT:
157 ehci = hcd_to_ehci(ci->hcd);
158 ehci->has_tdi_phy_lpm = false;
159 ehci_writel(ehci, usb->soc->txfifothresh << 16,
160 &ehci->regs->txfill_tuning);
168 static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
169 u32 __iomem *portsc_reg,
170 unsigned long *flags)
172 u32 saved_usbintr, temp;
173 unsigned int i, tries;
176 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
177 /* disable USB interrupt */
178 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
179 spin_unlock_irqrestore(&ehci->lock, *flags);
182 * Here we have to do Port Reset at most twice for
183 * Port Enable bit to be set.
185 for (i = 0; i < 2; i++) {
186 temp = ehci_readl(ehci, portsc_reg);
188 ehci_writel(ehci, temp, portsc_reg);
191 ehci_writel(ehci, temp, portsc_reg);
197 * Up to this point, Port Enable bit is
198 * expected to be set after 2 ms waiting.
199 * USB1 usually takes extra 45 ms, for safety,
200 * we take 100 ms as timeout.
202 temp = ehci_readl(ehci, portsc_reg);
203 } while (!(temp & PORT_PE) && tries--);
211 * Clear Connect Status Change bit if it's set.
212 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
215 ehci_writel(ehci, PORT_CSC, portsc_reg);
218 * Write to clear any interrupt status bits that might be set
221 temp = ehci_readl(ehci, &ehci->regs->status);
222 ehci_writel(ehci, temp, &ehci->regs->status);
224 /* restore original interrupt-enable bits */
225 spin_lock_irqsave(&ehci->lock, *flags);
226 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
231 static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
232 u16 wIndex, char *buf, u16 wLength,
233 bool *done, unsigned long *flags)
235 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
236 struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
237 u32 __iomem *status_reg;
240 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
244 if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
247 /* for USB1 port we need to issue Port Reset twice internally */
248 retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
256 static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
259 * Touching any register which belongs to AHB clock domain will
260 * hang CPU if USB controller is put into low power mode because
261 * AHB USB clock is gated on Tegra in the LPM.
263 * Tegra PHY has a separate register for checking the clock status
264 * and usb_phy_set_suspend() takes care of gating/ungating the clocks
265 * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
266 * shouldn't be touched directly by the CI driver.
268 usb_phy_set_suspend(ci->usb_phy, enable);
271 static int tegra_usb_probe(struct platform_device *pdev)
273 const struct tegra_usb_soc_info *soc;
274 struct tegra_usb *usb;
277 usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
281 soc = of_device_get_match_data(&pdev->dev);
283 dev_err(&pdev->dev, "failed to match OF data\n");
287 usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
288 if (IS_ERR(usb->phy))
289 return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
290 "failed to get PHY\n");
292 usb->clk = devm_clk_get(&pdev->dev, NULL);
293 if (IS_ERR(usb->clk)) {
294 err = PTR_ERR(usb->clk);
295 dev_err(&pdev->dev, "failed to get clock: %d\n", err);
299 err = clk_prepare_enable(usb->clk);
301 dev_err(&pdev->dev, "failed to enable clock: %d\n", err);
305 if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
306 usb->needs_double_reset = true;
308 err = tegra_usb_reset_controller(&pdev->dev);
310 dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
315 * USB controller registers shouldn't be touched before PHY is
316 * initialized, otherwise CPU will hang because clocks are gated.
317 * PHY driver controls gating of internal USB clocks on Tegra.
319 err = usb_phy_init(usb->phy);
323 platform_set_drvdata(pdev, usb);
325 /* setup and register ChipIdea HDRC device */
327 usb->data.name = "tegra-usb";
328 usb->data.flags = soc->flags;
329 usb->data.usb_phy = usb->phy;
330 usb->data.dr_mode = soc->dr_mode;
331 usb->data.capoffset = DEF_CAPOFFSET;
332 usb->data.enter_lpm = tegra_usb_enter_lpm;
333 usb->data.hub_control = tegra_ehci_hub_control;
334 usb->data.notify_event = tegra_usb_notify_event;
336 /* Tegra PHY driver currently doesn't support LPM for ULPI */
337 if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
338 usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
340 usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
341 pdev->num_resources, &usb->data);
342 if (IS_ERR(usb->dev)) {
343 err = PTR_ERR(usb->dev);
344 dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
351 usb_phy_shutdown(usb->phy);
353 clk_disable_unprepare(usb->clk);
357 static int tegra_usb_remove(struct platform_device *pdev)
359 struct tegra_usb *usb = platform_get_drvdata(pdev);
361 ci_hdrc_remove_device(usb->dev);
362 usb_phy_shutdown(usb->phy);
363 clk_disable_unprepare(usb->clk);
368 static struct platform_driver tegra_usb_driver = {
371 .of_match_table = tegra_usb_of_match,
373 .probe = tegra_usb_probe,
374 .remove = tegra_usb_remove,
376 module_platform_driver(tegra_usb_driver);
378 MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
379 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
380 MODULE_LICENSE("GPL v2");