drivers/tty/synclinkmp.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   4  *
   5  * Device driver for Microgate SyncLink Multiport
   6  * high speed multiprotocol serial adapter.
   7  *
   8  * written by Paul Fulghum for Microgate Corporation
   9  * paulkf@microgate.com
  10  *
  11  * Microgate and SyncLink are trademarks of Microgate Corporation
  12  *
  13  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/seq_file.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <linux/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         struct tty_port         port;
 155         int                     line;
 156         unsigned short          close_delay;
 157         unsigned short          closing_wait;   /* time to wait before closing */
 158
 159         struct mgsl_icount      icount;
 160
 161         int                     timeout;
 162         int                     x_char;         /* xon/xoff character */
 163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167         unsigned char           *tx_buf;
 168         int                     tx_put;
 169         int                     tx_get;
 170         int                     tx_count;
 171
 172         wait_queue_head_t       status_event_wait_q;
 173         wait_queue_head_t       event_wait_q;
 174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 175         struct _synclinkmp_info *next_device;   /* device list link */
 176         struct timer_list       status_timer;   /* input signal status check timer */
 177
 178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 179         struct work_struct task;                        /* task structure for scheduling bh */
 180
 181         u32 max_frame_size;                     /* as set by device config */
 182
 183         u32 pending_bh;
 184
 185         bool bh_running;                                /* Protection from multiple */
 186         int isr_overflow;
 187         bool bh_requested;
 188
 189         int dcd_chkcount;                       /* check counts to prevent */
 190         int cts_chkcount;                       /* too many IRQs if a signal */
 191         int dsr_chkcount;                       /* is floating */
 192         int ri_chkcount;
 193
 194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 195         unsigned long buffer_list_phys;
 196
 197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 200         unsigned int current_rx_buf;
 201
 202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 205         unsigned int last_tx_buf;
 206
 207         unsigned char *tmp_rx_buf;
 208         unsigned int tmp_rx_buf_count;
 209
 210         bool rx_enabled;
 211         bool rx_overflow;
 212
 213         bool tx_enabled;
 214         bool tx_active;
 215         u32 idle_mode;
 216
 217         unsigned char ie0_value;
 218         unsigned char ie1_value;
 219         unsigned char ie2_value;
 220         unsigned char ctrlreg_value;
 221         unsigned char old_signals;
 222
 223         char device_name[25];                   /* device instance name */
 224
 225         int port_count;
 226         int adapter_num;
 227         int port_num;
 228
 229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 230
 231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 232
 233         unsigned int irq_level;                 /* interrupt level */
 234         unsigned long irq_flags;
 235         bool irq_requested;                     /* true if IRQ requested */
 236
 237         MGSL_PARAMS params;                     /* communications parameters */
 238
 239         unsigned char serial_signals;           /* current serial signal states */
 240
 241         bool irq_occurred;                      /* for diagnostics use */
 242         unsigned int init_error;                /* Initialization startup error */
 243
 244         u32 last_mem_alloc;
 245         unsigned char* memory_base;             /* shared memory address (PCI only) */
 246         u32 phys_memory_base;
 247         int shared_mem_requested;
 248
 249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 250         u32 phys_sca_base;
 251         u32 sca_offset;
 252         bool sca_base_requested;
 253
 254         unsigned char* lcr_base;                /* local config registers (PCI only) */
 255         u32 phys_lcr_base;
 256         u32 lcr_offset;
 257         int lcr_mem_requested;
 258
 259         unsigned char* statctrl_base;           /* status/control register memory */
 260         u32 phys_statctrl_base;
 261         u32 statctrl_offset;
 262         bool sca_statctrl_requested;
 263
 264         u32 misc_ctrl_value;
 265         char *flag_buf;
 266         bool drop_rts_on_tx_done;
 267
 268         struct  _input_signal_events    input_signal_events;
 269
 270         /* SPPP/Cisco HDLC device parts */
 271         int netcount;
 272         spinlock_t netlock;
 273
 274 #if SYNCLINK_GENERIC_HDLC
 275         struct net_device *netdev;
 276 #endif
 277
 278 } SLMP_INFO;
 279
 280 #define MGSL_MAGIC 0x5401
 281
 282 /*
 283  * define serial signal status change macros
 284  */
 285 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 286 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 287 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 288 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 289
 290 /* Common Register macros */
 291 #define LPR     0x00
 292 #define PABR0   0x02
 293 #define PABR1   0x03
 294 #define WCRL    0x04
 295 #define WCRM    0x05
 296 #define WCRH    0x06
 297 #define DPCR    0x08
 298 #define DMER    0x09
 299 #define ISR0    0x10
 300 #define ISR1    0x11
 301 #define ISR2    0x12
 302 #define IER0    0x14
 303 #define IER1    0x15
 304 #define IER2    0x16
 305 #define ITCR    0x18
 306 #define INTVR   0x1a
 307 #define IMVR    0x1c
 308
 309 /* MSCI Register macros */
 310 #define TRB     0x20
 311 #define TRBL    0x20
 312 #define TRBH    0x21
 313 #define SR0     0x22
 314 #define SR1     0x23
 315 #define SR2     0x24
 316 #define SR3     0x25
 317 #define FST     0x26
 318 #define IE0     0x28
 319 #define IE1     0x29
 320 #define IE2     0x2a
 321 #define FIE     0x2b
 322 #define CMD     0x2c
 323 #define MD0     0x2e
 324 #define MD1     0x2f
 325 #define MD2     0x30
 326 #define CTL     0x31
 327 #define SA0     0x32
 328 #define SA1     0x33
 329 #define IDL     0x34
 330 #define TMC     0x35
 331 #define RXS     0x36
 332 #define TXS     0x37
 333 #define TRC0    0x38
 334 #define TRC1    0x39
 335 #define RRC     0x3a
 336 #define CST0    0x3c
 337 #define CST1    0x3d
 338
 339 /* Timer Register Macros */
 340 #define TCNT    0x60
 341 #define TCNTL   0x60
 342 #define TCNTH   0x61
 343 #define TCONR   0x62
 344 #define TCONRL  0x62
 345 #define TCONRH  0x63
 346 #define TMCS    0x64
 347 #define TEPR    0x65
 348
 349 /* DMA Controller Register macros */
 350 #define DARL    0x80
 351 #define DARH    0x81
 352 #define DARB    0x82
 353 #define BAR     0x80
 354 #define BARL    0x80
 355 #define BARH    0x81
 356 #define BARB    0x82
 357 #define SAR     0x84
 358 #define SARL    0x84
 359 #define SARH    0x85
 360 #define SARB    0x86
 361 #define CPB     0x86
 362 #define CDA     0x88
 363 #define CDAL    0x88
 364 #define CDAH    0x89
 365 #define EDA     0x8a
 366 #define EDAL    0x8a
 367 #define EDAH    0x8b
 368 #define BFL     0x8c
 369 #define BFLL    0x8c
 370 #define BFLH    0x8d
 371 #define BCR     0x8e
 372 #define BCRL    0x8e
 373 #define BCRH    0x8f
 374 #define DSR     0x90
 375 #define DMR     0x91
 376 #define FCT     0x93
 377 #define DIR     0x94
 378 #define DCMD    0x95
 379
 380 /* combine with timer or DMA register address */
 381 #define TIMER0  0x00
 382 #define TIMER1  0x08
 383 #define TIMER2  0x10
 384 #define TIMER3  0x18
 385 #define RXDMA   0x00
 386 #define TXDMA   0x20
 387
 388 /* SCA Command Codes */
 389 #define NOOP            0x00
 390 #define TXRESET         0x01
 391 #define TXENABLE        0x02
 392 #define TXDISABLE       0x03
 393 #define TXCRCINIT       0x04
 394 #define TXCRCEXCL       0x05
 395 #define TXEOM           0x06
 396 #define TXABORT         0x07
 397 #define MPON            0x08
 398 #define TXBUFCLR        0x09
 399 #define RXRESET         0x11
 400 #define RXENABLE        0x12
 401 #define RXDISABLE       0x13
 402 #define RXCRCINIT       0x14
 403 #define RXREJECT        0x15
 404 #define SEARCHMP        0x16
 405 #define RXCRCEXCL       0x17
 406 #define RXCRCCALC       0x18
 407 #define CHRESET         0x21
 408 #define HUNT            0x31
 409
 410 /* DMA command codes */
 411 #define SWABORT         0x01
 412 #define FEICLEAR        0x02
 413
 414 /* IE0 */
 415 #define TXINTE          BIT7
 416 #define RXINTE          BIT6
 417 #define TXRDYE          BIT1
 418 #define RXRDYE          BIT0
 419
 420 /* IE1 & SR1 */
 421 #define UDRN    BIT7
 422 #define IDLE    BIT6
 423 #define SYNCD   BIT4
 424 #define FLGD    BIT4
 425 #define CCTS    BIT3
 426 #define CDCD    BIT2
 427 #define BRKD    BIT1
 428 #define ABTD    BIT1
 429 #define GAPD    BIT1
 430 #define BRKE    BIT0
 431 #define IDLD    BIT0
 432
 433 /* IE2 & SR2 */
 434 #define EOM     BIT7
 435 #define PMP     BIT6
 436 #define SHRT    BIT6
 437 #define PE      BIT5
 438 #define ABT     BIT5
 439 #define FRME    BIT4
 440 #define RBIT    BIT4
 441 #define OVRN    BIT3
 442 #define CRCE    BIT2
 443
 444
 445 /*
 446  * Global linked list of SyncLink devices
 447  */
 448 static SLMP_INFO *synclinkmp_device_list = NULL;
 449 static int synclinkmp_adapter_count = -1;
 450 static int synclinkmp_device_count = 0;
 451
 452 /*
 453  * Set this param to non-zero to load eax with the
 454  * .text section address and breakpoint on module load.
 455  * This is useful for use with gdb and add-symbol-file command.
 456  */
 457 static bool break_on_load = 0;
 458
 459 /*
 460  * Driver major number, defaults to zero to get auto
 461  * assigned major number. May be forced as module parameter.
 462  */
 463 static int ttymajor = 0;
 464
 465 /*
 466  * Array of user specified options for ISA adapters.
 467  */
 468 static int debug_level = 0;
 469 static int maxframe[MAX_DEVICES] = {0,};
 470
 471 module_param(break_on_load, bool, 0);
 472 module_param(ttymajor, int, 0);
 473 module_param(debug_level, int, 0);
 474 module_param_array(maxframe, int, NULL, 0);
 475
 476 static char *driver_name = "SyncLink MultiPort driver";
 477 static char *driver_version = "$Revision: 4.38 $";
 478
 479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 480 static void synclinkmp_remove_one(struct pci_dev *dev);
 481
 482 static const struct pci_device_id synclinkmp_pci_tbl[] = {
 483         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 484         { 0, }, /* terminate list */
 485 };
 486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 487
 488 MODULE_LICENSE("GPL");
 489
 490 static struct pci_driver synclinkmp_pci_driver = {
 491         .name           = "synclinkmp",
 492         .id_table       = synclinkmp_pci_tbl,
 493         .probe          = synclinkmp_init_one,
 494         .remove         = synclinkmp_remove_one,
 495 };
 496
 497
 498 static struct tty_driver *serial_driver;
 499
 500 /* number of characters left in xmit buffer before we ask for more */
 501 #define WAKEUP_CHARS 256
 502
 503
 504 /* tty callbacks */
 505
 506 static int  open(struct tty_struct *tty, struct file * filp);
 507 static void close(struct tty_struct *tty, struct file * filp);
 508 static void hangup(struct tty_struct *tty);
 509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 510
 511 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 512 static int put_char(struct tty_struct *tty, unsigned char ch);
 513 static void send_xchar(struct tty_struct *tty, char ch);
 514 static void wait_until_sent(struct tty_struct *tty, int timeout);
 515 static int  write_room(struct tty_struct *tty);
 516 static void flush_chars(struct tty_struct *tty);
 517 static void flush_buffer(struct tty_struct *tty);
 518 static void tx_hold(struct tty_struct *tty);
 519 static void tx_release(struct tty_struct *tty);
 520
 521 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 522 static int  chars_in_buffer(struct tty_struct *tty);
 523 static void throttle(struct tty_struct * tty);
 524 static void unthrottle(struct tty_struct * tty);
 525 static int set_break(struct tty_struct *tty, int break_state);
 526
 527 #if SYNCLINK_GENERIC_HDLC
 528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 529 static void hdlcdev_tx_done(SLMP_INFO *info);
 530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 531 static int  hdlcdev_init(SLMP_INFO *info);
 532 static void hdlcdev_exit(SLMP_INFO *info);
 533 #endif
 534
 535 /* ioctl handlers */
 536
 537 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 538 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 539 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 540 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 541 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 542 static int  tx_enable(SLMP_INFO *info, int enable);
 543 static int  tx_abort(SLMP_INFO *info);
 544 static int  rx_enable(SLMP_INFO *info, int enable);
 545 static int  modem_input_wait(SLMP_INFO *info,int arg);
 546 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 547 static int  tiocmget(struct tty_struct *tty);
 548 static int  tiocmset(struct tty_struct *tty,
 549                         unsigned int set, unsigned int clear);
 550 static int  set_break(struct tty_struct *tty, int break_state);
 551
 552 static int  add_device(SLMP_INFO *info);
 553 static int  device_init(int adapter_num, struct pci_dev *pdev);
 554 static int  claim_resources(SLMP_INFO *info);
 555 static void release_resources(SLMP_INFO *info);
 556
 557 static int  startup(SLMP_INFO *info);
 558 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 559 static int carrier_raised(struct tty_port *port);
 560 static void shutdown(SLMP_INFO *info);
 561 static void program_hw(SLMP_INFO *info);
 562 static void change_params(SLMP_INFO *info);
 563
 564 static bool init_adapter(SLMP_INFO *info);
 565 static bool register_test(SLMP_INFO *info);
 566 static bool irq_test(SLMP_INFO *info);
 567 static bool loopback_test(SLMP_INFO *info);
 568 static int  adapter_test(SLMP_INFO *info);
 569 static bool memory_test(SLMP_INFO *info);
 570
 571 static void reset_adapter(SLMP_INFO *info);
 572 static void reset_port(SLMP_INFO *info);
 573 static void async_mode(SLMP_INFO *info);
 574 static void hdlc_mode(SLMP_INFO *info);
 575
 576 static void rx_stop(SLMP_INFO *info);
 577 static void rx_start(SLMP_INFO *info);
 578 static void rx_reset_buffers(SLMP_INFO *info);
 579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 580 static bool rx_get_frame(SLMP_INFO *info);
 581
 582 static void tx_start(SLMP_INFO *info);
 583 static void tx_stop(SLMP_INFO *info);
 584 static void tx_load_fifo(SLMP_INFO *info);
 585 static void tx_set_idle(SLMP_INFO *info);
 586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 587
 588 static void get_signals(SLMP_INFO *info);
 589 static void set_signals(SLMP_INFO *info);
 590 static void enable_loopback(SLMP_INFO *info, int enable);
 591 static void set_rate(SLMP_INFO *info, u32 data_rate);
 592
 593 static int  bh_action(SLMP_INFO *info);
 594 static void bh_handler(struct work_struct *work);
 595 static void bh_receive(SLMP_INFO *info);
 596 static void bh_transmit(SLMP_INFO *info);
 597 static void bh_status(SLMP_INFO *info);
 598 static void isr_timer(SLMP_INFO *info);
 599 static void isr_rxint(SLMP_INFO *info);
 600 static void isr_rxrdy(SLMP_INFO *info);
 601 static void isr_txint(SLMP_INFO *info);
 602 static void isr_txrdy(SLMP_INFO *info);
 603 static void isr_rxdmaok(SLMP_INFO *info);
 604 static void isr_rxdmaerror(SLMP_INFO *info);
 605 static void isr_txdmaok(SLMP_INFO *info);
 606 static void isr_txdmaerror(SLMP_INFO *info);
 607 static void isr_io_pin(SLMP_INFO *info, u16 status);
 608
 609 static int  alloc_dma_bufs(SLMP_INFO *info);
 610 static void free_dma_bufs(SLMP_INFO *info);
 611 static int  alloc_buf_list(SLMP_INFO *info);
 612 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 613 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 614 static void free_tmp_rx_buf(SLMP_INFO *info);
 615
 616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 618 static void tx_timeout(struct timer_list *t);
 619 static void status_timeout(struct timer_list *t);
 620
 621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 625 static unsigned char read_status_reg(SLMP_INFO * info);
 626 static void write_control_reg(SLMP_INFO * info);
 627
 628
 629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 632
 633 static u32 misc_ctrl_value = 0x007e4040;
 634 static u32 lcr1_brdr_value = 0x00800028;
 635
 636 static u32 read_ahead_count = 8;
 637
 638 /* DPCR, DMA Priority Control
 639  *
 640  * 07..05  Not used, must be 0
 641  * 04      BRC, bus release condition: 0=all transfers complete
 642  *              1=release after 1 xfer on all channels
 643  * 03      CCC, channel change condition: 0=every cycle
 644  *              1=after each channel completes all xfers
 645  * 02..00  PR<2..0>, priority 100=round robin
 646  *
 647  * 00000100 = 0x00
 648  */
 649 static unsigned char dma_priority = 0x04;
 650
 651 // Number of bytes that can be written to shared RAM
 652 // in a single write operation
 653 static u32 sca_pci_load_interval = 64;
 654
 655 /*
 656  * 1st function defined in .text section. Calling this function in
 657  * init_module() followed by a breakpoint allows a remote debugger
 658  * (gdb) to get the .text address for the add-symbol-file command.
 659  * This allows remote debugging of dynamically loadable modules.
 660  */
 661 static void* synclinkmp_get_text_ptr(void);
 662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 663
 664 static inline int sanity_check(SLMP_INFO *info,
 665                                char *name, const char *routine)
 666 {
 667 #ifdef SANITY_CHECK
 668         static const char *badmagic =
 669                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 670         static const char *badinfo =
 671                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 672
 673         if (!info) {
 674                 printk(badinfo, name, routine);
 675                 return 1;
 676         }
 677         if (info->magic != MGSL_MAGIC) {
 678                 printk(badmagic, name, routine);
 679                 return 1;
 680         }
 681 #else
 682         if (!info)
 683                 return 1;
 684 #endif
 685         return 0;
 686 }
 687
 688 /*
 689  * line discipline callback wrappers
 690  *
 691  * The wrappers maintain line discipline references
 692  * while calling into the line discipline.
 693  *
 694  * ldisc_receive_buf  - pass receive data to line discipline
 695  */
 696
 697 static void ldisc_receive_buf(struct tty_struct *tty,
 698                               const __u8 *data, char *flags, int count)
 699 {
 700         struct tty_ldisc *ld;
 701         if (!tty)
 702                 return;
 703         ld = tty_ldisc_ref(tty);
 704         if (ld) {
 705                 if (ld->ops->receive_buf)
 706                         ld->ops->receive_buf(tty, data, flags, count);
 707                 tty_ldisc_deref(ld);
 708         }
 709 }
 710
 711 /* tty callbacks */
 712
 713 static int install(struct tty_driver *driver, struct tty_struct *tty)
 714 {
 715         SLMP_INFO *info;
 716         int line = tty->index;
 717
 718         if (line >= synclinkmp_device_count) {
 719                 printk("%s(%d): open with invalid line #%d.\n",
 720                         __FILE__,__LINE__,line);
 721                 return -ENODEV;
 722         }
 723
 724         info = synclinkmp_device_list;
 725         while (info && info->line != line)
 726                 info = info->next_device;
 727         if (sanity_check(info, tty->name, "open"))
 728                 return -ENODEV;
 729         if (info->init_error) {
 730                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 731                         __FILE__, __LINE__, info->device_name,
 732                         info->init_error);
 733                 return -ENODEV;
 734         }
 735
 736         tty->driver_data = info;
 737
 738         return tty_port_install(&info->port, driver, tty);
 739 }
 740
 741 /* Called when a port is opened.  Init and enable port.
 742  */
 743 static int open(struct tty_struct *tty, struct file *filp)
 744 {
 745         SLMP_INFO *info = tty->driver_data;
 746         unsigned long flags;
 747         int retval;
 748
 749         info->port.tty = tty;
 750
 751         if (debug_level >= DEBUG_LEVEL_INFO)
 752                 printk("%s(%d):%s open(), old ref count = %d\n",
 753                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 754
 755         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 756
 757         spin_lock_irqsave(&info->netlock, flags);
 758         if (info->netcount) {
 759                 retval = -EBUSY;
 760                 spin_unlock_irqrestore(&info->netlock, flags);
 761                 goto cleanup;
 762         }
 763         info->port.count++;
 764         spin_unlock_irqrestore(&info->netlock, flags);
 765
 766         if (info->port.count == 1) {
 767                 /* 1st open on this device, init hardware */
 768                 retval = startup(info);
 769                 if (retval < 0)
 770                         goto cleanup;
 771         }
 772
 773         retval = block_til_ready(tty, filp, info);
 774         if (retval) {
 775                 if (debug_level >= DEBUG_LEVEL_INFO)
 776                         printk("%s(%d):%s block_til_ready() returned %d\n",
 777                                  __FILE__,__LINE__, info->device_name, retval);
 778                 goto cleanup;
 779         }
 780
 781         if (debug_level >= DEBUG_LEVEL_INFO)
 782                 printk("%s(%d):%s open() success\n",
 783                          __FILE__,__LINE__, info->device_name);
 784         retval = 0;
 785
 786 cleanup:
 787         if (retval) {
 788                 if (tty->count == 1)
 789                         info->port.tty = NULL; /* tty layer will release tty struct */
 790                 if(info->port.count)
 791                         info->port.count--;
 792         }
 793
 794         return retval;
 795 }
 796
 797 /* Called when port is closed. Wait for remaining data to be
 798  * sent. Disable port and free resources.
 799  */
 800 static void close(struct tty_struct *tty, struct file *filp)
 801 {
 802         SLMP_INFO * info = tty->driver_data;
 803
 804         if (sanity_check(info, tty->name, "close"))
 805                 return;
 806
 807         if (debug_level >= DEBUG_LEVEL_INFO)
 808                 printk("%s(%d):%s close() entry, count=%d\n",
 809                          __FILE__,__LINE__, info->device_name, info->port.count);
 810
 811         if (tty_port_close_start(&info->port, tty, filp) == 0)
 812                 goto cleanup;
 813
 814         mutex_lock(&info->port.mutex);
 815         if (tty_port_initialized(&info->port))
 816                 wait_until_sent(tty, info->timeout);
 817
 818         flush_buffer(tty);
 819         tty_ldisc_flush(tty);
 820         shutdown(info);
 821         mutex_unlock(&info->port.mutex);
 822
 823         tty_port_close_end(&info->port, tty);
 824         info->port.tty = NULL;
 825 cleanup:
 826         if (debug_level >= DEBUG_LEVEL_INFO)
 827                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 828                         tty->driver->name, info->port.count);
 829 }
 830
 831 /* Called by tty_hangup() when a hangup is signaled.
 832  * This is the same as closing all open descriptors for the port.
 833  */
 834 static void hangup(struct tty_struct *tty)
 835 {
 836         SLMP_INFO *info = tty->driver_data;
 837         unsigned long flags;
 838
 839         if (debug_level >= DEBUG_LEVEL_INFO)
 840                 printk("%s(%d):%s hangup()\n",
 841                          __FILE__,__LINE__, info->device_name );
 842
 843         if (sanity_check(info, tty->name, "hangup"))
 844                 return;
 845
 846         mutex_lock(&info->port.mutex);
 847         flush_buffer(tty);
 848         shutdown(info);
 849
 850         spin_lock_irqsave(&info->port.lock, flags);
 851         info->port.count = 0;
 852         info->port.tty = NULL;
 853         spin_unlock_irqrestore(&info->port.lock, flags);
 854         tty_port_set_active(&info->port, 1);
 855         mutex_unlock(&info->port.mutex);
 856
 857         wake_up_interruptible(&info->port.open_wait);
 858 }
 859
 860 /* Set new termios settings
 861  */
 862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 863 {
 864         SLMP_INFO *info = tty->driver_data;
 865         unsigned long flags;
 866
 867         if (debug_level >= DEBUG_LEVEL_INFO)
 868                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 869                         tty->driver->name );
 870
 871         change_params(info);
 872
 873         /* Handle transition to B0 status */
 874         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 875                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 876                 spin_lock_irqsave(&info->lock,flags);
 877                 set_signals(info);
 878                 spin_unlock_irqrestore(&info->lock,flags);
 879         }
 880
 881         /* Handle transition away from B0 status */
 882         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 883                 info->serial_signals |= SerialSignal_DTR;
 884                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 885                         info->serial_signals |= SerialSignal_RTS;
 886                 spin_lock_irqsave(&info->lock,flags);
 887                 set_signals(info);
 888                 spin_unlock_irqrestore(&info->lock,flags);
 889         }
 890
 891         /* Handle turning off CRTSCTS */
 892         if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
 893                 tty->hw_stopped = 0;
 894                 tx_release(tty);
 895         }
 896 }
 897
 898 /* Send a block of data
 899  *
 900  * Arguments:
 901  *
 902  *      tty             pointer to tty information structure
 903  *      buf             pointer to buffer containing send data
 904  *      count           size of send data in bytes
 905  *
 906  * Return Value:        number of characters written
 907  */
 908 static int write(struct tty_struct *tty,
 909                  const unsigned char *buf, int count)
 910 {
 911         int     c, ret = 0;
 912         SLMP_INFO *info = tty->driver_data;
 913         unsigned long flags;
 914
 915         if (debug_level >= DEBUG_LEVEL_INFO)
 916                 printk("%s(%d):%s write() count=%d\n",
 917                        __FILE__,__LINE__,info->device_name,count);
 918
 919         if (sanity_check(info, tty->name, "write"))
 920                 goto cleanup;
 921
 922         if (!info->tx_buf)
 923                 goto cleanup;
 924
 925         if (info->params.mode == MGSL_MODE_HDLC) {
 926                 if (count > info->max_frame_size) {
 927                         ret = -EIO;
 928                         goto cleanup;
 929                 }
 930                 if (info->tx_active)
 931                         goto cleanup;
 932                 if (info->tx_count) {
 933                         /* send accumulated data from send_char() calls */
 934                         /* as frame and wait before accepting more data. */
 935                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 936                         goto start;
 937                 }
 938                 ret = info->tx_count = count;
 939                 tx_load_dma_buffer(info, buf, count);
 940                 goto start;
 941         }
 942
 943         for (;;) {
 944                 c = min_t(int, count,
 945                         min(info->max_frame_size - info->tx_count - 1,
 946                             info->max_frame_size - info->tx_put));
 947                 if (c <= 0)
 948                         break;
 949
 950                 memcpy(info->tx_buf + info->tx_put, buf, c);
 951
 952                 spin_lock_irqsave(&info->lock,flags);
 953                 info->tx_put += c;
 954                 if (info->tx_put >= info->max_frame_size)
 955                         info->tx_put -= info->max_frame_size;
 956                 info->tx_count += c;
 957                 spin_unlock_irqrestore(&info->lock,flags);
 958
 959                 buf += c;
 960                 count -= c;
 961                 ret += c;
 962         }
 963
 964         if (info->params.mode == MGSL_MODE_HDLC) {
 965                 if (count) {
 966                         ret = info->tx_count = 0;
 967                         goto cleanup;
 968                 }
 969                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 970         }
 971 start:
 972         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 973                 spin_lock_irqsave(&info->lock,flags);
 974                 if (!info->tx_active)
 975                         tx_start(info);
 976                 spin_unlock_irqrestore(&info->lock,flags);
 977         }
 978
 979 cleanup:
 980         if (debug_level >= DEBUG_LEVEL_INFO)
 981                 printk( "%s(%d):%s write() returning=%d\n",
 982                         __FILE__,__LINE__,info->device_name,ret);
 983         return ret;
 984 }
 985
 986 /* Add a character to the transmit buffer.
 987  */
 988 static int put_char(struct tty_struct *tty, unsigned char ch)
 989 {
 990         SLMP_INFO *info = tty->driver_data;
 991         unsigned long flags;
 992         int ret = 0;
 993
 994         if ( debug_level >= DEBUG_LEVEL_INFO ) {
 995                 printk( "%s(%d):%s put_char(%d)\n",
 996                         __FILE__,__LINE__,info->device_name,ch);
 997         }
 998
 999         if (sanity_check(info, tty->name, "put_char"))
1000                 return 0;
1001
1002         if (!info->tx_buf)
1003                 return 0;
1004
1005         spin_lock_irqsave(&info->lock,flags);
1006
1007         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008              !info->tx_active ) {
1009
1010                 if (info->tx_count < info->max_frame_size - 1) {
1011                         info->tx_buf[info->tx_put++] = ch;
1012                         if (info->tx_put >= info->max_frame_size)
1013                                 info->tx_put -= info->max_frame_size;
1014                         info->tx_count++;
1015                         ret = 1;
1016                 }
1017         }
1018
1019         spin_unlock_irqrestore(&info->lock,flags);
1020         return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024  */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027         SLMP_INFO *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (debug_level >= DEBUG_LEVEL_INFO)
1031                 printk("%s(%d):%s send_xchar(%d)\n",
1032                          __FILE__,__LINE__, info->device_name, ch );
1033
1034         if (sanity_check(info, tty->name, "send_xchar"))
1035                 return;
1036
1037         info->x_char = ch;
1038         if (ch) {
1039                 /* Make sure transmit interrupts are on */
1040                 spin_lock_irqsave(&info->lock,flags);
1041                 if (!info->tx_enabled)
1042                         tx_start(info);
1043                 spin_unlock_irqrestore(&info->lock,flags);
1044         }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048  */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051         SLMP_INFO * info = tty->driver_data;
1052         unsigned long orig_jiffies, char_time;
1053
1054         if (!info )
1055                 return;
1056
1057         if (debug_level >= DEBUG_LEVEL_INFO)
1058                 printk("%s(%d):%s wait_until_sent() entry\n",
1059                          __FILE__,__LINE__, info->device_name );
1060
1061         if (sanity_check(info, tty->name, "wait_until_sent"))
1062                 return;
1063
1064         if (!tty_port_initialized(&info->port))
1065                 goto exit;
1066
1067         orig_jiffies = jiffies;
1068
1069         /* Set check interval to 1/5 of estimated time to
1070          * send a character, and make it at least 1. The check
1071          * interval should also be less than the timeout.
1072          * Note: use tight timings here to satisfy the NIST-PCTS.
1073          */
1074
1075         if ( info->params.data_rate ) {
1076                 char_time = info->timeout/(32 * 5);
1077                 if (!char_time)
1078                         char_time++;
1079         } else
1080                 char_time = 1;
1081
1082         if (timeout)
1083                 char_time = min_t(unsigned long, char_time, timeout);
1084
1085         if ( info->params.mode == MGSL_MODE_HDLC ) {
1086                 while (info->tx_active) {
1087                         msleep_interruptible(jiffies_to_msecs(char_time));
1088                         if (signal_pending(current))
1089                                 break;
1090                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091                                 break;
1092                 }
1093         } else {
1094                 /*
1095                  * TODO: determine if there is something similar to USC16C32
1096                  *       TXSTATUS_ALL_SENT status
1097                  */
1098                 while ( info->tx_active && info->tx_enabled) {
1099                         msleep_interruptible(jiffies_to_msecs(char_time));
1100                         if (signal_pending(current))
1101                                 break;
1102                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103                                 break;
1104                 }
1105         }
1106
1107 exit:
1108         if (debug_level >= DEBUG_LEVEL_INFO)
1109                 printk("%s(%d):%s wait_until_sent() exit\n",
1110                          __FILE__,__LINE__, info->device_name );
1111 }
1112
1113 /* Return the count of free bytes in transmit buffer
1114  */
1115 static int write_room(struct tty_struct *tty)
1116 {
1117         SLMP_INFO *info = tty->driver_data;
1118         int ret;
1119
1120         if (sanity_check(info, tty->name, "write_room"))
1121                 return 0;
1122
1123         if (info->params.mode == MGSL_MODE_HDLC) {
1124                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125         } else {
1126                 ret = info->max_frame_size - info->tx_count - 1;
1127                 if (ret < 0)
1128                         ret = 0;
1129         }
1130
1131         if (debug_level >= DEBUG_LEVEL_INFO)
1132                 printk("%s(%d):%s write_room()=%d\n",
1133                        __FILE__, __LINE__, info->device_name, ret);
1134
1135         return ret;
1136 }
1137
1138 /* enable transmitter and send remaining buffered characters
1139  */
1140 static void flush_chars(struct tty_struct *tty)
1141 {
1142         SLMP_INFO *info = tty->driver_data;
1143         unsigned long flags;
1144
1145         if ( debug_level >= DEBUG_LEVEL_INFO )
1146                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147                         __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149         if (sanity_check(info, tty->name, "flush_chars"))
1150                 return;
1151
1152         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153             !info->tx_buf)
1154                 return;
1155
1156         if ( debug_level >= DEBUG_LEVEL_INFO )
1157                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158                         __FILE__,__LINE__,info->device_name );
1159
1160         spin_lock_irqsave(&info->lock,flags);
1161
1162         if (!info->tx_active) {
1163                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164                         info->tx_count ) {
1165                         /* operating in synchronous (frame oriented) mode */
1166                         /* copy data from circular tx_buf to */
1167                         /* transmit DMA buffer. */
1168                         tx_load_dma_buffer(info,
1169                                  info->tx_buf,info->tx_count);
1170                 }
1171                 tx_start(info);
1172         }
1173
1174         spin_unlock_irqrestore(&info->lock,flags);
1175 }
1176
1177 /* Discard all data in the send buffer
1178  */
1179 static void flush_buffer(struct tty_struct *tty)
1180 {
1181         SLMP_INFO *info = tty->driver_data;
1182         unsigned long flags;
1183
1184         if (debug_level >= DEBUG_LEVEL_INFO)
1185                 printk("%s(%d):%s flush_buffer() entry\n",
1186                          __FILE__,__LINE__, info->device_name );
1187
1188         if (sanity_check(info, tty->name, "flush_buffer"))
1189                 return;
1190
1191         spin_lock_irqsave(&info->lock,flags);
1192         info->tx_count = info->tx_put = info->tx_get = 0;
1193         del_timer(&info->tx_timer);
1194         spin_unlock_irqrestore(&info->lock,flags);
1195
1196         tty_wakeup(tty);
1197 }
1198
1199 /* throttle (stop) transmitter
1200  */
1201 static void tx_hold(struct tty_struct *tty)
1202 {
1203         SLMP_INFO *info = tty->driver_data;
1204         unsigned long flags;
1205
1206         if (sanity_check(info, tty->name, "tx_hold"))
1207                 return;
1208
1209         if ( debug_level >= DEBUG_LEVEL_INFO )
1210                 printk("%s(%d):%s tx_hold()\n",
1211                         __FILE__,__LINE__,info->device_name);
1212
1213         spin_lock_irqsave(&info->lock,flags);
1214         if (info->tx_enabled)
1215                 tx_stop(info);
1216         spin_unlock_irqrestore(&info->lock,flags);
1217 }
1218
1219 /* release (start) transmitter
1220  */
1221 static void tx_release(struct tty_struct *tty)
1222 {
1223         SLMP_INFO *info = tty->driver_data;
1224         unsigned long flags;
1225
1226         if (sanity_check(info, tty->name, "tx_release"))
1227                 return;
1228
1229         if ( debug_level >= DEBUG_LEVEL_INFO )
1230                 printk("%s(%d):%s tx_release()\n",
1231                         __FILE__,__LINE__,info->device_name);
1232
1233         spin_lock_irqsave(&info->lock,flags);
1234         if (!info->tx_enabled)
1235                 tx_start(info);
1236         spin_unlock_irqrestore(&info->lock,flags);
1237 }
1238
1239 /* Service an IOCTL request
1240  *
1241  * Arguments:
1242  *
1243  *      tty     pointer to tty instance data
1244  *      cmd     IOCTL command code
1245  *      arg     command argument/context
1246  *
1247  * Return Value:        0 if success, otherwise error code
1248  */
1249 static int ioctl(struct tty_struct *tty,
1250                  unsigned int cmd, unsigned long arg)
1251 {
1252         SLMP_INFO *info = tty->driver_data;
1253         void __user *argp = (void __user *)arg;
1254
1255         if (debug_level >= DEBUG_LEVEL_INFO)
1256                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257                         info->device_name, cmd );
1258
1259         if (sanity_check(info, tty->name, "ioctl"))
1260                 return -ENODEV;
1261
1262         if (cmd != TIOCMIWAIT) {
1263                 if (tty_io_error(tty))
1264                     return -EIO;
1265         }
1266
1267         switch (cmd) {
1268         case MGSL_IOCGPARAMS:
1269                 return get_params(info, argp);
1270         case MGSL_IOCSPARAMS:
1271                 return set_params(info, argp);
1272         case MGSL_IOCGTXIDLE:
1273                 return get_txidle(info, argp);
1274         case MGSL_IOCSTXIDLE:
1275                 return set_txidle(info, (int)arg);
1276         case MGSL_IOCTXENABLE:
1277                 return tx_enable(info, (int)arg);
1278         case MGSL_IOCRXENABLE:
1279                 return rx_enable(info, (int)arg);
1280         case MGSL_IOCTXABORT:
1281                 return tx_abort(info);
1282         case MGSL_IOCGSTATS:
1283                 return get_stats(info, argp);
1284         case MGSL_IOCWAITEVENT:
1285                 return wait_mgsl_event(info, argp);
1286         case MGSL_IOCLOOPTXDONE:
1287                 return 0; // TODO: Not supported, need to document
1288                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1289                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1290                  */
1291         case TIOCMIWAIT:
1292                 return modem_input_wait(info,(int)arg);
1293
1294                 /*
1295                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1296                  * Return: write counters to the user passed counter struct
1297                  * NB: both 1->0 and 0->1 transitions are counted except for
1298                  *     RI where only 0->1 is counted.
1299                  */
1300         default:
1301                 return -ENOIOCTLCMD;
1302         }
1303         return 0;
1304 }
1305
1306 static int get_icount(struct tty_struct *tty,
1307                                 struct serial_icounter_struct *icount)
1308 {
1309         SLMP_INFO *info = tty->driver_data;
1310         struct mgsl_icount cnow;        /* kernel counter temps */
1311         unsigned long flags;
1312
1313         spin_lock_irqsave(&info->lock,flags);
1314         cnow = info->icount;
1315         spin_unlock_irqrestore(&info->lock,flags);
1316
1317         icount->cts = cnow.cts;
1318         icount->dsr = cnow.dsr;
1319         icount->rng = cnow.rng;
1320         icount->dcd = cnow.dcd;
1321         icount->rx = cnow.rx;
1322         icount->tx = cnow.tx;
1323         icount->frame = cnow.frame;
1324         icount->overrun = cnow.overrun;
1325         icount->parity = cnow.parity;
1326         icount->brk = cnow.brk;
1327         icount->buf_overrun = cnow.buf_overrun;
1328
1329         return 0;
1330 }
1331
1332 /*
1333  * /proc fs routines....
1334  */
1335
1336 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1337 {
1338         char    stat_buf[30];
1339         unsigned long flags;
1340
1341         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1342                        "\tIRQ=%d MaxFrameSize=%u\n",
1343                 info->device_name,
1344                 info->phys_sca_base,
1345                 info->phys_memory_base,
1346                 info->phys_statctrl_base,
1347                 info->phys_lcr_base,
1348                 info->irq_level,
1349                 info->max_frame_size );
1350
1351         /* output current serial signal states */
1352         spin_lock_irqsave(&info->lock,flags);
1353         get_signals(info);
1354         spin_unlock_irqrestore(&info->lock,flags);
1355
1356         stat_buf[0] = 0;
1357         stat_buf[1] = 0;
1358         if (info->serial_signals & SerialSignal_RTS)
1359                 strcat(stat_buf, "|RTS");
1360         if (info->serial_signals & SerialSignal_CTS)
1361                 strcat(stat_buf, "|CTS");
1362         if (info->serial_signals & SerialSignal_DTR)
1363                 strcat(stat_buf, "|DTR");
1364         if (info->serial_signals & SerialSignal_DSR)
1365                 strcat(stat_buf, "|DSR");
1366         if (info->serial_signals & SerialSignal_DCD)
1367                 strcat(stat_buf, "|CD");
1368         if (info->serial_signals & SerialSignal_RI)
1369                 strcat(stat_buf, "|RI");
1370
1371         if (info->params.mode == MGSL_MODE_HDLC) {
1372                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1373                               info->icount.txok, info->icount.rxok);
1374                 if (info->icount.txunder)
1375                         seq_printf(m, " txunder:%d", info->icount.txunder);
1376                 if (info->icount.txabort)
1377                         seq_printf(m, " txabort:%d", info->icount.txabort);
1378                 if (info->icount.rxshort)
1379                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1380                 if (info->icount.rxlong)
1381                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1382                 if (info->icount.rxover)
1383                         seq_printf(m, " rxover:%d", info->icount.rxover);
1384                 if (info->icount.rxcrc)
1385                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1386         } else {
1387                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1388                               info->icount.tx, info->icount.rx);
1389                 if (info->icount.frame)
1390                         seq_printf(m, " fe:%d", info->icount.frame);
1391                 if (info->icount.parity)
1392                         seq_printf(m, " pe:%d", info->icount.parity);
1393                 if (info->icount.brk)
1394                         seq_printf(m, " brk:%d", info->icount.brk);
1395                 if (info->icount.overrun)
1396                         seq_printf(m, " oe:%d", info->icount.overrun);
1397         }
1398
1399         /* Append serial signal status to end */
1400         seq_printf(m, " %s\n", stat_buf+1);
1401
1402         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1403          info->tx_active,info->bh_requested,info->bh_running,
1404          info->pending_bh);
1405 }
1406
1407 /* Called to print information about devices
1408  */
1409 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1410 {
1411         SLMP_INFO *info;
1412
1413         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1414
1415         info = synclinkmp_device_list;
1416         while( info ) {
1417                 line_info(m, info);
1418                 info = info->next_device;
1419         }
1420         return 0;
1421 }
1422
1423 /* Return the count of bytes in transmit buffer
1424  */
1425 static int chars_in_buffer(struct tty_struct *tty)
1426 {
1427         SLMP_INFO *info = tty->driver_data;
1428
1429         if (sanity_check(info, tty->name, "chars_in_buffer"))
1430                 return 0;
1431
1432         if (debug_level >= DEBUG_LEVEL_INFO)
1433                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1434                        __FILE__, __LINE__, info->device_name, info->tx_count);
1435
1436         return info->tx_count;
1437 }
1438
1439 /* Signal remote device to throttle send data (our receive data)
1440  */
1441 static void throttle(struct tty_struct * tty)
1442 {
1443         SLMP_INFO *info = tty->driver_data;
1444         unsigned long flags;
1445
1446         if (debug_level >= DEBUG_LEVEL_INFO)
1447                 printk("%s(%d):%s throttle() entry\n",
1448                          __FILE__,__LINE__, info->device_name );
1449
1450         if (sanity_check(info, tty->name, "throttle"))
1451                 return;
1452
1453         if (I_IXOFF(tty))
1454                 send_xchar(tty, STOP_CHAR(tty));
1455
1456         if (C_CRTSCTS(tty)) {
1457                 spin_lock_irqsave(&info->lock,flags);
1458                 info->serial_signals &= ~SerialSignal_RTS;
1459                 set_signals(info);
1460                 spin_unlock_irqrestore(&info->lock,flags);
1461         }
1462 }
1463
1464 /* Signal remote device to stop throttling send data (our receive data)
1465  */
1466 static void unthrottle(struct tty_struct * tty)
1467 {
1468         SLMP_INFO *info = tty->driver_data;
1469         unsigned long flags;
1470
1471         if (debug_level >= DEBUG_LEVEL_INFO)
1472                 printk("%s(%d):%s unthrottle() entry\n",
1473                          __FILE__,__LINE__, info->device_name );
1474
1475         if (sanity_check(info, tty->name, "unthrottle"))
1476                 return;
1477
1478         if (I_IXOFF(tty)) {
1479                 if (info->x_char)
1480                         info->x_char = 0;
1481                 else
1482                         send_xchar(tty, START_CHAR(tty));
1483         }
1484
1485         if (C_CRTSCTS(tty)) {
1486                 spin_lock_irqsave(&info->lock,flags);
1487                 info->serial_signals |= SerialSignal_RTS;
1488                 set_signals(info);
1489                 spin_unlock_irqrestore(&info->lock,flags);
1490         }
1491 }
1492
1493 /* set or clear transmit break condition
1494  * break_state  -1=set break condition, 0=clear
1495  */
1496 static int set_break(struct tty_struct *tty, int break_state)
1497 {
1498         unsigned char RegValue;
1499         SLMP_INFO * info = tty->driver_data;
1500         unsigned long flags;
1501
1502         if (debug_level >= DEBUG_LEVEL_INFO)
1503                 printk("%s(%d):%s set_break(%d)\n",
1504                          __FILE__,__LINE__, info->device_name, break_state);
1505
1506         if (sanity_check(info, tty->name, "set_break"))
1507                 return -EINVAL;
1508
1509         spin_lock_irqsave(&info->lock,flags);
1510         RegValue = read_reg(info, CTL);
1511         if (break_state == -1)
1512                 RegValue |= BIT3;
1513         else
1514                 RegValue &= ~BIT3;
1515         write_reg(info, CTL, RegValue);
1516         spin_unlock_irqrestore(&info->lock,flags);
1517         return 0;
1518 }
1519
1520 #if SYNCLINK_GENERIC_HDLC
1521
1522 /**
1523  * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1524  * @dev:      pointer to network device structure
1525  * @encoding: serial encoding setting
1526  * @parity:   FCS setting
1527  *
1528  * Set encoding and frame check sequence (FCS) options.
1529  *
1530  * Return: 0 if success, otherwise error code
1531  */
1532 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1533                           unsigned short parity)
1534 {
1535         SLMP_INFO *info = dev_to_port(dev);
1536         unsigned char  new_encoding;
1537         unsigned short new_crctype;
1538
1539         /* return error if TTY interface open */
1540         if (info->port.count)
1541                 return -EBUSY;
1542
1543         switch (encoding)
1544         {
1545         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1546         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1547         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1548         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1549         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1550         default: return -EINVAL;
1551         }
1552
1553         switch (parity)
1554         {
1555         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1556         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1557         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1558         default: return -EINVAL;
1559         }
1560
1561         info->params.encoding = new_encoding;
1562         info->params.crc_type = new_crctype;
1563
1564         /* if network interface up, reprogram hardware */
1565         if (info->netcount)
1566                 program_hw(info);
1567
1568         return 0;
1569 }
1570
1571 /**
1572  * hdlcdev_xmit - called by generic HDLC layer to send frame
1573  * @skb: socket buffer containing HDLC frame
1574  * @dev: pointer to network device structure
1575  */
1576 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1577                                       struct net_device *dev)
1578 {
1579         SLMP_INFO *info = dev_to_port(dev);
1580         unsigned long flags;
1581
1582         if (debug_level >= DEBUG_LEVEL_INFO)
1583                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1584
1585         /* stop sending until this frame completes */
1586         netif_stop_queue(dev);
1587
1588         /* copy data to device buffers */
1589         info->tx_count = skb->len;
1590         tx_load_dma_buffer(info, skb->data, skb->len);
1591
1592         /* update network statistics */
1593         dev->stats.tx_packets++;
1594         dev->stats.tx_bytes += skb->len;
1595
1596         /* done with socket buffer, so free it */
1597         dev_kfree_skb(skb);
1598
1599         /* save start time for transmit timeout detection */
1600         netif_trans_update(dev);
1601
1602         /* start hardware transmitter if necessary */
1603         spin_lock_irqsave(&info->lock,flags);
1604         if (!info->tx_active)
1605                 tx_start(info);
1606         spin_unlock_irqrestore(&info->lock,flags);
1607
1608         return NETDEV_TX_OK;
1609 }
1610
1611 /**
1612  * hdlcdev_open - called by network layer when interface enabled
1613  * @dev: pointer to network device structure
1614  *
1615  * Claim resources and initialize hardware.
1616  *
1617  * Return: 0 if success, otherwise error code
1618  */
1619 static int hdlcdev_open(struct net_device *dev)
1620 {
1621         SLMP_INFO *info = dev_to_port(dev);
1622         int rc;
1623         unsigned long flags;
1624
1625         if (debug_level >= DEBUG_LEVEL_INFO)
1626                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1627
1628         /* generic HDLC layer open processing */
1629         rc = hdlc_open(dev);
1630         if (rc)
1631                 return rc;
1632
1633         /* arbitrate between network and tty opens */
1634         spin_lock_irqsave(&info->netlock, flags);
1635         if (info->port.count != 0 || info->netcount != 0) {
1636                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1637                 spin_unlock_irqrestore(&info->netlock, flags);
1638                 return -EBUSY;
1639         }
1640         info->netcount=1;
1641         spin_unlock_irqrestore(&info->netlock, flags);
1642
1643         /* claim resources and init adapter */
1644         if ((rc = startup(info)) != 0) {
1645                 spin_lock_irqsave(&info->netlock, flags);
1646                 info->netcount=0;
1647                 spin_unlock_irqrestore(&info->netlock, flags);
1648                 return rc;
1649         }
1650
1651         /* assert RTS and DTR, apply hardware settings */
1652         info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1653         program_hw(info);
1654
1655         /* enable network layer transmit */
1656         netif_trans_update(dev);
1657         netif_start_queue(dev);
1658
1659         /* inform generic HDLC layer of current DCD status */
1660         spin_lock_irqsave(&info->lock, flags);
1661         get_signals(info);
1662         spin_unlock_irqrestore(&info->lock, flags);
1663         if (info->serial_signals & SerialSignal_DCD)
1664                 netif_carrier_on(dev);
1665         else
1666                 netif_carrier_off(dev);
1667         return 0;
1668 }
1669
1670 /**
1671  * hdlcdev_close - called by network layer when interface is disabled
1672  * @dev: pointer to network device structure
1673  *
1674  * Shutdown hardware and release resources.
1675  *
1676  * Return: 0 if success, otherwise error code
1677  */
1678 static int hdlcdev_close(struct net_device *dev)
1679 {
1680         SLMP_INFO *info = dev_to_port(dev);
1681         unsigned long flags;
1682
1683         if (debug_level >= DEBUG_LEVEL_INFO)
1684                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1685
1686         netif_stop_queue(dev);
1687
1688         /* shutdown adapter and release resources */
1689         shutdown(info);
1690
1691         hdlc_close(dev);
1692
1693         spin_lock_irqsave(&info->netlock, flags);
1694         info->netcount=0;
1695         spin_unlock_irqrestore(&info->netlock, flags);
1696
1697         return 0;
1698 }
1699
1700 /**
1701  * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1702  * @dev: pointer to network device structure
1703  * @ifr: pointer to network interface request structure
1704  * @cmd: IOCTL command code
1705  *
1706  * Return: 0 if success, otherwise error code
1707  */
1708 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1709 {
1710         const size_t size = sizeof(sync_serial_settings);
1711         sync_serial_settings new_line;
1712         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1713         SLMP_INFO *info = dev_to_port(dev);
1714         unsigned int flags;
1715
1716         if (debug_level >= DEBUG_LEVEL_INFO)
1717                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1718
1719         /* return error if TTY interface open */
1720         if (info->port.count)
1721                 return -EBUSY;
1722
1723         if (cmd != SIOCWANDEV)
1724                 return hdlc_ioctl(dev, ifr, cmd);
1725
1726         switch(ifr->ifr_settings.type) {
1727         case IF_GET_IFACE: /* return current sync_serial_settings */
1728
1729                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1730                 if (ifr->ifr_settings.size < size) {
1731                         ifr->ifr_settings.size = size; /* data size wanted */
1732                         return -ENOBUFS;
1733                 }
1734
1735                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1736                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1737                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1738                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1739
1740                 memset(&new_line, 0, sizeof(new_line));
1741                 switch (flags){
1742                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1743                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1744                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1745                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1746                 default: new_line.clock_type = CLOCK_DEFAULT;
1747                 }
1748
1749                 new_line.clock_rate = info->params.clock_speed;
1750                 new_line.loopback   = info->params.loopback ? 1:0;
1751
1752                 if (copy_to_user(line, &new_line, size))
1753                         return -EFAULT;
1754                 return 0;
1755
1756         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1757
1758                 if(!capable(CAP_NET_ADMIN))
1759                         return -EPERM;
1760                 if (copy_from_user(&new_line, line, size))
1761                         return -EFAULT;
1762
1763                 switch (new_line.clock_type)
1764                 {
1765                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1766                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1767                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1768                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1769                 case CLOCK_DEFAULT:  flags = info->params.flags &
1770                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1771                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1772                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1773                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1774                 default: return -EINVAL;
1775                 }
1776
1777                 if (new_line.loopback != 0 && new_line.loopback != 1)
1778                         return -EINVAL;
1779
1780                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1781                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1782                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1783                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1784                 info->params.flags |= flags;
1785
1786                 info->params.loopback = new_line.loopback;
1787
1788                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1789                         info->params.clock_speed = new_line.clock_rate;
1790                 else
1791                         info->params.clock_speed = 0;
1792
1793                 /* if network interface up, reprogram hardware */
1794                 if (info->netcount)
1795                         program_hw(info);
1796                 return 0;
1797
1798         default:
1799                 return hdlc_ioctl(dev, ifr, cmd);
1800         }
1801 }
1802
1803 /**
1804  * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1805  * @dev: pointer to network device structure
1806  */
1807 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1808 {
1809         SLMP_INFO *info = dev_to_port(dev);
1810         unsigned long flags;
1811
1812         if (debug_level >= DEBUG_LEVEL_INFO)
1813                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1814
1815         dev->stats.tx_errors++;
1816         dev->stats.tx_aborted_errors++;
1817
1818         spin_lock_irqsave(&info->lock,flags);
1819         tx_stop(info);
1820         spin_unlock_irqrestore(&info->lock,flags);
1821
1822         netif_wake_queue(dev);
1823 }
1824
1825 /**
1826  * hdlcdev_tx_done - called by device driver when transmit completes
1827  * @info: pointer to device instance information
1828  *
1829  * Reenable network layer transmit if stopped.
1830  */
1831 static void hdlcdev_tx_done(SLMP_INFO *info)
1832 {
1833         if (netif_queue_stopped(info->netdev))
1834                 netif_wake_queue(info->netdev);
1835 }
1836
1837 /**
1838  * hdlcdev_rx - called by device driver when frame received
1839  * @info: pointer to device instance information
1840  * @buf:  pointer to buffer contianing frame data
1841  * @size: count of data bytes in buf
1842  *
1843  * Pass frame to network layer.
1844  */
1845 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1846 {
1847         struct sk_buff *skb = dev_alloc_skb(size);
1848         struct net_device *dev = info->netdev;
1849
1850         if (debug_level >= DEBUG_LEVEL_INFO)
1851                 printk("hdlcdev_rx(%s)\n",dev->name);
1852
1853         if (skb == NULL) {
1854                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1855                        dev->name);
1856                 dev->stats.rx_dropped++;
1857                 return;
1858         }
1859
1860         skb_put_data(skb, buf, size);
1861
1862         skb->protocol = hdlc_type_trans(skb, dev);
1863
1864         dev->stats.rx_packets++;
1865         dev->stats.rx_bytes += size;
1866
1867         netif_rx(skb);
1868 }
1869
1870 static const struct net_device_ops hdlcdev_ops = {
1871         .ndo_open       = hdlcdev_open,
1872         .ndo_stop       = hdlcdev_close,
1873         .ndo_start_xmit = hdlc_start_xmit,
1874         .ndo_do_ioctl   = hdlcdev_ioctl,
1875         .ndo_tx_timeout = hdlcdev_tx_timeout,
1876 };
1877
1878 /**
1879  * hdlcdev_init - called by device driver when adding device instance
1880  * @info: pointer to device instance information
1881  *
1882  * Do generic HDLC initialization.
1883  *
1884  * Return: 0 if success, otherwise error code
1885  */
1886 static int hdlcdev_init(SLMP_INFO *info)
1887 {
1888         int rc;
1889         struct net_device *dev;
1890         hdlc_device *hdlc;
1891
1892         /* allocate and initialize network and HDLC layer objects */
1893
1894         dev = alloc_hdlcdev(info);
1895         if (!dev) {
1896                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1897                 return -ENOMEM;
1898         }
1899
1900         /* for network layer reporting purposes only */
1901         dev->mem_start = info->phys_sca_base;
1902         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1903         dev->irq       = info->irq_level;
1904
1905         /* network layer callbacks and settings */
1906         dev->netdev_ops     = &hdlcdev_ops;
1907         dev->watchdog_timeo = 10 * HZ;
1908         dev->tx_queue_len   = 50;
1909
1910         /* generic HDLC layer callbacks and settings */
1911         hdlc         = dev_to_hdlc(dev);
1912         hdlc->attach = hdlcdev_attach;
1913         hdlc->xmit   = hdlcdev_xmit;
1914
1915         /* register objects with HDLC layer */
1916         rc = register_hdlc_device(dev);
1917         if (rc) {
1918                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1919                 free_netdev(dev);
1920                 return rc;
1921         }
1922
1923         info->netdev = dev;
1924         return 0;
1925 }
1926
1927 /**
1928  * hdlcdev_exit - called by device driver when removing device instance
1929  * @info: pointer to device instance information
1930  *
1931  * Do generic HDLC cleanup.
1932  */
1933 static void hdlcdev_exit(SLMP_INFO *info)
1934 {
1935         unregister_hdlc_device(info->netdev);
1936         free_netdev(info->netdev);
1937         info->netdev = NULL;
1938 }
1939
1940 #endif /* CONFIG_HDLC */
1941
1942
1943 /* Return next bottom half action to perform.
1944  * Return Value:        BH action code or 0 if nothing to do.
1945  */
1946 static int bh_action(SLMP_INFO *info)
1947 {
1948         unsigned long flags;
1949         int rc = 0;
1950
1951         spin_lock_irqsave(&info->lock,flags);
1952
1953         if (info->pending_bh & BH_RECEIVE) {
1954                 info->pending_bh &= ~BH_RECEIVE;
1955                 rc = BH_RECEIVE;
1956         } else if (info->pending_bh & BH_TRANSMIT) {
1957                 info->pending_bh &= ~BH_TRANSMIT;
1958                 rc = BH_TRANSMIT;
1959         } else if (info->pending_bh & BH_STATUS) {
1960                 info->pending_bh &= ~BH_STATUS;
1961                 rc = BH_STATUS;
1962         }
1963
1964         if (!rc) {
1965                 /* Mark BH routine as complete */
1966                 info->bh_running = false;
1967                 info->bh_requested = false;
1968         }
1969
1970         spin_unlock_irqrestore(&info->lock,flags);
1971
1972         return rc;
1973 }
1974
1975 /* Perform bottom half processing of work items queued by ISR.
1976  */
1977 static void bh_handler(struct work_struct *work)
1978 {
1979         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1980         int action;
1981
1982         if ( debug_level >= DEBUG_LEVEL_BH )
1983                 printk( "%s(%d):%s bh_handler() entry\n",
1984                         __FILE__,__LINE__,info->device_name);
1985
1986         info->bh_running = true;
1987
1988         while((action = bh_action(info)) != 0) {
1989
1990                 /* Process work item */
1991                 if ( debug_level >= DEBUG_LEVEL_BH )
1992                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
1993                                 __FILE__,__LINE__,info->device_name, action);
1994
1995                 switch (action) {
1996
1997                 case BH_RECEIVE:
1998                         bh_receive(info);
1999                         break;
2000                 case BH_TRANSMIT:
2001                         bh_transmit(info);
2002                         break;
2003                 case BH_STATUS:
2004                         bh_status(info);
2005                         break;
2006                 default:
2007                         /* unknown work item ID */
2008                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2009                                 __FILE__,__LINE__,info->device_name,action);
2010                         break;
2011                 }
2012         }
2013
2014         if ( debug_level >= DEBUG_LEVEL_BH )
2015                 printk( "%s(%d):%s bh_handler() exit\n",
2016                         __FILE__,__LINE__,info->device_name);
2017 }
2018
2019 static void bh_receive(SLMP_INFO *info)
2020 {
2021         if ( debug_level >= DEBUG_LEVEL_BH )
2022                 printk( "%s(%d):%s bh_receive()\n",
2023                         __FILE__,__LINE__,info->device_name);
2024
2025         while( rx_get_frame(info) );
2026 }
2027
2028 static void bh_transmit(SLMP_INFO *info)
2029 {
2030         struct tty_struct *tty = info->port.tty;
2031
2032         if ( debug_level >= DEBUG_LEVEL_BH )
2033                 printk( "%s(%d):%s bh_transmit() entry\n",
2034                         __FILE__,__LINE__,info->device_name);
2035
2036         if (tty)
2037                 tty_wakeup(tty);
2038 }
2039
2040 static void bh_status(SLMP_INFO *info)
2041 {
2042         if ( debug_level >= DEBUG_LEVEL_BH )
2043                 printk( "%s(%d):%s bh_status() entry\n",
2044                         __FILE__,__LINE__,info->device_name);
2045
2046         info->ri_chkcount = 0;
2047         info->dsr_chkcount = 0;
2048         info->dcd_chkcount = 0;
2049         info->cts_chkcount = 0;
2050 }
2051
2052 static void isr_timer(SLMP_INFO * info)
2053 {
2054         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2055
2056         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2057         write_reg(info, IER2, 0);
2058
2059         /* TMCS, Timer Control/Status Register
2060          *
2061          * 07      CMF, Compare match flag (read only) 1=match
2062          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2063          * 05      Reserved, must be 0
2064          * 04      TME, Timer Enable
2065          * 03..00  Reserved, must be 0
2066          *
2067          * 0000 0000
2068          */
2069         write_reg(info, (unsigned char)(timer + TMCS), 0);
2070
2071         info->irq_occurred = true;
2072
2073         if ( debug_level >= DEBUG_LEVEL_ISR )
2074                 printk("%s(%d):%s isr_timer()\n",
2075                         __FILE__,__LINE__,info->device_name);
2076 }
2077
2078 static void isr_rxint(SLMP_INFO * info)
2079 {
2080         struct tty_struct *tty = info->port.tty;
2081         struct  mgsl_icount *icount = &info->icount;
2082         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2083         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2084
2085         /* clear status bits */
2086         if (status)
2087                 write_reg(info, SR1, status);
2088
2089         if (status2)
2090                 write_reg(info, SR2, status2);
2091
2092         if ( debug_level >= DEBUG_LEVEL_ISR )
2093                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2094                         __FILE__,__LINE__,info->device_name,status,status2);
2095
2096         if (info->params.mode == MGSL_MODE_ASYNC) {
2097                 if (status & BRKD) {
2098                         icount->brk++;
2099
2100                         /* process break detection if tty control
2101                          * is not set to ignore it
2102                          */
2103                         if (!(status & info->ignore_status_mask1)) {
2104                                 if (info->read_status_mask1 & BRKD) {
2105                                         tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2106                                         if (tty && (info->port.flags & ASYNC_SAK))
2107                                                 do_SAK(tty);
2108                                 }
2109                         }
2110                 }
2111         }
2112         else {
2113                 if (status & (FLGD|IDLD)) {
2114                         if (status & FLGD)
2115                                 info->icount.exithunt++;
2116                         else if (status & IDLD)
2117                                 info->icount.rxidle++;
2118                         wake_up_interruptible(&info->event_wait_q);
2119                 }
2120         }
2121
2122         if (status & CDCD) {
2123                 /* simulate a common modem status change interrupt
2124                  * for our handler
2125                  */
2126                 get_signals( info );
2127                 isr_io_pin(info,
2128                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2129         }
2130 }
2131
2132 /*
2133  * handle async rx data interrupts
2134  */
2135 static void isr_rxrdy(SLMP_INFO * info)
2136 {
2137         u16 status;
2138         unsigned char DataByte;
2139         struct  mgsl_icount *icount = &info->icount;
2140
2141         if ( debug_level >= DEBUG_LEVEL_ISR )
2142                 printk("%s(%d):%s isr_rxrdy\n",
2143                         __FILE__,__LINE__,info->device_name);
2144
2145         while((status = read_reg(info,CST0)) & BIT0)
2146         {
2147                 int flag = 0;
2148                 bool over = false;
2149                 DataByte = read_reg(info,TRB);
2150
2151                 icount->rx++;
2152
2153                 if ( status & (PE + FRME + OVRN) ) {
2154                         printk("%s(%d):%s rxerr=%04X\n",
2155                                 __FILE__,__LINE__,info->device_name,status);
2156
2157                         /* update error statistics */
2158                         if (status & PE)
2159                                 icount->parity++;
2160                         else if (status & FRME)
2161                                 icount->frame++;
2162                         else if (status & OVRN)
2163                                 icount->overrun++;
2164
2165                         /* discard char if tty control flags say so */
2166                         if (status & info->ignore_status_mask2)
2167                                 continue;
2168
2169                         status &= info->read_status_mask2;
2170
2171                         if (status & PE)
2172                                 flag = TTY_PARITY;
2173                         else if (status & FRME)
2174                                 flag = TTY_FRAME;
2175                         if (status & OVRN) {
2176                                 /* Overrun is special, since it's
2177                                  * reported immediately, and doesn't
2178                                  * affect the current character
2179                                  */
2180                                 over = true;
2181                         }
2182                 }       /* end of if (error) */
2183
2184                 tty_insert_flip_char(&info->port, DataByte, flag);
2185                 if (over)
2186                         tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2187         }
2188
2189         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2190                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2191                         __FILE__,__LINE__,info->device_name,
2192                         icount->rx,icount->brk,icount->parity,
2193                         icount->frame,icount->overrun);
2194         }
2195
2196         tty_flip_buffer_push(&info->port);
2197 }
2198
2199 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2200 {
2201         if ( debug_level >= DEBUG_LEVEL_ISR )
2202                 printk("%s(%d):%s isr_txeom status=%02x\n",
2203                         __FILE__,__LINE__,info->device_name,status);
2204
2205         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2206         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2207         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2208
2209         if (status & UDRN) {
2210                 write_reg(info, CMD, TXRESET);
2211                 write_reg(info, CMD, TXENABLE);
2212         } else
2213                 write_reg(info, CMD, TXBUFCLR);
2214
2215         /* disable and clear tx interrupts */
2216         info->ie0_value &= ~TXRDYE;
2217         info->ie1_value &= ~(IDLE + UDRN);
2218         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2219         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2220
2221         if ( info->tx_active ) {
2222                 if (info->params.mode != MGSL_MODE_ASYNC) {
2223                         if (status & UDRN)
2224                                 info->icount.txunder++;
2225                         else if (status & IDLE)
2226                                 info->icount.txok++;
2227                 }
2228
2229                 info->tx_active = false;
2230                 info->tx_count = info->tx_put = info->tx_get = 0;
2231
2232                 del_timer(&info->tx_timer);
2233
2234                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2235                         info->serial_signals &= ~SerialSignal_RTS;
2236                         info->drop_rts_on_tx_done = false;
2237                         set_signals(info);
2238                 }
2239
2240 #if SYNCLINK_GENERIC_HDLC
2241                 if (info->netcount)
2242                         hdlcdev_tx_done(info);
2243                 else
2244 #endif
2245                 {
2246                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2247                                 tx_stop(info);
2248                                 return;
2249                         }
2250                         info->pending_bh |= BH_TRANSMIT;
2251                 }
2252         }
2253 }
2254
2255
2256 /*
2257  * handle tx status interrupts
2258  */
2259 static void isr_txint(SLMP_INFO * info)
2260 {
2261         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2262
2263         /* clear status bits */
2264         write_reg(info, SR1, status);
2265
2266         if ( debug_level >= DEBUG_LEVEL_ISR )
2267                 printk("%s(%d):%s isr_txint status=%02x\n",
2268                         __FILE__,__LINE__,info->device_name,status);
2269
2270         if (status & (UDRN + IDLE))
2271                 isr_txeom(info, status);
2272
2273         if (status & CCTS) {
2274                 /* simulate a common modem status change interrupt
2275                  * for our handler
2276                  */
2277                 get_signals( info );
2278                 isr_io_pin(info,
2279                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2280
2281         }
2282 }
2283
2284 /*
2285  * handle async tx data interrupts
2286  */
2287 static void isr_txrdy(SLMP_INFO * info)
2288 {
2289         if ( debug_level >= DEBUG_LEVEL_ISR )
2290                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2291                         __FILE__,__LINE__,info->device_name,info->tx_count);
2292
2293         if (info->params.mode != MGSL_MODE_ASYNC) {
2294                 /* disable TXRDY IRQ, enable IDLE IRQ */
2295                 info->ie0_value &= ~TXRDYE;
2296                 info->ie1_value |= IDLE;
2297                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2298                 return;
2299         }
2300
2301         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2302                 tx_stop(info);
2303                 return;
2304         }
2305
2306         if ( info->tx_count )
2307                 tx_load_fifo( info );
2308         else {
2309                 info->tx_active = false;
2310                 info->ie0_value &= ~TXRDYE;
2311                 write_reg(info, IE0, info->ie0_value);
2312         }
2313
2314         if (info->tx_count < WAKEUP_CHARS)
2315                 info->pending_bh |= BH_TRANSMIT;
2316 }
2317
2318 static void isr_rxdmaok(SLMP_INFO * info)
2319 {
2320         /* BIT7 = EOT (end of transfer)
2321          * BIT6 = EOM (end of message/frame)
2322          */
2323         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2324
2325         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2326         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2327
2328         if ( debug_level >= DEBUG_LEVEL_ISR )
2329                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2330                         __FILE__,__LINE__,info->device_name,status);
2331
2332         info->pending_bh |= BH_RECEIVE;
2333 }
2334
2335 static void isr_rxdmaerror(SLMP_INFO * info)
2336 {
2337         /* BIT5 = BOF (buffer overflow)
2338          * BIT4 = COF (counter overflow)
2339          */
2340         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2341
2342         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2343         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2344
2345         if ( debug_level >= DEBUG_LEVEL_ISR )
2346                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2347                         __FILE__,__LINE__,info->device_name,status);
2348
2349         info->rx_overflow = true;
2350         info->pending_bh |= BH_RECEIVE;
2351 }
2352
2353 static void isr_txdmaok(SLMP_INFO * info)
2354 {
2355         unsigned char status_reg1 = read_reg(info, SR1);
2356
2357         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2358         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2359         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2360
2361         if ( debug_level >= DEBUG_LEVEL_ISR )
2362                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2363                         __FILE__,__LINE__,info->device_name,status_reg1);
2364
2365         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2366         write_reg16(info, TRC0, 0);
2367         info->ie0_value |= TXRDYE;
2368         write_reg(info, IE0, info->ie0_value);
2369 }
2370
2371 static void isr_txdmaerror(SLMP_INFO * info)
2372 {
2373         /* BIT5 = BOF (buffer overflow)
2374          * BIT4 = COF (counter overflow)
2375          */
2376         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2377
2378         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2379         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2380
2381         if ( debug_level >= DEBUG_LEVEL_ISR )
2382                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2383                         __FILE__,__LINE__,info->device_name,status);
2384 }
2385
2386 /* handle input serial signal changes
2387  */
2388 static void isr_io_pin( SLMP_INFO *info, u16 status )
2389 {
2390         struct  mgsl_icount *icount;
2391
2392         if ( debug_level >= DEBUG_LEVEL_ISR )
2393                 printk("%s(%d):isr_io_pin status=%04X\n",
2394                         __FILE__,__LINE__,status);
2395
2396         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2397                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2398                 icount = &info->icount;
2399                 /* update input line counters */
2400                 if (status & MISCSTATUS_RI_LATCHED) {
2401                         icount->rng++;
2402                         if ( status & SerialSignal_RI )
2403                                 info->input_signal_events.ri_up++;
2404                         else
2405                                 info->input_signal_events.ri_down++;
2406                 }
2407                 if (status & MISCSTATUS_DSR_LATCHED) {
2408                         icount->dsr++;
2409                         if ( status & SerialSignal_DSR )
2410                                 info->input_signal_events.dsr_up++;
2411                         else
2412                                 info->input_signal_events.dsr_down++;
2413                 }
2414                 if (status & MISCSTATUS_DCD_LATCHED) {
2415                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2416                                 info->ie1_value &= ~CDCD;
2417                                 write_reg(info, IE1, info->ie1_value);
2418                         }
2419                         icount->dcd++;
2420                         if (status & SerialSignal_DCD) {
2421                                 info->input_signal_events.dcd_up++;
2422                         } else
2423                                 info->input_signal_events.dcd_down++;
2424 #if SYNCLINK_GENERIC_HDLC
2425                         if (info->netcount) {
2426                                 if (status & SerialSignal_DCD)
2427                                         netif_carrier_on(info->netdev);
2428                                 else
2429                                         netif_carrier_off(info->netdev);
2430                         }
2431 #endif
2432                 }
2433                 if (status & MISCSTATUS_CTS_LATCHED)
2434                 {
2435                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2436                                 info->ie1_value &= ~CCTS;
2437                                 write_reg(info, IE1, info->ie1_value);
2438                         }
2439                         icount->cts++;
2440                         if ( status & SerialSignal_CTS )
2441                                 info->input_signal_events.cts_up++;
2442                         else
2443                                 info->input_signal_events.cts_down++;
2444                 }
2445                 wake_up_interruptible(&info->status_event_wait_q);
2446                 wake_up_interruptible(&info->event_wait_q);
2447
2448                 if (tty_port_check_carrier(&info->port) &&
2449                      (status & MISCSTATUS_DCD_LATCHED) ) {
2450                         if ( debug_level >= DEBUG_LEVEL_ISR )
2451                                 printk("%s CD now %s...", info->device_name,
2452                                        (status & SerialSignal_DCD) ? "on" : "off");
2453                         if (status & SerialSignal_DCD)
2454                                 wake_up_interruptible(&info->port.open_wait);
2455                         else {
2456                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2457                                         printk("doing serial hangup...");
2458                                 if (info->port.tty)
2459                                         tty_hangup(info->port.tty);
2460                         }
2461                 }
2462
2463                 if (tty_port_cts_enabled(&info->port) &&
2464                      (status & MISCSTATUS_CTS_LATCHED) ) {
2465                         if ( info->port.tty ) {
2466                                 if (info->port.tty->hw_stopped) {
2467                                         if (status & SerialSignal_CTS) {
2468                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2469                                                         printk("CTS tx start...");
2470                                                 info->port.tty->hw_stopped = 0;
2471                                                 tx_start(info);
2472                                                 info->pending_bh |= BH_TRANSMIT;
2473                                                 return;
2474                                         }
2475                                 } else {
2476                                         if (!(status & SerialSignal_CTS)) {
2477                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2478                                                         printk("CTS tx stop...");
2479                                                 info->port.tty->hw_stopped = 1;
2480                                                 tx_stop(info);
2481                                         }
2482                                 }
2483                         }
2484                 }
2485         }
2486
2487         info->pending_bh |= BH_STATUS;
2488 }
2489
2490 /* Interrupt service routine entry point.
2491  *
2492  * Arguments:
2493  *      irq             interrupt number that caused interrupt
2494  *      dev_id          device ID supplied during interrupt registration
2495  *      regs            interrupted processor context
2496  */
2497 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2498 {
2499         SLMP_INFO *info = dev_id;
2500         unsigned char status, status0, status1=0;
2501         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2502         unsigned char timerstatus0, timerstatus1=0;
2503         unsigned char shift;
2504         unsigned int i;
2505         unsigned short tmp;
2506
2507         if ( debug_level >= DEBUG_LEVEL_ISR )
2508                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2509                         __FILE__, __LINE__, info->irq_level);
2510
2511         spin_lock(&info->lock);
2512
2513         for(;;) {
2514
2515                 /* get status for SCA0 (ports 0-1) */
2516                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2517                 status0 = (unsigned char)tmp;
2518                 dmastatus0 = (unsigned char)(tmp>>8);
2519                 timerstatus0 = read_reg(info, ISR2);
2520
2521                 if ( debug_level >= DEBUG_LEVEL_ISR )
2522                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2523                                 __FILE__, __LINE__, info->device_name,
2524                                 status0, dmastatus0, timerstatus0);
2525
2526                 if (info->port_count == 4) {
2527                         /* get status for SCA1 (ports 2-3) */
2528                         tmp = read_reg16(info->port_array[2], ISR0);
2529                         status1 = (unsigned char)tmp;
2530                         dmastatus1 = (unsigned char)(tmp>>8);
2531                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2532
2533                         if ( debug_level >= DEBUG_LEVEL_ISR )
2534                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2535                                         __FILE__,__LINE__,info->device_name,
2536                                         status1,dmastatus1,timerstatus1);
2537                 }
2538
2539                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2540                          !status1 && !dmastatus1 && !timerstatus1)
2541                         break;
2542
2543                 for(i=0; i < info->port_count ; i++) {
2544                         if (info->port_array[i] == NULL)
2545                                 continue;
2546                         if (i < 2) {
2547                                 status = status0;
2548                                 dmastatus = dmastatus0;
2549                         } else {
2550                                 status = status1;
2551                                 dmastatus = dmastatus1;
2552                         }
2553
2554                         shift = i & 1 ? 4 :0;
2555
2556                         if (status & BIT0 << shift)
2557                                 isr_rxrdy(info->port_array[i]);
2558                         if (status & BIT1 << shift)
2559                                 isr_txrdy(info->port_array[i]);
2560                         if (status & BIT2 << shift)
2561                                 isr_rxint(info->port_array[i]);
2562                         if (status & BIT3 << shift)
2563                                 isr_txint(info->port_array[i]);
2564
2565                         if (dmastatus & BIT0 << shift)
2566                                 isr_rxdmaerror(info->port_array[i]);
2567                         if (dmastatus & BIT1 << shift)
2568                                 isr_rxdmaok(info->port_array[i]);
2569                         if (dmastatus & BIT2 << shift)
2570                                 isr_txdmaerror(info->port_array[i]);
2571                         if (dmastatus & BIT3 << shift)
2572                                 isr_txdmaok(info->port_array[i]);
2573                 }
2574
2575                 if (timerstatus0 & (BIT5 | BIT4))
2576                         isr_timer(info->port_array[0]);
2577                 if (timerstatus0 & (BIT7 | BIT6))
2578                         isr_timer(info->port_array[1]);
2579                 if (timerstatus1 & (BIT5 | BIT4))
2580                         isr_timer(info->port_array[2]);
2581                 if (timerstatus1 & (BIT7 | BIT6))
2582                         isr_timer(info->port_array[3]);
2583         }
2584
2585         for(i=0; i < info->port_count ; i++) {
2586                 SLMP_INFO * port = info->port_array[i];
2587
2588                 /* Request bottom half processing if there's something
2589                  * for it to do and the bh is not already running.
2590                  *
2591                  * Note: startup adapter diags require interrupts.
2592                  * do not request bottom half processing if the
2593                  * device is not open in a normal mode.
2594                  */
2595                 if ( port && (port->port.count || port->netcount) &&
2596                      port->pending_bh && !port->bh_running &&
2597                      !port->bh_requested ) {
2598                         if ( debug_level >= DEBUG_LEVEL_ISR )
2599                                 printk("%s(%d):%s queueing bh task.\n",
2600                                         __FILE__,__LINE__,port->device_name);
2601                         schedule_work(&port->task);
2602                         port->bh_requested = true;
2603                 }
2604         }
2605
2606         spin_unlock(&info->lock);
2607
2608         if ( debug_level >= DEBUG_LEVEL_ISR )
2609                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2610                         __FILE__, __LINE__, info->irq_level);
2611         return IRQ_HANDLED;
2612 }
2613
2614 /* Initialize and start device.
2615  */
2616 static int startup(SLMP_INFO * info)
2617 {
2618         if ( debug_level >= DEBUG_LEVEL_INFO )
2619                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2620
2621         if (tty_port_initialized(&info->port))
2622                 return 0;
2623
2624         if (!info->tx_buf) {
2625                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2626                 if (!info->tx_buf) {
2627                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2628                                 __FILE__,__LINE__,info->device_name);
2629                         return -ENOMEM;
2630                 }
2631         }
2632
2633         info->pending_bh = 0;
2634
2635         memset(&info->icount, 0, sizeof(info->icount));
2636
2637         /* program hardware for current parameters */
2638         reset_port(info);
2639
2640         change_params(info);
2641
2642         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2643
2644         if (info->port.tty)
2645                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2646
2647         tty_port_set_initialized(&info->port, 1);
2648
2649         return 0;
2650 }
2651
2652 /* Called by close() and hangup() to shutdown hardware
2653  */
2654 static void shutdown(SLMP_INFO * info)
2655 {
2656         unsigned long flags;
2657
2658         if (!tty_port_initialized(&info->port))
2659                 return;
2660
2661         if (debug_level >= DEBUG_LEVEL_INFO)
2662                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2663                          __FILE__,__LINE__, info->device_name );
2664
2665         /* clear status wait queue because status changes */
2666         /* can't happen after shutting down the hardware */
2667         wake_up_interruptible(&info->status_event_wait_q);
2668         wake_up_interruptible(&info->event_wait_q);
2669
2670         del_timer(&info->tx_timer);
2671         del_timer(&info->status_timer);
2672
2673         kfree(info->tx_buf);
2674         info->tx_buf = NULL;
2675
2676         spin_lock_irqsave(&info->lock,flags);
2677
2678         reset_port(info);
2679
2680         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2681                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2682                 set_signals(info);
2683         }
2684
2685         spin_unlock_irqrestore(&info->lock,flags);
2686
2687         if (info->port.tty)
2688                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2689
2690         tty_port_set_initialized(&info->port, 0);
2691 }
2692
2693 static void program_hw(SLMP_INFO *info)
2694 {
2695         unsigned long flags;
2696
2697         spin_lock_irqsave(&info->lock,flags);
2698
2699         rx_stop(info);
2700         tx_stop(info);
2701
2702         info->tx_count = info->tx_put = info->tx_get = 0;
2703
2704         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2705                 hdlc_mode(info);
2706         else
2707                 async_mode(info);
2708
2709         set_signals(info);
2710
2711         info->dcd_chkcount = 0;
2712         info->cts_chkcount = 0;
2713         info->ri_chkcount = 0;
2714         info->dsr_chkcount = 0;
2715
2716         info->ie1_value |= (CDCD|CCTS);
2717         write_reg(info, IE1, info->ie1_value);
2718
2719         get_signals(info);
2720
2721         if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2722                 rx_start(info);
2723
2724         spin_unlock_irqrestore(&info->lock,flags);
2725 }
2726
2727 /* Reconfigure adapter based on new parameters
2728  */
2729 static void change_params(SLMP_INFO *info)
2730 {
2731         unsigned cflag;
2732         int bits_per_char;
2733
2734         if (!info->port.tty)
2735                 return;
2736
2737         if (debug_level >= DEBUG_LEVEL_INFO)
2738                 printk("%s(%d):%s change_params()\n",
2739                          __FILE__,__LINE__, info->device_name );
2740
2741         cflag = info->port.tty->termios.c_cflag;
2742
2743         /* if B0 rate (hangup) specified then negate RTS and DTR */
2744         /* otherwise assert RTS and DTR */
2745         if (cflag & CBAUD)
2746                 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2747         else
2748                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2749
2750         /* byte size and parity */
2751
2752         switch (cflag & CSIZE) {
2753               case CS5: info->params.data_bits = 5; break;
2754               case CS6: info->params.data_bits = 6; break;
2755               case CS7: info->params.data_bits = 7; break;
2756               case CS8: info->params.data_bits = 8; break;
2757               /* Never happens, but GCC is too dumb to figure it out */
2758               default:  info->params.data_bits = 7; break;
2759               }
2760
2761         if (cflag & CSTOPB)
2762                 info->params.stop_bits = 2;
2763         else
2764                 info->params.stop_bits = 1;
2765
2766         info->params.parity = ASYNC_PARITY_NONE;
2767         if (cflag & PARENB) {
2768                 if (cflag & PARODD)
2769                         info->params.parity = ASYNC_PARITY_ODD;
2770                 else
2771                         info->params.parity = ASYNC_PARITY_EVEN;
2772 #ifdef CMSPAR
2773                 if (cflag & CMSPAR)
2774                         info->params.parity = ASYNC_PARITY_SPACE;
2775 #endif
2776         }
2777
2778         /* calculate number of jiffies to transmit a full
2779          * FIFO (32 bytes) at specified data rate
2780          */
2781         bits_per_char = info->params.data_bits +
2782                         info->params.stop_bits + 1;
2783
2784         /* if port data rate is set to 460800 or less then
2785          * allow tty settings to override, otherwise keep the
2786          * current data rate.
2787          */
2788         if (info->params.data_rate <= 460800) {
2789                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2790         }
2791
2792         if ( info->params.data_rate ) {
2793                 info->timeout = (32*HZ*bits_per_char) /
2794                                 info->params.data_rate;
2795         }
2796         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2797
2798         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2799         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2800
2801         /* process tty input control flags */
2802
2803         info->read_status_mask2 = OVRN;
2804         if (I_INPCK(info->port.tty))
2805                 info->read_status_mask2 |= PE | FRME;
2806         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2807                 info->read_status_mask1 |= BRKD;
2808         if (I_IGNPAR(info->port.tty))
2809                 info->ignore_status_mask2 |= PE | FRME;
2810         if (I_IGNBRK(info->port.tty)) {
2811                 info->ignore_status_mask1 |= BRKD;
2812                 /* If ignoring parity and break indicators, ignore
2813                  * overruns too.  (For real raw support).
2814                  */
2815                 if (I_IGNPAR(info->port.tty))
2816                         info->ignore_status_mask2 |= OVRN;
2817         }
2818
2819         program_hw(info);
2820 }
2821
2822 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2823 {
2824         int err;
2825
2826         if (debug_level >= DEBUG_LEVEL_INFO)
2827                 printk("%s(%d):%s get_params()\n",
2828                          __FILE__,__LINE__, info->device_name);
2829
2830         if (!user_icount) {
2831                 memset(&info->icount, 0, sizeof(info->icount));
2832         } else {
2833                 mutex_lock(&info->port.mutex);
2834                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2835                 mutex_unlock(&info->port.mutex);
2836                 if (err)
2837                         return -EFAULT;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2844 {
2845         int err;
2846         if (debug_level >= DEBUG_LEVEL_INFO)
2847                 printk("%s(%d):%s get_params()\n",
2848                          __FILE__,__LINE__, info->device_name);
2849
2850         mutex_lock(&info->port.mutex);
2851         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2852         mutex_unlock(&info->port.mutex);
2853         if (err) {
2854                 if ( debug_level >= DEBUG_LEVEL_INFO )
2855                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2856                                 __FILE__,__LINE__,info->device_name);
2857                 return -EFAULT;
2858         }
2859
2860         return 0;
2861 }
2862
2863 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2864 {
2865         unsigned long flags;
2866         MGSL_PARAMS tmp_params;
2867         int err;
2868
2869         if (debug_level >= DEBUG_LEVEL_INFO)
2870                 printk("%s(%d):%s set_params\n",
2871                         __FILE__,__LINE__,info->device_name );
2872         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2873         if (err) {
2874                 if ( debug_level >= DEBUG_LEVEL_INFO )
2875                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2876                                 __FILE__,__LINE__,info->device_name);
2877                 return -EFAULT;
2878         }
2879
2880         mutex_lock(&info->port.mutex);
2881         spin_lock_irqsave(&info->lock,flags);
2882         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2883         spin_unlock_irqrestore(&info->lock,flags);
2884
2885         change_params(info);
2886         mutex_unlock(&info->port.mutex);
2887
2888         return 0;
2889 }
2890
2891 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2892 {
2893         int err;
2894
2895         if (debug_level >= DEBUG_LEVEL_INFO)
2896                 printk("%s(%d):%s get_txidle()=%d\n",
2897                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2898
2899         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2900         if (err) {
2901                 if ( debug_level >= DEBUG_LEVEL_INFO )
2902                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2903                                 __FILE__,__LINE__,info->device_name);
2904                 return -EFAULT;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static int set_txidle(SLMP_INFO * info, int idle_mode)
2911 {
2912         unsigned long flags;
2913
2914         if (debug_level >= DEBUG_LEVEL_INFO)
2915                 printk("%s(%d):%s set_txidle(%d)\n",
2916                         __FILE__,__LINE__,info->device_name, idle_mode );
2917
2918         spin_lock_irqsave(&info->lock,flags);
2919         info->idle_mode = idle_mode;
2920         tx_set_idle( info );
2921         spin_unlock_irqrestore(&info->lock,flags);
2922         return 0;
2923 }
2924
2925 static int tx_enable(SLMP_INFO * info, int enable)
2926 {
2927         unsigned long flags;
2928
2929         if (debug_level >= DEBUG_LEVEL_INFO)
2930                 printk("%s(%d):%s tx_enable(%d)\n",
2931                         __FILE__,__LINE__,info->device_name, enable);
2932
2933         spin_lock_irqsave(&info->lock,flags);
2934         if ( enable ) {
2935                 if ( !info->tx_enabled ) {
2936                         tx_start(info);
2937                 }
2938         } else {
2939                 if ( info->tx_enabled )
2940                         tx_stop(info);
2941         }
2942         spin_unlock_irqrestore(&info->lock,flags);
2943         return 0;
2944 }
2945
2946 /* abort send HDLC frame
2947  */
2948 static int tx_abort(SLMP_INFO * info)
2949 {
2950         unsigned long flags;
2951
2952         if (debug_level >= DEBUG_LEVEL_INFO)
2953                 printk("%s(%d):%s tx_abort()\n",
2954                         __FILE__,__LINE__,info->device_name);
2955
2956         spin_lock_irqsave(&info->lock,flags);
2957         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2958                 info->ie1_value &= ~UDRN;
2959                 info->ie1_value |= IDLE;
2960                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2961                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
2962
2963                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
2964                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2965
2966                 write_reg(info, CMD, TXABORT);
2967         }
2968         spin_unlock_irqrestore(&info->lock,flags);
2969         return 0;
2970 }
2971
2972 static int rx_enable(SLMP_INFO * info, int enable)
2973 {
2974         unsigned long flags;
2975
2976         if (debug_level >= DEBUG_LEVEL_INFO)
2977                 printk("%s(%d):%s rx_enable(%d)\n",
2978                         __FILE__,__LINE__,info->device_name,enable);
2979
2980         spin_lock_irqsave(&info->lock,flags);
2981         if ( enable ) {
2982                 if ( !info->rx_enabled )
2983                         rx_start(info);
2984         } else {
2985                 if ( info->rx_enabled )
2986                         rx_stop(info);
2987         }
2988         spin_unlock_irqrestore(&info->lock,flags);
2989         return 0;
2990 }
2991
2992 /* wait for specified event to occur
2993  */
2994 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2995 {
2996         unsigned long flags;
2997         int s;
2998         int rc=0;
2999         struct mgsl_icount cprev, cnow;
3000         int events;
3001         int mask;
3002         struct  _input_signal_events oldsigs, newsigs;
3003         DECLARE_WAITQUEUE(wait, current);
3004
3005         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3006         if (rc) {
3007                 return  -EFAULT;
3008         }
3009
3010         if (debug_level >= DEBUG_LEVEL_INFO)
3011                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3012                         __FILE__,__LINE__,info->device_name,mask);
3013
3014         spin_lock_irqsave(&info->lock,flags);
3015
3016         /* return immediately if state matches requested events */
3017         get_signals(info);
3018         s = info->serial_signals;
3019
3020         events = mask &
3021                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3022                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3023                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3024                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3025         if (events) {
3026                 spin_unlock_irqrestore(&info->lock,flags);
3027                 goto exit;
3028         }
3029
3030         /* save current irq counts */
3031         cprev = info->icount;
3032         oldsigs = info->input_signal_events;
3033
3034         /* enable hunt and idle irqs if needed */
3035         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3036                 unsigned char oldval = info->ie1_value;
3037                 unsigned char newval = oldval +
3038                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3039                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3040                 if ( oldval != newval ) {
3041                         info->ie1_value = newval;
3042                         write_reg(info, IE1, info->ie1_value);
3043                 }
3044         }
3045
3046         set_current_state(TASK_INTERRUPTIBLE);
3047         add_wait_queue(&info->event_wait_q, &wait);
3048
3049         spin_unlock_irqrestore(&info->lock,flags);
3050
3051         for(;;) {
3052                 schedule();
3053                 if (signal_pending(current)) {
3054                         rc = -ERESTARTSYS;
3055                         break;
3056                 }
3057
3058                 /* get current irq counts */
3059                 spin_lock_irqsave(&info->lock,flags);
3060                 cnow = info->icount;
3061                 newsigs = info->input_signal_events;
3062                 set_current_state(TASK_INTERRUPTIBLE);
3063                 spin_unlock_irqrestore(&info->lock,flags);
3064
3065                 /* if no change, wait aborted for some reason */
3066                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3067                     newsigs.dsr_down == oldsigs.dsr_down &&
3068                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3069                     newsigs.dcd_down == oldsigs.dcd_down &&
3070                     newsigs.cts_up   == oldsigs.cts_up   &&
3071                     newsigs.cts_down == oldsigs.cts_down &&
3072                     newsigs.ri_up    == oldsigs.ri_up    &&
3073                     newsigs.ri_down  == oldsigs.ri_down  &&
3074                     cnow.exithunt    == cprev.exithunt   &&
3075                     cnow.rxidle      == cprev.rxidle) {
3076                         rc = -EIO;
3077                         break;
3078                 }
3079
3080                 events = mask &
3081                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3082                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3083                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3084                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3085                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3086                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3087                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3088                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3089                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3090                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3091                 if (events)
3092                         break;
3093
3094                 cprev = cnow;
3095                 oldsigs = newsigs;
3096         }
3097
3098         remove_wait_queue(&info->event_wait_q, &wait);
3099         set_current_state(TASK_RUNNING);
3100
3101
3102         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3103                 spin_lock_irqsave(&info->lock,flags);
3104                 if (!waitqueue_active(&info->event_wait_q)) {
3105                         /* disable enable exit hunt mode/idle rcvd IRQs */
3106                         info->ie1_value &= ~(FLGD|IDLD);
3107                         write_reg(info, IE1, info->ie1_value);
3108                 }
3109                 spin_unlock_irqrestore(&info->lock,flags);
3110         }
3111 exit:
3112         if ( rc == 0 )
3113                 PUT_USER(rc, events, mask_ptr);
3114
3115         return rc;
3116 }
3117
3118 static int modem_input_wait(SLMP_INFO *info,int arg)
3119 {
3120         unsigned long flags;
3121         int rc;
3122         struct mgsl_icount cprev, cnow;
3123         DECLARE_WAITQUEUE(wait, current);
3124
3125         /* save current irq counts */
3126         spin_lock_irqsave(&info->lock,flags);
3127         cprev = info->icount;
3128         add_wait_queue(&info->status_event_wait_q, &wait);
3129         set_current_state(TASK_INTERRUPTIBLE);
3130         spin_unlock_irqrestore(&info->lock,flags);
3131
3132         for(;;) {
3133                 schedule();
3134                 if (signal_pending(current)) {
3135                         rc = -ERESTARTSYS;
3136                         break;
3137                 }
3138
3139                 /* get new irq counts */
3140                 spin_lock_irqsave(&info->lock,flags);
3141                 cnow = info->icount;
3142                 set_current_state(TASK_INTERRUPTIBLE);
3143                 spin_unlock_irqrestore(&info->lock,flags);
3144
3145                 /* if no change, wait aborted for some reason */
3146                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3147                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3148                         rc = -EIO;
3149                         break;
3150                 }
3151
3152                 /* check for change in caller specified modem input */
3153                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3154                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3155                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3156                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3157                         rc = 0;
3158                         break;
3159                 }
3160
3161                 cprev = cnow;
3162         }
3163         remove_wait_queue(&info->status_event_wait_q, &wait);
3164         set_current_state(TASK_RUNNING);
3165         return rc;
3166 }
3167
3168 /* return the state of the serial control and status signals
3169  */
3170 static int tiocmget(struct tty_struct *tty)
3171 {
3172         SLMP_INFO *info = tty->driver_data;
3173         unsigned int result;
3174         unsigned long flags;
3175
3176         spin_lock_irqsave(&info->lock,flags);
3177         get_signals(info);
3178         spin_unlock_irqrestore(&info->lock,flags);
3179
3180         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3181                  ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3182                  ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3183                  ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG : 0) |
3184                  ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3185                  ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3186
3187         if (debug_level >= DEBUG_LEVEL_INFO)
3188                 printk("%s(%d):%s tiocmget() value=%08X\n",
3189                          __FILE__,__LINE__, info->device_name, result );
3190         return result;
3191 }
3192
3193 /* set modem control signals (DTR/RTS)
3194  */
3195 static int tiocmset(struct tty_struct *tty,
3196                                         unsigned int set, unsigned int clear)
3197 {
3198         SLMP_INFO *info = tty->driver_data;
3199         unsigned long flags;
3200
3201         if (debug_level >= DEBUG_LEVEL_INFO)
3202                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3203                         __FILE__,__LINE__,info->device_name, set, clear);
3204
3205         if (set & TIOCM_RTS)
3206                 info->serial_signals |= SerialSignal_RTS;
3207         if (set & TIOCM_DTR)
3208                 info->serial_signals |= SerialSignal_DTR;
3209         if (clear & TIOCM_RTS)
3210                 info->serial_signals &= ~SerialSignal_RTS;
3211         if (clear & TIOCM_DTR)
3212                 info->serial_signals &= ~SerialSignal_DTR;
3213
3214         spin_lock_irqsave(&info->lock,flags);
3215         set_signals(info);
3216         spin_unlock_irqrestore(&info->lock,flags);
3217
3218         return 0;
3219 }
3220
3221 static int carrier_raised(struct tty_port *port)
3222 {
3223         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3224         unsigned long flags;
3225
3226         spin_lock_irqsave(&info->lock,flags);
3227         get_signals(info);
3228         spin_unlock_irqrestore(&info->lock,flags);
3229
3230         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3231 }
3232
3233 static void dtr_rts(struct tty_port *port, int on)
3234 {
3235         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3236         unsigned long flags;
3237
3238         spin_lock_irqsave(&info->lock,flags);
3239         if (on)
3240                 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3241         else
3242                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3243         set_signals(info);
3244         spin_unlock_irqrestore(&info->lock,flags);
3245 }
3246
3247 /* Block the current process until the specified port is ready to open.
3248  */
3249 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3250                            SLMP_INFO *info)
3251 {
3252         DECLARE_WAITQUEUE(wait, current);
3253         int             retval;
3254         bool            do_clocal = false;
3255         unsigned long   flags;
3256         int             cd;
3257         struct tty_port *port = &info->port;
3258
3259         if (debug_level >= DEBUG_LEVEL_INFO)
3260                 printk("%s(%d):%s block_til_ready()\n",
3261                          __FILE__,__LINE__, tty->driver->name );
3262
3263         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3264                 /* nonblock mode is set or port is not enabled */
3265                 /* just verify that callout device is not active */
3266                 tty_port_set_active(port, 1);
3267                 return 0;
3268         }
3269
3270         if (C_CLOCAL(tty))
3271                 do_clocal = true;
3272
3273         /* Wait for carrier detect and the line to become
3274          * free (i.e., not in use by the callout).  While we are in
3275          * this loop, port->count is dropped by one, so that
3276          * close() knows when to free things.  We restore it upon
3277          * exit, either normal or abnormal.
3278          */
3279
3280         retval = 0;
3281         add_wait_queue(&port->open_wait, &wait);
3282
3283         if (debug_level >= DEBUG_LEVEL_INFO)
3284                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3285                          __FILE__,__LINE__, tty->driver->name, port->count );
3286
3287         spin_lock_irqsave(&info->lock, flags);
3288         port->count--;
3289         spin_unlock_irqrestore(&info->lock, flags);
3290         port->blocked_open++;
3291
3292         while (1) {
3293                 if (C_BAUD(tty) && tty_port_initialized(port))
3294                         tty_port_raise_dtr_rts(port);
3295
3296                 set_current_state(TASK_INTERRUPTIBLE);
3297
3298                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3299                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3300                                         -EAGAIN : -ERESTARTSYS;
3301                         break;
3302                 }
3303
3304                 cd = tty_port_carrier_raised(port);
3305                 if (do_clocal || cd)
3306                         break;
3307
3308                 if (signal_pending(current)) {
3309                         retval = -ERESTARTSYS;
3310                         break;
3311                 }
3312
3313                 if (debug_level >= DEBUG_LEVEL_INFO)
3314                         printk("%s(%d):%s block_til_ready() count=%d\n",
3315                                  __FILE__,__LINE__, tty->driver->name, port->count );
3316
3317                 tty_unlock(tty);
3318                 schedule();
3319                 tty_lock(tty);
3320         }
3321
3322         set_current_state(TASK_RUNNING);
3323         remove_wait_queue(&port->open_wait, &wait);
3324         if (!tty_hung_up_p(filp))
3325                 port->count++;
3326         port->blocked_open--;
3327
3328         if (debug_level >= DEBUG_LEVEL_INFO)
3329                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3330                          __FILE__,__LINE__, tty->driver->name, port->count );
3331
3332         if (!retval)
3333                 tty_port_set_active(port, 1);
3334
3335         return retval;
3336 }
3337
3338 static int alloc_dma_bufs(SLMP_INFO *info)
3339 {
3340         unsigned short BuffersPerFrame;
3341         unsigned short BufferCount;
3342
3343         // Force allocation to start at 64K boundary for each port.
3344         // This is necessary because *all* buffer descriptors for a port
3345         // *must* be in the same 64K block. All descriptors on a port
3346         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3347         // into the CBP register.
3348         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3349
3350         /* Calculate the number of DMA buffers necessary to hold the */
3351         /* largest allowable frame size. Note: If the max frame size is */
3352         /* not an even multiple of the DMA buffer size then we need to */
3353         /* round the buffer count per frame up one. */
3354
3355         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3356         if ( info->max_frame_size % SCABUFSIZE )
3357                 BuffersPerFrame++;
3358
3359         /* calculate total number of data buffers (SCABUFSIZE) possible
3360          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3361          * for the descriptor list (BUFFERLISTSIZE).
3362          */
3363         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3364
3365         /* limit number of buffers to maximum amount of descriptors */
3366         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3367                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3368
3369         /* use enough buffers to transmit one max size frame */
3370         info->tx_buf_count = BuffersPerFrame + 1;
3371
3372         /* never use more than half the available buffers for transmit */
3373         if (info->tx_buf_count > (BufferCount/2))
3374                 info->tx_buf_count = BufferCount/2;
3375
3376         if (info->tx_buf_count > SCAMAXDESC)
3377                 info->tx_buf_count = SCAMAXDESC;
3378
3379         /* use remaining buffers for receive */
3380         info->rx_buf_count = BufferCount - info->tx_buf_count;
3381
3382         if (info->rx_buf_count > SCAMAXDESC)
3383                 info->rx_buf_count = SCAMAXDESC;
3384
3385         if ( debug_level >= DEBUG_LEVEL_INFO )
3386                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3387                         __FILE__,__LINE__, info->device_name,
3388                         info->tx_buf_count,info->rx_buf_count);
3389
3390         if ( alloc_buf_list( info ) < 0 ||
3391                 alloc_frame_bufs(info,
3392                                         info->rx_buf_list,
3393                                         info->rx_buf_list_ex,
3394                                         info->rx_buf_count) < 0 ||
3395                 alloc_frame_bufs(info,
3396                                         info->tx_buf_list,
3397                                         info->tx_buf_list_ex,
3398                                         info->tx_buf_count) < 0 ||
3399                 alloc_tmp_rx_buf(info) < 0 ) {
3400                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3401                         __FILE__,__LINE__, info->device_name);
3402                 return -ENOMEM;
3403         }
3404
3405         rx_reset_buffers( info );
3406
3407         return 0;
3408 }
3409
3410 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3411  */
3412 static int alloc_buf_list(SLMP_INFO *info)
3413 {
3414         unsigned int i;
3415
3416         /* build list in adapter shared memory */
3417         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3418         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3419         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3420
3421         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3422
3423         /* Save virtual address pointers to the receive and */
3424         /* transmit buffer lists. (Receive 1st). These pointers will */
3425         /* be used by the processor to access the lists. */
3426         info->rx_buf_list = (SCADESC *)info->buffer_list;
3427
3428         info->tx_buf_list = (SCADESC *)info->buffer_list;
3429         info->tx_buf_list += info->rx_buf_count;
3430
3431         /* Build links for circular buffer entry lists (tx and rx)
3432          *
3433          * Note: links are physical addresses read by the SCA device
3434          * to determine the next buffer entry to use.
3435          */
3436
3437         for ( i = 0; i < info->rx_buf_count; i++ ) {
3438                 /* calculate and store physical address of this buffer entry */
3439                 info->rx_buf_list_ex[i].phys_entry =
3440                         info->buffer_list_phys + (i * SCABUFSIZE);
3441
3442                 /* calculate and store physical address of */
3443                 /* next entry in cirular list of entries */
3444                 info->rx_buf_list[i].next = info->buffer_list_phys;
3445                 if ( i < info->rx_buf_count - 1 )
3446                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3447
3448                 info->rx_buf_list[i].length = SCABUFSIZE;
3449         }
3450
3451         for ( i = 0; i < info->tx_buf_count; i++ ) {
3452                 /* calculate and store physical address of this buffer entry */
3453                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3454                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3455
3456                 /* calculate and store physical address of */
3457                 /* next entry in cirular list of entries */
3458
3459                 info->tx_buf_list[i].next = info->buffer_list_phys +
3460                         info->rx_buf_count * sizeof(SCADESC);
3461
3462                 if ( i < info->tx_buf_count - 1 )
3463                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3464         }
3465
3466         return 0;
3467 }
3468
3469 /* Allocate the frame DMA buffers used by the specified buffer list.
3470  */
3471 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3472 {
3473         int i;
3474         unsigned long phys_addr;
3475
3476         for ( i = 0; i < count; i++ ) {
3477                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3478                 phys_addr = info->port_array[0]->last_mem_alloc;
3479                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3480
3481                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3482                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3483         }
3484
3485         return 0;
3486 }
3487
3488 static void free_dma_bufs(SLMP_INFO *info)
3489 {
3490         info->buffer_list = NULL;
3491         info->rx_buf_list = NULL;
3492         info->tx_buf_list = NULL;
3493 }
3494
3495 /* allocate buffer large enough to hold max_frame_size.
3496  * This buffer is used to pass an assembled frame to the line discipline.
3497  */
3498 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3499 {
3500         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3501         if (info->tmp_rx_buf == NULL)
3502                 return -ENOMEM;
3503         /* unused flag buffer to satisfy receive_buf calling interface */
3504         info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3505         if (!info->flag_buf) {
3506                 kfree(info->tmp_rx_buf);
3507                 info->tmp_rx_buf = NULL;
3508                 return -ENOMEM;
3509         }
3510         return 0;
3511 }
3512
3513 static void free_tmp_rx_buf(SLMP_INFO *info)
3514 {
3515         kfree(info->tmp_rx_buf);
3516         info->tmp_rx_buf = NULL;
3517         kfree(info->flag_buf);
3518         info->flag_buf = NULL;
3519 }
3520
3521 static int claim_resources(SLMP_INFO *info)
3522 {
3523         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3524                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3525                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3526                 info->init_error = DiagStatus_AddressConflict;
3527                 goto errout;
3528         }
3529         else
3530                 info->shared_mem_requested = true;
3531
3532         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3533                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3534                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3535                 info->init_error = DiagStatus_AddressConflict;
3536                 goto errout;
3537         }
3538         else
3539                 info->lcr_mem_requested = true;
3540
3541         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3542                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3543                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3544                 info->init_error = DiagStatus_AddressConflict;
3545                 goto errout;
3546         }
3547         else
3548                 info->sca_base_requested = true;
3549
3550         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3551                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3552                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3553                 info->init_error = DiagStatus_AddressConflict;
3554                 goto errout;
3555         }
3556         else
3557                 info->sca_statctrl_requested = true;
3558
3559         info->memory_base = ioremap(info->phys_memory_base,
3560                                                                 SCA_MEM_SIZE);
3561         if (!info->memory_base) {
3562                 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3563                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3564                 info->init_error = DiagStatus_CantAssignPciResources;
3565                 goto errout;
3566         }
3567
3568         info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
3569         if (!info->lcr_base) {
3570                 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3571                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3572                 info->init_error = DiagStatus_CantAssignPciResources;
3573                 goto errout;
3574         }
3575         info->lcr_base += info->lcr_offset;
3576
3577         info->sca_base = ioremap(info->phys_sca_base, PAGE_SIZE);
3578         if (!info->sca_base) {
3579                 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3580                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3581                 info->init_error = DiagStatus_CantAssignPciResources;
3582                 goto errout;
3583         }
3584         info->sca_base += info->sca_offset;
3585
3586         info->statctrl_base = ioremap(info->phys_statctrl_base,
3587                                                                 PAGE_SIZE);
3588         if (!info->statctrl_base) {
3589                 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3590                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3591                 info->init_error = DiagStatus_CantAssignPciResources;
3592                 goto errout;
3593         }
3594         info->statctrl_base += info->statctrl_offset;
3595
3596         if ( !memory_test(info) ) {
3597                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3598                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3599                 info->init_error = DiagStatus_MemoryError;
3600                 goto errout;
3601         }
3602
3603         return 0;
3604
3605 errout:
3606         release_resources( info );
3607         return -ENODEV;
3608 }
3609
3610 static void release_resources(SLMP_INFO *info)
3611 {
3612         if ( debug_level >= DEBUG_LEVEL_INFO )
3613                 printk( "%s(%d):%s release_resources() entry\n",
3614                         __FILE__,__LINE__,info->device_name );
3615
3616         if ( info->irq_requested ) {
3617                 free_irq(info->irq_level, info);
3618                 info->irq_requested = false;
3619         }
3620
3621         if ( info->shared_mem_requested ) {
3622                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3623                 info->shared_mem_requested = false;
3624         }
3625         if ( info->lcr_mem_requested ) {
3626                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3627                 info->lcr_mem_requested = false;
3628         }
3629         if ( info->sca_base_requested ) {
3630                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3631                 info->sca_base_requested = false;
3632         }
3633         if ( info->sca_statctrl_requested ) {
3634                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3635                 info->sca_statctrl_requested = false;
3636         }
3637
3638         if (info->memory_base){
3639                 iounmap(info->memory_base);
3640                 info->memory_base = NULL;
3641         }
3642
3643         if (info->sca_base) {
3644                 iounmap(info->sca_base - info->sca_offset);
3645                 info->sca_base=NULL;
3646         }
3647
3648         if (info->statctrl_base) {
3649                 iounmap(info->statctrl_base - info->statctrl_offset);
3650                 info->statctrl_base=NULL;
3651         }
3652
3653         if (info->lcr_base){
3654                 iounmap(info->lcr_base - info->lcr_offset);
3655                 info->lcr_base = NULL;
3656         }
3657
3658         if ( debug_level >= DEBUG_LEVEL_INFO )
3659                 printk( "%s(%d):%s release_resources() exit\n",
3660                         __FILE__,__LINE__,info->device_name );
3661 }
3662
3663 /* Add the specified device instance data structure to the
3664  * global linked list of devices and increment the device count.
3665  */
3666 static int add_device(SLMP_INFO *info)
3667 {
3668         info->next_device = NULL;
3669         info->line = synclinkmp_device_count;
3670         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3671
3672         if (info->line < MAX_DEVICES) {
3673                 if (maxframe[info->line])
3674                         info->max_frame_size = maxframe[info->line];
3675         }
3676
3677         synclinkmp_device_count++;
3678
3679         if ( !synclinkmp_device_list )
3680                 synclinkmp_device_list = info;
3681         else {
3682                 SLMP_INFO *current_dev = synclinkmp_device_list;
3683                 while( current_dev->next_device )
3684                         current_dev = current_dev->next_device;
3685                 current_dev->next_device = info;
3686         }
3687
3688         if ( info->max_frame_size < 4096 )
3689                 info->max_frame_size = 4096;
3690         else if ( info->max_frame_size > 65535 )
3691                 info->max_frame_size = 65535;
3692
3693         printk( "SyncLink MultiPort %s: "
3694                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3695                 info->device_name,
3696                 info->phys_sca_base,
3697                 info->phys_memory_base,
3698                 info->phys_statctrl_base,
3699                 info->phys_lcr_base,
3700                 info->irq_level,
3701                 info->max_frame_size );
3702
3703 #if SYNCLINK_GENERIC_HDLC
3704         return hdlcdev_init(info);
3705 #else
3706         return 0;
3707 #endif
3708 }
3709
3710 static const struct tty_port_operations port_ops = {
3711         .carrier_raised = carrier_raised,
3712         .dtr_rts = dtr_rts,
3713 };
3714
3715 /* Allocate and initialize a device instance structure
3716  *
3717  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3718  */
3719 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3720 {
3721         SLMP_INFO *info;
3722
3723         info = kzalloc(sizeof(SLMP_INFO),
3724                  GFP_KERNEL);
3725
3726         if (!info) {
3727                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3728                         __FILE__,__LINE__, adapter_num, port_num);
3729         } else {
3730                 tty_port_init(&info->port);
3731                 info->port.ops = &port_ops;
3732                 info->magic = MGSL_MAGIC;
3733                 INIT_WORK(&info->task, bh_handler);
3734                 info->max_frame_size = 4096;
3735                 info->port.close_delay = 5*HZ/10;
3736                 info->port.closing_wait = 30*HZ;
3737                 init_waitqueue_head(&info->status_event_wait_q);
3738                 init_waitqueue_head(&info->event_wait_q);
3739                 spin_lock_init(&info->netlock);
3740                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3741                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3742                 info->adapter_num = adapter_num;
3743                 info->port_num = port_num;
3744
3745                 /* Copy configuration info to device instance data */
3746                 info->irq_level = pdev->irq;
3747                 info->phys_lcr_base = pci_resource_start(pdev,0);
3748                 info->phys_sca_base = pci_resource_start(pdev,2);
3749                 info->phys_memory_base = pci_resource_start(pdev,3);
3750                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3751
3752                 /* Because veremap only works on page boundaries we must map
3753                  * a larger area than is actually implemented for the LCR
3754                  * memory range. We map a full page starting at the page boundary.
3755                  */
3756                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3757                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3758
3759                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3760                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3761
3762                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3763                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3764
3765                 info->bus_type = MGSL_BUS_TYPE_PCI;
3766                 info->irq_flags = IRQF_SHARED;
3767
3768                 timer_setup(&info->tx_timer, tx_timeout, 0);
3769                 timer_setup(&info->status_timer, status_timeout, 0);
3770
3771                 /* Store the PCI9050 misc control register value because a flaw
3772                  * in the PCI9050 prevents LCR registers from being read if
3773                  * BIOS assigns an LCR base address with bit 7 set.
3774                  *
3775                  * Only the misc control register is accessed for which only
3776                  * write access is needed, so set an initial value and change
3777                  * bits to the device instance data as we write the value
3778                  * to the actual misc control register.
3779                  */
3780                 info->misc_ctrl_value = 0x087e4546;
3781
3782                 /* initial port state is unknown - if startup errors
3783                  * occur, init_error will be set to indicate the
3784                  * problem. Once the port is fully initialized,
3785                  * this value will be set to 0 to indicate the
3786                  * port is available.
3787                  */
3788                 info->init_error = -1;
3789         }
3790
3791         return info;
3792 }
3793
3794 static int device_init(int adapter_num, struct pci_dev *pdev)
3795 {
3796         SLMP_INFO *port_array[SCA_MAX_PORTS];
3797         int port, rc;
3798
3799         /* allocate device instances for up to SCA_MAX_PORTS devices */
3800         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3801                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3802                 if( port_array[port] == NULL ) {
3803                         for (--port; port >= 0; --port) {
3804                                 tty_port_destroy(&port_array[port]->port);
3805                                 kfree(port_array[port]);
3806                         }
3807                         return -ENOMEM;
3808                 }
3809         }
3810
3811         /* give copy of port_array to all ports and add to device list  */
3812         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3813                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3814                 rc = add_device( port_array[port] );
3815                 if (rc)
3816                         goto err_add;
3817                 spin_lock_init(&port_array[port]->lock);
3818         }
3819
3820         /* Allocate and claim adapter resources */
3821         if ( !claim_resources(port_array[0]) ) {
3822
3823                 alloc_dma_bufs(port_array[0]);
3824
3825                 /* copy resource information from first port to others */
3826                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3827                         port_array[port]->lock  = port_array[0]->lock;
3828                         port_array[port]->irq_level     = port_array[0]->irq_level;
3829                         port_array[port]->memory_base   = port_array[0]->memory_base;
3830                         port_array[port]->sca_base      = port_array[0]->sca_base;
3831                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3832                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3833                         alloc_dma_bufs(port_array[port]);
3834                 }
3835
3836                 rc = request_irq(port_array[0]->irq_level,
3837                                         synclinkmp_interrupt,
3838                                         port_array[0]->irq_flags,
3839                                         port_array[0]->device_name,
3840                                         port_array[0]);
3841                 if ( rc ) {
3842                         printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3843                                 __FILE__,__LINE__,
3844                                 port_array[0]->device_name,
3845                                 port_array[0]->irq_level );
3846                         goto err_irq;
3847                 }
3848                 port_array[0]->irq_requested = true;
3849                 adapter_test(port_array[0]);
3850         }
3851         return 0;
3852 err_irq:
3853         release_resources( port_array[0] );
3854 err_add:
3855         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3856                 tty_port_destroy(&port_array[port]->port);
3857                 kfree(port_array[port]);
3858         }
3859         return rc;
3860 }
3861
3862 static const struct tty_operations ops = {
3863         .install = install,
3864         .open = open,
3865         .close = close,
3866         .write = write,
3867         .put_char = put_char,
3868         .flush_chars = flush_chars,
3869         .write_room = write_room,
3870         .chars_in_buffer = chars_in_buffer,
3871         .flush_buffer = flush_buffer,
3872         .ioctl = ioctl,
3873         .throttle = throttle,
3874         .unthrottle = unthrottle,
3875         .send_xchar = send_xchar,
3876         .break_ctl = set_break,
3877         .wait_until_sent = wait_until_sent,
3878         .set_termios = set_termios,
3879         .stop = tx_hold,
3880         .start = tx_release,
3881         .hangup = hangup,
3882         .tiocmget = tiocmget,
3883         .tiocmset = tiocmset,
3884         .get_icount = get_icount,
3885         .proc_show = synclinkmp_proc_show,
3886 };
3887
3888
3889 static void synclinkmp_cleanup(void)
3890 {
3891         int rc;
3892         SLMP_INFO *info;
3893         SLMP_INFO *tmp;
3894
3895         printk("Unloading %s %s\n", driver_name, driver_version);
3896
3897         if (serial_driver) {
3898                 rc = tty_unregister_driver(serial_driver);
3899                 if (rc)
3900                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3901                                __FILE__,__LINE__,rc);
3902                 put_tty_driver(serial_driver);
3903         }
3904
3905         /* reset devices */
3906         info = synclinkmp_device_list;
3907         while(info) {
3908                 reset_port(info);
3909                 info = info->next_device;
3910         }
3911
3912         /* release devices */
3913         info = synclinkmp_device_list;
3914         while(info) {
3915 #if SYNCLINK_GENERIC_HDLC
3916                 hdlcdev_exit(info);
3917 #endif
3918                 free_dma_bufs(info);
3919                 free_tmp_rx_buf(info);
3920                 if ( info->port_num == 0 ) {
3921                         if (info->sca_base)
3922                                 write_reg(info, LPR, 1); /* set low power mode */
3923                         release_resources(info);
3924                 }
3925                 tmp = info;
3926                 info = info->next_device;
3927                 tty_port_destroy(&tmp->port);
3928                 kfree(tmp);
3929         }
3930
3931         pci_unregister_driver(&synclinkmp_pci_driver);
3932 }
3933
3934 /* Driver initialization entry point.
3935  */
3936
3937 static int __init synclinkmp_init(void)
3938 {
3939         int rc;
3940
3941         if (break_on_load) {
3942                 synclinkmp_get_text_ptr();
3943                 BREAKPOINT();
3944         }
3945
3946         printk("%s %s\n", driver_name, driver_version);
3947
3948         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3949                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3950                 return rc;
3951         }
3952
3953         serial_driver = alloc_tty_driver(128);
3954         if (!serial_driver) {
3955                 rc = -ENOMEM;
3956                 goto error;
3957         }
3958
3959         /* Initialize the tty_driver structure */
3960
3961         serial_driver->driver_name = "synclinkmp";
3962         serial_driver->name = "ttySLM";
3963         serial_driver->major = ttymajor;
3964         serial_driver->minor_start = 64;
3965         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3966         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3967         serial_driver->init_termios = tty_std_termios;
3968         serial_driver->init_termios.c_cflag =
3969                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3970         serial_driver->init_termios.c_ispeed = 9600;
3971         serial_driver->init_termios.c_ospeed = 9600;
3972         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3973         tty_set_operations(serial_driver, &ops);
3974         if ((rc = tty_register_driver(serial_driver)) < 0) {
3975                 printk("%s(%d):Couldn't register serial driver\n",
3976                         __FILE__,__LINE__);
3977                 put_tty_driver(serial_driver);
3978                 serial_driver = NULL;
3979                 goto error;
3980         }
3981
3982         printk("%s %s, tty major#%d\n",
3983                 driver_name, driver_version,
3984                 serial_driver->major);
3985
3986         return 0;
3987
3988 error:
3989         synclinkmp_cleanup();
3990         return rc;
3991 }
3992
3993 static void __exit synclinkmp_exit(void)
3994 {
3995         synclinkmp_cleanup();
3996 }
3997
3998 module_init(synclinkmp_init);
3999 module_exit(synclinkmp_exit);
4000
4001 /* Set the port for internal loopback mode.
4002  * The TxCLK and RxCLK signals are generated from the BRG and
4003  * the TxD is looped back to the RxD internally.
4004  */
4005 static void enable_loopback(SLMP_INFO *info, int enable)
4006 {
4007         if (enable) {
4008                 /* MD2 (Mode Register 2)
4009                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4010                  */
4011                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4012
4013                 /* degate external TxC clock source */
4014                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4015                 write_control_reg(info);
4016
4017                 /* RXS/TXS (Rx/Tx clock source)
4018                  * 07      Reserved, must be 0
4019                  * 06..04  Clock Source, 100=BRG
4020                  * 03..00  Clock Divisor, 0000=1
4021                  */
4022                 write_reg(info, RXS, 0x40);
4023                 write_reg(info, TXS, 0x40);
4024
4025         } else {
4026                 /* MD2 (Mode Register 2)
4027                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4028                  */
4029                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4030
4031                 /* RXS/TXS (Rx/Tx clock source)
4032                  * 07      Reserved, must be 0
4033                  * 06..04  Clock Source, 000=RxC/TxC Pin
4034                  * 03..00  Clock Divisor, 0000=1
4035                  */
4036                 write_reg(info, RXS, 0x00);
4037                 write_reg(info, TXS, 0x00);
4038         }
4039
4040         /* set LinkSpeed if available, otherwise default to 2Mbps */
4041         if (info->params.clock_speed)
4042                 set_rate(info, info->params.clock_speed);
4043         else
4044                 set_rate(info, 3686400);
4045 }
4046
4047 /* Set the baud rate register to the desired speed
4048  *
4049  *      data_rate       data rate of clock in bits per second
4050  *                      A data rate of 0 disables the AUX clock.
4051  */
4052 static void set_rate( SLMP_INFO *info, u32 data_rate )
4053 {
4054         u32 TMCValue;
4055         unsigned char BRValue;
4056         u32 Divisor=0;
4057
4058         /* fBRG = fCLK/(TMC * 2^BR)
4059          */
4060         if (data_rate != 0) {
4061                 Divisor = 14745600/data_rate;
4062                 if (!Divisor)
4063                         Divisor = 1;
4064
4065                 TMCValue = Divisor;
4066
4067                 BRValue = 0;
4068                 if (TMCValue != 1 && TMCValue != 2) {
4069                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4070                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4071                          * 50/50 duty cycle.
4072                          */
4073                         BRValue = 1;
4074                         TMCValue >>= 1;
4075                 }
4076
4077                 /* while TMCValue is too big for TMC register, divide
4078                  * by 2 and increment BR exponent.
4079                  */
4080                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4081                         TMCValue >>= 1;
4082
4083                 write_reg(info, TXS,
4084                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4085                 write_reg(info, RXS,
4086                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4087                 write_reg(info, TMC, (unsigned char)TMCValue);
4088         }
4089         else {
4090                 write_reg(info, TXS,0);
4091                 write_reg(info, RXS,0);
4092                 write_reg(info, TMC, 0);
4093         }
4094 }
4095
4096 /* Disable receiver
4097  */
4098 static void rx_stop(SLMP_INFO *info)
4099 {
4100         if (debug_level >= DEBUG_LEVEL_ISR)
4101                 printk("%s(%d):%s rx_stop()\n",
4102                          __FILE__,__LINE__, info->device_name );
4103
4104         write_reg(info, CMD, RXRESET);
4105
4106         info->ie0_value &= ~RXRDYE;
4107         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4108
4109         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4110         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4111         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4112
4113         info->rx_enabled = false;
4114         info->rx_overflow = false;
4115 }
4116
4117 /* enable the receiver
4118  */
4119 static void rx_start(SLMP_INFO *info)
4120 {
4121         int i;
4122
4123         if (debug_level >= DEBUG_LEVEL_ISR)
4124                 printk("%s(%d):%s rx_start()\n",
4125                          __FILE__,__LINE__, info->device_name );
4126
4127         write_reg(info, CMD, RXRESET);
4128
4129         if ( info->params.mode == MGSL_MODE_HDLC ) {
4130                 /* HDLC, disabe IRQ on rxdata */
4131                 info->ie0_value &= ~RXRDYE;
4132                 write_reg(info, IE0, info->ie0_value);
4133
4134                 /* Reset all Rx DMA buffers and program rx dma */
4135                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4136                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4137
4138                 for (i = 0; i < info->rx_buf_count; i++) {
4139                         info->rx_buf_list[i].status = 0xff;
4140
4141                         // throttle to 4 shared memory writes at a time to prevent
4142                         // hogging local bus (keep latency time for DMA requests low).
4143                         if (!(i % 4))
4144                                 read_status_reg(info);
4145                 }
4146                 info->current_rx_buf = 0;
4147
4148                 /* set current/1st descriptor address */
4149                 write_reg16(info, RXDMA + CDA,
4150                         info->rx_buf_list_ex[0].phys_entry);
4151
4152                 /* set new last rx descriptor address */
4153                 write_reg16(info, RXDMA + EDA,
4154                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4155
4156                 /* set buffer length (shared by all rx dma data buffers) */
4157                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4158
4159                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4160                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4161         } else {
4162                 /* async, enable IRQ on rxdata */
4163                 info->ie0_value |= RXRDYE;
4164                 write_reg(info, IE0, info->ie0_value);
4165         }
4166
4167         write_reg(info, CMD, RXENABLE);
4168
4169         info->rx_overflow = false;
4170         info->rx_enabled = true;
4171 }
4172
4173 /* Enable the transmitter and send a transmit frame if
4174  * one is loaded in the DMA buffers.
4175  */
4176 static void tx_start(SLMP_INFO *info)
4177 {
4178         if (debug_level >= DEBUG_LEVEL_ISR)
4179                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4180                          __FILE__,__LINE__, info->device_name,info->tx_count );
4181
4182         if (!info->tx_enabled ) {
4183                 write_reg(info, CMD, TXRESET);
4184                 write_reg(info, CMD, TXENABLE);
4185                 info->tx_enabled = true;
4186         }
4187
4188         if ( info->tx_count ) {
4189
4190                 /* If auto RTS enabled and RTS is inactive, then assert */
4191                 /* RTS and set a flag indicating that the driver should */
4192                 /* negate RTS when the transmission completes. */
4193
4194                 info->drop_rts_on_tx_done = false;
4195
4196                 if (info->params.mode != MGSL_MODE_ASYNC) {
4197
4198                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4199                                 get_signals( info );
4200                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4201                                         info->serial_signals |= SerialSignal_RTS;
4202                                         set_signals( info );
4203                                         info->drop_rts_on_tx_done = true;
4204                                 }
4205                         }
4206
4207                         write_reg16(info, TRC0,
4208                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4209
4210                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4211                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4212
4213                         /* set TX CDA (current descriptor address) */
4214                         write_reg16(info, TXDMA + CDA,
4215                                 info->tx_buf_list_ex[0].phys_entry);
4216
4217                         /* set TX EDA (last descriptor address) */
4218                         write_reg16(info, TXDMA + EDA,
4219                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4220
4221                         /* enable underrun IRQ */
4222                         info->ie1_value &= ~IDLE;
4223                         info->ie1_value |= UDRN;
4224                         write_reg(info, IE1, info->ie1_value);
4225                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4226
4227                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4228                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4229
4230                         mod_timer(&info->tx_timer, jiffies +
4231                                         msecs_to_jiffies(5000));
4232                 }
4233                 else {
4234                         tx_load_fifo(info);
4235                         /* async, enable IRQ on txdata */
4236                         info->ie0_value |= TXRDYE;
4237                         write_reg(info, IE0, info->ie0_value);
4238                 }
4239
4240                 info->tx_active = true;
4241         }
4242 }
4243
4244 /* stop the transmitter and DMA
4245  */
4246 static void tx_stop( SLMP_INFO *info )
4247 {
4248         if (debug_level >= DEBUG_LEVEL_ISR)
4249                 printk("%s(%d):%s tx_stop()\n",
4250                          __FILE__,__LINE__, info->device_name );
4251
4252         del_timer(&info->tx_timer);
4253
4254         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4255         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4256
4257         write_reg(info, CMD, TXRESET);
4258
4259         info->ie1_value &= ~(UDRN + IDLE);
4260         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4261         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4262
4263         info->ie0_value &= ~TXRDYE;
4264         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4265
4266         info->tx_enabled = false;
4267         info->tx_active = false;
4268 }
4269
4270 /* Fill the transmit FIFO until the FIFO is full or
4271  * there is no more data to load.
4272  */
4273 static void tx_load_fifo(SLMP_INFO *info)
4274 {
4275         u8 TwoBytes[2];
4276
4277         /* do nothing is now tx data available and no XON/XOFF pending */
4278
4279         if ( !info->tx_count && !info->x_char )
4280                 return;
4281
4282         /* load the Transmit FIFO until FIFOs full or all data sent */
4283
4284         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4285
4286                 /* there is more space in the transmit FIFO and */
4287                 /* there is more data in transmit buffer */
4288
4289                 if ( (info->tx_count > 1) && !info->x_char ) {
4290                         /* write 16-bits */
4291                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4292                         if (info->tx_get >= info->max_frame_size)
4293                                 info->tx_get -= info->max_frame_size;
4294                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4295                         if (info->tx_get >= info->max_frame_size)
4296                                 info->tx_get -= info->max_frame_size;
4297
4298                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4299
4300                         info->tx_count -= 2;
4301                         info->icount.tx += 2;
4302                 } else {
4303                         /* only 1 byte left to transmit or 1 FIFO slot left */
4304
4305                         if (info->x_char) {
4306                                 /* transmit pending high priority char */
4307                                 write_reg(info, TRB, info->x_char);
4308                                 info->x_char = 0;
4309                         } else {
4310                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4311                                 if (info->tx_get >= info->max_frame_size)
4312                                         info->tx_get -= info->max_frame_size;
4313                                 info->tx_count--;
4314                         }
4315                         info->icount.tx++;
4316                 }
4317         }
4318 }
4319
4320 /* Reset a port to a known state
4321  */
4322 static void reset_port(SLMP_INFO *info)
4323 {
4324         if (info->sca_base) {
4325
4326                 tx_stop(info);
4327                 rx_stop(info);
4328
4329                 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4330                 set_signals(info);
4331
4332                 /* disable all port interrupts */
4333                 info->ie0_value = 0;
4334                 info->ie1_value = 0;
4335                 info->ie2_value = 0;
4336                 write_reg(info, IE0, info->ie0_value);
4337                 write_reg(info, IE1, info->ie1_value);
4338                 write_reg(info, IE2, info->ie2_value);
4339
4340                 write_reg(info, CMD, CHRESET);
4341         }
4342 }
4343
4344 /* Reset all the ports to a known state.
4345  */
4346 static void reset_adapter(SLMP_INFO *info)
4347 {
4348         int i;
4349
4350         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4351                 if (info->port_array[i])
4352                         reset_port(info->port_array[i]);
4353         }
4354 }
4355
4356 /* Program port for asynchronous communications.
4357  */
4358 static void async_mode(SLMP_INFO *info)
4359 {
4360
4361         unsigned char RegValue;
4362
4363         tx_stop(info);
4364         rx_stop(info);
4365
4366         /* MD0, Mode Register 0
4367          *
4368          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4369          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4370          * 03      Reserved, must be 0
4371          * 02      CRCCC, CRC Calculation, 0=disabled
4372          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4373          *
4374          * 0000 0000
4375          */
4376         RegValue = 0x00;
4377         if (info->params.stop_bits != 1)
4378                 RegValue |= BIT1;
4379         write_reg(info, MD0, RegValue);
4380
4381         /* MD1, Mode Register 1
4382          *
4383          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4384          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4385          * 03..02  RXCHR<1..0>, rx char size
4386          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4387          *
4388          * 0100 0000
4389          */
4390         RegValue = 0x40;
4391         switch (info->params.data_bits) {
4392         case 7: RegValue |= BIT4 + BIT2; break;
4393         case 6: RegValue |= BIT5 + BIT3; break;
4394         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4395         }
4396         if (info->params.parity != ASYNC_PARITY_NONE) {
4397                 RegValue |= BIT1;
4398                 if (info->params.parity == ASYNC_PARITY_ODD)
4399                         RegValue |= BIT0;
4400         }
4401         write_reg(info, MD1, RegValue);
4402
4403         /* MD2, Mode Register 2
4404          *
4405          * 07..02  Reserved, must be 0
4406          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4407          *
4408          * 0000 0000
4409          */
4410         RegValue = 0x00;
4411         if (info->params.loopback)
4412                 RegValue |= (BIT1 + BIT0);
4413         write_reg(info, MD2, RegValue);
4414
4415         /* RXS, Receive clock source
4416          *
4417          * 07      Reserved, must be 0
4418          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4419          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4420          */
4421         RegValue=BIT6;
4422         write_reg(info, RXS, RegValue);
4423
4424         /* TXS, Transmit clock source
4425          *
4426          * 07      Reserved, must be 0
4427          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4428          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4429          */
4430         RegValue=BIT6;
4431         write_reg(info, TXS, RegValue);
4432
4433         /* Control Register
4434          *
4435          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4436          */
4437         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4438         write_control_reg(info);
4439
4440         tx_set_idle(info);
4441
4442         /* RRC Receive Ready Control 0
4443          *
4444          * 07..05  Reserved, must be 0
4445          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4446          */
4447         write_reg(info, RRC, 0x00);
4448
4449         /* TRC0 Transmit Ready Control 0
4450          *
4451          * 07..05  Reserved, must be 0
4452          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4453          */
4454         write_reg(info, TRC0, 0x10);
4455
4456         /* TRC1 Transmit Ready Control 1
4457          *
4458          * 07..05  Reserved, must be 0
4459          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4460          */
4461         write_reg(info, TRC1, 0x1e);
4462
4463         /* CTL, MSCI control register
4464          *
4465          * 07..06  Reserved, set to 0
4466          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4467          * 04      IDLC, idle control, 0=mark 1=idle register
4468          * 03      BRK, break, 0=off 1 =on (async)
4469          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4470          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4471          * 00      RTS, RTS output control, 0=active 1=inactive
4472          *
4473          * 0001 0001
4474          */
4475         RegValue = 0x10;
4476         if (!(info->serial_signals & SerialSignal_RTS))
4477                 RegValue |= 0x01;
4478         write_reg(info, CTL, RegValue);
4479
4480         /* enable status interrupts */
4481         info->ie0_value |= TXINTE + RXINTE;
4482         write_reg(info, IE0, info->ie0_value);
4483
4484         /* enable break detect interrupt */
4485         info->ie1_value = BRKD;
4486         write_reg(info, IE1, info->ie1_value);
4487
4488         /* enable rx overrun interrupt */
4489         info->ie2_value = OVRN;
4490         write_reg(info, IE2, info->ie2_value);
4491
4492         set_rate( info, info->params.data_rate * 16 );
4493 }
4494
4495 /* Program the SCA for HDLC communications.
4496  */
4497 static void hdlc_mode(SLMP_INFO *info)
4498 {
4499         unsigned char RegValue;
4500         u32 DpllDivisor;
4501
4502         // Can't use DPLL because SCA outputs recovered clock on RxC when
4503         // DPLL mode selected. This causes output contention with RxC receiver.
4504         // Use of DPLL would require external hardware to disable RxC receiver
4505         // when DPLL mode selected.
4506         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4507
4508         /* disable DMA interrupts */
4509         write_reg(info, TXDMA + DIR, 0);
4510         write_reg(info, RXDMA + DIR, 0);
4511
4512         /* MD0, Mode Register 0
4513          *
4514          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4515          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4516          * 03      Reserved, must be 0
4517          * 02      CRCCC, CRC Calculation, 1=enabled
4518          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4519          * 00      CRC0, CRC initial value, 1 = all 1s
4520          *
4521          * 1000 0001
4522          */
4523         RegValue = 0x81;
4524         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4525                 RegValue |= BIT4;
4526         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4527                 RegValue |= BIT4;
4528         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4529                 RegValue |= BIT2 + BIT1;
4530         write_reg(info, MD0, RegValue);
4531
4532         /* MD1, Mode Register 1
4533          *
4534          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4535          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4536          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4537          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4538          *
4539          * 0000 0000
4540          */
4541         RegValue = 0x00;
4542         write_reg(info, MD1, RegValue);
4543
4544         /* MD2, Mode Register 2
4545          *
4546          * 07      NRZFM, 0=NRZ, 1=FM
4547          * 06..05  CODE<1..0> Encoding, 00=NRZ
4548          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4549          * 02      Reserved, must be 0
4550          * 01..00  CNCT<1..0> Channel connection, 0=normal
4551          *
4552          * 0000 0000
4553          */
4554         RegValue = 0x00;
4555         switch(info->params.encoding) {
4556         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4557         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4558         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4559         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4560 #if 0
4561         case HDLC_ENCODING_NRZB:                                        /* not supported */
4562         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4563         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4564 #endif
4565         }
4566         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4567                 DpllDivisor = 16;
4568                 RegValue |= BIT3;
4569         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4570                 DpllDivisor = 8;
4571         } else {
4572                 DpllDivisor = 32;
4573                 RegValue |= BIT4;
4574         }
4575         write_reg(info, MD2, RegValue);
4576
4577
4578         /* RXS, Receive clock source
4579          *
4580          * 07      Reserved, must be 0
4581          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4582          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4583          */
4584         RegValue=0;
4585         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4586                 RegValue |= BIT6;
4587         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4588                 RegValue |= BIT6 + BIT5;
4589         write_reg(info, RXS, RegValue);
4590
4591         /* TXS, Transmit clock source
4592          *
4593          * 07      Reserved, must be 0
4594          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4595          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4596          */
4597         RegValue=0;
4598         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4599                 RegValue |= BIT6;
4600         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4601                 RegValue |= BIT6 + BIT5;
4602         write_reg(info, TXS, RegValue);
4603
4604         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4605                 set_rate(info, info->params.clock_speed * DpllDivisor);
4606         else
4607                 set_rate(info, info->params.clock_speed);
4608
4609         /* GPDATA (General Purpose I/O Data Register)
4610          *
4611          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4612          */
4613         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4614                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4615         else
4616                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4617         write_control_reg(info);
4618
4619         /* RRC Receive Ready Control 0
4620          *
4621          * 07..05  Reserved, must be 0
4622          * 04..00  RRC<4..0> Rx FIFO trigger active
4623          */
4624         write_reg(info, RRC, rx_active_fifo_level);
4625
4626         /* TRC0 Transmit Ready Control 0
4627          *
4628          * 07..05  Reserved, must be 0
4629          * 04..00  TRC<4..0> Tx FIFO trigger active
4630          */
4631         write_reg(info, TRC0, tx_active_fifo_level);
4632
4633         /* TRC1 Transmit Ready Control 1
4634          *
4635          * 07..05  Reserved, must be 0
4636          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4637          */
4638         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4639
4640         /* DMR, DMA Mode Register
4641          *
4642          * 07..05  Reserved, must be 0
4643          * 04      TMOD, Transfer Mode: 1=chained-block
4644          * 03      Reserved, must be 0
4645          * 02      NF, Number of Frames: 1=multi-frame
4646          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4647          * 00      Reserved, must be 0
4648          *
4649          * 0001 0100
4650          */
4651         write_reg(info, TXDMA + DMR, 0x14);
4652         write_reg(info, RXDMA + DMR, 0x14);
4653
4654         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4655         write_reg(info, RXDMA + CPB,
4656                 (unsigned char)(info->buffer_list_phys >> 16));
4657
4658         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4659         write_reg(info, TXDMA + CPB,
4660                 (unsigned char)(info->buffer_list_phys >> 16));
4661
4662         /* enable status interrupts. other code enables/disables
4663          * the individual sources for these two interrupt classes.
4664          */
4665         info->ie0_value |= TXINTE + RXINTE;
4666         write_reg(info, IE0, info->ie0_value);
4667
4668         /* CTL, MSCI control register
4669          *
4670          * 07..06  Reserved, set to 0
4671          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4672          * 04      IDLC, idle control, 0=mark 1=idle register
4673          * 03      BRK, break, 0=off 1 =on (async)
4674          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4675          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4676          * 00      RTS, RTS output control, 0=active 1=inactive
4677          *
4678          * 0001 0001
4679          */
4680         RegValue = 0x10;
4681         if (!(info->serial_signals & SerialSignal_RTS))
4682                 RegValue |= 0x01;
4683         write_reg(info, CTL, RegValue);
4684
4685         /* preamble not supported ! */
4686
4687         tx_set_idle(info);
4688         tx_stop(info);
4689         rx_stop(info);
4690
4691         set_rate(info, info->params.clock_speed);
4692
4693         if (info->params.loopback)
4694                 enable_loopback(info,1);
4695 }
4696
4697 /* Set the transmit HDLC idle mode
4698  */
4699 static void tx_set_idle(SLMP_INFO *info)
4700 {
4701         unsigned char RegValue = 0xff;
4702
4703         /* Map API idle mode to SCA register bits */
4704         switch(info->idle_mode) {
4705         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4706         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4707         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4708         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4709         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4710         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4711         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4712         }
4713
4714         write_reg(info, IDL, RegValue);
4715 }
4716
4717 /* Query the adapter for the state of the V24 status (input) signals.
4718  */
4719 static void get_signals(SLMP_INFO *info)
4720 {
4721         u16 status = read_reg(info, SR3);
4722         u16 gpstatus = read_status_reg(info);
4723         u16 testbit;
4724
4725         /* clear all serial signals except RTS and DTR */
4726         info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4727
4728         /* set serial signal bits to reflect MISR */
4729
4730         if (!(status & BIT3))
4731                 info->serial_signals |= SerialSignal_CTS;
4732
4733         if ( !(status & BIT2))
4734                 info->serial_signals |= SerialSignal_DCD;
4735
4736         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4737         if (!(gpstatus & testbit))
4738                 info->serial_signals |= SerialSignal_RI;
4739
4740         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4741         if (!(gpstatus & testbit))
4742                 info->serial_signals |= SerialSignal_DSR;
4743 }
4744
4745 /* Set the state of RTS and DTR based on contents of
4746  * serial_signals member of device context.
4747  */
4748 static void set_signals(SLMP_INFO *info)
4749 {
4750         unsigned char RegValue;
4751         u16 EnableBit;
4752
4753         RegValue = read_reg(info, CTL);
4754         if (info->serial_signals & SerialSignal_RTS)
4755                 RegValue &= ~BIT0;
4756         else
4757                 RegValue |= BIT0;
4758         write_reg(info, CTL, RegValue);
4759
4760         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4761         EnableBit = BIT1 << (info->port_num*2);
4762         if (info->serial_signals & SerialSignal_DTR)
4763                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4764         else
4765                 info->port_array[0]->ctrlreg_value |= EnableBit;
4766         write_control_reg(info);
4767 }
4768
4769 /*******************/
4770 /* DMA Buffer Code */
4771 /*******************/
4772
4773 /* Set the count for all receive buffers to SCABUFSIZE
4774  * and set the current buffer to the first buffer. This effectively
4775  * makes all buffers free and discards any data in buffers.
4776  */
4777 static void rx_reset_buffers(SLMP_INFO *info)
4778 {
4779         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4780 }
4781
4782 /* Free the buffers used by a received frame
4783  *
4784  * info   pointer to device instance data
4785  * first  index of 1st receive buffer of frame
4786  * last   index of last receive buffer of frame
4787  */
4788 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4789 {
4790         bool done = false;
4791
4792         while(!done) {
4793                 /* reset current buffer for reuse */
4794                 info->rx_buf_list[first].status = 0xff;
4795
4796                 if (first == last) {
4797                         done = true;
4798                         /* set new last rx descriptor address */
4799                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4800                 }
4801
4802                 first++;
4803                 if (first == info->rx_buf_count)
4804                         first = 0;
4805         }
4806
4807         /* set current buffer to next buffer after last buffer of frame */
4808         info->current_rx_buf = first;
4809 }
4810
4811 /* Return a received frame from the receive DMA buffers.
4812  * Only frames received without errors are returned.
4813  *
4814  * Return Value:        true if frame returned, otherwise false
4815  */
4816 static bool rx_get_frame(SLMP_INFO *info)
4817 {
4818         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4819         unsigned short status;
4820         unsigned int framesize = 0;
4821         bool ReturnCode = false;
4822         unsigned long flags;
4823         struct tty_struct *tty = info->port.tty;
4824         unsigned char addr_field = 0xff;
4825         SCADESC *desc;
4826         SCADESC_EX *desc_ex;
4827
4828 CheckAgain:
4829         /* assume no frame returned, set zero length */
4830         framesize = 0;
4831         addr_field = 0xff;
4832
4833         /*
4834          * current_rx_buf points to the 1st buffer of the next available
4835          * receive frame. To find the last buffer of the frame look for
4836          * a non-zero status field in the buffer entries. (The status
4837          * field is set by the 16C32 after completing a receive frame.
4838          */
4839         StartIndex = EndIndex = info->current_rx_buf;
4840
4841         for ( ;; ) {
4842                 desc = &info->rx_buf_list[EndIndex];
4843                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4844
4845                 if (desc->status == 0xff)
4846                         goto Cleanup;   /* current desc still in use, no frames available */
4847
4848                 if (framesize == 0 && info->params.addr_filter != 0xff)
4849                         addr_field = desc_ex->virt_addr[0];
4850
4851                 framesize += desc->length;
4852
4853                 /* Status != 0 means last buffer of frame */
4854                 if (desc->status)
4855                         break;
4856
4857                 EndIndex++;
4858                 if (EndIndex == info->rx_buf_count)
4859                         EndIndex = 0;
4860
4861                 if (EndIndex == info->current_rx_buf) {
4862                         /* all buffers have been 'used' but none mark      */
4863                         /* the end of a frame. Reset buffers and receiver. */
4864                         if ( info->rx_enabled ){
4865                                 spin_lock_irqsave(&info->lock,flags);
4866                                 rx_start(info);
4867                                 spin_unlock_irqrestore(&info->lock,flags);
4868                         }
4869                         goto Cleanup;
4870                 }
4871
4872         }
4873
4874         /* check status of receive frame */
4875
4876         /* frame status is byte stored after frame data
4877          *
4878          * 7 EOM (end of msg), 1 = last buffer of frame
4879          * 6 Short Frame, 1 = short frame
4880          * 5 Abort, 1 = frame aborted
4881          * 4 Residue, 1 = last byte is partial
4882          * 3 Overrun, 1 = overrun occurred during frame reception
4883          * 2 CRC,     1 = CRC error detected
4884          *
4885          */
4886         status = desc->status;
4887
4888         /* ignore CRC bit if not using CRC (bit is undefined) */
4889         /* Note:CRC is not save to data buffer */
4890         if (info->params.crc_type == HDLC_CRC_NONE)
4891                 status &= ~BIT2;
4892
4893         if (framesize == 0 ||
4894                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4895                 /* discard 0 byte frames, this seems to occur sometime
4896                  * when remote is idling flags.
4897                  */
4898                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4899                 goto CheckAgain;
4900         }
4901
4902         if (framesize < 2)
4903                 status |= BIT6;
4904
4905         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4906                 /* received frame has errors,
4907                  * update counts and mark frame size as 0
4908                  */
4909                 if (status & BIT6)
4910                         info->icount.rxshort++;
4911                 else if (status & BIT5)
4912                         info->icount.rxabort++;
4913                 else if (status & BIT3)
4914                         info->icount.rxover++;
4915                 else
4916                         info->icount.rxcrc++;
4917
4918                 framesize = 0;
4919 #if SYNCLINK_GENERIC_HDLC
4920                 {
4921                         info->netdev->stats.rx_errors++;
4922                         info->netdev->stats.rx_frame_errors++;
4923                 }
4924 #endif
4925         }
4926
4927         if ( debug_level >= DEBUG_LEVEL_BH )
4928                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4929                         __FILE__,__LINE__,info->device_name,status,framesize);
4930
4931         if ( debug_level >= DEBUG_LEVEL_DATA )
4932                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4933                         min_t(unsigned int, framesize, SCABUFSIZE), 0);
4934
4935         if (framesize) {
4936                 if (framesize > info->max_frame_size)
4937                         info->icount.rxlong++;
4938                 else {
4939                         /* copy dma buffer(s) to contiguous intermediate buffer */
4940                         int copy_count = framesize;
4941                         int index = StartIndex;
4942                         unsigned char *ptmp = info->tmp_rx_buf;
4943                         info->tmp_rx_buf_count = framesize;
4944
4945                         info->icount.rxok++;
4946
4947                         while(copy_count) {
4948                                 int partial_count = min(copy_count,SCABUFSIZE);
4949                                 memcpy( ptmp,
4950                                         info->rx_buf_list_ex[index].virt_addr,
4951                                         partial_count );
4952                                 ptmp += partial_count;
4953                                 copy_count -= partial_count;
4954
4955                                 if ( ++index == info->rx_buf_count )
4956                                         index = 0;
4957                         }
4958
4959 #if SYNCLINK_GENERIC_HDLC
4960                         if (info->netcount)
4961                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4962                         else
4963 #endif
4964                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4965                                                   info->flag_buf, framesize);
4966                 }
4967         }
4968         /* Free the buffers used by this frame. */
4969         rx_free_frame_buffers( info, StartIndex, EndIndex );
4970
4971         ReturnCode = true;
4972
4973 Cleanup:
4974         if ( info->rx_enabled && info->rx_overflow ) {
4975                 /* Receiver is enabled, but needs to restarted due to
4976                  * rx buffer overflow. If buffers are empty, restart receiver.
4977                  */
4978                 if (info->rx_buf_list[EndIndex].status == 0xff) {
4979                         spin_lock_irqsave(&info->lock,flags);
4980                         rx_start(info);
4981                         spin_unlock_irqrestore(&info->lock,flags);
4982                 }
4983         }
4984
4985         return ReturnCode;
4986 }
4987
4988 /* load the transmit DMA buffer with data
4989  */
4990 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4991 {
4992         unsigned short copy_count;
4993         unsigned int i = 0;
4994         SCADESC *desc;
4995         SCADESC_EX *desc_ex;
4996
4997         if ( debug_level >= DEBUG_LEVEL_DATA )
4998                 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
4999
5000         /* Copy source buffer to one or more DMA buffers, starting with
5001          * the first transmit dma buffer.
5002          */
5003         for(i=0;;)
5004         {
5005                 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5006
5007                 desc = &info->tx_buf_list[i];
5008                 desc_ex = &info->tx_buf_list_ex[i];
5009
5010                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5011
5012                 desc->length = copy_count;
5013                 desc->status = 0;
5014
5015                 buf += copy_count;
5016                 count -= copy_count;
5017
5018                 if (!count)
5019                         break;
5020
5021                 i++;
5022                 if (i >= info->tx_buf_count)
5023                         i = 0;
5024         }
5025
5026         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5027         info->last_tx_buf = ++i;
5028 }
5029
5030 static bool register_test(SLMP_INFO *info)
5031 {
5032         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5033         static unsigned int count = ARRAY_SIZE(testval);
5034         unsigned int i;
5035         bool rc = true;
5036         unsigned long flags;
5037
5038         spin_lock_irqsave(&info->lock,flags);
5039         reset_port(info);
5040
5041         /* assume failure */
5042         info->init_error = DiagStatus_AddressFailure;
5043
5044         /* Write bit patterns to various registers but do it out of */
5045         /* sync, then read back and verify values. */
5046
5047         for (i = 0 ; i < count ; i++) {
5048                 write_reg(info, TMC, testval[i]);
5049                 write_reg(info, IDL, testval[(i+1)%count]);
5050                 write_reg(info, SA0, testval[(i+2)%count]);
5051                 write_reg(info, SA1, testval[(i+3)%count]);
5052
5053                 if ( (read_reg(info, TMC) != testval[i]) ||
5054                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5055                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5056                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5057                 {
5058                         rc = false;
5059                         break;
5060                 }
5061         }
5062
5063         reset_port(info);
5064         spin_unlock_irqrestore(&info->lock,flags);
5065
5066         return rc;
5067 }
5068
5069 static bool irq_test(SLMP_INFO *info)
5070 {
5071         unsigned long timeout;
5072         unsigned long flags;
5073
5074         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5075
5076         spin_lock_irqsave(&info->lock,flags);
5077         reset_port(info);
5078
5079         /* assume failure */
5080         info->init_error = DiagStatus_IrqFailure;
5081         info->irq_occurred = false;
5082
5083         /* setup timer0 on SCA0 to interrupt */
5084
5085         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5086         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5087
5088         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5089         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5090
5091
5092         /* TMCS, Timer Control/Status Register
5093          *
5094          * 07      CMF, Compare match flag (read only) 1=match
5095          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5096          * 05      Reserved, must be 0
5097          * 04      TME, Timer Enable
5098          * 03..00  Reserved, must be 0
5099          *
5100          * 0101 0000
5101          */
5102         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5103
5104         spin_unlock_irqrestore(&info->lock,flags);
5105
5106         timeout=100;
5107         while( timeout-- && !info->irq_occurred ) {
5108                 msleep_interruptible(10);
5109         }
5110
5111         spin_lock_irqsave(&info->lock,flags);
5112         reset_port(info);
5113         spin_unlock_irqrestore(&info->lock,flags);
5114
5115         return info->irq_occurred;
5116 }
5117
5118 /* initialize individual SCA device (2 ports)
5119  */
5120 static bool sca_init(SLMP_INFO *info)
5121 {
5122         /* set wait controller to single mem partition (low), no wait states */
5123         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5124         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5125         write_reg(info, WCRL, 0);       /* wait controller low range */
5126         write_reg(info, WCRM, 0);       /* wait controller mid range */
5127         write_reg(info, WCRH, 0);       /* wait controller high range */
5128
5129         /* DPCR, DMA Priority Control
5130          *
5131          * 07..05  Not used, must be 0
5132          * 04      BRC, bus release condition: 0=all transfers complete
5133          * 03      CCC, channel change condition: 0=every cycle
5134          * 02..00  PR<2..0>, priority 100=round robin
5135          *
5136          * 00000100 = 0x04
5137          */
5138         write_reg(info, DPCR, dma_priority);
5139
5140         /* DMA Master Enable, BIT7: 1=enable all channels */
5141         write_reg(info, DMER, 0x80);
5142
5143         /* enable all interrupt classes */
5144         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5145         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5146         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5147
5148         /* ITCR, interrupt control register
5149          * 07      IPC, interrupt priority, 0=MSCI->DMA
5150          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5151          * 04      VOS, Vector Output, 0=unmodified vector
5152          * 03..00  Reserved, must be 0
5153          */
5154         write_reg(info, ITCR, 0);
5155
5156         return true;
5157 }
5158
5159 /* initialize adapter hardware
5160  */
5161 static bool init_adapter(SLMP_INFO *info)
5162 {
5163         int i;
5164
5165         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5166         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5167         u32 readval;
5168
5169         info->misc_ctrl_value |= BIT30;
5170         *MiscCtrl = info->misc_ctrl_value;
5171
5172         /*
5173          * Force at least 170ns delay before clearing
5174          * reset bit. Each read from LCR takes at least
5175          * 30ns so 10 times for 300ns to be safe.
5176          */
5177         for(i=0;i<10;i++)
5178                 readval = *MiscCtrl;
5179
5180         info->misc_ctrl_value &= ~BIT30;
5181         *MiscCtrl = info->misc_ctrl_value;
5182
5183         /* init control reg (all DTRs off, all clksel=input) */
5184         info->ctrlreg_value = 0xaa;
5185         write_control_reg(info);
5186
5187         {
5188                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5189                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5190
5191                 switch(read_ahead_count)
5192                 {
5193                 case 16:
5194                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5195                         break;
5196                 case 8:
5197                         lcr1_brdr_value |= BIT5 + BIT4;
5198                         break;
5199                 case 4:
5200                         lcr1_brdr_value |= BIT5 + BIT3;
5201                         break;
5202                 case 0:
5203                         lcr1_brdr_value |= BIT5;
5204                         break;
5205                 }
5206
5207                 *LCR1BRDR = lcr1_brdr_value;
5208                 *MiscCtrl = misc_ctrl_value;
5209         }
5210
5211         sca_init(info->port_array[0]);
5212         sca_init(info->port_array[2]);
5213
5214         return true;
5215 }
5216
5217 /* Loopback an HDLC frame to test the hardware
5218  * interrupt and DMA functions.
5219  */
5220 static bool loopback_test(SLMP_INFO *info)
5221 {
5222 #define TESTFRAMESIZE 20
5223
5224         unsigned long timeout;
5225         u16 count = TESTFRAMESIZE;
5226         unsigned char buf[TESTFRAMESIZE];
5227         bool rc = false;
5228         unsigned long flags;
5229
5230         struct tty_struct *oldtty = info->port.tty;
5231         u32 speed = info->params.clock_speed;
5232
5233         info->params.clock_speed = 3686400;
5234         info->port.tty = NULL;
5235
5236         /* assume failure */
5237         info->init_error = DiagStatus_DmaFailure;
5238
5239         /* build and send transmit frame */
5240         for (count = 0; count < TESTFRAMESIZE;++count)
5241                 buf[count] = (unsigned char)count;
5242
5243         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5244
5245         /* program hardware for HDLC and enabled receiver */
5246         spin_lock_irqsave(&info->lock,flags);
5247         hdlc_mode(info);
5248         enable_loopback(info,1);
5249         rx_start(info);
5250         info->tx_count = count;
5251         tx_load_dma_buffer(info,buf,count);
5252         tx_start(info);
5253         spin_unlock_irqrestore(&info->lock,flags);
5254
5255         /* wait for receive complete */
5256         /* Set a timeout for waiting for interrupt. */
5257         for ( timeout = 100; timeout; --timeout ) {
5258                 msleep_interruptible(10);
5259
5260                 if (rx_get_frame(info)) {
5261                         rc = true;
5262                         break;
5263                 }
5264         }
5265
5266         /* verify received frame length and contents */
5267         if (rc &&
5268             ( info->tmp_rx_buf_count != count ||
5269               memcmp(buf, info->tmp_rx_buf,count))) {
5270                 rc = false;
5271         }
5272
5273         spin_lock_irqsave(&info->lock,flags);
5274         reset_adapter(info);
5275         spin_unlock_irqrestore(&info->lock,flags);
5276
5277         info->params.clock_speed = speed;
5278         info->port.tty = oldtty;
5279
5280         return rc;
5281 }
5282
5283 /* Perform diagnostics on hardware
5284  */
5285 static int adapter_test( SLMP_INFO *info )
5286 {
5287         unsigned long flags;
5288         if ( debug_level >= DEBUG_LEVEL_INFO )
5289                 printk( "%s(%d):Testing device %s\n",
5290                         __FILE__,__LINE__,info->device_name );
5291
5292         spin_lock_irqsave(&info->lock,flags);
5293         init_adapter(info);
5294         spin_unlock_irqrestore(&info->lock,flags);
5295
5296         info->port_array[0]->port_count = 0;
5297
5298         if ( register_test(info->port_array[0]) &&
5299                 register_test(info->port_array[1])) {
5300
5301                 info->port_array[0]->port_count = 2;
5302
5303                 if ( register_test(info->port_array[2]) &&
5304                         register_test(info->port_array[3]) )
5305                         info->port_array[0]->port_count += 2;
5306         }
5307         else {
5308                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5309                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5310                 return -ENODEV;
5311         }
5312
5313         if ( !irq_test(info->port_array[0]) ||
5314                 !irq_test(info->port_array[1]) ||
5315                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5316                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5317                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5318                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5319                 return -ENODEV;
5320         }
5321
5322         if (!loopback_test(info->port_array[0]) ||
5323                 !loopback_test(info->port_array[1]) ||
5324                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5325                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5326                 printk( "%s(%d):DMA test failure for device %s\n",
5327                         __FILE__,__LINE__,info->device_name);
5328                 return -ENODEV;
5329         }
5330
5331         if ( debug_level >= DEBUG_LEVEL_INFO )
5332                 printk( "%s(%d):device %s passed diagnostics\n",
5333                         __FILE__,__LINE__,info->device_name );
5334
5335         info->port_array[0]->init_error = 0;
5336         info->port_array[1]->init_error = 0;
5337         if ( info->port_count > 2 ) {
5338                 info->port_array[2]->init_error = 0;
5339                 info->port_array[3]->init_error = 0;
5340         }
5341
5342         return 0;
5343 }
5344
5345 /* Test the shared memory on a PCI adapter.
5346  */
5347 static bool memory_test(SLMP_INFO *info)
5348 {
5349         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5350                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5351         unsigned long count = ARRAY_SIZE(testval);
5352         unsigned long i;
5353         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5354         unsigned long * addr = (unsigned long *)info->memory_base;
5355
5356         /* Test data lines with test pattern at one location. */
5357
5358         for ( i = 0 ; i < count ; i++ ) {
5359                 *addr = testval[i];
5360                 if ( *addr != testval[i] )
5361                         return false;
5362         }
5363
5364         /* Test address lines with incrementing pattern over */
5365         /* entire address range. */
5366
5367         for ( i = 0 ; i < limit ; i++ ) {
5368                 *addr = i * 4;
5369                 addr++;
5370         }
5371
5372         addr = (unsigned long *)info->memory_base;
5373
5374         for ( i = 0 ; i < limit ; i++ ) {
5375                 if ( *addr != i * 4 )
5376                         return false;
5377                 addr++;
5378         }
5379
5380         memset( info->memory_base, 0, SCA_MEM_SIZE );
5381         return true;
5382 }
5383
5384 /* Load data into PCI adapter shared memory.
5385  *
5386  * The PCI9050 releases control of the local bus
5387  * after completing the current read or write operation.
5388  *
5389  * While the PCI9050 write FIFO not empty, the
5390  * PCI9050 treats all of the writes as a single transaction
5391  * and does not release the bus. This causes DMA latency problems
5392  * at high speeds when copying large data blocks to the shared memory.
5393  *
5394  * This function breaks a write into multiple transations by
5395  * interleaving a read which flushes the write FIFO and 'completes'
5396  * the write transation. This allows any pending DMA request to gain control
5397  * of the local bus in a timely fasion.
5398  */
5399 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5400 {
5401         /* A load interval of 16 allows for 4 32-bit writes at */
5402         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5403
5404         unsigned short interval = count / sca_pci_load_interval;
5405         unsigned short i;
5406
5407         for ( i = 0 ; i < interval ; i++ )
5408         {
5409                 memcpy(dest, src, sca_pci_load_interval);
5410                 read_status_reg(info);
5411                 dest += sca_pci_load_interval;
5412                 src += sca_pci_load_interval;
5413         }
5414
5415         memcpy(dest, src, count % sca_pci_load_interval);
5416 }
5417
5418 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5419 {
5420         int i;
5421         int linecount;
5422         if (xmit)
5423                 printk("%s tx data:\n",info->device_name);
5424         else
5425                 printk("%s rx data:\n",info->device_name);
5426
5427         while(count) {
5428                 if (count > 16)
5429                         linecount = 16;
5430                 else
5431                         linecount = count;
5432
5433                 for(i=0;i<linecount;i++)
5434                         printk("%02X ",(unsigned char)data[i]);
5435                 for(;i<17;i++)
5436                         printk("   ");
5437                 for(i=0;i<linecount;i++) {
5438                         if (data[i]>=040 && data[i]<=0176)
5439                                 printk("%c",data[i]);
5440                         else
5441                                 printk(".");
5442                 }
5443                 printk("\n");
5444
5445                 data  += linecount;
5446                 count -= linecount;
5447         }
5448 }       /* end of trace_block() */
5449
5450 /* called when HDLC frame times out
5451  * update stats and do tx completion processing
5452  */
5453 static void tx_timeout(struct timer_list *t)
5454 {
5455         SLMP_INFO *info = from_timer(info, t, tx_timer);
5456         unsigned long flags;
5457
5458         if ( debug_level >= DEBUG_LEVEL_INFO )
5459                 printk( "%s(%d):%s tx_timeout()\n",
5460                         __FILE__,__LINE__,info->device_name);
5461         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5462                 info->icount.txtimeout++;
5463         }
5464         spin_lock_irqsave(&info->lock,flags);
5465         info->tx_active = false;
5466         info->tx_count = info->tx_put = info->tx_get = 0;
5467
5468         spin_unlock_irqrestore(&info->lock,flags);
5469
5470 #if SYNCLINK_GENERIC_HDLC
5471         if (info->netcount)
5472                 hdlcdev_tx_done(info);
5473         else
5474 #endif
5475                 bh_transmit(info);
5476 }
5477
5478 /* called to periodically check the DSR/RI modem signal input status
5479  */
5480 static void status_timeout(struct timer_list *t)
5481 {
5482         u16 status = 0;
5483         SLMP_INFO *info = from_timer(info, t, status_timer);
5484         unsigned long flags;
5485         unsigned char delta;
5486
5487
5488         spin_lock_irqsave(&info->lock,flags);
5489         get_signals(info);
5490         spin_unlock_irqrestore(&info->lock,flags);
5491
5492         /* check for DSR/RI state change */
5493
5494         delta = info->old_signals ^ info->serial_signals;
5495         info->old_signals = info->serial_signals;
5496
5497         if (delta & SerialSignal_DSR)
5498                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5499
5500         if (delta & SerialSignal_RI)
5501                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5502
5503         if (delta & SerialSignal_DCD)
5504                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5505
5506         if (delta & SerialSignal_CTS)
5507                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5508
5509         if (status)
5510                 isr_io_pin(info,status);
5511
5512         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5513 }
5514
5515
5516 /* Register Access Routines -
5517  * All registers are memory mapped
5518  */
5519 #define CALC_REGADDR() \
5520         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5521         if (info->port_num > 1) \
5522                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5523         if ( info->port_num & 1) { \
5524                 if (Addr > 0x7f) \
5525                         RegAddr += 0x40;        /* DMA access */ \
5526                 else if (Addr > 0x1f && Addr < 0x60) \
5527                         RegAddr += 0x20;        /* MSCI access */ \
5528         }
5529
5530
5531 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5532 {
5533         CALC_REGADDR();
5534         return *RegAddr;
5535 }
5536 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5537 {
5538         CALC_REGADDR();
5539         *RegAddr = Value;
5540 }
5541
5542 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5543 {
5544         CALC_REGADDR();
5545         return *((u16 *)RegAddr);
5546 }
5547
5548 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5549 {
5550         CALC_REGADDR();
5551         *((u16 *)RegAddr) = Value;
5552 }
5553
5554 static unsigned char read_status_reg(SLMP_INFO * info)
5555 {
5556         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5557         return *RegAddr;
5558 }
5559
5560 static void write_control_reg(SLMP_INFO * info)
5561 {
5562         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5563         *RegAddr = info->port_array[0]->ctrlreg_value;
5564 }
5565
5566
5567 static int synclinkmp_init_one (struct pci_dev *dev,
5568                                           const struct pci_device_id *ent)
5569 {
5570         if (pci_enable_device(dev)) {
5571                 printk("error enabling pci device %p\n", dev);
5572                 return -EIO;
5573         }
5574         return device_init( ++synclinkmp_adapter_count, dev );
5575 }
5576
5577 static void synclinkmp_remove_one (struct pci_dev *dev)
5578 {
5579 }