drivers/tty/synclink_gt.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Device driver for Microgate SyncLink GT serial adapters.
   4  *
   5  * written by Paul Fulghum for Microgate Corporation
   6  * paulkf@microgate.com
   7  *
   8  * Microgate and SyncLink are trademarks of Microgate Corporation
   9  *
  10  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20  * OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 /*
  24  * DEBUG OUTPUT DEFINITIONS
  25  *
  26  * uncomment lines below to enable specific types of debug output
  27  *
  28  * DBGINFO   information - most verbose output
  29  * DBGERR    serious errors
  30  * DBGBH     bottom half service routine debugging
  31  * DBGISR    interrupt service routine debugging
  32  * DBGDATA   output receive and transmit data
  33  * DBGTBUF   output transmit DMA buffers and registers
  34  * DBGRBUF   output receive DMA buffers and registers
  35  */
  36
  37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42 /*#define DBGTBUF(info) dump_tbufs(info)*/
  43 /*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46 #include <linux/module.h>
  47 #include <linux/errno.h>
  48 #include <linux/signal.h>
  49 #include <linux/sched.h>
  50 #include <linux/timer.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/pci.h>
  53 #include <linux/tty.h>
  54 #include <linux/tty_flip.h>
  55 #include <linux/serial.h>
  56 #include <linux/major.h>
  57 #include <linux/string.h>
  58 #include <linux/fcntl.h>
  59 #include <linux/ptrace.h>
  60 #include <linux/ioport.h>
  61 #include <linux/mm.h>
  62 #include <linux/seq_file.h>
  63 #include <linux/slab.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/init.h>
  67 #include <linux/delay.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/termios.h>
  70 #include <linux/bitops.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/hdlc.h>
  73 #include <linux/synclink.h>
  74
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77 #include <asm/dma.h>
  78 #include <asm/types.h>
  79 #include <linux/uaccess.h>
  80
  81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82 #define SYNCLINK_GENERIC_HDLC 1
  83 #else
  84 #define SYNCLINK_GENERIC_HDLC 0
  85 #endif
  86
  87 /*
  88  * module identification
  89  */
  90 static char *driver_name     = "SyncLink GT";
  91 static char *slgt_driver_name = "synclink_gt";
  92 static char *tty_dev_prefix  = "ttySLG";
  93 MODULE_LICENSE("GPL");
  94 #define MGSL_MAGIC 0x5401
  95 #define MAX_DEVICES 32
  96
  97 static const struct pci_device_id pci_table[] = {
  98         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {0,}, /* terminate list */
 103 };
 104 MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107 static void remove_one(struct pci_dev *dev);
 108 static struct pci_driver pci_driver = {
 109         .name           = "synclink_gt",
 110         .id_table       = pci_table,
 111         .probe          = init_one,
 112         .remove         = remove_one,
 113 };
 114
 115 static bool pci_registered;
 116
 117 /*
 118  * module configuration and status
 119  */
 120 static struct slgt_info *slgt_device_list;
 121 static int slgt_device_count;
 122
 123 static int ttymajor;
 124 static int debug_level;
 125 static int maxframe[MAX_DEVICES];
 126
 127 module_param(ttymajor, int, 0);
 128 module_param(debug_level, int, 0);
 129 module_param_array(maxframe, int, NULL, 0);
 130
 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135 /*
 136  * tty support and callbacks
 137  */
 138 static struct tty_driver *serial_driver;
 139
 140 static int  open(struct tty_struct *tty, struct file * filp);
 141 static void close(struct tty_struct *tty, struct file * filp);
 142 static void hangup(struct tty_struct *tty);
 143 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 144
 145 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 146 static int put_char(struct tty_struct *tty, unsigned char ch);
 147 static void send_xchar(struct tty_struct *tty, char ch);
 148 static void wait_until_sent(struct tty_struct *tty, int timeout);
 149 static int  write_room(struct tty_struct *tty);
 150 static void flush_chars(struct tty_struct *tty);
 151 static void flush_buffer(struct tty_struct *tty);
 152 static void tx_hold(struct tty_struct *tty);
 153 static void tx_release(struct tty_struct *tty);
 154
 155 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 156 static int  chars_in_buffer(struct tty_struct *tty);
 157 static void throttle(struct tty_struct * tty);
 158 static void unthrottle(struct tty_struct * tty);
 159 static int set_break(struct tty_struct *tty, int break_state);
 160
 161 /*
 162  * generic HDLC support and callbacks
 163  */
 164 #if SYNCLINK_GENERIC_HDLC
 165 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 166 static void hdlcdev_tx_done(struct slgt_info *info);
 167 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 168 static int  hdlcdev_init(struct slgt_info *info);
 169 static void hdlcdev_exit(struct slgt_info *info);
 170 #endif
 171
 172
 173 /*
 174  * device specific structures, macros and functions
 175  */
 176
 177 #define SLGT_MAX_PORTS 4
 178 #define SLGT_REG_SIZE  256
 179
 180 /*
 181  * conditional wait facility
 182  */
 183 struct cond_wait {
 184         struct cond_wait *next;
 185         wait_queue_head_t q;
 186         wait_queue_entry_t wait;
 187         unsigned int data;
 188 };
 189 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 190 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 191 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192 static void flush_cond_wait(struct cond_wait **head);
 193
 194 /*
 195  * DMA buffer descriptor and access macros
 196  */
 197 struct slgt_desc
 198 {
 199         __le16 count;
 200         __le16 status;
 201         __le32 pbuf;  /* physical address of data buffer */
 202         __le32 next;  /* physical address of next descriptor */
 203
 204         /* driver book keeping */
 205         char *buf;          /* virtual  address of data buffer */
 206         unsigned int pdesc; /* physical address of this descriptor */
 207         dma_addr_t buf_dma_addr;
 208         unsigned short buf_count;
 209 };
 210
 211 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 212 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 213 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 214 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 215 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 216 #define desc_count(a)      (le16_to_cpu((a).count))
 217 #define desc_status(a)     (le16_to_cpu((a).status))
 218 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 219 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 220 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 221 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 222 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 223
 224 struct _input_signal_events {
 225         int ri_up;
 226         int ri_down;
 227         int dsr_up;
 228         int dsr_down;
 229         int dcd_up;
 230         int dcd_down;
 231         int cts_up;
 232         int cts_down;
 233 };
 234
 235 /*
 236  * device instance data structure
 237  */
 238 struct slgt_info {
 239         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 240         struct tty_port port;
 241
 242         struct slgt_info *next_device;  /* device list link */
 243
 244         int magic;
 245
 246         char device_name[25];
 247         struct pci_dev *pdev;
 248
 249         int port_count;  /* count of ports on adapter */
 250         int adapter_num; /* adapter instance number */
 251         int port_num;    /* port instance number */
 252
 253         /* array of pointers to port contexts on this adapter */
 254         struct slgt_info *port_array[SLGT_MAX_PORTS];
 255
 256         int                     line;           /* tty line instance number */
 257
 258         struct mgsl_icount      icount;
 259
 260         int                     timeout;
 261         int                     x_char;         /* xon/xoff character */
 262         unsigned int            read_status_mask;
 263         unsigned int            ignore_status_mask;
 264
 265         wait_queue_head_t       status_event_wait_q;
 266         wait_queue_head_t       event_wait_q;
 267         struct timer_list       tx_timer;
 268         struct timer_list       rx_timer;
 269
 270         unsigned int            gpio_present;
 271         struct cond_wait        *gpio_wait_q;
 272
 273         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 274
 275         struct work_struct task;
 276         u32 pending_bh;
 277         bool bh_requested;
 278         bool bh_running;
 279
 280         int isr_overflow;
 281         bool irq_requested;     /* true if IRQ requested */
 282         bool irq_occurred;      /* for diagnostics use */
 283
 284         /* device configuration */
 285
 286         unsigned int bus_type;
 287         unsigned int irq_level;
 288         unsigned long irq_flags;
 289
 290         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 291         u32 phys_reg_addr;
 292         bool reg_addr_requested;
 293
 294         MGSL_PARAMS params;       /* communications parameters */
 295         u32 idle_mode;
 296         u32 max_frame_size;       /* as set by device config */
 297
 298         unsigned int rbuf_fill_level;
 299         unsigned int rx_pio;
 300         unsigned int if_mode;
 301         unsigned int base_clock;
 302         unsigned int xsync;
 303         unsigned int xctrl;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char *flag_buf;
 320         bool drop_rts_on_tx_done;
 321         struct  _input_signal_events    input_signal_events;
 322
 323         int dcd_chkcount;       /* check counts to prevent */
 324         int cts_chkcount;       /* too many IRQs if a signal */
 325         int dsr_chkcount;       /* is floating */
 326         int ri_chkcount;
 327
 328         char *bufs;             /* virtual address of DMA buffer lists */
 329         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 330
 331         unsigned int rbuf_count;
 332         struct slgt_desc *rbufs;
 333         unsigned int rbuf_current;
 334         unsigned int rbuf_index;
 335         unsigned int rbuf_fill_index;
 336         unsigned short rbuf_fill_count;
 337
 338         unsigned int tbuf_count;
 339         struct slgt_desc *tbufs;
 340         unsigned int tbuf_current;
 341         unsigned int tbuf_start;
 342
 343         unsigned char *tmp_rbuf;
 344         unsigned int tmp_rbuf_count;
 345
 346         /* SPPP/Cisco HDLC device parts */
 347
 348         int netcount;
 349         spinlock_t netlock;
 350 #if SYNCLINK_GENERIC_HDLC
 351         struct net_device *netdev;
 352 #endif
 353
 354 };
 355
 356 static MGSL_PARAMS default_params = {
 357         .mode            = MGSL_MODE_HDLC,
 358         .loopback        = 0,
 359         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 360         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 361         .clock_speed     = 0,
 362         .addr_filter     = 0xff,
 363         .crc_type        = HDLC_CRC_16_CCITT,
 364         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 365         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 366         .data_rate       = 9600,
 367         .data_bits       = 8,
 368         .stop_bits       = 1,
 369         .parity          = ASYNC_PARITY_NONE
 370 };
 371
 372
 373 #define BH_RECEIVE  1
 374 #define BH_TRANSMIT 2
 375 #define BH_STATUS   4
 376 #define IO_PIN_SHUTDOWN_LIMIT 100
 377
 378 #define DMABUFSIZE 256
 379 #define DESC_LIST_SIZE 4096
 380
 381 #define MASK_PARITY  BIT1
 382 #define MASK_FRAMING BIT0
 383 #define MASK_BREAK   BIT14
 384 #define MASK_OVERRUN BIT4
 385
 386 #define GSR   0x00 /* global status */
 387 #define JCR   0x04 /* JTAG control */
 388 #define IODR  0x08 /* GPIO direction */
 389 #define IOER  0x0c /* GPIO interrupt enable */
 390 #define IOVR  0x10 /* GPIO value */
 391 #define IOSR  0x14 /* GPIO interrupt status */
 392 #define TDR   0x80 /* tx data */
 393 #define RDR   0x80 /* rx data */
 394 #define TCR   0x82 /* tx control */
 395 #define TIR   0x84 /* tx idle */
 396 #define TPR   0x85 /* tx preamble */
 397 #define RCR   0x86 /* rx control */
 398 #define VCR   0x88 /* V.24 control */
 399 #define CCR   0x89 /* clock control */
 400 #define BDR   0x8a /* baud divisor */
 401 #define SCR   0x8c /* serial control */
 402 #define SSR   0x8e /* serial status */
 403 #define RDCSR 0x90 /* rx DMA control/status */
 404 #define TDCSR 0x94 /* tx DMA control/status */
 405 #define RDDAR 0x98 /* rx DMA descriptor address */
 406 #define TDDAR 0x9c /* tx DMA descriptor address */
 407 #define XSR   0x40 /* extended sync pattern */
 408 #define XCR   0x44 /* extended control */
 409
 410 #define RXIDLE      BIT14
 411 #define RXBREAK     BIT14
 412 #define IRQ_TXDATA  BIT13
 413 #define IRQ_TXIDLE  BIT12
 414 #define IRQ_TXUNDER BIT11 /* HDLC */
 415 #define IRQ_RXDATA  BIT10
 416 #define IRQ_RXIDLE  BIT9  /* HDLC */
 417 #define IRQ_RXBREAK BIT9  /* async */
 418 #define IRQ_RXOVER  BIT8
 419 #define IRQ_DSR     BIT7
 420 #define IRQ_CTS     BIT6
 421 #define IRQ_DCD     BIT5
 422 #define IRQ_RI      BIT4
 423 #define IRQ_ALL     0x3ff0
 424 #define IRQ_MASTER  BIT0
 425
 426 #define slgt_irq_on(info, mask) \
 427         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 428 #define slgt_irq_off(info, mask) \
 429         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 430
 431 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 432 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 434 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 436 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 437
 438 static void  msc_set_vcr(struct slgt_info *info);
 439
 440 static int  startup(struct slgt_info *info);
 441 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 442 static void shutdown(struct slgt_info *info);
 443 static void program_hw(struct slgt_info *info);
 444 static void change_params(struct slgt_info *info);
 445
 446 static int  register_test(struct slgt_info *info);
 447 static int  irq_test(struct slgt_info *info);
 448 static int  loopback_test(struct slgt_info *info);
 449 static int  adapter_test(struct slgt_info *info);
 450
 451 static void reset_adapter(struct slgt_info *info);
 452 static void reset_port(struct slgt_info *info);
 453 static void async_mode(struct slgt_info *info);
 454 static void sync_mode(struct slgt_info *info);
 455
 456 static void rx_stop(struct slgt_info *info);
 457 static void rx_start(struct slgt_info *info);
 458 static void reset_rbufs(struct slgt_info *info);
 459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 460 static void rdma_reset(struct slgt_info *info);
 461 static bool rx_get_frame(struct slgt_info *info);
 462 static bool rx_get_buf(struct slgt_info *info);
 463
 464 static void tx_start(struct slgt_info *info);
 465 static void tx_stop(struct slgt_info *info);
 466 static void tx_set_idle(struct slgt_info *info);
 467 static unsigned int free_tbuf_count(struct slgt_info *info);
 468 static unsigned int tbuf_bytes(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 472
 473 static void get_signals(struct slgt_info *info);
 474 static void set_signals(struct slgt_info *info);
 475 static void enable_loopback(struct slgt_info *info);
 476 static void set_rate(struct slgt_info *info, u32 data_rate);
 477
 478 static int  bh_action(struct slgt_info *info);
 479 static void bh_handler(struct work_struct *work);
 480 static void bh_transmit(struct slgt_info *info);
 481 static void isr_serial(struct slgt_info *info);
 482 static void isr_rdma(struct slgt_info *info);
 483 static void isr_txeom(struct slgt_info *info, unsigned short status);
 484 static void isr_tdma(struct slgt_info *info);
 485
 486 static int  alloc_dma_bufs(struct slgt_info *info);
 487 static void free_dma_bufs(struct slgt_info *info);
 488 static int  alloc_desc(struct slgt_info *info);
 489 static void free_desc(struct slgt_info *info);
 490 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492
 493 static int  alloc_tmp_rbuf(struct slgt_info *info);
 494 static void free_tmp_rbuf(struct slgt_info *info);
 495
 496 static void tx_timeout(struct timer_list *t);
 497 static void rx_timeout(struct timer_list *t);
 498
 499 /*
 500  * ioctl handlers
 501  */
 502 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 503 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 506 static int  set_txidle(struct slgt_info *info, int idle_mode);
 507 static int  tx_enable(struct slgt_info *info, int enable);
 508 static int  tx_abort(struct slgt_info *info);
 509 static int  rx_enable(struct slgt_info *info, int enable);
 510 static int  modem_input_wait(struct slgt_info *info,int arg);
 511 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 512 static int  tiocmget(struct tty_struct *tty);
 513 static int  tiocmset(struct tty_struct *tty,
 514                                 unsigned int set, unsigned int clear);
 515 static int set_break(struct tty_struct *tty, int break_state);
 516 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 517 static int  set_interface(struct slgt_info *info, int if_mode);
 518 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 522 static int  set_xsync(struct slgt_info *info, int if_mode);
 523 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 524 static int  set_xctrl(struct slgt_info *info, int if_mode);
 525
 526 /*
 527  * driver functions
 528  */
 529 static void add_device(struct slgt_info *info);
 530 static void device_init(int adapter_num, struct pci_dev *pdev);
 531 static int  claim_resources(struct slgt_info *info);
 532 static void release_resources(struct slgt_info *info);
 533
 534 /*
 535  * DEBUG OUTPUT CODE
 536  */
 537 #ifndef DBGINFO
 538 #define DBGINFO(fmt)
 539 #endif
 540 #ifndef DBGERR
 541 #define DBGERR(fmt)
 542 #endif
 543 #ifndef DBGBH
 544 #define DBGBH(fmt)
 545 #endif
 546 #ifndef DBGISR
 547 #define DBGISR(fmt)
 548 #endif
 549
 550 #ifdef DBGDATA
 551 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 552 {
 553         int i;
 554         int linecount;
 555         printk("%s %s data:\n",info->device_name, label);
 556         while(count) {
 557                 linecount = (count > 16) ? 16 : count;
 558                 for(i=0; i < linecount; i++)
 559                         printk("%02X ",(unsigned char)data[i]);
 560                 for(;i<17;i++)
 561                         printk("   ");
 562                 for(i=0;i<linecount;i++) {
 563                         if (data[i]>=040 && data[i]<=0176)
 564                                 printk("%c",data[i]);
 565                         else
 566                                 printk(".");
 567                 }
 568                 printk("\n");
 569                 data  += linecount;
 570                 count -= linecount;
 571         }
 572 }
 573 #else
 574 #define DBGDATA(info, buf, size, label)
 575 #endif
 576
 577 #ifdef DBGTBUF
 578 static void dump_tbufs(struct slgt_info *info)
 579 {
 580         int i;
 581         printk("tbuf_current=%d\n", info->tbuf_current);
 582         for (i=0 ; i < info->tbuf_count ; i++) {
 583                 printk("%d: count=%04X status=%04X\n",
 584                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 585         }
 586 }
 587 #else
 588 #define DBGTBUF(info)
 589 #endif
 590
 591 #ifdef DBGRBUF
 592 static void dump_rbufs(struct slgt_info *info)
 593 {
 594         int i;
 595         printk("rbuf_current=%d\n", info->rbuf_current);
 596         for (i=0 ; i < info->rbuf_count ; i++) {
 597                 printk("%d: count=%04X status=%04X\n",
 598                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 599         }
 600 }
 601 #else
 602 #define DBGRBUF(info)
 603 #endif
 604
 605 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 606 {
 607 #ifdef SANITY_CHECK
 608         if (!info) {
 609                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 610                 return 1;
 611         }
 612         if (info->magic != MGSL_MAGIC) {
 613                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 614                 return 1;
 615         }
 616 #else
 617         if (!info)
 618                 return 1;
 619 #endif
 620         return 0;
 621 }
 622
 623 /**
 624  * line discipline callback wrappers
 625  *
 626  * The wrappers maintain line discipline references
 627  * while calling into the line discipline.
 628  *
 629  * ldisc_receive_buf  - pass receive data to line discipline
 630  */
 631 static void ldisc_receive_buf(struct tty_struct *tty,
 632                               const __u8 *data, char *flags, int count)
 633 {
 634         struct tty_ldisc *ld;
 635         if (!tty)
 636                 return;
 637         ld = tty_ldisc_ref(tty);
 638         if (ld) {
 639                 if (ld->ops->receive_buf)
 640                         ld->ops->receive_buf(tty, data, flags, count);
 641                 tty_ldisc_deref(ld);
 642         }
 643 }
 644
 645 /* tty callbacks */
 646
 647 static int open(struct tty_struct *tty, struct file *filp)
 648 {
 649         struct slgt_info *info;
 650         int retval, line;
 651         unsigned long flags;
 652
 653         line = tty->index;
 654         if (line >= slgt_device_count) {
 655                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 656                 return -ENODEV;
 657         }
 658
 659         info = slgt_device_list;
 660         while(info && info->line != line)
 661                 info = info->next_device;
 662         if (sanity_check(info, tty->name, "open"))
 663                 return -ENODEV;
 664         if (info->init_error) {
 665                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 666                 return -ENODEV;
 667         }
 668
 669         tty->driver_data = info;
 670         info->port.tty = tty;
 671
 672         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 673
 674         mutex_lock(&info->port.mutex);
 675         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 676
 677         spin_lock_irqsave(&info->netlock, flags);
 678         if (info->netcount) {
 679                 retval = -EBUSY;
 680                 spin_unlock_irqrestore(&info->netlock, flags);
 681                 mutex_unlock(&info->port.mutex);
 682                 goto cleanup;
 683         }
 684         info->port.count++;
 685         spin_unlock_irqrestore(&info->netlock, flags);
 686
 687         if (info->port.count == 1) {
 688                 /* 1st open on this device, init hardware */
 689                 retval = startup(info);
 690                 if (retval < 0) {
 691                         mutex_unlock(&info->port.mutex);
 692                         goto cleanup;
 693                 }
 694         }
 695         mutex_unlock(&info->port.mutex);
 696         retval = block_til_ready(tty, filp, info);
 697         if (retval) {
 698                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 699                 goto cleanup;
 700         }
 701
 702         retval = 0;
 703
 704 cleanup:
 705         if (retval) {
 706                 if (tty->count == 1)
 707                         info->port.tty = NULL; /* tty layer will release tty struct */
 708                 if(info->port.count)
 709                         info->port.count--;
 710         }
 711
 712         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 713         return retval;
 714 }
 715
 716 static void close(struct tty_struct *tty, struct file *filp)
 717 {
 718         struct slgt_info *info = tty->driver_data;
 719
 720         if (sanity_check(info, tty->name, "close"))
 721                 return;
 722         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 723
 724         if (tty_port_close_start(&info->port, tty, filp) == 0)
 725                 goto cleanup;
 726
 727         mutex_lock(&info->port.mutex);
 728         if (tty_port_initialized(&info->port))
 729                 wait_until_sent(tty, info->timeout);
 730         flush_buffer(tty);
 731         tty_ldisc_flush(tty);
 732
 733         shutdown(info);
 734         mutex_unlock(&info->port.mutex);
 735
 736         tty_port_close_end(&info->port, tty);
 737         info->port.tty = NULL;
 738 cleanup:
 739         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 740 }
 741
 742 static void hangup(struct tty_struct *tty)
 743 {
 744         struct slgt_info *info = tty->driver_data;
 745         unsigned long flags;
 746
 747         if (sanity_check(info, tty->name, "hangup"))
 748                 return;
 749         DBGINFO(("%s hangup\n", info->device_name));
 750
 751         flush_buffer(tty);
 752
 753         mutex_lock(&info->port.mutex);
 754         shutdown(info);
 755
 756         spin_lock_irqsave(&info->port.lock, flags);
 757         info->port.count = 0;
 758         info->port.tty = NULL;
 759         spin_unlock_irqrestore(&info->port.lock, flags);
 760         tty_port_set_active(&info->port, 0);
 761         mutex_unlock(&info->port.mutex);
 762
 763         wake_up_interruptible(&info->port.open_wait);
 764 }
 765
 766 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 767 {
 768         struct slgt_info *info = tty->driver_data;
 769         unsigned long flags;
 770
 771         DBGINFO(("%s set_termios\n", tty->driver->name));
 772
 773         change_params(info);
 774
 775         /* Handle transition to B0 status */
 776         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 777                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 778                 spin_lock_irqsave(&info->lock,flags);
 779                 set_signals(info);
 780                 spin_unlock_irqrestore(&info->lock,flags);
 781         }
 782
 783         /* Handle transition away from B0 status */
 784         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 785                 info->signals |= SerialSignal_DTR;
 786                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 787                         info->signals |= SerialSignal_RTS;
 788                 spin_lock_irqsave(&info->lock,flags);
 789                 set_signals(info);
 790                 spin_unlock_irqrestore(&info->lock,flags);
 791         }
 792
 793         /* Handle turning off CRTSCTS */
 794         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 795                 tty->hw_stopped = 0;
 796                 tx_release(tty);
 797         }
 798 }
 799
 800 static void update_tx_timer(struct slgt_info *info)
 801 {
 802         /*
 803          * use worst case speed of 1200bps to calculate transmit timeout
 804          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 805          */
 806         if (info->params.mode == MGSL_MODE_HDLC) {
 807                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 808                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 809         }
 810 }
 811
 812 static int write(struct tty_struct *tty,
 813                  const unsigned char *buf, int count)
 814 {
 815         int ret = 0;
 816         struct slgt_info *info = tty->driver_data;
 817         unsigned long flags;
 818
 819         if (sanity_check(info, tty->name, "write"))
 820                 return -EIO;
 821
 822         DBGINFO(("%s write count=%d\n", info->device_name, count));
 823
 824         if (!info->tx_buf || (count > info->max_frame_size))
 825                 return -EIO;
 826
 827         if (!count || tty->stopped || tty->hw_stopped)
 828                 return 0;
 829
 830         spin_lock_irqsave(&info->lock, flags);
 831
 832         if (info->tx_count) {
 833                 /* send accumulated data from send_char() */
 834                 if (!tx_load(info, info->tx_buf, info->tx_count))
 835                         goto cleanup;
 836                 info->tx_count = 0;
 837         }
 838
 839         if (tx_load(info, buf, count))
 840                 ret = count;
 841
 842 cleanup:
 843         spin_unlock_irqrestore(&info->lock, flags);
 844         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 845         return ret;
 846 }
 847
 848 static int put_char(struct tty_struct *tty, unsigned char ch)
 849 {
 850         struct slgt_info *info = tty->driver_data;
 851         unsigned long flags;
 852         int ret = 0;
 853
 854         if (sanity_check(info, tty->name, "put_char"))
 855                 return 0;
 856         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 857         if (!info->tx_buf)
 858                 return 0;
 859         spin_lock_irqsave(&info->lock,flags);
 860         if (info->tx_count < info->max_frame_size) {
 861                 info->tx_buf[info->tx_count++] = ch;
 862                 ret = 1;
 863         }
 864         spin_unlock_irqrestore(&info->lock,flags);
 865         return ret;
 866 }
 867
 868 static void send_xchar(struct tty_struct *tty, char ch)
 869 {
 870         struct slgt_info *info = tty->driver_data;
 871         unsigned long flags;
 872
 873         if (sanity_check(info, tty->name, "send_xchar"))
 874                 return;
 875         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 876         info->x_char = ch;
 877         if (ch) {
 878                 spin_lock_irqsave(&info->lock,flags);
 879                 if (!info->tx_enabled)
 880                         tx_start(info);
 881                 spin_unlock_irqrestore(&info->lock,flags);
 882         }
 883 }
 884
 885 static void wait_until_sent(struct tty_struct *tty, int timeout)
 886 {
 887         struct slgt_info *info = tty->driver_data;
 888         unsigned long orig_jiffies, char_time;
 889
 890         if (!info )
 891                 return;
 892         if (sanity_check(info, tty->name, "wait_until_sent"))
 893                 return;
 894         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 895         if (!tty_port_initialized(&info->port))
 896                 goto exit;
 897
 898         orig_jiffies = jiffies;
 899
 900         /* Set check interval to 1/5 of estimated time to
 901          * send a character, and make it at least 1. The check
 902          * interval should also be less than the timeout.
 903          * Note: use tight timings here to satisfy the NIST-PCTS.
 904          */
 905
 906         if (info->params.data_rate) {
 907                 char_time = info->timeout/(32 * 5);
 908                 if (!char_time)
 909                         char_time++;
 910         } else
 911                 char_time = 1;
 912
 913         if (timeout)
 914                 char_time = min_t(unsigned long, char_time, timeout);
 915
 916         while (info->tx_active) {
 917                 msleep_interruptible(jiffies_to_msecs(char_time));
 918                 if (signal_pending(current))
 919                         break;
 920                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 921                         break;
 922         }
 923 exit:
 924         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 925 }
 926
 927 static int write_room(struct tty_struct *tty)
 928 {
 929         struct slgt_info *info = tty->driver_data;
 930         int ret;
 931
 932         if (sanity_check(info, tty->name, "write_room"))
 933                 return 0;
 934         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 935         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 936         return ret;
 937 }
 938
 939 static void flush_chars(struct tty_struct *tty)
 940 {
 941         struct slgt_info *info = tty->driver_data;
 942         unsigned long flags;
 943
 944         if (sanity_check(info, tty->name, "flush_chars"))
 945                 return;
 946         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 947
 948         if (info->tx_count <= 0 || tty->stopped ||
 949             tty->hw_stopped || !info->tx_buf)
 950                 return;
 951
 952         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 953
 954         spin_lock_irqsave(&info->lock,flags);
 955         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 956                 info->tx_count = 0;
 957         spin_unlock_irqrestore(&info->lock,flags);
 958 }
 959
 960 static void flush_buffer(struct tty_struct *tty)
 961 {
 962         struct slgt_info *info = tty->driver_data;
 963         unsigned long flags;
 964
 965         if (sanity_check(info, tty->name, "flush_buffer"))
 966                 return;
 967         DBGINFO(("%s flush_buffer\n", info->device_name));
 968
 969         spin_lock_irqsave(&info->lock, flags);
 970         info->tx_count = 0;
 971         spin_unlock_irqrestore(&info->lock, flags);
 972
 973         tty_wakeup(tty);
 974 }
 975
 976 /*
 977  * throttle (stop) transmitter
 978  */
 979 static void tx_hold(struct tty_struct *tty)
 980 {
 981         struct slgt_info *info = tty->driver_data;
 982         unsigned long flags;
 983
 984         if (sanity_check(info, tty->name, "tx_hold"))
 985                 return;
 986         DBGINFO(("%s tx_hold\n", info->device_name));
 987         spin_lock_irqsave(&info->lock,flags);
 988         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 989                 tx_stop(info);
 990         spin_unlock_irqrestore(&info->lock,flags);
 991 }
 992
 993 /*
 994  * release (start) transmitter
 995  */
 996 static void tx_release(struct tty_struct *tty)
 997 {
 998         struct slgt_info *info = tty->driver_data;
 999         unsigned long flags;
1000
1001         if (sanity_check(info, tty->name, "tx_release"))
1002                 return;
1003         DBGINFO(("%s tx_release\n", info->device_name));
1004         spin_lock_irqsave(&info->lock, flags);
1005         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006                 info->tx_count = 0;
1007         spin_unlock_irqrestore(&info->lock, flags);
1008 }
1009
1010 /*
1011  * Service an IOCTL request
1012  *
1013  * Arguments
1014  *
1015  *      tty     pointer to tty instance data
1016  *      cmd     IOCTL command code
1017  *      arg     command argument/context
1018  *
1019  * Return 0 if success, otherwise error code
1020  */
1021 static int ioctl(struct tty_struct *tty,
1022                  unsigned int cmd, unsigned long arg)
1023 {
1024         struct slgt_info *info = tty->driver_data;
1025         void __user *argp = (void __user *)arg;
1026         int ret;
1027
1028         if (sanity_check(info, tty->name, "ioctl"))
1029                 return -ENODEV;
1030         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1033             (cmd != TIOCMIWAIT)) {
1034                 if (tty_io_error(tty))
1035                     return -EIO;
1036         }
1037
1038         switch (cmd) {
1039         case MGSL_IOCWAITEVENT:
1040                 return wait_mgsl_event(info, argp);
1041         case TIOCMIWAIT:
1042                 return modem_input_wait(info,(int)arg);
1043         case MGSL_IOCSGPIO:
1044                 return set_gpio(info, argp);
1045         case MGSL_IOCGGPIO:
1046                 return get_gpio(info, argp);
1047         case MGSL_IOCWAITGPIO:
1048                 return wait_gpio(info, argp);
1049         case MGSL_IOCGXSYNC:
1050                 return get_xsync(info, argp);
1051         case MGSL_IOCSXSYNC:
1052                 return set_xsync(info, (int)arg);
1053         case MGSL_IOCGXCTRL:
1054                 return get_xctrl(info, argp);
1055         case MGSL_IOCSXCTRL:
1056                 return set_xctrl(info, (int)arg);
1057         }
1058         mutex_lock(&info->port.mutex);
1059         switch (cmd) {
1060         case MGSL_IOCGPARAMS:
1061                 ret = get_params(info, argp);
1062                 break;
1063         case MGSL_IOCSPARAMS:
1064                 ret = set_params(info, argp);
1065                 break;
1066         case MGSL_IOCGTXIDLE:
1067                 ret = get_txidle(info, argp);
1068                 break;
1069         case MGSL_IOCSTXIDLE:
1070                 ret = set_txidle(info, (int)arg);
1071                 break;
1072         case MGSL_IOCTXENABLE:
1073                 ret = tx_enable(info, (int)arg);
1074                 break;
1075         case MGSL_IOCRXENABLE:
1076                 ret = rx_enable(info, (int)arg);
1077                 break;
1078         case MGSL_IOCTXABORT:
1079                 ret = tx_abort(info);
1080                 break;
1081         case MGSL_IOCGSTATS:
1082                 ret = get_stats(info, argp);
1083                 break;
1084         case MGSL_IOCGIF:
1085                 ret = get_interface(info, argp);
1086                 break;
1087         case MGSL_IOCSIF:
1088                 ret = set_interface(info,(int)arg);
1089                 break;
1090         default:
1091                 ret = -ENOIOCTLCMD;
1092         }
1093         mutex_unlock(&info->port.mutex);
1094         return ret;
1095 }
1096
1097 static int get_icount(struct tty_struct *tty,
1098                                 struct serial_icounter_struct *icount)
1099
1100 {
1101         struct slgt_info *info = tty->driver_data;
1102         struct mgsl_icount cnow;        /* kernel counter temps */
1103         unsigned long flags;
1104
1105         spin_lock_irqsave(&info->lock,flags);
1106         cnow = info->icount;
1107         spin_unlock_irqrestore(&info->lock,flags);
1108
1109         icount->cts = cnow.cts;
1110         icount->dsr = cnow.dsr;
1111         icount->rng = cnow.rng;
1112         icount->dcd = cnow.dcd;
1113         icount->rx = cnow.rx;
1114         icount->tx = cnow.tx;
1115         icount->frame = cnow.frame;
1116         icount->overrun = cnow.overrun;
1117         icount->parity = cnow.parity;
1118         icount->brk = cnow.brk;
1119         icount->buf_overrun = cnow.buf_overrun;
1120
1121         return 0;
1122 }
1123
1124 /*
1125  * support for 32 bit ioctl calls on 64 bit systems
1126  */
1127 #ifdef CONFIG_COMPAT
1128 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1129 {
1130         struct MGSL_PARAMS32 tmp_params;
1131
1132         DBGINFO(("%s get_params32\n", info->device_name));
1133         memset(&tmp_params, 0, sizeof(tmp_params));
1134         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1135         tmp_params.loopback        = info->params.loopback;
1136         tmp_params.flags           = info->params.flags;
1137         tmp_params.encoding        = info->params.encoding;
1138         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1139         tmp_params.addr_filter     = info->params.addr_filter;
1140         tmp_params.crc_type        = info->params.crc_type;
1141         tmp_params.preamble_length = info->params.preamble_length;
1142         tmp_params.preamble        = info->params.preamble;
1143         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1144         tmp_params.data_bits       = info->params.data_bits;
1145         tmp_params.stop_bits       = info->params.stop_bits;
1146         tmp_params.parity          = info->params.parity;
1147         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1148                 return -EFAULT;
1149         return 0;
1150 }
1151
1152 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1153 {
1154         struct MGSL_PARAMS32 tmp_params;
1155
1156         DBGINFO(("%s set_params32\n", info->device_name));
1157         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1158                 return -EFAULT;
1159
1160         spin_lock(&info->lock);
1161         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1162                 info->base_clock = tmp_params.clock_speed;
1163         } else {
1164                 info->params.mode            = tmp_params.mode;
1165                 info->params.loopback        = tmp_params.loopback;
1166                 info->params.flags           = tmp_params.flags;
1167                 info->params.encoding        = tmp_params.encoding;
1168                 info->params.clock_speed     = tmp_params.clock_speed;
1169                 info->params.addr_filter     = tmp_params.addr_filter;
1170                 info->params.crc_type        = tmp_params.crc_type;
1171                 info->params.preamble_length = tmp_params.preamble_length;
1172                 info->params.preamble        = tmp_params.preamble;
1173                 info->params.data_rate       = tmp_params.data_rate;
1174                 info->params.data_bits       = tmp_params.data_bits;
1175                 info->params.stop_bits       = tmp_params.stop_bits;
1176                 info->params.parity          = tmp_params.parity;
1177         }
1178         spin_unlock(&info->lock);
1179
1180         program_hw(info);
1181
1182         return 0;
1183 }
1184
1185 static long slgt_compat_ioctl(struct tty_struct *tty,
1186                          unsigned int cmd, unsigned long arg)
1187 {
1188         struct slgt_info *info = tty->driver_data;
1189         int rc = -ENOIOCTLCMD;
1190
1191         if (sanity_check(info, tty->name, "compat_ioctl"))
1192                 return -ENODEV;
1193         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1194
1195         switch (cmd) {
1196
1197         case MGSL_IOCSPARAMS32:
1198                 rc = set_params32(info, compat_ptr(arg));
1199                 break;
1200
1201         case MGSL_IOCGPARAMS32:
1202                 rc = get_params32(info, compat_ptr(arg));
1203                 break;
1204
1205         case MGSL_IOCGPARAMS:
1206         case MGSL_IOCSPARAMS:
1207         case MGSL_IOCGTXIDLE:
1208         case MGSL_IOCGSTATS:
1209         case MGSL_IOCWAITEVENT:
1210         case MGSL_IOCGIF:
1211         case MGSL_IOCSGPIO:
1212         case MGSL_IOCGGPIO:
1213         case MGSL_IOCWAITGPIO:
1214         case MGSL_IOCGXSYNC:
1215         case MGSL_IOCGXCTRL:
1216         case MGSL_IOCSTXIDLE:
1217         case MGSL_IOCTXENABLE:
1218         case MGSL_IOCRXENABLE:
1219         case MGSL_IOCTXABORT:
1220         case TIOCMIWAIT:
1221         case MGSL_IOCSIF:
1222         case MGSL_IOCSXSYNC:
1223         case MGSL_IOCSXCTRL:
1224                 rc = ioctl(tty, cmd, arg);
1225                 break;
1226         }
1227
1228         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1229         return rc;
1230 }
1231 #else
1232 #define slgt_compat_ioctl NULL
1233 #endif /* ifdef CONFIG_COMPAT */
1234
1235 /*
1236  * proc fs support
1237  */
1238 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1239 {
1240         char stat_buf[30];
1241         unsigned long flags;
1242
1243         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1244                       info->device_name, info->phys_reg_addr,
1245                       info->irq_level, info->max_frame_size);
1246
1247         /* output current serial signal states */
1248         spin_lock_irqsave(&info->lock,flags);
1249         get_signals(info);
1250         spin_unlock_irqrestore(&info->lock,flags);
1251
1252         stat_buf[0] = 0;
1253         stat_buf[1] = 0;
1254         if (info->signals & SerialSignal_RTS)
1255                 strcat(stat_buf, "|RTS");
1256         if (info->signals & SerialSignal_CTS)
1257                 strcat(stat_buf, "|CTS");
1258         if (info->signals & SerialSignal_DTR)
1259                 strcat(stat_buf, "|DTR");
1260         if (info->signals & SerialSignal_DSR)
1261                 strcat(stat_buf, "|DSR");
1262         if (info->signals & SerialSignal_DCD)
1263                 strcat(stat_buf, "|CD");
1264         if (info->signals & SerialSignal_RI)
1265                 strcat(stat_buf, "|RI");
1266
1267         if (info->params.mode != MGSL_MODE_ASYNC) {
1268                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1269                                info->icount.txok, info->icount.rxok);
1270                 if (info->icount.txunder)
1271                         seq_printf(m, " txunder:%d", info->icount.txunder);
1272                 if (info->icount.txabort)
1273                         seq_printf(m, " txabort:%d", info->icount.txabort);
1274                 if (info->icount.rxshort)
1275                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1276                 if (info->icount.rxlong)
1277                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1278                 if (info->icount.rxover)
1279                         seq_printf(m, " rxover:%d", info->icount.rxover);
1280                 if (info->icount.rxcrc)
1281                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1282         } else {
1283                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1284                                info->icount.tx, info->icount.rx);
1285                 if (info->icount.frame)
1286                         seq_printf(m, " fe:%d", info->icount.frame);
1287                 if (info->icount.parity)
1288                         seq_printf(m, " pe:%d", info->icount.parity);
1289                 if (info->icount.brk)
1290                         seq_printf(m, " brk:%d", info->icount.brk);
1291                 if (info->icount.overrun)
1292                         seq_printf(m, " oe:%d", info->icount.overrun);
1293         }
1294
1295         /* Append serial signal status to end */
1296         seq_printf(m, " %s\n", stat_buf+1);
1297
1298         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1299                        info->tx_active,info->bh_requested,info->bh_running,
1300                        info->pending_bh);
1301 }
1302
1303 /* Called to print information about devices
1304  */
1305 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1306 {
1307         struct slgt_info *info;
1308
1309         seq_puts(m, "synclink_gt driver\n");
1310
1311         info = slgt_device_list;
1312         while( info ) {
1313                 line_info(m, info);
1314                 info = info->next_device;
1315         }
1316         return 0;
1317 }
1318
1319 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1320 {
1321         return single_open(file, synclink_gt_proc_show, NULL);
1322 }
1323
1324 static const struct file_operations synclink_gt_proc_fops = {
1325         .owner          = THIS_MODULE,
1326         .open           = synclink_gt_proc_open,
1327         .read           = seq_read,
1328         .llseek         = seq_lseek,
1329         .release        = single_release,
1330 };
1331
1332 /*
1333  * return count of bytes in transmit buffer
1334  */
1335 static int chars_in_buffer(struct tty_struct *tty)
1336 {
1337         struct slgt_info *info = tty->driver_data;
1338         int count;
1339         if (sanity_check(info, tty->name, "chars_in_buffer"))
1340                 return 0;
1341         count = tbuf_bytes(info);
1342         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1343         return count;
1344 }
1345
1346 /*
1347  * signal remote device to throttle send data (our receive data)
1348  */
1349 static void throttle(struct tty_struct * tty)
1350 {
1351         struct slgt_info *info = tty->driver_data;
1352         unsigned long flags;
1353
1354         if (sanity_check(info, tty->name, "throttle"))
1355                 return;
1356         DBGINFO(("%s throttle\n", info->device_name));
1357         if (I_IXOFF(tty))
1358                 send_xchar(tty, STOP_CHAR(tty));
1359         if (C_CRTSCTS(tty)) {
1360                 spin_lock_irqsave(&info->lock,flags);
1361                 info->signals &= ~SerialSignal_RTS;
1362                 set_signals(info);
1363                 spin_unlock_irqrestore(&info->lock,flags);
1364         }
1365 }
1366
1367 /*
1368  * signal remote device to stop throttling send data (our receive data)
1369  */
1370 static void unthrottle(struct tty_struct * tty)
1371 {
1372         struct slgt_info *info = tty->driver_data;
1373         unsigned long flags;
1374
1375         if (sanity_check(info, tty->name, "unthrottle"))
1376                 return;
1377         DBGINFO(("%s unthrottle\n", info->device_name));
1378         if (I_IXOFF(tty)) {
1379                 if (info->x_char)
1380                         info->x_char = 0;
1381                 else
1382                         send_xchar(tty, START_CHAR(tty));
1383         }
1384         if (C_CRTSCTS(tty)) {
1385                 spin_lock_irqsave(&info->lock,flags);
1386                 info->signals |= SerialSignal_RTS;
1387                 set_signals(info);
1388                 spin_unlock_irqrestore(&info->lock,flags);
1389         }
1390 }
1391
1392 /*
1393  * set or clear transmit break condition
1394  * break_state  -1=set break condition, 0=clear
1395  */
1396 static int set_break(struct tty_struct *tty, int break_state)
1397 {
1398         struct slgt_info *info = tty->driver_data;
1399         unsigned short value;
1400         unsigned long flags;
1401
1402         if (sanity_check(info, tty->name, "set_break"))
1403                 return -EINVAL;
1404         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1405
1406         spin_lock_irqsave(&info->lock,flags);
1407         value = rd_reg16(info, TCR);
1408         if (break_state == -1)
1409                 value |= BIT6;
1410         else
1411                 value &= ~BIT6;
1412         wr_reg16(info, TCR, value);
1413         spin_unlock_irqrestore(&info->lock,flags);
1414         return 0;
1415 }
1416
1417 #if SYNCLINK_GENERIC_HDLC
1418
1419 /**
1420  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1421  * set encoding and frame check sequence (FCS) options
1422  *
1423  * dev       pointer to network device structure
1424  * encoding  serial encoding setting
1425  * parity    FCS setting
1426  *
1427  * returns 0 if success, otherwise error code
1428  */
1429 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1430                           unsigned short parity)
1431 {
1432         struct slgt_info *info = dev_to_port(dev);
1433         unsigned char  new_encoding;
1434         unsigned short new_crctype;
1435
1436         /* return error if TTY interface open */
1437         if (info->port.count)
1438                 return -EBUSY;
1439
1440         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1441
1442         switch (encoding)
1443         {
1444         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1445         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1446         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1447         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1448         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1449         default: return -EINVAL;
1450         }
1451
1452         switch (parity)
1453         {
1454         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1455         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1456         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1457         default: return -EINVAL;
1458         }
1459
1460         info->params.encoding = new_encoding;
1461         info->params.crc_type = new_crctype;
1462
1463         /* if network interface up, reprogram hardware */
1464         if (info->netcount)
1465                 program_hw(info);
1466
1467         return 0;
1468 }
1469
1470 /**
1471  * called by generic HDLC layer to send frame
1472  *
1473  * skb  socket buffer containing HDLC frame
1474  * dev  pointer to network device structure
1475  */
1476 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1477                                       struct net_device *dev)
1478 {
1479         struct slgt_info *info = dev_to_port(dev);
1480         unsigned long flags;
1481
1482         DBGINFO(("%s hdlc_xmit\n", dev->name));
1483
1484         if (!skb->len)
1485                 return NETDEV_TX_OK;
1486
1487         /* stop sending until this frame completes */
1488         netif_stop_queue(dev);
1489
1490         /* update network statistics */
1491         dev->stats.tx_packets++;
1492         dev->stats.tx_bytes += skb->len;
1493
1494         /* save start time for transmit timeout detection */
1495         netif_trans_update(dev);
1496
1497         spin_lock_irqsave(&info->lock, flags);
1498         tx_load(info, skb->data, skb->len);
1499         spin_unlock_irqrestore(&info->lock, flags);
1500
1501         /* done with socket buffer, so free it */
1502         dev_kfree_skb(skb);
1503
1504         return NETDEV_TX_OK;
1505 }
1506
1507 /**
1508  * called by network layer when interface enabled
1509  * claim resources and initialize hardware
1510  *
1511  * dev  pointer to network device structure
1512  *
1513  * returns 0 if success, otherwise error code
1514  */
1515 static int hdlcdev_open(struct net_device *dev)
1516 {
1517         struct slgt_info *info = dev_to_port(dev);
1518         int rc;
1519         unsigned long flags;
1520
1521         if (!try_module_get(THIS_MODULE))
1522                 return -EBUSY;
1523
1524         DBGINFO(("%s hdlcdev_open\n", dev->name));
1525
1526         /* generic HDLC layer open processing */
1527         rc = hdlc_open(dev);
1528         if (rc)
1529                 return rc;
1530
1531         /* arbitrate between network and tty opens */
1532         spin_lock_irqsave(&info->netlock, flags);
1533         if (info->port.count != 0 || info->netcount != 0) {
1534                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1535                 spin_unlock_irqrestore(&info->netlock, flags);
1536                 return -EBUSY;
1537         }
1538         info->netcount=1;
1539         spin_unlock_irqrestore(&info->netlock, flags);
1540
1541         /* claim resources and init adapter */
1542         if ((rc = startup(info)) != 0) {
1543                 spin_lock_irqsave(&info->netlock, flags);
1544                 info->netcount=0;
1545                 spin_unlock_irqrestore(&info->netlock, flags);
1546                 return rc;
1547         }
1548
1549         /* assert RTS and DTR, apply hardware settings */
1550         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1551         program_hw(info);
1552
1553         /* enable network layer transmit */
1554         netif_trans_update(dev);
1555         netif_start_queue(dev);
1556
1557         /* inform generic HDLC layer of current DCD status */
1558         spin_lock_irqsave(&info->lock, flags);
1559         get_signals(info);
1560         spin_unlock_irqrestore(&info->lock, flags);
1561         if (info->signals & SerialSignal_DCD)
1562                 netif_carrier_on(dev);
1563         else
1564                 netif_carrier_off(dev);
1565         return 0;
1566 }
1567
1568 /**
1569  * called by network layer when interface is disabled
1570  * shutdown hardware and release resources
1571  *
1572  * dev  pointer to network device structure
1573  *
1574  * returns 0 if success, otherwise error code
1575  */
1576 static int hdlcdev_close(struct net_device *dev)
1577 {
1578         struct slgt_info *info = dev_to_port(dev);
1579         unsigned long flags;
1580
1581         DBGINFO(("%s hdlcdev_close\n", dev->name));
1582
1583         netif_stop_queue(dev);
1584
1585         /* shutdown adapter and release resources */
1586         shutdown(info);
1587
1588         hdlc_close(dev);
1589
1590         spin_lock_irqsave(&info->netlock, flags);
1591         info->netcount=0;
1592         spin_unlock_irqrestore(&info->netlock, flags);
1593
1594         module_put(THIS_MODULE);
1595         return 0;
1596 }
1597
1598 /**
1599  * called by network layer to process IOCTL call to network device
1600  *
1601  * dev  pointer to network device structure
1602  * ifr  pointer to network interface request structure
1603  * cmd  IOCTL command code
1604  *
1605  * returns 0 if success, otherwise error code
1606  */
1607 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1608 {
1609         const size_t size = sizeof(sync_serial_settings);
1610         sync_serial_settings new_line;
1611         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1612         struct slgt_info *info = dev_to_port(dev);
1613         unsigned int flags;
1614
1615         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1616
1617         /* return error if TTY interface open */
1618         if (info->port.count)
1619                 return -EBUSY;
1620
1621         if (cmd != SIOCWANDEV)
1622                 return hdlc_ioctl(dev, ifr, cmd);
1623
1624         memset(&new_line, 0, sizeof(new_line));
1625
1626         switch(ifr->ifr_settings.type) {
1627         case IF_GET_IFACE: /* return current sync_serial_settings */
1628
1629                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1630                 if (ifr->ifr_settings.size < size) {
1631                         ifr->ifr_settings.size = size; /* data size wanted */
1632                         return -ENOBUFS;
1633                 }
1634
1635                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1636                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1637                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1638                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1639
1640                 switch (flags){
1641                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1642                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1643                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1644                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1645                 default: new_line.clock_type = CLOCK_DEFAULT;
1646                 }
1647
1648                 new_line.clock_rate = info->params.clock_speed;
1649                 new_line.loopback   = info->params.loopback ? 1:0;
1650
1651                 if (copy_to_user(line, &new_line, size))
1652                         return -EFAULT;
1653                 return 0;
1654
1655         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1656
1657                 if(!capable(CAP_NET_ADMIN))
1658                         return -EPERM;
1659                 if (copy_from_user(&new_line, line, size))
1660                         return -EFAULT;
1661
1662                 switch (new_line.clock_type)
1663                 {
1664                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1665                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1666                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1667                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1668                 case CLOCK_DEFAULT:  flags = info->params.flags &
1669                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1670                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1671                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1672                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1673                 default: return -EINVAL;
1674                 }
1675
1676                 if (new_line.loopback != 0 && new_line.loopback != 1)
1677                         return -EINVAL;
1678
1679                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1680                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1681                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1682                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1683                 info->params.flags |= flags;
1684
1685                 info->params.loopback = new_line.loopback;
1686
1687                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1688                         info->params.clock_speed = new_line.clock_rate;
1689                 else
1690                         info->params.clock_speed = 0;
1691
1692                 /* if network interface up, reprogram hardware */
1693                 if (info->netcount)
1694                         program_hw(info);
1695                 return 0;
1696
1697         default:
1698                 return hdlc_ioctl(dev, ifr, cmd);
1699         }
1700 }
1701
1702 /**
1703  * called by network layer when transmit timeout is detected
1704  *
1705  * dev  pointer to network device structure
1706  */
1707 static void hdlcdev_tx_timeout(struct net_device *dev)
1708 {
1709         struct slgt_info *info = dev_to_port(dev);
1710         unsigned long flags;
1711
1712         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1713
1714         dev->stats.tx_errors++;
1715         dev->stats.tx_aborted_errors++;
1716
1717         spin_lock_irqsave(&info->lock,flags);
1718         tx_stop(info);
1719         spin_unlock_irqrestore(&info->lock,flags);
1720
1721         netif_wake_queue(dev);
1722 }
1723
1724 /**
1725  * called by device driver when transmit completes
1726  * reenable network layer transmit if stopped
1727  *
1728  * info  pointer to device instance information
1729  */
1730 static void hdlcdev_tx_done(struct slgt_info *info)
1731 {
1732         if (netif_queue_stopped(info->netdev))
1733                 netif_wake_queue(info->netdev);
1734 }
1735
1736 /**
1737  * called by device driver when frame received
1738  * pass frame to network layer
1739  *
1740  * info  pointer to device instance information
1741  * buf   pointer to buffer contianing frame data
1742  * size  count of data bytes in buf
1743  */
1744 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1745 {
1746         struct sk_buff *skb = dev_alloc_skb(size);
1747         struct net_device *dev = info->netdev;
1748
1749         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1750
1751         if (skb == NULL) {
1752                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1753                 dev->stats.rx_dropped++;
1754                 return;
1755         }
1756
1757         skb_put_data(skb, buf, size);
1758
1759         skb->protocol = hdlc_type_trans(skb, dev);
1760
1761         dev->stats.rx_packets++;
1762         dev->stats.rx_bytes += size;
1763
1764         netif_rx(skb);
1765 }
1766
1767 static const struct net_device_ops hdlcdev_ops = {
1768         .ndo_open       = hdlcdev_open,
1769         .ndo_stop       = hdlcdev_close,
1770         .ndo_start_xmit = hdlc_start_xmit,
1771         .ndo_do_ioctl   = hdlcdev_ioctl,
1772         .ndo_tx_timeout = hdlcdev_tx_timeout,
1773 };
1774
1775 /**
1776  * called by device driver when adding device instance
1777  * do generic HDLC initialization
1778  *
1779  * info  pointer to device instance information
1780  *
1781  * returns 0 if success, otherwise error code
1782  */
1783 static int hdlcdev_init(struct slgt_info *info)
1784 {
1785         int rc;
1786         struct net_device *dev;
1787         hdlc_device *hdlc;
1788
1789         /* allocate and initialize network and HDLC layer objects */
1790
1791         dev = alloc_hdlcdev(info);
1792         if (!dev) {
1793                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1794                 return -ENOMEM;
1795         }
1796
1797         /* for network layer reporting purposes only */
1798         dev->mem_start = info->phys_reg_addr;
1799         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1800         dev->irq       = info->irq_level;
1801
1802         /* network layer callbacks and settings */
1803         dev->netdev_ops     = &hdlcdev_ops;
1804         dev->watchdog_timeo = 10 * HZ;
1805         dev->tx_queue_len   = 50;
1806
1807         /* generic HDLC layer callbacks and settings */
1808         hdlc         = dev_to_hdlc(dev);
1809         hdlc->attach = hdlcdev_attach;
1810         hdlc->xmit   = hdlcdev_xmit;
1811
1812         /* register objects with HDLC layer */
1813         rc = register_hdlc_device(dev);
1814         if (rc) {
1815                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1816                 free_netdev(dev);
1817                 return rc;
1818         }
1819
1820         info->netdev = dev;
1821         return 0;
1822 }
1823
1824 /**
1825  * called by device driver when removing device instance
1826  * do generic HDLC cleanup
1827  *
1828  * info  pointer to device instance information
1829  */
1830 static void hdlcdev_exit(struct slgt_info *info)
1831 {
1832         unregister_hdlc_device(info->netdev);
1833         free_netdev(info->netdev);
1834         info->netdev = NULL;
1835 }
1836
1837 #endif /* ifdef CONFIG_HDLC */
1838
1839 /*
1840  * get async data from rx DMA buffers
1841  */
1842 static void rx_async(struct slgt_info *info)
1843 {
1844         struct mgsl_icount *icount = &info->icount;
1845         unsigned int start, end;
1846         unsigned char *p;
1847         unsigned char status;
1848         struct slgt_desc *bufs = info->rbufs;
1849         int i, count;
1850         int chars = 0;
1851         int stat;
1852         unsigned char ch;
1853
1854         start = end = info->rbuf_current;
1855
1856         while(desc_complete(bufs[end])) {
1857                 count = desc_count(bufs[end]) - info->rbuf_index;
1858                 p     = bufs[end].buf + info->rbuf_index;
1859
1860                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1861                 DBGDATA(info, p, count, "rx");
1862
1863                 for(i=0 ; i < count; i+=2, p+=2) {
1864                         ch = *p;
1865                         icount->rx++;
1866
1867                         stat = 0;
1868
1869                         status = *(p + 1) & (BIT1 + BIT0);
1870                         if (status) {
1871                                 if (status & BIT1)
1872                                         icount->parity++;
1873                                 else if (status & BIT0)
1874                                         icount->frame++;
1875                                 /* discard char if tty control flags say so */
1876                                 if (status & info->ignore_status_mask)
1877                                         continue;
1878                                 if (status & BIT1)
1879                                         stat = TTY_PARITY;
1880                                 else if (status & BIT0)
1881                                         stat = TTY_FRAME;
1882                         }
1883                         tty_insert_flip_char(&info->port, ch, stat);
1884                         chars++;
1885                 }
1886
1887                 if (i < count) {
1888                         /* receive buffer not completed */
1889                         info->rbuf_index += i;
1890                         mod_timer(&info->rx_timer, jiffies + 1);
1891                         break;
1892                 }
1893
1894                 info->rbuf_index = 0;
1895                 free_rbufs(info, end, end);
1896
1897                 if (++end == info->rbuf_count)
1898                         end = 0;
1899
1900                 /* if entire list searched then no frame available */
1901                 if (end == start)
1902                         break;
1903         }
1904
1905         if (chars)
1906                 tty_flip_buffer_push(&info->port);
1907 }
1908
1909 /*
1910  * return next bottom half action to perform
1911  */
1912 static int bh_action(struct slgt_info *info)
1913 {
1914         unsigned long flags;
1915         int rc;
1916
1917         spin_lock_irqsave(&info->lock,flags);
1918
1919         if (info->pending_bh & BH_RECEIVE) {
1920                 info->pending_bh &= ~BH_RECEIVE;
1921                 rc = BH_RECEIVE;
1922         } else if (info->pending_bh & BH_TRANSMIT) {
1923                 info->pending_bh &= ~BH_TRANSMIT;
1924                 rc = BH_TRANSMIT;
1925         } else if (info->pending_bh & BH_STATUS) {
1926                 info->pending_bh &= ~BH_STATUS;
1927                 rc = BH_STATUS;
1928         } else {
1929                 /* Mark BH routine as complete */
1930                 info->bh_running = false;
1931                 info->bh_requested = false;
1932                 rc = 0;
1933         }
1934
1935         spin_unlock_irqrestore(&info->lock,flags);
1936
1937         return rc;
1938 }
1939
1940 /*
1941  * perform bottom half processing
1942  */
1943 static void bh_handler(struct work_struct *work)
1944 {
1945         struct slgt_info *info = container_of(work, struct slgt_info, task);
1946         int action;
1947
1948         info->bh_running = true;
1949
1950         while((action = bh_action(info))) {
1951                 switch (action) {
1952                 case BH_RECEIVE:
1953                         DBGBH(("%s bh receive\n", info->device_name));
1954                         switch(info->params.mode) {
1955                         case MGSL_MODE_ASYNC:
1956                                 rx_async(info);
1957                                 break;
1958                         case MGSL_MODE_HDLC:
1959                                 while(rx_get_frame(info));
1960                                 break;
1961                         case MGSL_MODE_RAW:
1962                         case MGSL_MODE_MONOSYNC:
1963                         case MGSL_MODE_BISYNC:
1964                         case MGSL_MODE_XSYNC:
1965                                 while(rx_get_buf(info));
1966                                 break;
1967                         }
1968                         /* restart receiver if rx DMA buffers exhausted */
1969                         if (info->rx_restart)
1970                                 rx_start(info);
1971                         break;
1972                 case BH_TRANSMIT:
1973                         bh_transmit(info);
1974                         break;
1975                 case BH_STATUS:
1976                         DBGBH(("%s bh status\n", info->device_name));
1977                         info->ri_chkcount = 0;
1978                         info->dsr_chkcount = 0;
1979                         info->dcd_chkcount = 0;
1980                         info->cts_chkcount = 0;
1981                         break;
1982                 default:
1983                         DBGBH(("%s unknown action\n", info->device_name));
1984                         break;
1985                 }
1986         }
1987         DBGBH(("%s bh_handler exit\n", info->device_name));
1988 }
1989
1990 static void bh_transmit(struct slgt_info *info)
1991 {
1992         struct tty_struct *tty = info->port.tty;
1993
1994         DBGBH(("%s bh_transmit\n", info->device_name));
1995         if (tty)
1996                 tty_wakeup(tty);
1997 }
1998
1999 static void dsr_change(struct slgt_info *info, unsigned short status)
2000 {
2001         if (status & BIT3) {
2002                 info->signals |= SerialSignal_DSR;
2003                 info->input_signal_events.dsr_up++;
2004         } else {
2005                 info->signals &= ~SerialSignal_DSR;
2006                 info->input_signal_events.dsr_down++;
2007         }
2008         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2009         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2010                 slgt_irq_off(info, IRQ_DSR);
2011                 return;
2012         }
2013         info->icount.dsr++;
2014         wake_up_interruptible(&info->status_event_wait_q);
2015         wake_up_interruptible(&info->event_wait_q);
2016         info->pending_bh |= BH_STATUS;
2017 }
2018
2019 static void cts_change(struct slgt_info *info, unsigned short status)
2020 {
2021         if (status & BIT2) {
2022                 info->signals |= SerialSignal_CTS;
2023                 info->input_signal_events.cts_up++;
2024         } else {
2025                 info->signals &= ~SerialSignal_CTS;
2026                 info->input_signal_events.cts_down++;
2027         }
2028         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2029         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2030                 slgt_irq_off(info, IRQ_CTS);
2031                 return;
2032         }
2033         info->icount.cts++;
2034         wake_up_interruptible(&info->status_event_wait_q);
2035         wake_up_interruptible(&info->event_wait_q);
2036         info->pending_bh |= BH_STATUS;
2037
2038         if (tty_port_cts_enabled(&info->port)) {
2039                 if (info->port.tty) {
2040                         if (info->port.tty->hw_stopped) {
2041                                 if (info->signals & SerialSignal_CTS) {
2042                                         info->port.tty->hw_stopped = 0;
2043                                         info->pending_bh |= BH_TRANSMIT;
2044                                         return;
2045                                 }
2046                         } else {
2047                                 if (!(info->signals & SerialSignal_CTS))
2048                                         info->port.tty->hw_stopped = 1;
2049                         }
2050                 }
2051         }
2052 }
2053
2054 static void dcd_change(struct slgt_info *info, unsigned short status)
2055 {
2056         if (status & BIT1) {
2057                 info->signals |= SerialSignal_DCD;
2058                 info->input_signal_events.dcd_up++;
2059         } else {
2060                 info->signals &= ~SerialSignal_DCD;
2061                 info->input_signal_events.dcd_down++;
2062         }
2063         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2064         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2065                 slgt_irq_off(info, IRQ_DCD);
2066                 return;
2067         }
2068         info->icount.dcd++;
2069 #if SYNCLINK_GENERIC_HDLC
2070         if (info->netcount) {
2071                 if (info->signals & SerialSignal_DCD)
2072                         netif_carrier_on(info->netdev);
2073                 else
2074                         netif_carrier_off(info->netdev);
2075         }
2076 #endif
2077         wake_up_interruptible(&info->status_event_wait_q);
2078         wake_up_interruptible(&info->event_wait_q);
2079         info->pending_bh |= BH_STATUS;
2080
2081         if (tty_port_check_carrier(&info->port)) {
2082                 if (info->signals & SerialSignal_DCD)
2083                         wake_up_interruptible(&info->port.open_wait);
2084                 else {
2085                         if (info->port.tty)
2086                                 tty_hangup(info->port.tty);
2087                 }
2088         }
2089 }
2090
2091 static void ri_change(struct slgt_info *info, unsigned short status)
2092 {
2093         if (status & BIT0) {
2094                 info->signals |= SerialSignal_RI;
2095                 info->input_signal_events.ri_up++;
2096         } else {
2097                 info->signals &= ~SerialSignal_RI;
2098                 info->input_signal_events.ri_down++;
2099         }
2100         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2101         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2102                 slgt_irq_off(info, IRQ_RI);
2103                 return;
2104         }
2105         info->icount.rng++;
2106         wake_up_interruptible(&info->status_event_wait_q);
2107         wake_up_interruptible(&info->event_wait_q);
2108         info->pending_bh |= BH_STATUS;
2109 }
2110
2111 static void isr_rxdata(struct slgt_info *info)
2112 {
2113         unsigned int count = info->rbuf_fill_count;
2114         unsigned int i = info->rbuf_fill_index;
2115         unsigned short reg;
2116
2117         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2118                 reg = rd_reg16(info, RDR);
2119                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2120                 if (desc_complete(info->rbufs[i])) {
2121                         /* all buffers full */
2122                         rx_stop(info);
2123                         info->rx_restart = 1;
2124                         continue;
2125                 }
2126                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2127                 /* async mode saves status byte to buffer for each data byte */
2128                 if (info->params.mode == MGSL_MODE_ASYNC)
2129                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2130                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2131                         /* buffer full or end of frame */
2132                         set_desc_count(info->rbufs[i], count);
2133                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2134                         info->rbuf_fill_count = count = 0;
2135                         if (++i == info->rbuf_count)
2136                                 i = 0;
2137                         info->pending_bh |= BH_RECEIVE;
2138                 }
2139         }
2140
2141         info->rbuf_fill_index = i;
2142         info->rbuf_fill_count = count;
2143 }
2144
2145 static void isr_serial(struct slgt_info *info)
2146 {
2147         unsigned short status = rd_reg16(info, SSR);
2148
2149         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2150
2151         wr_reg16(info, SSR, status); /* clear pending */
2152
2153         info->irq_occurred = true;
2154
2155         if (info->params.mode == MGSL_MODE_ASYNC) {
2156                 if (status & IRQ_TXIDLE) {
2157                         if (info->tx_active)
2158                                 isr_txeom(info, status);
2159                 }
2160                 if (info->rx_pio && (status & IRQ_RXDATA))
2161                         isr_rxdata(info);
2162                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2163                         info->icount.brk++;
2164                         /* process break detection if tty control allows */
2165                         if (info->port.tty) {
2166                                 if (!(status & info->ignore_status_mask)) {
2167                                         if (info->read_status_mask & MASK_BREAK) {
2168                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2169                                                 if (info->port.flags & ASYNC_SAK)
2170                                                         do_SAK(info->port.tty);
2171                                         }
2172                                 }
2173                         }
2174                 }
2175         } else {
2176                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2177                         isr_txeom(info, status);
2178                 if (info->rx_pio && (status & IRQ_RXDATA))
2179                         isr_rxdata(info);
2180                 if (status & IRQ_RXIDLE) {
2181                         if (status & RXIDLE)
2182                                 info->icount.rxidle++;
2183                         else
2184                                 info->icount.exithunt++;
2185                         wake_up_interruptible(&info->event_wait_q);
2186                 }
2187
2188                 if (status & IRQ_RXOVER)
2189                         rx_start(info);
2190         }
2191
2192         if (status & IRQ_DSR)
2193                 dsr_change(info, status);
2194         if (status & IRQ_CTS)
2195                 cts_change(info, status);
2196         if (status & IRQ_DCD)
2197                 dcd_change(info, status);
2198         if (status & IRQ_RI)
2199                 ri_change(info, status);
2200 }
2201
2202 static void isr_rdma(struct slgt_info *info)
2203 {
2204         unsigned int status = rd_reg32(info, RDCSR);
2205
2206         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2207
2208         /* RDCSR (rx DMA control/status)
2209          *
2210          * 31..07  reserved
2211          * 06      save status byte to DMA buffer
2212          * 05      error
2213          * 04      eol (end of list)
2214          * 03      eob (end of buffer)
2215          * 02      IRQ enable
2216          * 01      reset
2217          * 00      enable
2218          */
2219         wr_reg32(info, RDCSR, status);  /* clear pending */
2220
2221         if (status & (BIT5 + BIT4)) {
2222                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2223                 info->rx_restart = true;
2224         }
2225         info->pending_bh |= BH_RECEIVE;
2226 }
2227
2228 static void isr_tdma(struct slgt_info *info)
2229 {
2230         unsigned int status = rd_reg32(info, TDCSR);
2231
2232         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2233
2234         /* TDCSR (tx DMA control/status)
2235          *
2236          * 31..06  reserved
2237          * 05      error
2238          * 04      eol (end of list)
2239          * 03      eob (end of buffer)
2240          * 02      IRQ enable
2241          * 01      reset
2242          * 00      enable
2243          */
2244         wr_reg32(info, TDCSR, status);  /* clear pending */
2245
2246         if (status & (BIT5 + BIT4 + BIT3)) {
2247                 // another transmit buffer has completed
2248                 // run bottom half to get more send data from user
2249                 info->pending_bh |= BH_TRANSMIT;
2250         }
2251 }
2252
2253 /*
2254  * return true if there are unsent tx DMA buffers, otherwise false
2255  *
2256  * if there are unsent buffers then info->tbuf_start
2257  * is set to index of first unsent buffer
2258  */
2259 static bool unsent_tbufs(struct slgt_info *info)
2260 {
2261         unsigned int i = info->tbuf_current;
2262         bool rc = false;
2263
2264         /*
2265          * search backwards from last loaded buffer (precedes tbuf_current)
2266          * for first unsent buffer (desc_count > 0)
2267          */
2268
2269         do {
2270                 if (i)
2271                         i--;
2272                 else
2273                         i = info->tbuf_count - 1;
2274                 if (!desc_count(info->tbufs[i]))
2275                         break;
2276                 info->tbuf_start = i;
2277                 rc = true;
2278         } while (i != info->tbuf_current);
2279
2280         return rc;
2281 }
2282
2283 static void isr_txeom(struct slgt_info *info, unsigned short status)
2284 {
2285         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2286
2287         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2288         tdma_reset(info);
2289         if (status & IRQ_TXUNDER) {
2290                 unsigned short val = rd_reg16(info, TCR);
2291                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2292                 wr_reg16(info, TCR, val); /* clear reset bit */
2293         }
2294
2295         if (info->tx_active) {
2296                 if (info->params.mode != MGSL_MODE_ASYNC) {
2297                         if (status & IRQ_TXUNDER)
2298                                 info->icount.txunder++;
2299                         else if (status & IRQ_TXIDLE)
2300                                 info->icount.txok++;
2301                 }
2302
2303                 if (unsent_tbufs(info)) {
2304                         tx_start(info);
2305                         update_tx_timer(info);
2306                         return;
2307                 }
2308                 info->tx_active = false;
2309
2310                 del_timer(&info->tx_timer);
2311
2312                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2313                         info->signals &= ~SerialSignal_RTS;
2314                         info->drop_rts_on_tx_done = false;
2315                         set_signals(info);
2316                 }
2317
2318 #if SYNCLINK_GENERIC_HDLC
2319                 if (info->netcount)
2320                         hdlcdev_tx_done(info);
2321                 else
2322 #endif
2323                 {
2324                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2325                                 tx_stop(info);
2326                                 return;
2327                         }
2328                         info->pending_bh |= BH_TRANSMIT;
2329                 }
2330         }
2331 }
2332
2333 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2334 {
2335         struct cond_wait *w, *prev;
2336
2337         /* wake processes waiting for specific transitions */
2338         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2339                 if (w->data & changed) {
2340                         w->data = state;
2341                         wake_up_interruptible(&w->q);
2342                         if (prev != NULL)
2343                                 prev->next = w->next;
2344                         else
2345                                 info->gpio_wait_q = w->next;
2346                 } else
2347                         prev = w;
2348         }
2349 }
2350
2351 /* interrupt service routine
2352  *
2353  *      irq     interrupt number
2354  *      dev_id  device ID supplied during interrupt registration
2355  */
2356 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2357 {
2358         struct slgt_info *info = dev_id;
2359         unsigned int gsr;
2360         unsigned int i;
2361
2362         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2363
2364         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2365                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2366                 info->irq_occurred = true;
2367                 for(i=0; i < info->port_count ; i++) {
2368                         if (info->port_array[i] == NULL)
2369                                 continue;
2370                         spin_lock(&info->port_array[i]->lock);
2371                         if (gsr & (BIT8 << i))
2372                                 isr_serial(info->port_array[i]);
2373                         if (gsr & (BIT16 << (i*2)))
2374                                 isr_rdma(info->port_array[i]);
2375                         if (gsr & (BIT17 << (i*2)))
2376                                 isr_tdma(info->port_array[i]);
2377                         spin_unlock(&info->port_array[i]->lock);
2378                 }
2379         }
2380
2381         if (info->gpio_present) {
2382                 unsigned int state;
2383                 unsigned int changed;
2384                 spin_lock(&info->lock);
2385                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2386                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2387                         /* read latched state of GPIO signals */
2388                         state = rd_reg32(info, IOVR);
2389                         /* clear pending GPIO interrupt bits */
2390                         wr_reg32(info, IOSR, changed);
2391                         for (i=0 ; i < info->port_count ; i++) {
2392                                 if (info->port_array[i] != NULL)
2393                                         isr_gpio(info->port_array[i], changed, state);
2394                         }
2395                 }
2396                 spin_unlock(&info->lock);
2397         }
2398
2399         for(i=0; i < info->port_count ; i++) {
2400                 struct slgt_info *port = info->port_array[i];
2401                 if (port == NULL)
2402                         continue;
2403                 spin_lock(&port->lock);
2404                 if ((port->port.count || port->netcount) &&
2405                     port->pending_bh && !port->bh_running &&
2406                     !port->bh_requested) {
2407                         DBGISR(("%s bh queued\n", port->device_name));
2408                         schedule_work(&port->task);
2409                         port->bh_requested = true;
2410                 }
2411                 spin_unlock(&port->lock);
2412         }
2413
2414         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2415         return IRQ_HANDLED;
2416 }
2417
2418 static int startup(struct slgt_info *info)
2419 {
2420         DBGINFO(("%s startup\n", info->device_name));
2421
2422         if (tty_port_initialized(&info->port))
2423                 return 0;
2424
2425         if (!info->tx_buf) {
2426                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2427                 if (!info->tx_buf) {
2428                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2429                         return -ENOMEM;
2430                 }
2431         }
2432
2433         info->pending_bh = 0;
2434
2435         memset(&info->icount, 0, sizeof(info->icount));
2436
2437         /* program hardware for current parameters */
2438         change_params(info);
2439
2440         if (info->port.tty)
2441                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2442
2443         tty_port_set_initialized(&info->port, 1);
2444
2445         return 0;
2446 }
2447
2448 /*
2449  *  called by close() and hangup() to shutdown hardware
2450  */
2451 static void shutdown(struct slgt_info *info)
2452 {
2453         unsigned long flags;
2454
2455         if (!tty_port_initialized(&info->port))
2456                 return;
2457
2458         DBGINFO(("%s shutdown\n", info->device_name));
2459
2460         /* clear status wait queue because status changes */
2461         /* can't happen after shutting down the hardware */
2462         wake_up_interruptible(&info->status_event_wait_q);
2463         wake_up_interruptible(&info->event_wait_q);
2464
2465         del_timer_sync(&info->tx_timer);
2466         del_timer_sync(&info->rx_timer);
2467
2468         kfree(info->tx_buf);
2469         info->tx_buf = NULL;
2470
2471         spin_lock_irqsave(&info->lock,flags);
2472
2473         tx_stop(info);
2474         rx_stop(info);
2475
2476         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2477
2478         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2479                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2480                 set_signals(info);
2481         }
2482
2483         flush_cond_wait(&info->gpio_wait_q);
2484
2485         spin_unlock_irqrestore(&info->lock,flags);
2486
2487         if (info->port.tty)
2488                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2489
2490         tty_port_set_initialized(&info->port, 0);
2491 }
2492
2493 static void program_hw(struct slgt_info *info)
2494 {
2495         unsigned long flags;
2496
2497         spin_lock_irqsave(&info->lock,flags);
2498
2499         rx_stop(info);
2500         tx_stop(info);
2501
2502         if (info->params.mode != MGSL_MODE_ASYNC ||
2503             info->netcount)
2504                 sync_mode(info);
2505         else
2506                 async_mode(info);
2507
2508         set_signals(info);
2509
2510         info->dcd_chkcount = 0;
2511         info->cts_chkcount = 0;
2512         info->ri_chkcount = 0;
2513         info->dsr_chkcount = 0;
2514
2515         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2516         get_signals(info);
2517
2518         if (info->netcount ||
2519             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2520                 rx_start(info);
2521
2522         spin_unlock_irqrestore(&info->lock,flags);
2523 }
2524
2525 /*
2526  * reconfigure adapter based on new parameters
2527  */
2528 static void change_params(struct slgt_info *info)
2529 {
2530         unsigned cflag;
2531         int bits_per_char;
2532
2533         if (!info->port.tty)
2534                 return;
2535         DBGINFO(("%s change_params\n", info->device_name));
2536
2537         cflag = info->port.tty->termios.c_cflag;
2538
2539         /* if B0 rate (hangup) specified then negate RTS and DTR */
2540         /* otherwise assert RTS and DTR */
2541         if (cflag & CBAUD)
2542                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2543         else
2544                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2545
2546         /* byte size and parity */
2547
2548         switch (cflag & CSIZE) {
2549         case CS5: info->params.data_bits = 5; break;
2550         case CS6: info->params.data_bits = 6; break;
2551         case CS7: info->params.data_bits = 7; break;
2552         case CS8: info->params.data_bits = 8; break;
2553         default:  info->params.data_bits = 7; break;
2554         }
2555
2556         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2557
2558         if (cflag & PARENB)
2559                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2560         else
2561                 info->params.parity = ASYNC_PARITY_NONE;
2562
2563         /* calculate number of jiffies to transmit a full
2564          * FIFO (32 bytes) at specified data rate
2565          */
2566         bits_per_char = info->params.data_bits +
2567                         info->params.stop_bits + 1;
2568
2569         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2570
2571         if (info->params.data_rate) {
2572                 info->timeout = (32*HZ*bits_per_char) /
2573                                 info->params.data_rate;
2574         }
2575         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2576
2577         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2578         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2579
2580         /* process tty input control flags */
2581
2582         info->read_status_mask = IRQ_RXOVER;
2583         if (I_INPCK(info->port.tty))
2584                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2585         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2586                 info->read_status_mask |= MASK_BREAK;
2587         if (I_IGNPAR(info->port.tty))
2588                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2589         if (I_IGNBRK(info->port.tty)) {
2590                 info->ignore_status_mask |= MASK_BREAK;
2591                 /* If ignoring parity and break indicators, ignore
2592                  * overruns too.  (For real raw support).
2593                  */
2594                 if (I_IGNPAR(info->port.tty))
2595                         info->ignore_status_mask |= MASK_OVERRUN;
2596         }
2597
2598         program_hw(info);
2599 }
2600
2601 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2602 {
2603         DBGINFO(("%s get_stats\n",  info->device_name));
2604         if (!user_icount) {
2605                 memset(&info->icount, 0, sizeof(info->icount));
2606         } else {
2607                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2608                         return -EFAULT;
2609         }
2610         return 0;
2611 }
2612
2613 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2614 {
2615         DBGINFO(("%s get_params\n", info->device_name));
2616         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2617                 return -EFAULT;
2618         return 0;
2619 }
2620
2621 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2622 {
2623         unsigned long flags;
2624         MGSL_PARAMS tmp_params;
2625
2626         DBGINFO(("%s set_params\n", info->device_name));
2627         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2628                 return -EFAULT;
2629
2630         spin_lock_irqsave(&info->lock, flags);
2631         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2632                 info->base_clock = tmp_params.clock_speed;
2633         else
2634                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2635         spin_unlock_irqrestore(&info->lock, flags);
2636
2637         program_hw(info);
2638
2639         return 0;
2640 }
2641
2642 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2643 {
2644         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2645         if (put_user(info->idle_mode, idle_mode))
2646                 return -EFAULT;
2647         return 0;
2648 }
2649
2650 static int set_txidle(struct slgt_info *info, int idle_mode)
2651 {
2652         unsigned long flags;
2653         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2654         spin_lock_irqsave(&info->lock,flags);
2655         info->idle_mode = idle_mode;
2656         if (info->params.mode != MGSL_MODE_ASYNC)
2657                 tx_set_idle(info);
2658         spin_unlock_irqrestore(&info->lock,flags);
2659         return 0;
2660 }
2661
2662 static int tx_enable(struct slgt_info *info, int enable)
2663 {
2664         unsigned long flags;
2665         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2666         spin_lock_irqsave(&info->lock,flags);
2667         if (enable) {
2668                 if (!info->tx_enabled)
2669                         tx_start(info);
2670         } else {
2671                 if (info->tx_enabled)
2672                         tx_stop(info);
2673         }
2674         spin_unlock_irqrestore(&info->lock,flags);
2675         return 0;
2676 }
2677
2678 /*
2679  * abort transmit HDLC frame
2680  */
2681 static int tx_abort(struct slgt_info *info)
2682 {
2683         unsigned long flags;
2684         DBGINFO(("%s tx_abort\n", info->device_name));
2685         spin_lock_irqsave(&info->lock,flags);
2686         tdma_reset(info);
2687         spin_unlock_irqrestore(&info->lock,flags);
2688         return 0;
2689 }
2690
2691 static int rx_enable(struct slgt_info *info, int enable)
2692 {
2693         unsigned long flags;
2694         unsigned int rbuf_fill_level;
2695         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2696         spin_lock_irqsave(&info->lock,flags);
2697         /*
2698          * enable[31..16] = receive DMA buffer fill level
2699          * 0 = noop (leave fill level unchanged)
2700          * fill level must be multiple of 4 and <= buffer size
2701          */
2702         rbuf_fill_level = ((unsigned int)enable) >> 16;
2703         if (rbuf_fill_level) {
2704                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2705                         spin_unlock_irqrestore(&info->lock, flags);
2706                         return -EINVAL;
2707                 }
2708                 info->rbuf_fill_level = rbuf_fill_level;
2709                 if (rbuf_fill_level < 128)
2710                         info->rx_pio = 1; /* PIO mode */
2711                 else
2712                         info->rx_pio = 0; /* DMA mode */
2713                 rx_stop(info); /* restart receiver to use new fill level */
2714         }
2715
2716         /*
2717          * enable[1..0] = receiver enable command
2718          * 0 = disable
2719          * 1 = enable
2720          * 2 = enable or force hunt mode if already enabled
2721          */
2722         enable &= 3;
2723         if (enable) {
2724                 if (!info->rx_enabled)
2725                         rx_start(info);
2726                 else if (enable == 2) {
2727                         /* force hunt mode (write 1 to RCR[3]) */
2728                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2729                 }
2730         } else {
2731                 if (info->rx_enabled)
2732                         rx_stop(info);
2733         }
2734         spin_unlock_irqrestore(&info->lock,flags);
2735         return 0;
2736 }
2737
2738 /*
2739  *  wait for specified event to occur
2740  */
2741 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2742 {
2743         unsigned long flags;
2744         int s;
2745         int rc=0;
2746         struct mgsl_icount cprev, cnow;
2747         int events;
2748         int mask;
2749         struct  _input_signal_events oldsigs, newsigs;
2750         DECLARE_WAITQUEUE(wait, current);
2751
2752         if (get_user(mask, mask_ptr))
2753                 return -EFAULT;
2754
2755         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2756
2757         spin_lock_irqsave(&info->lock,flags);
2758
2759         /* return immediately if state matches requested events */
2760         get_signals(info);
2761         s = info->signals;
2762
2763         events = mask &
2764                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2765                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2766                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2767                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2768         if (events) {
2769                 spin_unlock_irqrestore(&info->lock,flags);
2770                 goto exit;
2771         }
2772
2773         /* save current irq counts */
2774         cprev = info->icount;
2775         oldsigs = info->input_signal_events;
2776
2777         /* enable hunt and idle irqs if needed */
2778         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2779                 unsigned short val = rd_reg16(info, SCR);
2780                 if (!(val & IRQ_RXIDLE))
2781                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2782         }
2783
2784         set_current_state(TASK_INTERRUPTIBLE);
2785         add_wait_queue(&info->event_wait_q, &wait);
2786
2787         spin_unlock_irqrestore(&info->lock,flags);
2788
2789         for(;;) {
2790                 schedule();
2791                 if (signal_pending(current)) {
2792                         rc = -ERESTARTSYS;
2793                         break;
2794                 }
2795
2796                 /* get current irq counts */
2797                 spin_lock_irqsave(&info->lock,flags);
2798                 cnow = info->icount;
2799                 newsigs = info->input_signal_events;
2800                 set_current_state(TASK_INTERRUPTIBLE);
2801                 spin_unlock_irqrestore(&info->lock,flags);
2802
2803                 /* if no change, wait aborted for some reason */
2804                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2805                     newsigs.dsr_down == oldsigs.dsr_down &&
2806                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2807                     newsigs.dcd_down == oldsigs.dcd_down &&
2808                     newsigs.cts_up   == oldsigs.cts_up   &&
2809                     newsigs.cts_down == oldsigs.cts_down &&
2810                     newsigs.ri_up    == oldsigs.ri_up    &&
2811                     newsigs.ri_down  == oldsigs.ri_down  &&
2812                     cnow.exithunt    == cprev.exithunt   &&
2813                     cnow.rxidle      == cprev.rxidle) {
2814                         rc = -EIO;
2815                         break;
2816                 }
2817
2818                 events = mask &
2819                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2820                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2821                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2822                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2823                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2824                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2825                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2826                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2827                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2828                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2829                 if (events)
2830                         break;
2831
2832                 cprev = cnow;
2833                 oldsigs = newsigs;
2834         }
2835
2836         remove_wait_queue(&info->event_wait_q, &wait);
2837         set_current_state(TASK_RUNNING);
2838
2839
2840         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2841                 spin_lock_irqsave(&info->lock,flags);
2842                 if (!waitqueue_active(&info->event_wait_q)) {
2843                         /* disable enable exit hunt mode/idle rcvd IRQs */
2844                         wr_reg16(info, SCR,
2845                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2846                 }
2847                 spin_unlock_irqrestore(&info->lock,flags);
2848         }
2849 exit:
2850         if (rc == 0)
2851                 rc = put_user(events, mask_ptr);
2852         return rc;
2853 }
2854
2855 static int get_interface(struct slgt_info *info, int __user *if_mode)
2856 {
2857         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2858         if (put_user(info->if_mode, if_mode))
2859                 return -EFAULT;
2860         return 0;
2861 }
2862
2863 static int set_interface(struct slgt_info *info, int if_mode)
2864 {
2865         unsigned long flags;
2866         unsigned short val;
2867
2868         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2869         spin_lock_irqsave(&info->lock,flags);
2870         info->if_mode = if_mode;
2871
2872         msc_set_vcr(info);
2873
2874         /* TCR (tx control) 07  1=RTS driver control */
2875         val = rd_reg16(info, TCR);
2876         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2877                 val |= BIT7;
2878         else
2879                 val &= ~BIT7;
2880         wr_reg16(info, TCR, val);
2881
2882         spin_unlock_irqrestore(&info->lock,flags);
2883         return 0;
2884 }
2885
2886 static int get_xsync(struct slgt_info *info, int __user *xsync)
2887 {
2888         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2889         if (put_user(info->xsync, xsync))
2890                 return -EFAULT;
2891         return 0;
2892 }
2893
2894 /*
2895  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2896  *
2897  * sync pattern is contained in least significant bytes of value
2898  * most significant byte of sync pattern is oldest (1st sent/detected)
2899  */
2900 static int set_xsync(struct slgt_info *info, int xsync)
2901 {
2902         unsigned long flags;
2903
2904         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2905         spin_lock_irqsave(&info->lock, flags);
2906         info->xsync = xsync;
2907         wr_reg32(info, XSR, xsync);
2908         spin_unlock_irqrestore(&info->lock, flags);
2909         return 0;
2910 }
2911
2912 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2913 {
2914         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2915         if (put_user(info->xctrl, xctrl))
2916                 return -EFAULT;
2917         return 0;
2918 }
2919
2920 /*
2921  * set extended control options
2922  *
2923  * xctrl[31:19] reserved, must be zero
2924  * xctrl[18:17] extended sync pattern length in bytes
2925  *              00 = 1 byte  in xsr[7:0]
2926  *              01 = 2 bytes in xsr[15:0]
2927  *              10 = 3 bytes in xsr[23:0]
2928  *              11 = 4 bytes in xsr[31:0]
2929  * xctrl[16]    1 = enable terminal count, 0=disabled
2930  * xctrl[15:0]  receive terminal count for fixed length packets
2931  *              value is count minus one (0 = 1 byte packet)
2932  *              when terminal count is reached, receiver
2933  *              automatically returns to hunt mode and receive
2934  *              FIFO contents are flushed to DMA buffers with
2935  *              end of frame (EOF) status
2936  */
2937 static int set_xctrl(struct slgt_info *info, int xctrl)
2938 {
2939         unsigned long flags;
2940
2941         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2942         spin_lock_irqsave(&info->lock, flags);
2943         info->xctrl = xctrl;
2944         wr_reg32(info, XCR, xctrl);
2945         spin_unlock_irqrestore(&info->lock, flags);
2946         return 0;
2947 }
2948
2949 /*
2950  * set general purpose IO pin state and direction
2951  *
2952  * user_gpio fields:
2953  * state   each bit indicates a pin state
2954  * smask   set bit indicates pin state to set
2955  * dir     each bit indicates a pin direction (0=input, 1=output)
2956  * dmask   set bit indicates pin direction to set
2957  */
2958 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2959 {
2960         unsigned long flags;
2961         struct gpio_desc gpio;
2962         __u32 data;
2963
2964         if (!info->gpio_present)
2965                 return -EINVAL;
2966         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2967                 return -EFAULT;
2968         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2969                  info->device_name, gpio.state, gpio.smask,
2970                  gpio.dir, gpio.dmask));
2971
2972         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2973         if (gpio.dmask) {
2974                 data = rd_reg32(info, IODR);
2975                 data |= gpio.dmask & gpio.dir;
2976                 data &= ~(gpio.dmask & ~gpio.dir);
2977                 wr_reg32(info, IODR, data);
2978         }
2979         if (gpio.smask) {
2980                 data = rd_reg32(info, IOVR);
2981                 data |= gpio.smask & gpio.state;
2982                 data &= ~(gpio.smask & ~gpio.state);
2983                 wr_reg32(info, IOVR, data);
2984         }
2985         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2986
2987         return 0;
2988 }
2989
2990 /*
2991  * get general purpose IO pin state and direction
2992  */
2993 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2994 {
2995         struct gpio_desc gpio;
2996         if (!info->gpio_present)
2997                 return -EINVAL;
2998         gpio.state = rd_reg32(info, IOVR);
2999         gpio.smask = 0xffffffff;
3000         gpio.dir   = rd_reg32(info, IODR);
3001         gpio.dmask = 0xffffffff;
3002         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3003                 return -EFAULT;
3004         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3005                  info->device_name, gpio.state, gpio.dir));
3006         return 0;
3007 }
3008
3009 /*
3010  * conditional wait facility
3011  */
3012 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3013 {
3014         init_waitqueue_head(&w->q);
3015         init_waitqueue_entry(&w->wait, current);
3016         w->data = data;
3017 }
3018
3019 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3020 {
3021         set_current_state(TASK_INTERRUPTIBLE);
3022         add_wait_queue(&w->q, &w->wait);
3023         w->next = *head;
3024         *head = w;
3025 }
3026
3027 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3028 {
3029         struct cond_wait *w, *prev;
3030         remove_wait_queue(&cw->q, &cw->wait);
3031         set_current_state(TASK_RUNNING);
3032         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3033                 if (w == cw) {
3034                         if (prev != NULL)
3035                                 prev->next = w->next;
3036                         else
3037                                 *head = w->next;
3038                         break;
3039                 }
3040         }
3041 }
3042
3043 static void flush_cond_wait(struct cond_wait **head)
3044 {
3045         while (*head != NULL) {
3046                 wake_up_interruptible(&(*head)->q);
3047                 *head = (*head)->next;
3048         }
3049 }
3050
3051 /*
3052  * wait for general purpose I/O pin(s) to enter specified state
3053  *
3054  * user_gpio fields:
3055  * state - bit indicates target pin state
3056  * smask - set bit indicates watched pin
3057  *
3058  * The wait ends when at least one watched pin enters the specified
3059  * state. When 0 (no error) is returned, user_gpio->state is set to the
3060  * state of all GPIO pins when the wait ends.
3061  *
3062  * Note: Each pin may be a dedicated input, dedicated output, or
3063  * configurable input/output. The number and configuration of pins
3064  * varies with the specific adapter model. Only input pins (dedicated
3065  * or configured) can be monitored with this function.
3066  */
3067 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3068 {
3069         unsigned long flags;
3070         int rc = 0;
3071         struct gpio_desc gpio;
3072         struct cond_wait wait;
3073         u32 state;
3074
3075         if (!info->gpio_present)
3076                 return -EINVAL;
3077         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3078                 return -EFAULT;
3079         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3080                  info->device_name, gpio.state, gpio.smask));
3081         /* ignore output pins identified by set IODR bit */
3082         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3083                 return -EINVAL;
3084         init_cond_wait(&wait, gpio.smask);
3085
3086         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3087         /* enable interrupts for watched pins */
3088         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3089         /* get current pin states */
3090         state = rd_reg32(info, IOVR);
3091
3092         if (gpio.smask & ~(state ^ gpio.state)) {
3093                 /* already in target state */
3094                 gpio.state = state;
3095         } else {
3096                 /* wait for target state */
3097                 add_cond_wait(&info->gpio_wait_q, &wait);
3098                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3099                 schedule();
3100                 if (signal_pending(current))
3101                         rc = -ERESTARTSYS;
3102                 else
3103                         gpio.state = wait.data;
3104                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3105                 remove_cond_wait(&info->gpio_wait_q, &wait);
3106         }
3107
3108         /* disable all GPIO interrupts if no waiting processes */
3109         if (info->gpio_wait_q == NULL)
3110                 wr_reg32(info, IOER, 0);
3111         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3112
3113         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3114                 rc = -EFAULT;
3115         return rc;
3116 }
3117
3118 static int modem_input_wait(struct slgt_info *info,int arg)
3119 {
3120         unsigned long flags;
3121         int rc;
3122         struct mgsl_icount cprev, cnow;
3123         DECLARE_WAITQUEUE(wait, current);
3124
3125         /* save current irq counts */
3126         spin_lock_irqsave(&info->lock,flags);
3127         cprev = info->icount;
3128         add_wait_queue(&info->status_event_wait_q, &wait);
3129         set_current_state(TASK_INTERRUPTIBLE);
3130         spin_unlock_irqrestore(&info->lock,flags);
3131
3132         for(;;) {
3133                 schedule();
3134                 if (signal_pending(current)) {
3135                         rc = -ERESTARTSYS;
3136                         break;
3137                 }
3138
3139                 /* get new irq counts */
3140                 spin_lock_irqsave(&info->lock,flags);
3141                 cnow = info->icount;
3142                 set_current_state(TASK_INTERRUPTIBLE);
3143                 spin_unlock_irqrestore(&info->lock,flags);
3144
3145                 /* if no change, wait aborted for some reason */
3146                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3147                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3148                         rc = -EIO;
3149                         break;
3150                 }
3151
3152                 /* check for change in caller specified modem input */
3153                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3154                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3155                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3156                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3157                         rc = 0;
3158                         break;
3159                 }
3160
3161                 cprev = cnow;
3162         }
3163         remove_wait_queue(&info->status_event_wait_q, &wait);
3164         set_current_state(TASK_RUNNING);
3165         return rc;
3166 }
3167
3168 /*
3169  *  return state of serial control and status signals
3170  */
3171 static int tiocmget(struct tty_struct *tty)
3172 {
3173         struct slgt_info *info = tty->driver_data;
3174         unsigned int result;
3175         unsigned long flags;
3176
3177         spin_lock_irqsave(&info->lock,flags);
3178         get_signals(info);
3179         spin_unlock_irqrestore(&info->lock,flags);
3180
3181         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3182                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3183                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3184                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3185                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3186                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3187
3188         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3189         return result;
3190 }
3191
3192 /*
3193  * set modem control signals (DTR/RTS)
3194  *
3195  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3196  *              TIOCMSET = set/clear signal values
3197  *      value   bit mask for command
3198  */
3199 static int tiocmset(struct tty_struct *tty,
3200                     unsigned int set, unsigned int clear)
3201 {
3202         struct slgt_info *info = tty->driver_data;
3203         unsigned long flags;
3204
3205         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3206
3207         if (set & TIOCM_RTS)
3208                 info->signals |= SerialSignal_RTS;
3209         if (set & TIOCM_DTR)
3210                 info->signals |= SerialSignal_DTR;
3211         if (clear & TIOCM_RTS)
3212                 info->signals &= ~SerialSignal_RTS;
3213         if (clear & TIOCM_DTR)
3214                 info->signals &= ~SerialSignal_DTR;
3215
3216         spin_lock_irqsave(&info->lock,flags);
3217         set_signals(info);
3218         spin_unlock_irqrestore(&info->lock,flags);
3219         return 0;
3220 }
3221
3222 static int carrier_raised(struct tty_port *port)
3223 {
3224         unsigned long flags;
3225         struct slgt_info *info = container_of(port, struct slgt_info, port);
3226
3227         spin_lock_irqsave(&info->lock,flags);
3228         get_signals(info);
3229         spin_unlock_irqrestore(&info->lock,flags);
3230         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3231 }
3232
3233 static void dtr_rts(struct tty_port *port, int on)
3234 {
3235         unsigned long flags;
3236         struct slgt_info *info = container_of(port, struct slgt_info, port);
3237
3238         spin_lock_irqsave(&info->lock,flags);
3239         if (on)
3240                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3241         else
3242                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3243         set_signals(info);
3244         spin_unlock_irqrestore(&info->lock,flags);
3245 }
3246
3247
3248 /*
3249  *  block current process until the device is ready to open
3250  */
3251 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3252                            struct slgt_info *info)
3253 {
3254         DECLARE_WAITQUEUE(wait, current);
3255         int             retval;
3256         bool            do_clocal = false;
3257         unsigned long   flags;
3258         int             cd;
3259         struct tty_port *port = &info->port;
3260
3261         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3262
3263         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3264                 /* nonblock mode is set or port is not enabled */
3265                 tty_port_set_active(port, 1);
3266                 return 0;
3267         }
3268
3269         if (C_CLOCAL(tty))
3270                 do_clocal = true;
3271
3272         /* Wait for carrier detect and the line to become
3273          * free (i.e., not in use by the callout).  While we are in
3274          * this loop, port->count is dropped by one, so that
3275          * close() knows when to free things.  We restore it upon
3276          * exit, either normal or abnormal.
3277          */
3278
3279         retval = 0;
3280         add_wait_queue(&port->open_wait, &wait);
3281
3282         spin_lock_irqsave(&info->lock, flags);
3283         port->count--;
3284         spin_unlock_irqrestore(&info->lock, flags);
3285         port->blocked_open++;
3286
3287         while (1) {
3288                 if (C_BAUD(tty) && tty_port_initialized(port))
3289                         tty_port_raise_dtr_rts(port);
3290
3291                 set_current_state(TASK_INTERRUPTIBLE);
3292
3293                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3294                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3295                                         -EAGAIN : -ERESTARTSYS;
3296                         break;
3297                 }
3298
3299                 cd = tty_port_carrier_raised(port);
3300                 if (do_clocal || cd)
3301                         break;
3302
3303                 if (signal_pending(current)) {
3304                         retval = -ERESTARTSYS;
3305                         break;
3306                 }
3307
3308                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3309                 tty_unlock(tty);
3310                 schedule();
3311                 tty_lock(tty);
3312         }
3313
3314         set_current_state(TASK_RUNNING);
3315         remove_wait_queue(&port->open_wait, &wait);
3316
3317         if (!tty_hung_up_p(filp))
3318                 port->count++;
3319         port->blocked_open--;
3320
3321         if (!retval)
3322                 tty_port_set_active(port, 1);
3323
3324         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3325         return retval;
3326 }
3327
3328 /*
3329  * allocate buffers used for calling line discipline receive_buf
3330  * directly in synchronous mode
3331  * note: add 5 bytes to max frame size to allow appending
3332  * 32-bit CRC and status byte when configured to do so
3333  */
3334 static int alloc_tmp_rbuf(struct slgt_info *info)
3335 {
3336         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3337         if (info->tmp_rbuf == NULL)
3338                 return -ENOMEM;
3339         /* unused flag buffer to satisfy receive_buf calling interface */
3340         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3341         if (!info->flag_buf) {
3342                 kfree(info->tmp_rbuf);
3343                 info->tmp_rbuf = NULL;
3344                 return -ENOMEM;
3345         }
3346         return 0;
3347 }
3348
3349 static void free_tmp_rbuf(struct slgt_info *info)
3350 {
3351         kfree(info->tmp_rbuf);
3352         info->tmp_rbuf = NULL;
3353         kfree(info->flag_buf);
3354         info->flag_buf = NULL;
3355 }
3356
3357 /*
3358  * allocate DMA descriptor lists.
3359  */
3360 static int alloc_desc(struct slgt_info *info)
3361 {
3362         unsigned int i;
3363         unsigned int pbufs;
3364
3365         /* allocate memory to hold descriptor lists */
3366         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3367                                            &info->bufs_dma_addr);
3368         if (info->bufs == NULL)
3369                 return -ENOMEM;
3370
3371         info->rbufs = (struct slgt_desc*)info->bufs;
3372         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3373
3374         pbufs = (unsigned int)info->bufs_dma_addr;
3375
3376         /*
3377          * Build circular lists of descriptors
3378          */
3379
3380         for (i=0; i < info->rbuf_count; i++) {
3381                 /* physical address of this descriptor */
3382                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3383
3384                 /* physical address of next descriptor */
3385                 if (i == info->rbuf_count - 1)
3386                         info->rbufs[i].next = cpu_to_le32(pbufs);
3387                 else
3388                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3389                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3390         }
3391
3392         for (i=0; i < info->tbuf_count; i++) {
3393                 /* physical address of this descriptor */
3394                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3395
3396                 /* physical address of next descriptor */
3397                 if (i == info->tbuf_count - 1)
3398                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3399                 else
3400                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3401         }
3402
3403         return 0;
3404 }
3405
3406 static void free_desc(struct slgt_info *info)
3407 {
3408         if (info->bufs != NULL) {
3409                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3410                 info->bufs  = NULL;
3411                 info->rbufs = NULL;
3412                 info->tbufs = NULL;
3413         }
3414 }
3415
3416 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3417 {
3418         int i;
3419         for (i=0; i < count; i++) {
3420                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3421                         return -ENOMEM;
3422                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3423         }
3424         return 0;
3425 }
3426
3427 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3428 {
3429         int i;
3430         for (i=0; i < count; i++) {
3431                 if (bufs[i].buf == NULL)
3432                         continue;
3433                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3434                 bufs[i].buf = NULL;
3435         }
3436 }
3437
3438 static int alloc_dma_bufs(struct slgt_info *info)
3439 {
3440         info->rbuf_count = 32;
3441         info->tbuf_count = 32;
3442
3443         if (alloc_desc(info) < 0 ||
3444             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3445             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3446             alloc_tmp_rbuf(info) < 0) {
3447                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3448                 return -ENOMEM;
3449         }
3450         reset_rbufs(info);
3451         return 0;
3452 }
3453
3454 static void free_dma_bufs(struct slgt_info *info)
3455 {
3456         if (info->bufs) {
3457                 free_bufs(info, info->rbufs, info->rbuf_count);
3458                 free_bufs(info, info->tbufs, info->tbuf_count);
3459                 free_desc(info);
3460         }
3461         free_tmp_rbuf(info);
3462 }
3463
3464 static int claim_resources(struct slgt_info *info)
3465 {
3466         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3467                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3468                         info->device_name, info->phys_reg_addr));
3469                 info->init_error = DiagStatus_AddressConflict;
3470                 goto errout;
3471         }
3472         else
3473                 info->reg_addr_requested = true;
3474
3475         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3476         if (!info->reg_addr) {
3477                 DBGERR(("%s can't map device registers, addr=%08X\n",
3478                         info->device_name, info->phys_reg_addr));
3479                 info->init_error = DiagStatus_CantAssignPciResources;
3480                 goto errout;
3481         }
3482         return 0;
3483
3484 errout:
3485         release_resources(info);
3486         return -ENODEV;
3487 }
3488
3489 static void release_resources(struct slgt_info *info)
3490 {
3491         if (info->irq_requested) {
3492                 free_irq(info->irq_level, info);
3493                 info->irq_requested = false;
3494         }
3495
3496         if (info->reg_addr_requested) {
3497                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3498                 info->reg_addr_requested = false;
3499         }
3500
3501         if (info->reg_addr) {
3502                 iounmap(info->reg_addr);
3503                 info->reg_addr = NULL;
3504         }
3505 }
3506
3507 /* Add the specified device instance data structure to the
3508  * global linked list of devices and increment the device count.
3509  */
3510 static void add_device(struct slgt_info *info)
3511 {
3512         char *devstr;
3513
3514         info->next_device = NULL;
3515         info->line = slgt_device_count;
3516         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3517
3518         if (info->line < MAX_DEVICES) {
3519                 if (maxframe[info->line])
3520                         info->max_frame_size = maxframe[info->line];
3521         }
3522
3523         slgt_device_count++;
3524
3525         if (!slgt_device_list)
3526                 slgt_device_list = info;
3527         else {
3528                 struct slgt_info *current_dev = slgt_device_list;
3529                 while(current_dev->next_device)
3530                         current_dev = current_dev->next_device;
3531                 current_dev->next_device = info;
3532         }
3533
3534         if (info->max_frame_size < 4096)
3535                 info->max_frame_size = 4096;
3536         else if (info->max_frame_size > 65535)
3537                 info->max_frame_size = 65535;
3538
3539         switch(info->pdev->device) {
3540         case SYNCLINK_GT_DEVICE_ID:
3541                 devstr = "GT";
3542                 break;
3543         case SYNCLINK_GT2_DEVICE_ID:
3544                 devstr = "GT2";
3545                 break;
3546         case SYNCLINK_GT4_DEVICE_ID:
3547                 devstr = "GT4";
3548                 break;
3549         case SYNCLINK_AC_DEVICE_ID:
3550                 devstr = "AC";
3551                 info->params.mode = MGSL_MODE_ASYNC;
3552                 break;
3553         default:
3554                 devstr = "(unknown model)";
3555         }
3556         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3557                 devstr, info->device_name, info->phys_reg_addr,
3558                 info->irq_level, info->max_frame_size);
3559
3560 #if SYNCLINK_GENERIC_HDLC
3561         hdlcdev_init(info);
3562 #endif
3563 }
3564
3565 static const struct tty_port_operations slgt_port_ops = {
3566         .carrier_raised = carrier_raised,
3567         .dtr_rts = dtr_rts,
3568 };
3569
3570 /*
3571  *  allocate device instance structure, return NULL on failure
3572  */
3573 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3574 {
3575         struct slgt_info *info;
3576
3577         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3578
3579         if (!info) {
3580                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3581                         driver_name, adapter_num, port_num));
3582         } else {
3583                 tty_port_init(&info->port);
3584                 info->port.ops = &slgt_port_ops;
3585                 info->magic = MGSL_MAGIC;
3586                 INIT_WORK(&info->task, bh_handler);
3587                 info->max_frame_size = 4096;
3588                 info->base_clock = 14745600;
3589                 info->rbuf_fill_level = DMABUFSIZE;
3590                 info->port.close_delay = 5*HZ/10;
3591                 info->port.closing_wait = 30*HZ;
3592                 init_waitqueue_head(&info->status_event_wait_q);
3593                 init_waitqueue_head(&info->event_wait_q);
3594                 spin_lock_init(&info->netlock);
3595                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3596                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3597                 info->adapter_num = adapter_num;
3598                 info->port_num = port_num;
3599
3600                 timer_setup(&info->tx_timer, tx_timeout, 0);
3601                 timer_setup(&info->rx_timer, rx_timeout, 0);
3602
3603                 /* Copy configuration info to device instance data */
3604                 info->pdev = pdev;
3605                 info->irq_level = pdev->irq;
3606                 info->phys_reg_addr = pci_resource_start(pdev,0);
3607
3608                 info->bus_type = MGSL_BUS_TYPE_PCI;
3609                 info->irq_flags = IRQF_SHARED;
3610
3611                 info->init_error = -1; /* assume error, set to 0 on successful init */
3612         }
3613
3614         return info;
3615 }
3616
3617 static void device_init(int adapter_num, struct pci_dev *pdev)
3618 {
3619         struct slgt_info *port_array[SLGT_MAX_PORTS];
3620         int i;
3621         int port_count = 1;
3622
3623         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3624                 port_count = 2;
3625         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3626                 port_count = 4;
3627
3628         /* allocate device instances for all ports */
3629         for (i=0; i < port_count; ++i) {
3630                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3631                 if (port_array[i] == NULL) {
3632                         for (--i; i >= 0; --i) {
3633                                 tty_port_destroy(&port_array[i]->port);
3634                                 kfree(port_array[i]);
3635                         }
3636                         return;
3637                 }
3638         }
3639
3640         /* give copy of port_array to all ports and add to device list  */
3641         for (i=0; i < port_count; ++i) {
3642                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3643                 add_device(port_array[i]);
3644                 port_array[i]->port_count = port_count;
3645                 spin_lock_init(&port_array[i]->lock);
3646         }
3647
3648         /* Allocate and claim adapter resources */
3649         if (!claim_resources(port_array[0])) {
3650
3651                 alloc_dma_bufs(port_array[0]);
3652
3653                 /* copy resource information from first port to others */
3654                 for (i = 1; i < port_count; ++i) {
3655                         port_array[i]->irq_level = port_array[0]->irq_level;
3656                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3657                         alloc_dma_bufs(port_array[i]);
3658                 }
3659
3660                 if (request_irq(port_array[0]->irq_level,
3661                                         slgt_interrupt,
3662                                         port_array[0]->irq_flags,
3663                                         port_array[0]->device_name,
3664                                         port_array[0]) < 0) {
3665                         DBGERR(("%s request_irq failed IRQ=%d\n",
3666                                 port_array[0]->device_name,
3667                                 port_array[0]->irq_level));
3668                 } else {
3669                         port_array[0]->irq_requested = true;
3670                         adapter_test(port_array[0]);
3671                         for (i=1 ; i < port_count ; i++) {
3672                                 port_array[i]->init_error = port_array[0]->init_error;
3673                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3674                         }
3675                 }
3676         }
3677
3678         for (i = 0; i < port_count; ++i) {
3679                 struct slgt_info *info = port_array[i];
3680                 tty_port_register_device(&info->port, serial_driver, info->line,
3681                                 &info->pdev->dev);
3682         }
3683 }
3684
3685 static int init_one(struct pci_dev *dev,
3686                               const struct pci_device_id *ent)
3687 {
3688         if (pci_enable_device(dev)) {
3689                 printk("error enabling pci device %p\n", dev);
3690                 return -EIO;
3691         }
3692         pci_set_master(dev);
3693         device_init(slgt_device_count, dev);
3694         return 0;
3695 }
3696
3697 static void remove_one(struct pci_dev *dev)
3698 {
3699 }
3700
3701 static const struct tty_operations ops = {
3702         .open = open,
3703         .close = close,
3704         .write = write,
3705         .put_char = put_char,
3706         .flush_chars = flush_chars,
3707         .write_room = write_room,
3708         .chars_in_buffer = chars_in_buffer,
3709         .flush_buffer = flush_buffer,
3710         .ioctl = ioctl,
3711         .compat_ioctl = slgt_compat_ioctl,
3712         .throttle = throttle,
3713         .unthrottle = unthrottle,
3714         .send_xchar = send_xchar,
3715         .break_ctl = set_break,
3716         .wait_until_sent = wait_until_sent,
3717         .set_termios = set_termios,
3718         .stop = tx_hold,
3719         .start = tx_release,
3720         .hangup = hangup,
3721         .tiocmget = tiocmget,
3722         .tiocmset = tiocmset,
3723         .get_icount = get_icount,
3724         .proc_fops = &synclink_gt_proc_fops,
3725 };
3726
3727 static void slgt_cleanup(void)
3728 {
3729         int rc;
3730         struct slgt_info *info;
3731         struct slgt_info *tmp;
3732
3733         printk(KERN_INFO "unload %s\n", driver_name);
3734
3735         if (serial_driver) {
3736                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3737                         tty_unregister_device(serial_driver, info->line);
3738                 rc = tty_unregister_driver(serial_driver);
3739                 if (rc)
3740                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3741                 put_tty_driver(serial_driver);
3742         }
3743
3744         /* reset devices */
3745         info = slgt_device_list;
3746         while(info) {
3747                 reset_port(info);
3748                 info = info->next_device;
3749         }
3750
3751         /* release devices */
3752         info = slgt_device_list;
3753         while(info) {
3754 #if SYNCLINK_GENERIC_HDLC
3755                 hdlcdev_exit(info);
3756 #endif
3757                 free_dma_bufs(info);
3758                 free_tmp_rbuf(info);
3759                 if (info->port_num == 0)
3760                         release_resources(info);
3761                 tmp = info;
3762                 info = info->next_device;
3763                 tty_port_destroy(&tmp->port);
3764                 kfree(tmp);
3765         }
3766
3767         if (pci_registered)
3768                 pci_unregister_driver(&pci_driver);
3769 }
3770
3771 /*
3772  *  Driver initialization entry point.
3773  */
3774 static int __init slgt_init(void)
3775 {
3776         int rc;
3777
3778         printk(KERN_INFO "%s\n", driver_name);
3779
3780         serial_driver = alloc_tty_driver(MAX_DEVICES);
3781         if (!serial_driver) {
3782                 printk("%s can't allocate tty driver\n", driver_name);
3783                 return -ENOMEM;
3784         }
3785
3786         /* Initialize the tty_driver structure */
3787
3788         serial_driver->driver_name = slgt_driver_name;
3789         serial_driver->name = tty_dev_prefix;
3790         serial_driver->major = ttymajor;
3791         serial_driver->minor_start = 64;
3792         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3793         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3794         serial_driver->init_termios = tty_std_termios;
3795         serial_driver->init_termios.c_cflag =
3796                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3797         serial_driver->init_termios.c_ispeed = 9600;
3798         serial_driver->init_termios.c_ospeed = 9600;
3799         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3800         tty_set_operations(serial_driver, &ops);
3801         if ((rc = tty_register_driver(serial_driver)) < 0) {
3802                 DBGERR(("%s can't register serial driver\n", driver_name));
3803                 put_tty_driver(serial_driver);
3804                 serial_driver = NULL;
3805                 goto error;
3806         }
3807
3808         printk(KERN_INFO "%s, tty major#%d\n",
3809                driver_name, serial_driver->major);
3810
3811         slgt_device_count = 0;
3812         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3813                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3814                 goto error;
3815         }
3816         pci_registered = true;
3817
3818         if (!slgt_device_list)
3819                 printk("%s no devices found\n",driver_name);
3820
3821         return 0;
3822
3823 error:
3824         slgt_cleanup();
3825         return rc;
3826 }
3827
3828 static void __exit slgt_exit(void)
3829 {
3830         slgt_cleanup();
3831 }
3832
3833 module_init(slgt_init);
3834 module_exit(slgt_exit);
3835
3836 /*
3837  * register access routines
3838  */
3839
3840 #define CALC_REGADDR() \
3841         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3842         if (addr >= 0x80) \
3843                 reg_addr += (info->port_num) * 32; \
3844         else if (addr >= 0x40)  \
3845                 reg_addr += (info->port_num) * 16;
3846
3847 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3848 {
3849         CALC_REGADDR();
3850         return readb((void __iomem *)reg_addr);
3851 }
3852
3853 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3854 {
3855         CALC_REGADDR();
3856         writeb(value, (void __iomem *)reg_addr);
3857 }
3858
3859 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3860 {
3861         CALC_REGADDR();
3862         return readw((void __iomem *)reg_addr);
3863 }
3864
3865 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3866 {
3867         CALC_REGADDR();
3868         writew(value, (void __iomem *)reg_addr);
3869 }
3870
3871 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3872 {
3873         CALC_REGADDR();
3874         return readl((void __iomem *)reg_addr);
3875 }
3876
3877 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3878 {
3879         CALC_REGADDR();
3880         writel(value, (void __iomem *)reg_addr);
3881 }
3882
3883 static void rdma_reset(struct slgt_info *info)
3884 {
3885         unsigned int i;
3886
3887         /* set reset bit */
3888         wr_reg32(info, RDCSR, BIT1);
3889
3890         /* wait for enable bit cleared */
3891         for(i=0 ; i < 1000 ; i++)
3892                 if (!(rd_reg32(info, RDCSR) & BIT0))
3893                         break;
3894 }
3895
3896 static void tdma_reset(struct slgt_info *info)
3897 {
3898         unsigned int i;
3899
3900         /* set reset bit */
3901         wr_reg32(info, TDCSR, BIT1);
3902
3903         /* wait for enable bit cleared */
3904         for(i=0 ; i < 1000 ; i++)
3905                 if (!(rd_reg32(info, TDCSR) & BIT0))
3906                         break;
3907 }
3908
3909 /*
3910  * enable internal loopback
3911  * TxCLK and RxCLK are generated from BRG
3912  * and TxD is looped back to RxD internally.
3913  */
3914 static void enable_loopback(struct slgt_info *info)
3915 {
3916         /* SCR (serial control) BIT2=loopback enable */
3917         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3918
3919         if (info->params.mode != MGSL_MODE_ASYNC) {
3920                 /* CCR (clock control)
3921                  * 07..05  tx clock source (010 = BRG)
3922                  * 04..02  rx clock source (010 = BRG)
3923                  * 01      auxclk enable   (0 = disable)
3924                  * 00      BRG enable      (1 = enable)
3925                  *
3926                  * 0100 1001
3927                  */
3928                 wr_reg8(info, CCR, 0x49);
3929
3930                 /* set speed if available, otherwise use default */
3931                 if (info->params.clock_speed)
3932                         set_rate(info, info->params.clock_speed);
3933                 else
3934                         set_rate(info, 3686400);
3935         }
3936 }
3937
3938 /*
3939  *  set baud rate generator to specified rate
3940  */
3941 static void set_rate(struct slgt_info *info, u32 rate)
3942 {
3943         unsigned int div;
3944         unsigned int osc = info->base_clock;
3945
3946         /* div = osc/rate - 1
3947          *
3948          * Round div up if osc/rate is not integer to
3949          * force to next slowest rate.
3950          */
3951
3952         if (rate) {
3953                 div = osc/rate;
3954                 if (!(osc % rate) && div)
3955                         div--;
3956                 wr_reg16(info, BDR, (unsigned short)div);
3957         }
3958 }
3959
3960 static void rx_stop(struct slgt_info *info)
3961 {
3962         unsigned short val;
3963
3964         /* disable and reset receiver */
3965         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3966         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3967         wr_reg16(info, RCR, val);                  /* clear reset bit */
3968
3969         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3970
3971         /* clear pending rx interrupts */
3972         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3973
3974         rdma_reset(info);
3975
3976         info->rx_enabled = false;
3977         info->rx_restart = false;
3978 }
3979
3980 static void rx_start(struct slgt_info *info)
3981 {
3982         unsigned short val;
3983
3984         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3985
3986         /* clear pending rx overrun IRQ */
3987         wr_reg16(info, SSR, IRQ_RXOVER);
3988
3989         /* reset and disable receiver */
3990         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3991         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3992         wr_reg16(info, RCR, val);                  /* clear reset bit */
3993
3994         rdma_reset(info);
3995         reset_rbufs(info);
3996
3997         if (info->rx_pio) {
3998                 /* rx request when rx FIFO not empty */
3999                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4000                 slgt_irq_on(info, IRQ_RXDATA);
4001                 if (info->params.mode == MGSL_MODE_ASYNC) {
4002                         /* enable saving of rx status */
4003                         wr_reg32(info, RDCSR, BIT6);
4004                 }
4005         } else {
4006                 /* rx request when rx FIFO half full */
4007                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4008                 /* set 1st descriptor address */
4009                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4010
4011                 if (info->params.mode != MGSL_MODE_ASYNC) {
4012                         /* enable rx DMA and DMA interrupt */
4013                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4014                 } else {
4015                         /* enable saving of rx status, rx DMA and DMA interrupt */
4016                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4017                 }
4018         }
4019
4020         slgt_irq_on(info, IRQ_RXOVER);
4021
4022         /* enable receiver */
4023         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4024
4025         info->rx_restart = false;
4026         info->rx_enabled = true;
4027 }
4028
4029 static void tx_start(struct slgt_info *info)
4030 {
4031         if (!info->tx_enabled) {
4032                 wr_reg16(info, TCR,
4033                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4034                 info->tx_enabled = true;
4035         }
4036
4037         if (desc_count(info->tbufs[info->tbuf_start])) {
4038                 info->drop_rts_on_tx_done = false;
4039
4040                 if (info->params.mode != MGSL_MODE_ASYNC) {
4041                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4042                                 get_signals(info);
4043                                 if (!(info->signals & SerialSignal_RTS)) {
4044                                         info->signals |= SerialSignal_RTS;
4045                                         set_signals(info);
4046                                         info->drop_rts_on_tx_done = true;
4047                                 }
4048                         }
4049
4050                         slgt_irq_off(info, IRQ_TXDATA);
4051                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4052                         /* clear tx idle and underrun status bits */
4053                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4054                 } else {
4055                         slgt_irq_off(info, IRQ_TXDATA);
4056                         slgt_irq_on(info, IRQ_TXIDLE);
4057                         /* clear tx idle status bit */
4058                         wr_reg16(info, SSR, IRQ_TXIDLE);
4059                 }
4060                 /* set 1st descriptor address and start DMA */
4061                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4062                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4063                 info->tx_active = true;
4064         }
4065 }
4066
4067 static void tx_stop(struct slgt_info *info)
4068 {
4069         unsigned short val;
4070
4071         del_timer(&info->tx_timer);
4072
4073         tdma_reset(info);
4074
4075         /* reset and disable transmitter */
4076         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4077         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4078
4079         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4080
4081         /* clear tx idle and underrun status bit */
4082         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4083
4084         reset_tbufs(info);
4085
4086         info->tx_enabled = false;
4087         info->tx_active = false;
4088 }
4089
4090 static void reset_port(struct slgt_info *info)
4091 {
4092         if (!info->reg_addr)
4093                 return;
4094
4095         tx_stop(info);
4096         rx_stop(info);
4097
4098         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4099         set_signals(info);
4100
4101         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4102 }
4103
4104 static void reset_adapter(struct slgt_info *info)
4105 {
4106         int i;
4107         for (i=0; i < info->port_count; ++i) {
4108                 if (info->port_array[i])
4109                         reset_port(info->port_array[i]);
4110         }
4111 }
4112
4113 static void async_mode(struct slgt_info *info)
4114 {
4115         unsigned short val;
4116
4117         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4118         tx_stop(info);
4119         rx_stop(info);
4120
4121         /* TCR (tx control)
4122          *
4123          * 15..13  mode, 010=async
4124          * 12..10  encoding, 000=NRZ
4125          * 09      parity enable
4126          * 08      1=odd parity, 0=even parity
4127          * 07      1=RTS driver control
4128          * 06      1=break enable
4129          * 05..04  character length
4130          *         00=5 bits
4131          *         01=6 bits
4132          *         10=7 bits
4133          *         11=8 bits
4134          * 03      0=1 stop bit, 1=2 stop bits
4135          * 02      reset
4136          * 01      enable
4137          * 00      auto-CTS enable
4138          */
4139         val = 0x4000;
4140
4141         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4142                 val |= BIT7;
4143
4144         if (info->params.parity != ASYNC_PARITY_NONE) {
4145                 val |= BIT9;
4146                 if (info->params.parity == ASYNC_PARITY_ODD)
4147                         val |= BIT8;
4148         }
4149
4150         switch (info->params.data_bits)
4151         {
4152         case 6: val |= BIT4; break;
4153         case 7: val |= BIT5; break;
4154         case 8: val |= BIT5 + BIT4; break;
4155         }
4156
4157         if (info->params.stop_bits != 1)
4158                 val |= BIT3;
4159
4160         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4161                 val |= BIT0;
4162
4163         wr_reg16(info, TCR, val);
4164
4165         /* RCR (rx control)
4166          *
4167          * 15..13  mode, 010=async
4168          * 12..10  encoding, 000=NRZ
4169          * 09      parity enable
4170          * 08      1=odd parity, 0=even parity
4171          * 07..06  reserved, must be 0
4172          * 05..04  character length
4173          *         00=5 bits
4174          *         01=6 bits
4175          *         10=7 bits
4176          *         11=8 bits
4177          * 03      reserved, must be zero
4178          * 02      reset
4179          * 01      enable
4180          * 00      auto-DCD enable
4181          */
4182         val = 0x4000;
4183
4184         if (info->params.parity != ASYNC_PARITY_NONE) {
4185                 val |= BIT9;
4186                 if (info->params.parity == ASYNC_PARITY_ODD)
4187                         val |= BIT8;
4188         }
4189
4190         switch (info->params.data_bits)
4191         {
4192         case 6: val |= BIT4; break;
4193         case 7: val |= BIT5; break;
4194         case 8: val |= BIT5 + BIT4; break;
4195         }
4196
4197         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4198                 val |= BIT0;
4199
4200         wr_reg16(info, RCR, val);
4201
4202         /* CCR (clock control)
4203          *
4204          * 07..05  011 = tx clock source is BRG/16
4205          * 04..02  010 = rx clock source is BRG
4206          * 01      0 = auxclk disabled
4207          * 00      1 = BRG enabled
4208          *
4209          * 0110 1001
4210          */
4211         wr_reg8(info, CCR, 0x69);
4212
4213         msc_set_vcr(info);
4214
4215         /* SCR (serial control)
4216          *
4217          * 15  1=tx req on FIFO half empty
4218          * 14  1=rx req on FIFO half full
4219          * 13  tx data  IRQ enable
4220          * 12  tx idle  IRQ enable
4221          * 11  rx break on IRQ enable
4222          * 10  rx data  IRQ enable
4223          * 09  rx break off IRQ enable
4224          * 08  overrun  IRQ enable
4225          * 07  DSR      IRQ enable
4226          * 06  CTS      IRQ enable
4227          * 05  DCD      IRQ enable
4228          * 04  RI       IRQ enable
4229          * 03  0=16x sampling, 1=8x sampling
4230          * 02  1=txd->rxd internal loopback enable
4231          * 01  reserved, must be zero
4232          * 00  1=master IRQ enable
4233          */
4234         val = BIT15 + BIT14 + BIT0;
4235         /* JCR[8] : 1 = x8 async mode feature available */
4236         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4237             ((info->base_clock < (info->params.data_rate * 16)) ||
4238              (info->base_clock % (info->params.data_rate * 16)))) {
4239                 /* use 8x sampling */
4240                 val |= BIT3;
4241                 set_rate(info, info->params.data_rate * 8);
4242         } else {
4243                 /* use 16x sampling */
4244                 set_rate(info, info->params.data_rate * 16);
4245         }
4246         wr_reg16(info, SCR, val);
4247
4248         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4249
4250         if (info->params.loopback)
4251                 enable_loopback(info);
4252 }
4253
4254 static void sync_mode(struct slgt_info *info)
4255 {
4256         unsigned short val;
4257
4258         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4259         tx_stop(info);
4260         rx_stop(info);
4261
4262         /* TCR (tx control)
4263          *
4264          * 15..13  mode
4265          *         000=HDLC/SDLC
4266          *         001=raw bit synchronous
4267          *         010=asynchronous/isochronous
4268          *         011=monosync byte synchronous
4269          *         100=bisync byte synchronous
4270          *         101=xsync byte synchronous
4271          * 12..10  encoding
4272          * 09      CRC enable
4273          * 08      CRC32
4274          * 07      1=RTS driver control
4275          * 06      preamble enable
4276          * 05..04  preamble length
4277          * 03      share open/close flag
4278          * 02      reset
4279          * 01      enable
4280          * 00      auto-CTS enable
4281          */
4282         val = BIT2;
4283
4284         switch(info->params.mode) {
4285         case MGSL_MODE_XSYNC:
4286                 val |= BIT15 + BIT13;
4287                 break;
4288         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4289         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4290         case MGSL_MODE_RAW:      val |= BIT13; break;
4291         }
4292         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4293                 val |= BIT7;
4294
4295         switch(info->params.encoding)
4296         {
4297         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4298         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4299         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4300         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4301         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4302         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4303         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4304         }
4305
4306         switch (info->params.crc_type & HDLC_CRC_MASK)
4307         {
4308         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4309         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4310         }
4311
4312         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4313                 val |= BIT6;
4314
4315         switch (info->params.preamble_length)
4316         {
4317         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4318         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4319         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4320         }
4321
4322         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4323                 val |= BIT0;
4324
4325         wr_reg16(info, TCR, val);
4326
4327         /* TPR (transmit preamble) */
4328
4329         switch (info->params.preamble)
4330         {
4331         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4332         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4333         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4334         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4335         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4336         default:                          val = 0x7e; break;
4337         }
4338         wr_reg8(info, TPR, (unsigned char)val);
4339
4340         /* RCR (rx control)
4341          *
4342          * 15..13  mode
4343          *         000=HDLC/SDLC
4344          *         001=raw bit synchronous
4345          *         010=asynchronous/isochronous
4346          *         011=monosync byte synchronous
4347          *         100=bisync byte synchronous
4348          *         101=xsync byte synchronous
4349          * 12..10  encoding
4350          * 09      CRC enable
4351          * 08      CRC32
4352          * 07..03  reserved, must be 0
4353          * 02      reset
4354          * 01      enable
4355          * 00      auto-DCD enable
4356          */
4357         val = 0;
4358
4359         switch(info->params.mode) {
4360         case MGSL_MODE_XSYNC:
4361                 val |= BIT15 + BIT13;
4362                 break;
4363         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4364         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4365         case MGSL_MODE_RAW:      val |= BIT13; break;
4366         }
4367
4368         switch(info->params.encoding)
4369         {
4370         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4371         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4372         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4373         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4374         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4375         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4376         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4377         }
4378
4379         switch (info->params.crc_type & HDLC_CRC_MASK)
4380         {
4381         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4382         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4383         }
4384
4385         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4386                 val |= BIT0;
4387
4388         wr_reg16(info, RCR, val);
4389
4390         /* CCR (clock control)
4391          *
4392          * 07..05  tx clock source
4393          * 04..02  rx clock source
4394          * 01      auxclk enable
4395          * 00      BRG enable
4396          */
4397         val = 0;
4398
4399         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4400         {
4401                 // when RxC source is DPLL, BRG generates 16X DPLL
4402                 // reference clock, so take TxC from BRG/16 to get
4403                 // transmit clock at actual data rate
4404                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4405                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4406                 else
4407                         val |= BIT6;    /* 010, txclk = BRG */
4408         }
4409         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4410                 val |= BIT7;    /* 100, txclk = DPLL Input */
4411         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4412                 val |= BIT5;    /* 001, txclk = RXC Input */
4413
4414         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4415                 val |= BIT3;    /* 010, rxclk = BRG */
4416         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4417                 val |= BIT4;    /* 100, rxclk = DPLL */
4418         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4419                 val |= BIT2;    /* 001, rxclk = TXC Input */
4420
4421         if (info->params.clock_speed)
4422                 val |= BIT1 + BIT0;
4423
4424         wr_reg8(info, CCR, (unsigned char)val);
4425
4426         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4427         {
4428                 // program DPLL mode
4429                 switch(info->params.encoding)
4430                 {
4431                 case HDLC_ENCODING_BIPHASE_MARK:
4432                 case HDLC_ENCODING_BIPHASE_SPACE:
4433                         val = BIT7; break;
4434                 case HDLC_ENCODING_BIPHASE_LEVEL:
4435                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4436                         val = BIT7 + BIT6; break;
4437                 default: val = BIT6;    // NRZ encodings
4438                 }
4439                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4440
4441                 // DPLL requires a 16X reference clock from BRG
4442                 set_rate(info, info->params.clock_speed * 16);
4443         }
4444         else
4445                 set_rate(info, info->params.clock_speed);
4446
4447         tx_set_idle(info);
4448
4449         msc_set_vcr(info);
4450
4451         /* SCR (serial control)
4452          *
4453          * 15  1=tx req on FIFO half empty
4454          * 14  1=rx req on FIFO half full
4455          * 13  tx data  IRQ enable
4456          * 12  tx idle  IRQ enable
4457          * 11  underrun IRQ enable
4458          * 10  rx data  IRQ enable
4459          * 09  rx idle  IRQ enable
4460          * 08  overrun  IRQ enable
4461          * 07  DSR      IRQ enable
4462          * 06  CTS      IRQ enable
4463          * 05  DCD      IRQ enable
4464          * 04  RI       IRQ enable
4465          * 03  reserved, must be zero
4466          * 02  1=txd->rxd internal loopback enable
4467          * 01  reserved, must be zero
4468          * 00  1=master IRQ enable
4469          */
4470         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4471
4472         if (info->params.loopback)
4473                 enable_loopback(info);
4474 }
4475
4476 /*
4477  *  set transmit idle mode
4478  */
4479 static void tx_set_idle(struct slgt_info *info)
4480 {
4481         unsigned char val;
4482         unsigned short tcr;
4483
4484         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4485          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4486          */
4487         tcr = rd_reg16(info, TCR);
4488         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4489                 /* disable preamble, set idle size to 16 bits */
4490                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4491                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4492                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4493         } else if (!(tcr & BIT6)) {
4494                 /* preamble is disabled, set idle size to 8 bits */
4495                 tcr &= ~(BIT5 + BIT4);
4496         }
4497         wr_reg16(info, TCR, tcr);
4498
4499         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4500                 /* LSB of custom tx idle specified in tx idle register */
4501                 val = (unsigned char)(info->idle_mode & 0xff);
4502         } else {
4503                 /* standard 8 bit idle patterns */
4504                 switch(info->idle_mode)
4505                 {
4506                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4507                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4508                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4509                 case HDLC_TXIDLE_ZEROS:
4510                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4511                 default:                         val = 0xff;
4512                 }
4513         }
4514
4515         wr_reg8(info, TIR, val);
4516 }
4517
4518 /*
4519  * get state of V24 status (input) signals
4520  */
4521 static void get_signals(struct slgt_info *info)
4522 {
4523         unsigned short status = rd_reg16(info, SSR);
4524
4525         /* clear all serial signals except RTS and DTR */
4526         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4527
4528         if (status & BIT3)
4529                 info->signals |= SerialSignal_DSR;
4530         if (status & BIT2)
4531                 info->signals |= SerialSignal_CTS;
4532         if (status & BIT1)
4533                 info->signals |= SerialSignal_DCD;
4534         if (status & BIT0)
4535                 info->signals |= SerialSignal_RI;
4536 }
4537
4538 /*
4539  * set V.24 Control Register based on current configuration
4540  */
4541 static void msc_set_vcr(struct slgt_info *info)
4542 {
4543         unsigned char val = 0;
4544
4545         /* VCR (V.24 control)
4546          *
4547          * 07..04  serial IF select
4548          * 03      DTR
4549          * 02      RTS
4550          * 01      LL
4551          * 00      RL
4552          */
4553
4554         switch(info->if_mode & MGSL_INTERFACE_MASK)
4555         {
4556         case MGSL_INTERFACE_RS232:
4557                 val |= BIT5; /* 0010 */
4558                 break;
4559         case MGSL_INTERFACE_V35:
4560                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4561                 break;
4562         case MGSL_INTERFACE_RS422:
4563                 val |= BIT6; /* 0100 */
4564                 break;
4565         }
4566
4567         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4568                 val |= BIT4;
4569         if (info->signals & SerialSignal_DTR)
4570                 val |= BIT3;
4571         if (info->signals & SerialSignal_RTS)
4572                 val |= BIT2;
4573         if (info->if_mode & MGSL_INTERFACE_LL)
4574                 val |= BIT1;
4575         if (info->if_mode & MGSL_INTERFACE_RL)
4576                 val |= BIT0;
4577         wr_reg8(info, VCR, val);
4578 }
4579
4580 /*
4581  * set state of V24 control (output) signals
4582  */
4583 static void set_signals(struct slgt_info *info)
4584 {
4585         unsigned char val = rd_reg8(info, VCR);
4586         if (info->signals & SerialSignal_DTR)
4587                 val |= BIT3;
4588         else
4589                 val &= ~BIT3;
4590         if (info->signals & SerialSignal_RTS)
4591                 val |= BIT2;
4592         else
4593                 val &= ~BIT2;
4594         wr_reg8(info, VCR, val);
4595 }
4596
4597 /*
4598  * free range of receive DMA buffers (i to last)
4599  */
4600 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4601 {
4602         int done = 0;
4603
4604         while(!done) {
4605                 /* reset current buffer for reuse */
4606                 info->rbufs[i].status = 0;
4607                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4608                 if (i == last)
4609                         done = 1;
4610                 if (++i == info->rbuf_count)
4611                         i = 0;
4612         }
4613         info->rbuf_current = i;
4614 }
4615
4616 /*
4617  * mark all receive DMA buffers as free
4618  */
4619 static void reset_rbufs(struct slgt_info *info)
4620 {
4621         free_rbufs(info, 0, info->rbuf_count - 1);
4622         info->rbuf_fill_index = 0;
4623         info->rbuf_fill_count = 0;
4624 }
4625
4626 /*
4627  * pass receive HDLC frame to upper layer
4628  *
4629  * return true if frame available, otherwise false
4630  */
4631 static bool rx_get_frame(struct slgt_info *info)
4632 {
4633         unsigned int start, end;
4634         unsigned short status;
4635         unsigned int framesize = 0;
4636         unsigned long flags;
4637         struct tty_struct *tty = info->port.tty;
4638         unsigned char addr_field = 0xff;
4639         unsigned int crc_size = 0;
4640
4641         switch (info->params.crc_type & HDLC_CRC_MASK) {
4642         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4643         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4644         }
4645
4646 check_again:
4647
4648         framesize = 0;
4649         addr_field = 0xff;
4650         start = end = info->rbuf_current;
4651
4652         for (;;) {
4653                 if (!desc_complete(info->rbufs[end]))
4654                         goto cleanup;
4655
4656                 if (framesize == 0 && info->params.addr_filter != 0xff)
4657                         addr_field = info->rbufs[end].buf[0];
4658
4659                 framesize += desc_count(info->rbufs[end]);
4660
4661                 if (desc_eof(info->rbufs[end]))
4662                         break;
4663
4664                 if (++end == info->rbuf_count)
4665                         end = 0;
4666
4667                 if (end == info->rbuf_current) {
4668                         if (info->rx_enabled){
4669                                 spin_lock_irqsave(&info->lock,flags);
4670                                 rx_start(info);
4671                                 spin_unlock_irqrestore(&info->lock,flags);
4672                         }
4673                         goto cleanup;
4674                 }
4675         }
4676
4677         /* status
4678          *
4679          * 15      buffer complete
4680          * 14..06  reserved
4681          * 05..04  residue
4682          * 02      eof (end of frame)
4683          * 01      CRC error
4684          * 00      abort
4685          */
4686         status = desc_status(info->rbufs[end]);
4687
4688         /* ignore CRC bit if not using CRC (bit is undefined) */
4689         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4690                 status &= ~BIT1;
4691
4692         if (framesize == 0 ||
4693                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4694                 free_rbufs(info, start, end);
4695                 goto check_again;
4696         }
4697
4698         if (framesize < (2 + crc_size) || status & BIT0) {
4699                 info->icount.rxshort++;
4700                 framesize = 0;
4701         } else if (status & BIT1) {
4702                 info->icount.rxcrc++;
4703                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4704                         framesize = 0;
4705         }
4706
4707 #if SYNCLINK_GENERIC_HDLC
4708         if (framesize == 0) {
4709                 info->netdev->stats.rx_errors++;
4710                 info->netdev->stats.rx_frame_errors++;
4711         }
4712 #endif
4713
4714         DBGBH(("%s rx frame status=%04X size=%d\n",
4715                 info->device_name, status, framesize));
4716         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4717
4718         if (framesize) {
4719                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4720                         framesize -= crc_size;
4721                         crc_size = 0;
4722                 }
4723
4724                 if (framesize > info->max_frame_size + crc_size)
4725                         info->icount.rxlong++;
4726                 else {
4727                         /* copy dma buffer(s) to contiguous temp buffer */
4728                         int copy_count = framesize;
4729                         int i = start;
4730                         unsigned char *p = info->tmp_rbuf;
4731                         info->tmp_rbuf_count = framesize;
4732
4733                         info->icount.rxok++;
4734
4735                         while(copy_count) {
4736                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4737                                 memcpy(p, info->rbufs[i].buf, partial_count);
4738                                 p += partial_count;
4739                                 copy_count -= partial_count;
4740                                 if (++i == info->rbuf_count)
4741                                         i = 0;
4742                         }
4743
4744                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4745                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4746                                 framesize++;
4747                         }
4748
4749 #if SYNCLINK_GENERIC_HDLC
4750                         if (info->netcount)
4751                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4752                         else
4753 #endif
4754                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4755                 }
4756         }
4757         free_rbufs(info, start, end);
4758         return true;
4759
4760 cleanup:
4761         return false;
4762 }
4763
4764 /*
4765  * pass receive buffer (RAW synchronous mode) to tty layer
4766  * return true if buffer available, otherwise false
4767  */
4768 static bool rx_get_buf(struct slgt_info *info)
4769 {
4770         unsigned int i = info->rbuf_current;
4771         unsigned int count;
4772
4773         if (!desc_complete(info->rbufs[i]))
4774                 return false;
4775         count = desc_count(info->rbufs[i]);
4776         switch(info->params.mode) {
4777         case MGSL_MODE_MONOSYNC:
4778         case MGSL_MODE_BISYNC:
4779         case MGSL_MODE_XSYNC:
4780                 /* ignore residue in byte synchronous modes */
4781                 if (desc_residue(info->rbufs[i]))
4782                         count--;
4783                 break;
4784         }
4785         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4786         DBGINFO(("rx_get_buf size=%d\n", count));
4787         if (count)
4788                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4789                                   info->flag_buf, count);
4790         free_rbufs(info, i, i);
4791         return true;
4792 }
4793
4794 static void reset_tbufs(struct slgt_info *info)
4795 {
4796         unsigned int i;
4797         info->tbuf_current = 0;
4798         for (i=0 ; i < info->tbuf_count ; i++) {
4799                 info->tbufs[i].status = 0;
4800                 info->tbufs[i].count  = 0;
4801         }
4802 }
4803
4804 /*
4805  * return number of free transmit DMA buffers
4806  */
4807 static unsigned int free_tbuf_count(struct slgt_info *info)
4808 {
4809         unsigned int count = 0;
4810         unsigned int i = info->tbuf_current;
4811
4812         do
4813         {
4814                 if (desc_count(info->tbufs[i]))
4815                         break; /* buffer in use */
4816                 ++count;
4817                 if (++i == info->tbuf_count)
4818                         i=0;
4819         } while (i != info->tbuf_current);
4820
4821         /* if tx DMA active, last zero count buffer is in use */
4822         if (count && (rd_reg32(info, TDCSR) & BIT0))
4823                 --count;
4824
4825         return count;
4826 }
4827
4828 /*
4829  * return number of bytes in unsent transmit DMA buffers
4830  * and the serial controller tx FIFO
4831  */
4832 static unsigned int tbuf_bytes(struct slgt_info *info)
4833 {
4834         unsigned int total_count = 0;
4835         unsigned int i = info->tbuf_current;
4836         unsigned int reg_value;
4837         unsigned int count;
4838         unsigned int active_buf_count = 0;
4839
4840         /*
4841          * Add descriptor counts for all tx DMA buffers.
4842          * If count is zero (cleared by DMA controller after read),
4843          * the buffer is complete or is actively being read from.
4844          *
4845          * Record buf_count of last buffer with zero count starting
4846          * from current ring position. buf_count is mirror
4847          * copy of count and is not cleared by serial controller.
4848          * If DMA controller is active, that buffer is actively
4849          * being read so add to total.
4850          */
4851         do {
4852                 count = desc_count(info->tbufs[i]);
4853                 if (count)
4854                         total_count += count;
4855                 else if (!total_count)
4856                         active_buf_count = info->tbufs[i].buf_count;
4857                 if (++i == info->tbuf_count)
4858                         i = 0;
4859         } while (i != info->tbuf_current);
4860
4861         /* read tx DMA status register */
4862         reg_value = rd_reg32(info, TDCSR);
4863
4864         /* if tx DMA active, last zero count buffer is in use */
4865         if (reg_value & BIT0)
4866                 total_count += active_buf_count;
4867
4868         /* add tx FIFO count = reg_value[15..8] */
4869         total_count += (reg_value >> 8) & 0xff;
4870
4871         /* if transmitter active add one byte for shift register */
4872         if (info->tx_active)
4873                 total_count++;
4874
4875         return total_count;
4876 }
4877
4878 /*
4879  * load data into transmit DMA buffer ring and start transmitter if needed
4880  * return true if data accepted, otherwise false (buffers full)
4881  */
4882 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4883 {
4884         unsigned short count;
4885         unsigned int i;
4886         struct slgt_desc *d;
4887
4888         /* check required buffer space */
4889         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4890                 return false;
4891
4892         DBGDATA(info, buf, size, "tx");
4893
4894         /*
4895          * copy data to one or more DMA buffers in circular ring
4896          * tbuf_start   = first buffer for this data
4897          * tbuf_current = next free buffer
4898          *
4899          * Copy all data before making data visible to DMA controller by
4900          * setting descriptor count of the first buffer.
4901          * This prevents an active DMA controller from reading the first DMA
4902          * buffers of a frame and stopping before the final buffers are filled.
4903          */
4904
4905         info->tbuf_start = i = info->tbuf_current;
4906
4907         while (size) {
4908                 d = &info->tbufs[i];
4909
4910                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4911                 memcpy(d->buf, buf, count);
4912
4913                 size -= count;
4914                 buf  += count;
4915
4916                 /*
4917                  * set EOF bit for last buffer of HDLC frame or
4918                  * for every buffer in raw mode
4919                  */
4920                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4921                     info->params.mode == MGSL_MODE_RAW)
4922                         set_desc_eof(*d, 1);
4923                 else
4924                         set_desc_eof(*d, 0);
4925
4926                 /* set descriptor count for all but first buffer */
4927                 if (i != info->tbuf_start)
4928                         set_desc_count(*d, count);
4929                 d->buf_count = count;
4930
4931                 if (++i == info->tbuf_count)
4932                         i = 0;
4933         }
4934
4935         info->tbuf_current = i;
4936
4937         /* set first buffer count to make new data visible to DMA controller */
4938         d = &info->tbufs[info->tbuf_start];
4939         set_desc_count(*d, d->buf_count);
4940
4941         /* start transmitter if needed and update transmit timeout */
4942         if (!info->tx_active)
4943                 tx_start(info);
4944         update_tx_timer(info);
4945
4946         return true;
4947 }
4948
4949 static int register_test(struct slgt_info *info)
4950 {
4951         static unsigned short patterns[] =
4952                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4953         static unsigned int count = ARRAY_SIZE(patterns);
4954         unsigned int i;
4955         int rc = 0;
4956
4957         for (i=0 ; i < count ; i++) {
4958                 wr_reg16(info, TIR, patterns[i]);
4959                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4960                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4961                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4962                         rc = -ENODEV;
4963                         break;
4964                 }
4965         }
4966         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4967         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4968         return rc;
4969 }
4970
4971 static int irq_test(struct slgt_info *info)
4972 {
4973         unsigned long timeout;
4974         unsigned long flags;
4975         struct tty_struct *oldtty = info->port.tty;
4976         u32 speed = info->params.data_rate;
4977
4978         info->params.data_rate = 921600;
4979         info->port.tty = NULL;
4980
4981         spin_lock_irqsave(&info->lock, flags);
4982         async_mode(info);
4983         slgt_irq_on(info, IRQ_TXIDLE);
4984
4985         /* enable transmitter */
4986         wr_reg16(info, TCR,
4987                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4988
4989         /* write one byte and wait for tx idle */
4990         wr_reg16(info, TDR, 0);
4991
4992         /* assume failure */
4993         info->init_error = DiagStatus_IrqFailure;
4994         info->irq_occurred = false;
4995
4996         spin_unlock_irqrestore(&info->lock, flags);
4997
4998         timeout=100;
4999         while(timeout-- && !info->irq_occurred)
5000                 msleep_interruptible(10);
5001
5002         spin_lock_irqsave(&info->lock,flags);
5003         reset_port(info);
5004         spin_unlock_irqrestore(&info->lock,flags);
5005
5006         info->params.data_rate = speed;
5007         info->port.tty = oldtty;
5008
5009         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5010         return info->irq_occurred ? 0 : -ENODEV;
5011 }
5012
5013 static int loopback_test_rx(struct slgt_info *info)
5014 {
5015         unsigned char *src, *dest;
5016         int count;
5017
5018         if (desc_complete(info->rbufs[0])) {
5019                 count = desc_count(info->rbufs[0]);
5020                 src   = info->rbufs[0].buf;
5021                 dest  = info->tmp_rbuf;
5022
5023                 for( ; count ; count-=2, src+=2) {
5024                         /* src=data byte (src+1)=status byte */
5025                         if (!(*(src+1) & (BIT9 + BIT8))) {
5026                                 *dest = *src;
5027                                 dest++;
5028                                 info->tmp_rbuf_count++;
5029                         }
5030                 }
5031                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5032                 return 1;
5033         }
5034         return 0;
5035 }
5036
5037 static int loopback_test(struct slgt_info *info)
5038 {
5039 #define TESTFRAMESIZE 20
5040
5041         unsigned long timeout;
5042         u16 count = TESTFRAMESIZE;
5043         unsigned char buf[TESTFRAMESIZE];
5044         int rc = -ENODEV;
5045         unsigned long flags;
5046
5047         struct tty_struct *oldtty = info->port.tty;
5048         MGSL_PARAMS params;
5049
5050         memcpy(&params, &info->params, sizeof(params));
5051
5052         info->params.mode = MGSL_MODE_ASYNC;
5053         info->params.data_rate = 921600;
5054         info->params.loopback = 1;
5055         info->port.tty = NULL;
5056
5057         /* build and send transmit frame */
5058         for (count = 0; count < TESTFRAMESIZE; ++count)
5059                 buf[count] = (unsigned char)count;
5060
5061         info->tmp_rbuf_count = 0;
5062         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5063
5064         /* program hardware for HDLC and enabled receiver */
5065         spin_lock_irqsave(&info->lock,flags);
5066         async_mode(info);
5067         rx_start(info);
5068         tx_load(info, buf, count);
5069         spin_unlock_irqrestore(&info->lock, flags);
5070
5071         /* wait for receive complete */
5072         for (timeout = 100; timeout; --timeout) {
5073                 msleep_interruptible(10);
5074                 if (loopback_test_rx(info)) {
5075                         rc = 0;
5076                         break;
5077                 }
5078         }
5079
5080         /* verify received frame length and contents */
5081         if (!rc && (info->tmp_rbuf_count != count ||
5082                   memcmp(buf, info->tmp_rbuf, count))) {
5083                 rc = -ENODEV;
5084         }
5085
5086         spin_lock_irqsave(&info->lock,flags);
5087         reset_adapter(info);
5088         spin_unlock_irqrestore(&info->lock,flags);
5089
5090         memcpy(&info->params, &params, sizeof(info->params));
5091         info->port.tty = oldtty;
5092
5093         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5094         return rc;
5095 }
5096
5097 static int adapter_test(struct slgt_info *info)
5098 {
5099         DBGINFO(("testing %s\n", info->device_name));
5100         if (register_test(info) < 0) {
5101                 printk("register test failure %s addr=%08X\n",
5102                         info->device_name, info->phys_reg_addr);
5103         } else if (irq_test(info) < 0) {
5104                 printk("IRQ test failure %s IRQ=%d\n",
5105                         info->device_name, info->irq_level);
5106         } else if (loopback_test(info) < 0) {
5107                 printk("loopback test failure %s\n", info->device_name);
5108         }
5109         return info->init_error;
5110 }
5111
5112 /*
5113  * transmit timeout handler
5114  */
5115 static void tx_timeout(struct timer_list *t)
5116 {
5117         struct slgt_info *info = from_timer(info, t, tx_timer);
5118         unsigned long flags;
5119
5120         DBGINFO(("%s tx_timeout\n", info->device_name));
5121         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5122                 info->icount.txtimeout++;
5123         }
5124         spin_lock_irqsave(&info->lock,flags);
5125         tx_stop(info);
5126         spin_unlock_irqrestore(&info->lock,flags);
5127
5128 #if SYNCLINK_GENERIC_HDLC
5129         if (info->netcount)
5130                 hdlcdev_tx_done(info);
5131         else
5132 #endif
5133                 bh_transmit(info);
5134 }
5135
5136 /*
5137  * receive buffer polling timer
5138  */
5139 static void rx_timeout(struct timer_list *t)
5140 {
5141         struct slgt_info *info = from_timer(info, t, rx_timer);
5142         unsigned long flags;
5143
5144         DBGINFO(("%s rx_timeout\n", info->device_name));
5145         spin_lock_irqsave(&info->lock, flags);
5146         info->pending_bh |= BH_RECEIVE;
5147         spin_unlock_irqrestore(&info->lock, flags);
5148         bh_handler(&info->task);
5149 }
5150