1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * 2011 - 2014 (C) Xilinx Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/iopoll.h>
31 #define CDNS_UART_TTY_NAME "ttyPS"
32 #define CDNS_UART_NAME "xuartps"
33 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34 #define CDNS_UART_REGISTER_SPACE 0x1000
35 #define TX_TIMEOUT 500000
37 /* Rx Trigger level */
38 static int rx_trigger_level = 56;
39 static int uartps_major;
40 module_param(rx_trigger_level, uint, 0444);
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
44 static int rx_timeout = 10;
45 module_param(rx_timeout, uint, 0444);
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
48 /* Register offsets for the UART. */
49 #define CDNS_UART_CR 0x00 /* Control Register */
50 #define CDNS_UART_MR 0x04 /* Mode Register */
51 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
52 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
55 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60 #define CDNS_UART_SR 0x2C /* Channel Status */
61 #define CDNS_UART_FIFO 0x30 /* FIFO */
62 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
69 /* Control Register Bit Definitions */
70 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
94 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
97 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
103 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
118 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
142 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
148 #define CDNS_UART_IXR_BRK 0x00002000
150 #define CDNS_UART_RXBS_SUPPORT BIT(1)
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
156 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
166 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
170 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
172 /* baud dividers min/max values */
173 #define CDNS_UART_BDIV_MIN 4
174 #define CDNS_UART_BDIV_MAX 255
175 #define CDNS_UART_CD_MAX 65535
176 #define UART_AUTOSUSPEND_TIMEOUT 3000
179 * struct cdns_uart - device data
180 * @port: Pointer to the UART port
181 * @uartclk: Reference clock
183 * @cdns_uart_driver: Pointer to UART driver
184 * @baud: Current baud rate
186 * @clk_rate_change_nb: Notifier block for clock changes
187 * @quirks: Flags for RXBS support.
190 struct uart_port *port;
193 struct uart_driver *cdns_uart_driver;
196 struct notifier_block clk_rate_change_nb;
200 struct cdns_platform_data {
203 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
207 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
208 * @dev_id: Id of the UART port
209 * @isrstatus: The interrupt status register value as read
212 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
214 struct uart_port *port = (struct uart_port *)dev_id;
215 struct cdns_uart *cdns_uart = port->private_data;
217 unsigned int rxbs_status = 0;
218 unsigned int status_mask;
219 unsigned int framerrprocessed = 0;
220 char status = TTY_NORMAL;
221 bool is_rxbs_support;
223 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
225 while ((readl(port->membase + CDNS_UART_SR) &
226 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
228 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
229 data = readl(port->membase + CDNS_UART_FIFO);
232 * There is no hardware break detection in Zynq, so we interpret
233 * framing error with all-zeros data as a break sequence.
234 * Most of the time, there's another non-zero byte at the
235 * end of the sequence.
237 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
239 port->read_status_mask |= CDNS_UART_IXR_BRK;
240 framerrprocessed = 1;
244 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
247 if (uart_handle_break(port))
251 isrstatus &= port->read_status_mask;
252 isrstatus &= ~port->ignore_status_mask;
253 status_mask = port->read_status_mask;
254 status_mask &= ~port->ignore_status_mask;
257 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
258 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
260 if (uart_handle_break(port))
264 if (uart_handle_sysrq_char(port, data))
267 if (is_rxbs_support) {
268 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
269 && (status_mask & CDNS_UART_IXR_PARITY)) {
270 port->icount.parity++;
273 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
274 && (status_mask & CDNS_UART_IXR_PARITY)) {
275 port->icount.frame++;
279 if (isrstatus & CDNS_UART_IXR_PARITY) {
280 port->icount.parity++;
283 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
285 port->icount.frame++;
289 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
290 port->icount.overrun++;
291 tty_insert_flip_char(&port->state->port, 0,
294 tty_insert_flip_char(&port->state->port, data, status);
297 spin_unlock(&port->lock);
298 tty_flip_buffer_push(&port->state->port);
299 spin_lock(&port->lock);
303 * cdns_uart_handle_tx - Handle the bytes to be Txed.
304 * @dev_id: Id of the UART port
307 static void cdns_uart_handle_tx(void *dev_id)
309 struct uart_port *port = (struct uart_port *)dev_id;
310 unsigned int numbytes;
312 if (uart_circ_empty(&port->state->xmit)) {
313 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
315 numbytes = port->fifosize;
316 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
317 !(readl(port->membase + CDNS_UART_SR) &
318 CDNS_UART_SR_TXFULL)) {
320 * Get the data from the UART circular buffer
321 * and write it to the cdns_uart's TX_FIFO
325 port->state->xmit.buf[port->state->xmit.tail],
326 port->membase + CDNS_UART_FIFO);
331 * Adjust the tail of the UART buffer and wrap
332 * the buffer if it reaches limit.
334 port->state->xmit.tail =
335 (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
341 if (uart_circ_chars_pending(
342 &port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
348 * cdns_uart_isr - Interrupt handler
350 * @dev_id: Id of the port
354 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
356 struct uart_port *port = (struct uart_port *)dev_id;
357 unsigned int isrstatus;
359 spin_lock(&port->lock);
361 /* Read the interrupt status register to determine which
362 * interrupt(s) is/are active and clear them.
364 isrstatus = readl(port->membase + CDNS_UART_ISR);
365 writel(isrstatus, port->membase + CDNS_UART_ISR);
367 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
368 cdns_uart_handle_tx(dev_id);
369 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
373 * Skip RX processing if RX is disabled as RXEMPTY will never be set
374 * as read bytes will not be removed from the FIFO.
376 if (isrstatus & CDNS_UART_IXR_RXMASK &&
377 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
378 cdns_uart_handle_rx(dev_id, isrstatus);
380 spin_unlock(&port->lock);
385 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
386 * @clk: UART module input clock
387 * @baud: Desired baud rate
388 * @rbdiv: BDIV value (return value)
389 * @rcd: CD value (return value)
390 * @div8: Value for clk_sel bit in mod (return value)
391 * Return: baud rate, requested baud when possible, or actual baud when there
392 * was too much error, zero if no valid divisors are found.
394 * Formula to obtain baud rate is
395 * baud_tx/rx rate = clk/CD * (BDIV + 1)
396 * input_clk = (Uart User Defined Clock or Apb Clock)
397 * depends on UCLKEN in MR Reg
398 * clk = input_clk or input_clk/8;
399 * depends on CLKS in MR reg
400 * CD and BDIV depends on values in
401 * baud rate generate register
402 * baud rate clock divisor register
404 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
405 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
408 unsigned int calc_baud;
409 unsigned int bestbaud = 0;
410 unsigned int bauderror;
411 unsigned int besterror = ~0;
413 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
420 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
421 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
422 if (cd < 1 || cd > CDNS_UART_CD_MAX)
425 calc_baud = clk / (cd * (bdiv + 1));
427 if (baud > calc_baud)
428 bauderror = baud - calc_baud;
430 bauderror = calc_baud - baud;
432 if (besterror > bauderror) {
435 bestbaud = calc_baud;
436 besterror = bauderror;
439 /* use the values when percent error is acceptable */
440 if (((besterror * 100) / baud) < 3)
447 * cdns_uart_set_baud_rate - Calculate and set the baud rate
448 * @port: Handle to the uart port structure
449 * @baud: Baud rate to set
450 * Return: baud rate, requested baud when possible, or actual baud when there
451 * was too much error, zero if no valid divisors are found.
453 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
456 unsigned int calc_baud;
457 u32 cd = 0, bdiv = 0;
460 struct cdns_uart *cdns_uart = port->private_data;
462 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
465 /* Write new divisors to hardware */
466 mreg = readl(port->membase + CDNS_UART_MR);
468 mreg |= CDNS_UART_MR_CLKSEL;
470 mreg &= ~CDNS_UART_MR_CLKSEL;
471 writel(mreg, port->membase + CDNS_UART_MR);
472 writel(cd, port->membase + CDNS_UART_BAUDGEN);
473 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
474 cdns_uart->baud = baud;
479 #ifdef CONFIG_COMMON_CLK
481 * cdns_uart_clk_notitifer_cb - Clock notifier callback
482 * @nb: Notifier block
483 * @event: Notify event
484 * @data: Notifier data
485 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
487 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
488 unsigned long event, void *data)
491 struct uart_port *port;
493 struct clk_notifier_data *ndata = data;
494 unsigned long flags = 0;
495 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
497 port = cdns_uart->port;
502 case PRE_RATE_CHANGE:
508 * Find out if current baud-rate can be achieved with new clock
511 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
512 &bdiv, &cd, &div8)) {
513 dev_warn(port->dev, "clock rate change rejected\n");
517 spin_lock_irqsave(&cdns_uart->port->lock, flags);
519 /* Disable the TX and RX to set baud rate */
520 ctrl_reg = readl(port->membase + CDNS_UART_CR);
521 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
522 writel(ctrl_reg, port->membase + CDNS_UART_CR);
524 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
528 case POST_RATE_CHANGE:
530 * Set clk dividers to generate correct baud with new clock
534 spin_lock_irqsave(&cdns_uart->port->lock, flags);
537 port->uartclk = ndata->new_rate;
539 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
542 case ABORT_RATE_CHANGE:
544 spin_lock_irqsave(&cdns_uart->port->lock, flags);
546 /* Set TX/RX Reset */
547 ctrl_reg = readl(port->membase + CDNS_UART_CR);
548 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
549 writel(ctrl_reg, port->membase + CDNS_UART_CR);
551 while (readl(port->membase + CDNS_UART_CR) &
552 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
556 * Clear the RX disable and TX disable bits and then set the TX
557 * enable bit and RX enable bit to enable the transmitter and
560 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
561 ctrl_reg = readl(port->membase + CDNS_UART_CR);
562 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
563 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
564 writel(ctrl_reg, port->membase + CDNS_UART_CR);
566 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
576 * cdns_uart_start_tx - Start transmitting bytes
577 * @port: Handle to the uart port structure
579 static void cdns_uart_start_tx(struct uart_port *port)
583 if (uart_tx_stopped(port))
587 * Set the TX enable bit and clear the TX disable bit to enable the
590 status = readl(port->membase + CDNS_UART_CR);
591 status &= ~CDNS_UART_CR_TX_DIS;
592 status |= CDNS_UART_CR_TX_EN;
593 writel(status, port->membase + CDNS_UART_CR);
595 if (uart_circ_empty(&port->state->xmit))
598 cdns_uart_handle_tx(port);
600 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
601 /* Enable the TX Empty interrupt */
602 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
606 * cdns_uart_stop_tx - Stop TX
607 * @port: Handle to the uart port structure
609 static void cdns_uart_stop_tx(struct uart_port *port)
613 regval = readl(port->membase + CDNS_UART_CR);
614 regval |= CDNS_UART_CR_TX_DIS;
615 /* Disable the transmitter */
616 writel(regval, port->membase + CDNS_UART_CR);
620 * cdns_uart_stop_rx - Stop RX
621 * @port: Handle to the uart port structure
623 static void cdns_uart_stop_rx(struct uart_port *port)
627 /* Disable RX IRQs */
628 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
630 /* Disable the receiver */
631 regval = readl(port->membase + CDNS_UART_CR);
632 regval |= CDNS_UART_CR_RX_DIS;
633 writel(regval, port->membase + CDNS_UART_CR);
637 * cdns_uart_tx_empty - Check whether TX is empty
638 * @port: Handle to the uart port structure
640 * Return: TIOCSER_TEMT on success, 0 otherwise
642 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
646 status = readl(port->membase + CDNS_UART_SR) &
647 CDNS_UART_SR_TXEMPTY;
648 return status ? TIOCSER_TEMT : 0;
652 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
653 * transmitting char breaks
654 * @port: Handle to the uart port structure
655 * @ctl: Value based on which start or stop decision is taken
657 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
662 spin_lock_irqsave(&port->lock, flags);
664 status = readl(port->membase + CDNS_UART_CR);
667 writel(CDNS_UART_CR_STARTBRK | status,
668 port->membase + CDNS_UART_CR);
670 if ((status & CDNS_UART_CR_STOPBRK) == 0)
671 writel(CDNS_UART_CR_STOPBRK | status,
672 port->membase + CDNS_UART_CR);
674 spin_unlock_irqrestore(&port->lock, flags);
678 * cdns_uart_set_termios - termios operations, handling data length, parity,
679 * stop bits, flow control, baud rate
680 * @port: Handle to the uart port structure
681 * @termios: Handle to the input termios structure
682 * @old: Values of the previously saved termios structure
684 static void cdns_uart_set_termios(struct uart_port *port,
685 struct ktermios *termios, struct ktermios *old)
687 unsigned int cval = 0;
688 unsigned int baud, minbaud, maxbaud;
690 unsigned int ctrl_reg, mode_reg, val;
693 /* Wait for the transmit FIFO to empty before making changes */
694 if (!(readl(port->membase + CDNS_UART_CR) &
695 CDNS_UART_CR_TX_DIS)) {
696 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
697 val, (val & CDNS_UART_SR_TXEMPTY),
700 dev_err(port->dev, "timed out waiting for tx empty");
704 spin_lock_irqsave(&port->lock, flags);
706 /* Disable the TX and RX to set baud rate */
707 ctrl_reg = readl(port->membase + CDNS_UART_CR);
708 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
709 writel(ctrl_reg, port->membase + CDNS_UART_CR);
712 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
713 * min and max baud should be calculated here based on port->uartclk.
714 * this way we get a valid baud and can safely call set_baud()
716 minbaud = port->uartclk /
717 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
718 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
719 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
720 baud = cdns_uart_set_baud_rate(port, baud);
721 if (tty_termios_baud_rate(termios))
722 tty_termios_encode_baud_rate(termios, baud, baud);
724 /* Update the per-port timeout. */
725 uart_update_timeout(port, termios->c_cflag, baud);
727 /* Set TX/RX Reset */
728 ctrl_reg = readl(port->membase + CDNS_UART_CR);
729 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
730 writel(ctrl_reg, port->membase + CDNS_UART_CR);
732 while (readl(port->membase + CDNS_UART_CR) &
733 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
737 * Clear the RX disable and TX disable bits and then set the TX enable
738 * bit and RX enable bit to enable the transmitter and receiver.
740 ctrl_reg = readl(port->membase + CDNS_UART_CR);
741 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
742 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
743 writel(ctrl_reg, port->membase + CDNS_UART_CR);
745 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
747 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
748 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
749 port->ignore_status_mask = 0;
751 if (termios->c_iflag & INPCK)
752 port->read_status_mask |= CDNS_UART_IXR_PARITY |
753 CDNS_UART_IXR_FRAMING;
755 if (termios->c_iflag & IGNPAR)
756 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
757 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
759 /* ignore all characters if CREAD is not set */
760 if ((termios->c_cflag & CREAD) == 0)
761 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
762 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
763 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
765 mode_reg = readl(port->membase + CDNS_UART_MR);
767 /* Handling Data Size */
768 switch (termios->c_cflag & CSIZE) {
770 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
773 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
777 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
778 termios->c_cflag &= ~CSIZE;
779 termios->c_cflag |= CS8;
783 /* Handling Parity and Stop Bits length */
784 if (termios->c_cflag & CSTOPB)
785 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
787 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
789 if (termios->c_cflag & PARENB) {
790 /* Mark or Space parity */
791 if (termios->c_cflag & CMSPAR) {
792 if (termios->c_cflag & PARODD)
793 cval |= CDNS_UART_MR_PARITY_MARK;
795 cval |= CDNS_UART_MR_PARITY_SPACE;
797 if (termios->c_cflag & PARODD)
798 cval |= CDNS_UART_MR_PARITY_ODD;
800 cval |= CDNS_UART_MR_PARITY_EVEN;
803 cval |= CDNS_UART_MR_PARITY_NONE;
805 cval |= mode_reg & 1;
806 writel(cval, port->membase + CDNS_UART_MR);
808 spin_unlock_irqrestore(&port->lock, flags);
812 * cdns_uart_startup - Called when an application opens a cdns_uart port
813 * @port: Handle to the uart port structure
815 * Return: 0 on success, negative errno otherwise
817 static int cdns_uart_startup(struct uart_port *port)
819 struct cdns_uart *cdns_uart = port->private_data;
823 unsigned int status = 0;
825 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
827 spin_lock_irqsave(&port->lock, flags);
829 /* Disable the TX and RX */
830 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
831 port->membase + CDNS_UART_CR);
833 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
836 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
837 port->membase + CDNS_UART_CR);
839 while (readl(port->membase + CDNS_UART_CR) &
840 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
844 * Clear the RX disable bit and then set the RX enable bit to enable
847 status = readl(port->membase + CDNS_UART_CR);
848 status &= ~CDNS_UART_CR_RX_DIS;
849 status |= CDNS_UART_CR_RX_EN;
850 writel(status, port->membase + CDNS_UART_CR);
852 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
855 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
856 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
857 port->membase + CDNS_UART_MR);
860 * Set the RX FIFO Trigger level to use most of the FIFO, but it
861 * can be tuned with a module parameter
863 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
866 * Receive Timeout register is enabled but it
867 * can be tuned with a module parameter
869 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
871 /* Clear out any pending interrupts before enabling them */
872 writel(readl(port->membase + CDNS_UART_ISR),
873 port->membase + CDNS_UART_ISR);
875 spin_unlock_irqrestore(&port->lock, flags);
877 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
879 dev_err(port->dev, "request_irq '%d' failed with %d\n",
884 /* Set the Interrupt Registers with desired interrupts */
886 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
887 port->membase + CDNS_UART_IER);
889 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
895 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
896 * @port: Handle to the uart port structure
898 static void cdns_uart_shutdown(struct uart_port *port)
903 spin_lock_irqsave(&port->lock, flags);
905 /* Disable interrupts */
906 status = readl(port->membase + CDNS_UART_IMR);
907 writel(status, port->membase + CDNS_UART_IDR);
908 writel(0xffffffff, port->membase + CDNS_UART_ISR);
910 /* Disable the TX and RX */
911 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
912 port->membase + CDNS_UART_CR);
914 spin_unlock_irqrestore(&port->lock, flags);
916 free_irq(port->irq, port);
920 * cdns_uart_type - Set UART type to cdns_uart port
921 * @port: Handle to the uart port structure
923 * Return: string on success, NULL otherwise
925 static const char *cdns_uart_type(struct uart_port *port)
927 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
931 * cdns_uart_verify_port - Verify the port params
932 * @port: Handle to the uart port structure
933 * @ser: Handle to the structure whose members are compared
935 * Return: 0 on success, negative errno otherwise.
937 static int cdns_uart_verify_port(struct uart_port *port,
938 struct serial_struct *ser)
940 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
942 if (port->irq != ser->irq)
944 if (ser->io_type != UPIO_MEM)
946 if (port->iobase != ser->port)
954 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
955 * called when the driver adds a cdns_uart port via
956 * uart_add_one_port()
957 * @port: Handle to the uart port structure
959 * Return: 0 on success, negative errno otherwise.
961 static int cdns_uart_request_port(struct uart_port *port)
963 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
968 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
969 if (!port->membase) {
970 dev_err(port->dev, "Unable to map registers\n");
971 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
978 * cdns_uart_release_port - Release UART port
979 * @port: Handle to the uart port structure
981 * Release the memory region attached to a cdns_uart port. Called when the
982 * driver removes a cdns_uart port via uart_remove_one_port().
984 static void cdns_uart_release_port(struct uart_port *port)
986 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
987 iounmap(port->membase);
988 port->membase = NULL;
992 * cdns_uart_config_port - Configure UART port
993 * @port: Handle to the uart port structure
996 static void cdns_uart_config_port(struct uart_port *port, int flags)
998 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
999 port->type = PORT_XUARTPS;
1003 * cdns_uart_get_mctrl - Get the modem control state
1004 * @port: Handle to the uart port structure
1006 * Return: the modem control state
1008 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1010 struct cdns_uart *cdns_uart_data = port->private_data;
1012 if (cdns_uart_data->cts_override)
1015 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1018 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1022 struct cdns_uart *cdns_uart_data = port->private_data;
1024 if (cdns_uart_data->cts_override)
1027 val = readl(port->membase + CDNS_UART_MODEMCR);
1028 mode_reg = readl(port->membase + CDNS_UART_MR);
1030 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1031 CDNS_UART_MODEMCR_FCM);
1032 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1034 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1035 val |= CDNS_UART_MODEMCR_FCM;
1036 if (mctrl & TIOCM_LOOP)
1037 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1039 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1041 writel(val, port->membase + CDNS_UART_MODEMCR);
1042 writel(mode_reg, port->membase + CDNS_UART_MR);
1045 #ifdef CONFIG_CONSOLE_POLL
1046 static int cdns_uart_poll_get_char(struct uart_port *port)
1049 unsigned long flags;
1051 spin_lock_irqsave(&port->lock, flags);
1053 /* Check if FIFO is empty */
1054 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1056 else /* Read a character */
1057 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1059 spin_unlock_irqrestore(&port->lock, flags);
1064 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1066 unsigned long flags;
1068 spin_lock_irqsave(&port->lock, flags);
1070 /* Wait until FIFO is empty */
1071 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1074 /* Write a character */
1075 writel(c, port->membase + CDNS_UART_FIFO);
1077 /* Wait until FIFO is empty */
1078 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1081 spin_unlock_irqrestore(&port->lock, flags);
1085 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1086 unsigned int oldstate)
1089 case UART_PM_STATE_OFF:
1090 pm_runtime_mark_last_busy(port->dev);
1091 pm_runtime_put_autosuspend(port->dev);
1094 pm_runtime_get_sync(port->dev);
1099 static const struct uart_ops cdns_uart_ops = {
1100 .set_mctrl = cdns_uart_set_mctrl,
1101 .get_mctrl = cdns_uart_get_mctrl,
1102 .start_tx = cdns_uart_start_tx,
1103 .stop_tx = cdns_uart_stop_tx,
1104 .stop_rx = cdns_uart_stop_rx,
1105 .tx_empty = cdns_uart_tx_empty,
1106 .break_ctl = cdns_uart_break_ctl,
1107 .set_termios = cdns_uart_set_termios,
1108 .startup = cdns_uart_startup,
1109 .shutdown = cdns_uart_shutdown,
1111 .type = cdns_uart_type,
1112 .verify_port = cdns_uart_verify_port,
1113 .request_port = cdns_uart_request_port,
1114 .release_port = cdns_uart_release_port,
1115 .config_port = cdns_uart_config_port,
1116 #ifdef CONFIG_CONSOLE_POLL
1117 .poll_get_char = cdns_uart_poll_get_char,
1118 .poll_put_char = cdns_uart_poll_put_char,
1122 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1124 * cdns_uart_console_putchar - write the character to the FIFO buffer
1125 * @port: Handle to the uart port structure
1126 * @ch: Character to be written
1128 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1130 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1132 writel(ch, port->membase + CDNS_UART_FIFO);
1135 static void cdns_early_write(struct console *con, const char *s,
1138 struct earlycon_device *dev = con->data;
1140 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1143 static int __init cdns_early_console_setup(struct earlycon_device *device,
1146 struct uart_port *port = &device->port;
1151 /* initialise control register */
1152 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1153 port->membase + CDNS_UART_CR);
1155 /* only set baud if specified on command line - otherwise
1156 * assume it has been initialized by a boot loader.
1158 if (port->uartclk && device->baud) {
1159 u32 cd = 0, bdiv = 0;
1163 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1165 mr = CDNS_UART_MR_PARITY_NONE;
1167 mr |= CDNS_UART_MR_CLKSEL;
1169 writel(mr, port->membase + CDNS_UART_MR);
1170 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1171 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1174 device->con->write = cdns_early_write;
1178 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1179 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1180 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1181 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1184 /* Static pointer to console port */
1185 static struct uart_port *console_port;
1188 * cdns_uart_console_write - perform write operation
1189 * @co: Console handle
1190 * @s: Pointer to character array
1191 * @count: No of characters
1193 static void cdns_uart_console_write(struct console *co, const char *s,
1196 struct uart_port *port = console_port;
1197 unsigned long flags = 0;
1198 unsigned int imr, ctrl;
1203 else if (oops_in_progress)
1204 locked = spin_trylock_irqsave(&port->lock, flags);
1206 spin_lock_irqsave(&port->lock, flags);
1208 /* save and disable interrupt */
1209 imr = readl(port->membase + CDNS_UART_IMR);
1210 writel(imr, port->membase + CDNS_UART_IDR);
1213 * Make sure that the tx part is enabled. Set the TX enable bit and
1214 * clear the TX disable bit to enable the transmitter.
1216 ctrl = readl(port->membase + CDNS_UART_CR);
1217 ctrl &= ~CDNS_UART_CR_TX_DIS;
1218 ctrl |= CDNS_UART_CR_TX_EN;
1219 writel(ctrl, port->membase + CDNS_UART_CR);
1221 uart_console_write(port, s, count, cdns_uart_console_putchar);
1222 while ((readl(port->membase + CDNS_UART_SR) &
1223 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1224 CDNS_UART_SR_TXEMPTY)
1227 /* restore interrupt state */
1228 writel(imr, port->membase + CDNS_UART_IER);
1231 spin_unlock_irqrestore(&port->lock, flags);
1235 * cdns_uart_console_setup - Initialize the uart to default config
1236 * @co: Console handle
1237 * @options: Initial settings of uart
1239 * Return: 0 on success, negative errno otherwise.
1241 static int cdns_uart_console_setup(struct console *co, char *options)
1243 struct uart_port *port = console_port;
1250 if (!port->membase) {
1251 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1257 uart_parse_options(options, &baud, &parity, &bits, &flow);
1259 return uart_set_options(port, co, baud, parity, bits, flow);
1261 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1263 #ifdef CONFIG_PM_SLEEP
1265 * cdns_uart_suspend - suspend event
1266 * @device: Pointer to the device structure
1270 static int cdns_uart_suspend(struct device *device)
1272 struct uart_port *port = dev_get_drvdata(device);
1273 struct cdns_uart *cdns_uart = port->private_data;
1276 may_wake = device_may_wakeup(device);
1278 if (console_suspend_enabled && uart_console(port) && may_wake) {
1279 unsigned long flags = 0;
1281 spin_lock_irqsave(&port->lock, flags);
1282 /* Empty the receive FIFO 1st before making changes */
1283 while (!(readl(port->membase + CDNS_UART_SR) &
1284 CDNS_UART_SR_RXEMPTY))
1285 readl(port->membase + CDNS_UART_FIFO);
1286 /* set RX trigger level to 1 */
1287 writel(1, port->membase + CDNS_UART_RXWM);
1288 /* disable RX timeout interrups */
1289 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1290 spin_unlock_irqrestore(&port->lock, flags);
1294 * Call the API provided in serial_core.c file which handles
1297 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1301 * cdns_uart_resume - Resume after a previous suspend
1302 * @device: Pointer to the device structure
1306 static int cdns_uart_resume(struct device *device)
1308 struct uart_port *port = dev_get_drvdata(device);
1309 struct cdns_uart *cdns_uart = port->private_data;
1310 unsigned long flags = 0;
1314 may_wake = device_may_wakeup(device);
1316 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1317 clk_enable(cdns_uart->pclk);
1318 clk_enable(cdns_uart->uartclk);
1320 spin_lock_irqsave(&port->lock, flags);
1322 /* Set TX/RX Reset */
1323 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1324 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1325 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1326 while (readl(port->membase + CDNS_UART_CR) &
1327 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1330 /* restore rx timeout value */
1331 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1333 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1334 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1335 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1336 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1338 clk_disable(cdns_uart->uartclk);
1339 clk_disable(cdns_uart->pclk);
1340 spin_unlock_irqrestore(&port->lock, flags);
1342 spin_lock_irqsave(&port->lock, flags);
1343 /* restore original rx trigger level */
1344 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1345 /* enable RX timeout interrupt */
1346 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1347 spin_unlock_irqrestore(&port->lock, flags);
1350 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1352 #endif /* ! CONFIG_PM_SLEEP */
1353 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1355 struct uart_port *port = dev_get_drvdata(dev);
1356 struct cdns_uart *cdns_uart = port->private_data;
1358 clk_disable(cdns_uart->uartclk);
1359 clk_disable(cdns_uart->pclk);
1363 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1365 struct uart_port *port = dev_get_drvdata(dev);
1366 struct cdns_uart *cdns_uart = port->private_data;
1368 clk_enable(cdns_uart->pclk);
1369 clk_enable(cdns_uart->uartclk);
1373 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1374 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1375 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1376 cdns_runtime_resume, NULL)
1379 static const struct cdns_platform_data zynqmp_uart_def = {
1380 .quirks = CDNS_UART_RXBS_SUPPORT, };
1382 /* Match table for of_platform binding */
1383 static const struct of_device_id cdns_uart_of_match[] = {
1384 { .compatible = "xlnx,xuartps", },
1385 { .compatible = "cdns,uart-r1p8", },
1386 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1387 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1390 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1393 * Maximum number of instances without alias IDs but if there is alias
1394 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1396 #define MAX_UART_INSTANCES 32
1398 /* Stores static aliases list */
1399 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1400 static int alias_bitmap_initialized;
1402 /* Stores actual bitmap of allocated IDs with alias IDs together */
1403 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1404 /* Protect bitmap operations to have unique IDs */
1405 static DEFINE_MUTEX(bitmap_lock);
1407 static int cdns_get_id(struct platform_device *pdev)
1411 mutex_lock(&bitmap_lock);
1413 /* Alias list is stable that's why get alias bitmap only once */
1414 if (!alias_bitmap_initialized) {
1415 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1416 alias_bitmap, MAX_UART_INSTANCES);
1417 if (ret && ret != -EOVERFLOW) {
1418 mutex_unlock(&bitmap_lock);
1422 alias_bitmap_initialized++;
1425 /* Make sure that alias ID is not taken by instance without alias */
1426 bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1428 dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1429 MAX_UART_INSTANCES, bitmap);
1431 /* Look for a serialN alias */
1432 id = of_alias_get_id(pdev->dev.of_node, "serial");
1434 dev_warn(&pdev->dev,
1435 "No serial alias passed. Using the first free id\n");
1438 * Start with id 0 and check if there is no serial0 alias
1439 * which points to device which is compatible with this driver.
1440 * If alias exists then try next free position.
1445 dev_info(&pdev->dev, "Checking id %d\n", id);
1446 id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1448 /* No free empty instance */
1449 if (id == MAX_UART_INSTANCES) {
1450 dev_err(&pdev->dev, "No free ID\n");
1451 mutex_unlock(&bitmap_lock);
1455 dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1456 /* Check if ID is empty */
1457 if (!test_and_set_bit(id, bitmap)) {
1458 /* Break the loop if bit is taken */
1460 "Selected ID %d allocation passed\n",
1465 "Selected ID %d allocation failed\n", id);
1466 /* if taking bit fails then try next one */
1471 mutex_unlock(&bitmap_lock);
1477 * cdns_uart_probe - Platform driver probe
1478 * @pdev: Pointer to the platform device structure
1480 * Return: 0 on success, negative errno otherwise
1482 static int cdns_uart_probe(struct platform_device *pdev)
1485 struct uart_port *port;
1486 struct resource *res;
1487 struct cdns_uart *cdns_uart_data;
1488 const struct of_device_id *match;
1489 struct uart_driver *cdns_uart_uart_driver;
1491 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1492 struct console *cdns_uart_console;
1495 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1497 if (!cdns_uart_data)
1499 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1503 cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1504 sizeof(*cdns_uart_uart_driver),
1506 if (!cdns_uart_uart_driver)
1509 cdns_uart_data->id = cdns_get_id(pdev);
1510 if (cdns_uart_data->id < 0)
1511 return cdns_uart_data->id;
1513 /* There is a need to use unique driver name */
1514 driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1515 CDNS_UART_NAME, cdns_uart_data->id);
1521 cdns_uart_uart_driver->owner = THIS_MODULE;
1522 cdns_uart_uart_driver->driver_name = driver_name;
1523 cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1524 cdns_uart_uart_driver->major = uartps_major;
1525 cdns_uart_uart_driver->minor = cdns_uart_data->id;
1526 cdns_uart_uart_driver->nr = 1;
1528 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1529 cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1531 if (!cdns_uart_console) {
1536 strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1537 sizeof(cdns_uart_console->name));
1538 cdns_uart_console->index = cdns_uart_data->id;
1539 cdns_uart_console->write = cdns_uart_console_write;
1540 cdns_uart_console->device = uart_console_device;
1541 cdns_uart_console->setup = cdns_uart_console_setup;
1542 cdns_uart_console->flags = CON_PRINTBUFFER;
1543 cdns_uart_console->data = cdns_uart_uart_driver;
1544 cdns_uart_uart_driver->cons = cdns_uart_console;
1547 rc = uart_register_driver(cdns_uart_uart_driver);
1549 dev_err(&pdev->dev, "Failed to register driver\n");
1553 cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1556 * Setting up proper name_base needs to be done after uart
1557 * registration because tty_driver structure is not filled.
1558 * name_base is 0 by default.
1560 cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1562 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1563 if (match && match->data) {
1564 const struct cdns_platform_data *data = match->data;
1566 cdns_uart_data->quirks = data->quirks;
1569 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1570 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1571 rc = PTR_ERR(cdns_uart_data->pclk);
1572 goto err_out_unregister_driver;
1575 if (IS_ERR(cdns_uart_data->pclk)) {
1576 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1577 if (IS_ERR(cdns_uart_data->pclk)) {
1578 rc = PTR_ERR(cdns_uart_data->pclk);
1579 goto err_out_unregister_driver;
1581 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1584 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1585 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1586 rc = PTR_ERR(cdns_uart_data->uartclk);
1587 goto err_out_unregister_driver;
1590 if (IS_ERR(cdns_uart_data->uartclk)) {
1591 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1592 if (IS_ERR(cdns_uart_data->uartclk)) {
1593 rc = PTR_ERR(cdns_uart_data->uartclk);
1594 goto err_out_unregister_driver;
1596 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1599 rc = clk_prepare_enable(cdns_uart_data->pclk);
1601 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1602 goto err_out_unregister_driver;
1604 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1606 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1607 goto err_out_clk_dis_pclk;
1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1613 goto err_out_clk_disable;
1616 irq = platform_get_irq(pdev, 0);
1619 goto err_out_clk_disable;
1622 #ifdef CONFIG_COMMON_CLK
1623 cdns_uart_data->clk_rate_change_nb.notifier_call =
1624 cdns_uart_clk_notifier_cb;
1625 if (clk_notifier_register(cdns_uart_data->uartclk,
1626 &cdns_uart_data->clk_rate_change_nb))
1627 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1630 /* At this point, we've got an empty uart_port struct, initialize it */
1631 spin_lock_init(&port->lock);
1632 port->type = PORT_UNKNOWN;
1633 port->iotype = UPIO_MEM32;
1634 port->flags = UPF_BOOT_AUTOCONF;
1635 port->ops = &cdns_uart_ops;
1636 port->fifosize = CDNS_UART_FIFO_SIZE;
1639 * Register the port.
1640 * This function also registers this device with the tty layer
1641 * and triggers invocation of the config_port() entry point.
1643 port->mapbase = res->start;
1645 port->dev = &pdev->dev;
1646 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1647 port->private_data = cdns_uart_data;
1648 cdns_uart_data->port = port;
1649 platform_set_drvdata(pdev, port);
1651 pm_runtime_use_autosuspend(&pdev->dev);
1652 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1653 pm_runtime_set_active(&pdev->dev);
1654 pm_runtime_enable(&pdev->dev);
1655 device_init_wakeup(port->dev, true);
1657 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1659 * If console hasn't been found yet try to assign this port
1660 * because it is required to be assigned for console setup function.
1661 * If register_console() don't assign value, then console_port pointer
1665 console_port = port;
1668 rc = uart_add_one_port(cdns_uart_uart_driver, port);
1671 "uart_add_one_port() failed; err=%i\n", rc);
1672 goto err_out_pm_disable;
1675 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1676 /* This is not port which is used for console that's why clean it up */
1677 if (console_port == port &&
1678 !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1679 console_port = NULL;
1682 uartps_major = cdns_uart_uart_driver->tty_driver->major;
1683 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1688 pm_runtime_disable(&pdev->dev);
1689 pm_runtime_set_suspended(&pdev->dev);
1690 pm_runtime_dont_use_autosuspend(&pdev->dev);
1691 #ifdef CONFIG_COMMON_CLK
1692 clk_notifier_unregister(cdns_uart_data->uartclk,
1693 &cdns_uart_data->clk_rate_change_nb);
1695 err_out_clk_disable:
1696 clk_disable_unprepare(cdns_uart_data->uartclk);
1697 err_out_clk_dis_pclk:
1698 clk_disable_unprepare(cdns_uart_data->pclk);
1699 err_out_unregister_driver:
1700 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1702 mutex_lock(&bitmap_lock);
1703 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1704 clear_bit(cdns_uart_data->id, bitmap);
1705 mutex_unlock(&bitmap_lock);
1710 * cdns_uart_remove - called when the platform driver is unregistered
1711 * @pdev: Pointer to the platform device structure
1713 * Return: 0 on success, negative errno otherwise
1715 static int cdns_uart_remove(struct platform_device *pdev)
1717 struct uart_port *port = platform_get_drvdata(pdev);
1718 struct cdns_uart *cdns_uart_data = port->private_data;
1721 /* Remove the cdns_uart port from the serial core */
1722 #ifdef CONFIG_COMMON_CLK
1723 clk_notifier_unregister(cdns_uart_data->uartclk,
1724 &cdns_uart_data->clk_rate_change_nb);
1726 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1728 mutex_lock(&bitmap_lock);
1729 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1730 clear_bit(cdns_uart_data->id, bitmap);
1731 mutex_unlock(&bitmap_lock);
1732 clk_disable_unprepare(cdns_uart_data->uartclk);
1733 clk_disable_unprepare(cdns_uart_data->pclk);
1734 pm_runtime_disable(&pdev->dev);
1735 pm_runtime_set_suspended(&pdev->dev);
1736 pm_runtime_dont_use_autosuspend(&pdev->dev);
1737 device_init_wakeup(&pdev->dev, false);
1739 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1740 if (console_port == port)
1741 console_port = NULL;
1744 /* If this is last instance major number should be initialized */
1745 mutex_lock(&bitmap_lock);
1746 if (bitmap_empty(bitmap, MAX_UART_INSTANCES))
1748 mutex_unlock(&bitmap_lock);
1750 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1754 static struct platform_driver cdns_uart_platform_driver = {
1755 .probe = cdns_uart_probe,
1756 .remove = cdns_uart_remove,
1758 .name = CDNS_UART_NAME,
1759 .of_match_table = cdns_uart_of_match,
1760 .pm = &cdns_uart_dev_pm_ops,
1761 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1765 static int __init cdns_uart_init(void)
1767 /* Register the platform driver */
1768 return platform_driver_register(&cdns_uart_platform_driver);
1771 static void __exit cdns_uart_exit(void)
1773 /* Unregister the platform driver */
1774 platform_driver_unregister(&cdns_uart_platform_driver);
1777 arch_initcall(cdns_uart_init);
1778 module_exit(cdns_uart_exit);
1780 MODULE_DESCRIPTION("Driver for Cadence UART");
1781 MODULE_AUTHOR("Xilinx Inc.");
1782 MODULE_LICENSE("GPL");