drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/serial.h>
  18 #include <linux/console.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/clk.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #define CDNS_UART_TTY_NAME      "ttyPS"
  31 #define CDNS_UART_NAME          "xuartps"
  32 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
  33 #define CDNS_UART_MINOR         0       /* works best with devtmpfs */
  34 #define CDNS_UART_NR_PORTS      2
  35 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  36 #define CDNS_UART_REGISTER_SPACE        0x1000
  37
  38 /* Rx Trigger level */
  39 static int rx_trigger_level = 56;
  40 module_param(rx_trigger_level, uint, S_IRUGO);
  41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  42
  43 /* Rx Timeout */
  44 static int rx_timeout = 10;
  45 module_param(rx_timeout, uint, S_IRUGO);
  46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  47
  48 /* Register offsets for the UART. */
  49 #define CDNS_UART_CR            0x00  /* Control Register */
  50 #define CDNS_UART_MR            0x04  /* Mode Register */
  51 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  52 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  53 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  54 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  55 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  56 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  57 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  58 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  59 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  60 #define CDNS_UART_SR            0x2C  /* Channel Status */
  61 #define CDNS_UART_FIFO          0x30  /* FIFO */
  62 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  63 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  64 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  65 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  66 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  67 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  68
  69 /* Control Register Bit Definitions */
  70 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  71 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  72 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  73 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  74 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  75 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  76 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  77 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  78 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  79 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  80 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  81 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  82
  83 /*
  84  * Mode Register:
  85  * The mode register (MR) defines the mode of transfer as well as the data
  86  * format. If this register is modified during transmission or reception,
  87  * data validity cannot be guaranteed.
  88  */
  89 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  90 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  91 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  92 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  93
  94 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  95 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  96
  97 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  98 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  99 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
 100 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
 101 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
 102
 103 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 104 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 105 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 106
 107 /*
 108  * Interrupt Registers:
 109  * Interrupt control logic uses the interrupt enable register (IER) and the
 110  * interrupt disable register (IDR) to set the value of the bits in the
 111  * interrupt mask register (IMR). The IMR determines whether to pass an
 112  * interrupt to the interrupt status register (ISR).
 113  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 114  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 115  * Reading either IER or IDR returns 0x00.
 116  * All four registers have the same bit definitions.
 117  */
 118 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 119 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 120 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 121 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 122 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 123 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 124 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 125 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 126 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 127 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 128 #define CDNS_UART_IXR_MASK      0x00001FFF /* Valid bit mask */
 129
 130         /*
 131          * Do not enable parity error interrupt for the following
 132          * reason: When parity error interrupt is enabled, each Rx
 133          * parity error always results in 2 events. The first one
 134          * being parity error interrupt and the second one with a
 135          * proper Rx interrupt with the incoming data.  Disabling
 136          * parity error interrupt ensures better handling of parity
 137          * error events. With this change, for a parity error case, we
 138          * get a Rx interrupt with parity error set in ISR register
 139          * and we still handle parity errors in the desired way.
 140          */
 141
 142 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 143                                  CDNS_UART_IXR_OVERRUN | \
 144                                  CDNS_UART_IXR_RXTRIG |  \
 145                                  CDNS_UART_IXR_TOUT)
 146
 147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 148 #define CDNS_UART_IXR_BRK       0x00002000
 149
 150 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 151 /*
 152  * Modem Control register:
 153  * The read/write Modem Control register controls the interface with the modem
 154  * or data set, or a peripheral device emulating a modem.
 155  */
 156 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 157 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 158 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 159
 160 /*
 161  * Channel Status Register:
 162  * The channel status register (CSR) is provided to enable the control logic
 163  * to monitor the status of bits in the channel interrupt status register,
 164  * even if these are masked out by the interrupt mask register.
 165  */
 166 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 167 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 168 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 169 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 170 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 171
 172 /* baud dividers min/max values */
 173 #define CDNS_UART_BDIV_MIN      4
 174 #define CDNS_UART_BDIV_MAX      255
 175 #define CDNS_UART_CD_MAX        65535
 176 #define UART_AUTOSUSPEND_TIMEOUT        3000
 177
 178 /**
 179  * struct cdns_uart - device data
 180  * @port:               Pointer to the UART port
 181  * @uartclk:            Reference clock
 182  * @pclk:               APB clock
 183  * @baud:               Current baud rate
 184  * @clk_rate_change_nb: Notifier block for clock changes
 185  * @quirks:             Flags for RXBS support.
 186  */
 187 struct cdns_uart {
 188         struct uart_port        *port;
 189         struct clk              *uartclk;
 190         struct clk              *pclk;
 191         unsigned int            baud;
 192         struct notifier_block   clk_rate_change_nb;
 193         u32                     quirks;
 194 };
 195 struct cdns_platform_data {
 196         u32 quirks;
 197 };
 198 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 199                 clk_rate_change_nb);
 200
 201 /**
 202  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 203  * @dev_id: Id of the UART port
 204  * @isrstatus: The interrupt status register value as read
 205  * Return: None
 206  */
 207 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 208 {
 209         struct uart_port *port = (struct uart_port *)dev_id;
 210         struct cdns_uart *cdns_uart = port->private_data;
 211         unsigned int data;
 212         unsigned int rxbs_status = 0;
 213         unsigned int status_mask;
 214         unsigned int framerrprocessed = 0;
 215         char status = TTY_NORMAL;
 216         bool is_rxbs_support;
 217
 218         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 219
 220         while ((readl(port->membase + CDNS_UART_SR) &
 221                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 222                 if (is_rxbs_support)
 223                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 224                 data = readl(port->membase + CDNS_UART_FIFO);
 225                 port->icount.rx++;
 226                 /*
 227                  * There is no hardware break detection in Zynq, so we interpret
 228                  * framing error with all-zeros data as a break sequence.
 229                  * Most of the time, there's another non-zero byte at the
 230                  * end of the sequence.
 231                  */
 232                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 233                         if (!data) {
 234                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 235                                 framerrprocessed = 1;
 236                                 continue;
 237                         }
 238                 }
 239                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 240                         port->icount.brk++;
 241                         status = TTY_BREAK;
 242                         if (uart_handle_break(port))
 243                                 continue;
 244                 }
 245
 246                 isrstatus &= port->read_status_mask;
 247                 isrstatus &= ~port->ignore_status_mask;
 248                 status_mask = port->read_status_mask;
 249                 status_mask &= ~port->ignore_status_mask;
 250
 251                 if (data &&
 252                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 253                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 254                         port->icount.brk++;
 255                         if (uart_handle_break(port))
 256                                 continue;
 257                 }
 258
 259                 if (uart_handle_sysrq_char(port, data))
 260                         continue;
 261
 262                 if (is_rxbs_support) {
 263                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 264                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 265                                 port->icount.parity++;
 266                                 status = TTY_PARITY;
 267                         }
 268                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 269                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 270                                 port->icount.frame++;
 271                                 status = TTY_FRAME;
 272                         }
 273                 } else {
 274                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 275                                 port->icount.parity++;
 276                                 status = TTY_PARITY;
 277                         }
 278                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 279                             !framerrprocessed) {
 280                                 port->icount.frame++;
 281                                 status = TTY_FRAME;
 282                         }
 283                 }
 284                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 285                         port->icount.overrun++;
 286                         tty_insert_flip_char(&port->state->port, 0,
 287                                              TTY_OVERRUN);
 288                 }
 289                 tty_insert_flip_char(&port->state->port, data, status);
 290                 isrstatus = 0;
 291         }
 292         spin_unlock(&port->lock);
 293         tty_flip_buffer_push(&port->state->port);
 294         spin_lock(&port->lock);
 295 }
 296
 297 /**
 298  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 299  * @dev_id: Id of the UART port
 300  * Return: None
 301  */
 302 static void cdns_uart_handle_tx(void *dev_id)
 303 {
 304         struct uart_port *port = (struct uart_port *)dev_id;
 305         unsigned int numbytes;
 306
 307         if (uart_circ_empty(&port->state->xmit)) {
 308                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 309         } else {
 310                 numbytes = port->fifosize;
 311                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 312                        !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
 313                         /*
 314                          * Get the data from the UART circular buffer
 315                          * and write it to the cdns_uart's TX_FIFO
 316                          * register.
 317                          */
 318                         writel(
 319                                 port->state->xmit.buf[port->state->xmit.
 320                                 tail], port->membase + CDNS_UART_FIFO);
 321
 322                         port->icount.tx++;
 323
 324                         /*
 325                          * Adjust the tail of the UART buffer and wrap
 326                          * the buffer if it reaches limit.
 327                          */
 328                         port->state->xmit.tail =
 329                                 (port->state->xmit.tail + 1) &
 330                                         (UART_XMIT_SIZE - 1);
 331
 332                         numbytes--;
 333                 }
 334
 335                 if (uart_circ_chars_pending(
 336                                 &port->state->xmit) < WAKEUP_CHARS)
 337                         uart_write_wakeup(port);
 338         }
 339 }
 340
 341 /**
 342  * cdns_uart_isr - Interrupt handler
 343  * @irq: Irq number
 344  * @dev_id: Id of the port
 345  *
 346  * Return: IRQHANDLED
 347  */
 348 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 349 {
 350         struct uart_port *port = (struct uart_port *)dev_id;
 351         unsigned int isrstatus;
 352
 353         spin_lock(&port->lock);
 354
 355         /* Read the interrupt status register to determine which
 356          * interrupt(s) is/are active and clear them.
 357          */
 358         isrstatus = readl(port->membase + CDNS_UART_ISR);
 359         writel(isrstatus, port->membase + CDNS_UART_ISR);
 360
 361         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 362                 cdns_uart_handle_tx(dev_id);
 363                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 364         }
 365         if (isrstatus & CDNS_UART_IXR_MASK)
 366                 cdns_uart_handle_rx(dev_id, isrstatus);
 367
 368         spin_unlock(&port->lock);
 369         return IRQ_HANDLED;
 370 }
 371
 372 /**
 373  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 374  * @clk: UART module input clock
 375  * @baud: Desired baud rate
 376  * @rbdiv: BDIV value (return value)
 377  * @rcd: CD value (return value)
 378  * @div8: Value for clk_sel bit in mod (return value)
 379  * Return: baud rate, requested baud when possible, or actual baud when there
 380  *      was too much error, zero if no valid divisors are found.
 381  *
 382  * Formula to obtain baud rate is
 383  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 384  *      input_clk = (Uart User Defined Clock or Apb Clock)
 385  *              depends on UCLKEN in MR Reg
 386  *      clk = input_clk or input_clk/8;
 387  *              depends on CLKS in MR reg
 388  *      CD and BDIV depends on values in
 389  *                      baud rate generate register
 390  *                      baud rate clock divisor register
 391  */
 392 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 393                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 394 {
 395         u32 cd, bdiv;
 396         unsigned int calc_baud;
 397         unsigned int bestbaud = 0;
 398         unsigned int bauderror;
 399         unsigned int besterror = ~0;
 400
 401         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 402                 *div8 = 1;
 403                 clk /= 8;
 404         } else {
 405                 *div8 = 0;
 406         }
 407
 408         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 409                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 410                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 411                         continue;
 412
 413                 calc_baud = clk / (cd * (bdiv + 1));
 414
 415                 if (baud > calc_baud)
 416                         bauderror = baud - calc_baud;
 417                 else
 418                         bauderror = calc_baud - baud;
 419
 420                 if (besterror > bauderror) {
 421                         *rbdiv = bdiv;
 422                         *rcd = cd;
 423                         bestbaud = calc_baud;
 424                         besterror = bauderror;
 425                 }
 426         }
 427         /* use the values when percent error is acceptable */
 428         if (((besterror * 100) / baud) < 3)
 429                 bestbaud = baud;
 430
 431         return bestbaud;
 432 }
 433
 434 /**
 435  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 436  * @port: Handle to the uart port structure
 437  * @baud: Baud rate to set
 438  * Return: baud rate, requested baud when possible, or actual baud when there
 439  *         was too much error, zero if no valid divisors are found.
 440  */
 441 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 442                 unsigned int baud)
 443 {
 444         unsigned int calc_baud;
 445         u32 cd = 0, bdiv = 0;
 446         u32 mreg;
 447         int div8;
 448         struct cdns_uart *cdns_uart = port->private_data;
 449
 450         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 451                         &div8);
 452
 453         /* Write new divisors to hardware */
 454         mreg = readl(port->membase + CDNS_UART_MR);
 455         if (div8)
 456                 mreg |= CDNS_UART_MR_CLKSEL;
 457         else
 458                 mreg &= ~CDNS_UART_MR_CLKSEL;
 459         writel(mreg, port->membase + CDNS_UART_MR);
 460         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 461         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 462         cdns_uart->baud = baud;
 463
 464         return calc_baud;
 465 }
 466
 467 #ifdef CONFIG_COMMON_CLK
 468 /**
 469  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 470  * @nb:         Notifier block
 471  * @event:      Notify event
 472  * @data:       Notifier data
 473  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 474  */
 475 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 476                 unsigned long event, void *data)
 477 {
 478         u32 ctrl_reg;
 479         struct uart_port *port;
 480         int locked = 0;
 481         struct clk_notifier_data *ndata = data;
 482         unsigned long flags = 0;
 483         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 484
 485         port = cdns_uart->port;
 486         if (port->suspended)
 487                 return NOTIFY_OK;
 488
 489         switch (event) {
 490         case PRE_RATE_CHANGE:
 491         {
 492                 u32 bdiv, cd;
 493                 int div8;
 494
 495                 /*
 496                  * Find out if current baud-rate can be achieved with new clock
 497                  * frequency.
 498                  */
 499                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 500                                         &bdiv, &cd, &div8)) {
 501                         dev_warn(port->dev, "clock rate change rejected\n");
 502                         return NOTIFY_BAD;
 503                 }
 504
 505                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 506
 507                 /* Disable the TX and RX to set baud rate */
 508                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 509                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 510                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 511
 512                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 513
 514                 return NOTIFY_OK;
 515         }
 516         case POST_RATE_CHANGE:
 517                 /*
 518                  * Set clk dividers to generate correct baud with new clock
 519                  * frequency.
 520                  */
 521
 522                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 523
 524                 locked = 1;
 525                 port->uartclk = ndata->new_rate;
 526
 527                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 528                                 cdns_uart->baud);
 529                 /* fall through */
 530         case ABORT_RATE_CHANGE:
 531                 if (!locked)
 532                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 533
 534                 /* Set TX/RX Reset */
 535                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 536                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 537                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 538
 539                 while (readl(port->membase + CDNS_UART_CR) &
 540                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 541                         cpu_relax();
 542
 543                 /*
 544                  * Clear the RX disable and TX disable bits and then set the TX
 545                  * enable bit and RX enable bit to enable the transmitter and
 546                  * receiver.
 547                  */
 548                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 549                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 550                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 551                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 552                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 553
 554                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 555
 556                 return NOTIFY_OK;
 557         default:
 558                 return NOTIFY_DONE;
 559         }
 560 }
 561 #endif
 562
 563 /**
 564  * cdns_uart_start_tx -  Start transmitting bytes
 565  * @port: Handle to the uart port structure
 566  */
 567 static void cdns_uart_start_tx(struct uart_port *port)
 568 {
 569         unsigned int status;
 570
 571         if (uart_tx_stopped(port))
 572                 return;
 573
 574         /*
 575          * Set the TX enable bit and clear the TX disable bit to enable the
 576          * transmitter.
 577          */
 578         status = readl(port->membase + CDNS_UART_CR);
 579         status &= ~CDNS_UART_CR_TX_DIS;
 580         status |= CDNS_UART_CR_TX_EN;
 581         writel(status, port->membase + CDNS_UART_CR);
 582
 583         if (uart_circ_empty(&port->state->xmit))
 584                 return;
 585
 586         cdns_uart_handle_tx(port);
 587
 588         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 589         /* Enable the TX Empty interrupt */
 590         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 591 }
 592
 593 /**
 594  * cdns_uart_stop_tx - Stop TX
 595  * @port: Handle to the uart port structure
 596  */
 597 static void cdns_uart_stop_tx(struct uart_port *port)
 598 {
 599         unsigned int regval;
 600
 601         regval = readl(port->membase + CDNS_UART_CR);
 602         regval |= CDNS_UART_CR_TX_DIS;
 603         /* Disable the transmitter */
 604         writel(regval, port->membase + CDNS_UART_CR);
 605 }
 606
 607 /**
 608  * cdns_uart_stop_rx - Stop RX
 609  * @port: Handle to the uart port structure
 610  */
 611 static void cdns_uart_stop_rx(struct uart_port *port)
 612 {
 613         unsigned int regval;
 614
 615         /* Disable RX IRQs */
 616         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 617
 618         /* Disable the receiver */
 619         regval = readl(port->membase + CDNS_UART_CR);
 620         regval |= CDNS_UART_CR_RX_DIS;
 621         writel(regval, port->membase + CDNS_UART_CR);
 622 }
 623
 624 /**
 625  * cdns_uart_tx_empty -  Check whether TX is empty
 626  * @port: Handle to the uart port structure
 627  *
 628  * Return: TIOCSER_TEMT on success, 0 otherwise
 629  */
 630 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 631 {
 632         unsigned int status;
 633
 634         status = readl(port->membase + CDNS_UART_SR) &
 635                                 CDNS_UART_SR_TXEMPTY;
 636         return status ? TIOCSER_TEMT : 0;
 637 }
 638
 639 /**
 640  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 641  *                      transmitting char breaks
 642  * @port: Handle to the uart port structure
 643  * @ctl: Value based on which start or stop decision is taken
 644  */
 645 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 646 {
 647         unsigned int status;
 648         unsigned long flags;
 649
 650         spin_lock_irqsave(&port->lock, flags);
 651
 652         status = readl(port->membase + CDNS_UART_CR);
 653
 654         if (ctl == -1)
 655                 writel(CDNS_UART_CR_STARTBRK | status,
 656                                 port->membase + CDNS_UART_CR);
 657         else {
 658                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 659                         writel(CDNS_UART_CR_STOPBRK | status,
 660                                         port->membase + CDNS_UART_CR);
 661         }
 662         spin_unlock_irqrestore(&port->lock, flags);
 663 }
 664
 665 /**
 666  * cdns_uart_set_termios - termios operations, handling data length, parity,
 667  *                              stop bits, flow control, baud rate
 668  * @port: Handle to the uart port structure
 669  * @termios: Handle to the input termios structure
 670  * @old: Values of the previously saved termios structure
 671  */
 672 static void cdns_uart_set_termios(struct uart_port *port,
 673                                 struct ktermios *termios, struct ktermios *old)
 674 {
 675         unsigned int cval = 0;
 676         unsigned int baud, minbaud, maxbaud;
 677         unsigned long flags;
 678         unsigned int ctrl_reg, mode_reg;
 679
 680         spin_lock_irqsave(&port->lock, flags);
 681
 682         /* Wait for the transmit FIFO to empty before making changes */
 683         if (!(readl(port->membase + CDNS_UART_CR) &
 684                                 CDNS_UART_CR_TX_DIS)) {
 685                 while (!(readl(port->membase + CDNS_UART_SR) &
 686                                 CDNS_UART_SR_TXEMPTY)) {
 687                         cpu_relax();
 688                 }
 689         }
 690
 691         /* Disable the TX and RX to set baud rate */
 692         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 693         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 694         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 695
 696         /*
 697          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 698          * min and max baud should be calculated here based on port->uartclk.
 699          * this way we get a valid baud and can safely call set_baud()
 700          */
 701         minbaud = port->uartclk /
 702                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 703         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 704         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 705         baud = cdns_uart_set_baud_rate(port, baud);
 706         if (tty_termios_baud_rate(termios))
 707                 tty_termios_encode_baud_rate(termios, baud, baud);
 708
 709         /* Update the per-port timeout. */
 710         uart_update_timeout(port, termios->c_cflag, baud);
 711
 712         /* Set TX/RX Reset */
 713         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 714         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 715         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 716
 717         while (readl(port->membase + CDNS_UART_CR) &
 718                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 719                 cpu_relax();
 720
 721         /*
 722          * Clear the RX disable and TX disable bits and then set the TX enable
 723          * bit and RX enable bit to enable the transmitter and receiver.
 724          */
 725         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 726         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 727         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 728         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 729
 730         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 731
 732         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 733                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 734         port->ignore_status_mask = 0;
 735
 736         if (termios->c_iflag & INPCK)
 737                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 738                 CDNS_UART_IXR_FRAMING;
 739
 740         if (termios->c_iflag & IGNPAR)
 741                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 742                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 743
 744         /* ignore all characters if CREAD is not set */
 745         if ((termios->c_cflag & CREAD) == 0)
 746                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 747                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 748                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 749
 750         mode_reg = readl(port->membase + CDNS_UART_MR);
 751
 752         /* Handling Data Size */
 753         switch (termios->c_cflag & CSIZE) {
 754         case CS6:
 755                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 756                 break;
 757         case CS7:
 758                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 759                 break;
 760         default:
 761         case CS8:
 762                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 763                 termios->c_cflag &= ~CSIZE;
 764                 termios->c_cflag |= CS8;
 765                 break;
 766         }
 767
 768         /* Handling Parity and Stop Bits length */
 769         if (termios->c_cflag & CSTOPB)
 770                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 771         else
 772                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 773
 774         if (termios->c_cflag & PARENB) {
 775                 /* Mark or Space parity */
 776                 if (termios->c_cflag & CMSPAR) {
 777                         if (termios->c_cflag & PARODD)
 778                                 cval |= CDNS_UART_MR_PARITY_MARK;
 779                         else
 780                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 781                 } else {
 782                         if (termios->c_cflag & PARODD)
 783                                 cval |= CDNS_UART_MR_PARITY_ODD;
 784                         else
 785                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 786                 }
 787         } else {
 788                 cval |= CDNS_UART_MR_PARITY_NONE;
 789         }
 790         cval |= mode_reg & 1;
 791         writel(cval, port->membase + CDNS_UART_MR);
 792
 793         spin_unlock_irqrestore(&port->lock, flags);
 794 }
 795
 796 /**
 797  * cdns_uart_startup - Called when an application opens a cdns_uart port
 798  * @port: Handle to the uart port structure
 799  *
 800  * Return: 0 on success, negative errno otherwise
 801  */
 802 static int cdns_uart_startup(struct uart_port *port)
 803 {
 804         struct cdns_uart *cdns_uart = port->private_data;
 805         bool is_brk_support;
 806         int ret;
 807         unsigned long flags;
 808         unsigned int status = 0;
 809
 810         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 811
 812         spin_lock_irqsave(&port->lock, flags);
 813
 814         /* Disable the TX and RX */
 815         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 816                         port->membase + CDNS_UART_CR);
 817
 818         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 819          * no break chars.
 820          */
 821         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 822                         port->membase + CDNS_UART_CR);
 823
 824         while (readl(port->membase + CDNS_UART_CR) &
 825                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 826                 cpu_relax();
 827
 828         /*
 829          * Clear the RX disable bit and then set the RX enable bit to enable
 830          * the receiver.
 831          */
 832         status = readl(port->membase + CDNS_UART_CR);
 833         status &= ~CDNS_UART_CR_RX_DIS;
 834         status |= CDNS_UART_CR_RX_EN;
 835         writel(status, port->membase + CDNS_UART_CR);
 836
 837         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 838          * no parity.
 839          */
 840         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 841                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 842                 port->membase + CDNS_UART_MR);
 843
 844         /*
 845          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 846          * can be tuned with a module parameter
 847          */
 848         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 849
 850         /*
 851          * Receive Timeout register is enabled but it
 852          * can be tuned with a module parameter
 853          */
 854         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 855
 856         /* Clear out any pending interrupts before enabling them */
 857         writel(readl(port->membase + CDNS_UART_ISR),
 858                         port->membase + CDNS_UART_ISR);
 859
 860         spin_unlock_irqrestore(&port->lock, flags);
 861
 862         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 863         if (ret) {
 864                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 865                         port->irq, ret);
 866                 return ret;
 867         }
 868
 869         /* Set the Interrupt Registers with desired interrupts */
 870         if (is_brk_support)
 871                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 872                                         port->membase + CDNS_UART_IER);
 873         else
 874                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 875
 876         return 0;
 877 }
 878
 879 /**
 880  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 881  * @port: Handle to the uart port structure
 882  */
 883 static void cdns_uart_shutdown(struct uart_port *port)
 884 {
 885         int status;
 886         unsigned long flags;
 887
 888         spin_lock_irqsave(&port->lock, flags);
 889
 890         /* Disable interrupts */
 891         status = readl(port->membase + CDNS_UART_IMR);
 892         writel(status, port->membase + CDNS_UART_IDR);
 893         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 894
 895         /* Disable the TX and RX */
 896         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 897                         port->membase + CDNS_UART_CR);
 898
 899         spin_unlock_irqrestore(&port->lock, flags);
 900
 901         free_irq(port->irq, port);
 902 }
 903
 904 /**
 905  * cdns_uart_type - Set UART type to cdns_uart port
 906  * @port: Handle to the uart port structure
 907  *
 908  * Return: string on success, NULL otherwise
 909  */
 910 static const char *cdns_uart_type(struct uart_port *port)
 911 {
 912         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 913 }
 914
 915 /**
 916  * cdns_uart_verify_port - Verify the port params
 917  * @port: Handle to the uart port structure
 918  * @ser: Handle to the structure whose members are compared
 919  *
 920  * Return: 0 on success, negative errno otherwise.
 921  */
 922 static int cdns_uart_verify_port(struct uart_port *port,
 923                                         struct serial_struct *ser)
 924 {
 925         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 926                 return -EINVAL;
 927         if (port->irq != ser->irq)
 928                 return -EINVAL;
 929         if (ser->io_type != UPIO_MEM)
 930                 return -EINVAL;
 931         if (port->iobase != ser->port)
 932                 return -EINVAL;
 933         if (ser->hub6 != 0)
 934                 return -EINVAL;
 935         return 0;
 936 }
 937
 938 /**
 939  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 940  *                              called when the driver adds a cdns_uart port via
 941  *                              uart_add_one_port()
 942  * @port: Handle to the uart port structure
 943  *
 944  * Return: 0 on success, negative errno otherwise.
 945  */
 946 static int cdns_uart_request_port(struct uart_port *port)
 947 {
 948         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 949                                          CDNS_UART_NAME)) {
 950                 return -ENOMEM;
 951         }
 952
 953         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 954         if (!port->membase) {
 955                 dev_err(port->dev, "Unable to map registers\n");
 956                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 957                 return -ENOMEM;
 958         }
 959         return 0;
 960 }
 961
 962 /**
 963  * cdns_uart_release_port - Release UART port
 964  * @port: Handle to the uart port structure
 965  *
 966  * Release the memory region attached to a cdns_uart port. Called when the
 967  * driver removes a cdns_uart port via uart_remove_one_port().
 968  */
 969 static void cdns_uart_release_port(struct uart_port *port)
 970 {
 971         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 972         iounmap(port->membase);
 973         port->membase = NULL;
 974 }
 975
 976 /**
 977  * cdns_uart_config_port - Configure UART port
 978  * @port: Handle to the uart port structure
 979  * @flags: If any
 980  */
 981 static void cdns_uart_config_port(struct uart_port *port, int flags)
 982 {
 983         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 984                 port->type = PORT_XUARTPS;
 985 }
 986
 987 /**
 988  * cdns_uart_get_mctrl - Get the modem control state
 989  * @port: Handle to the uart port structure
 990  *
 991  * Return: the modem control state
 992  */
 993 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
 994 {
 995         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 996 }
 997
 998 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 999 {
1000         u32 val;
1001         u32 mode_reg;
1002
1003         val = readl(port->membase + CDNS_UART_MODEMCR);
1004         mode_reg = readl(port->membase + CDNS_UART_MR);
1005
1006         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1007         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1008
1009         if (mctrl & TIOCM_RTS)
1010                 val |= CDNS_UART_MODEMCR_RTS;
1011         if (mctrl & TIOCM_DTR)
1012                 val |= CDNS_UART_MODEMCR_DTR;
1013         if (mctrl & TIOCM_LOOP)
1014                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1015         else
1016                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1017
1018         writel(val, port->membase + CDNS_UART_MODEMCR);
1019         writel(mode_reg, port->membase + CDNS_UART_MR);
1020 }
1021
1022 #ifdef CONFIG_CONSOLE_POLL
1023 static int cdns_uart_poll_get_char(struct uart_port *port)
1024 {
1025         int c;
1026         unsigned long flags;
1027
1028         spin_lock_irqsave(&port->lock, flags);
1029
1030         /* Check if FIFO is empty */
1031         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1032                 c = NO_POLL_CHAR;
1033         else /* Read a character */
1034                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1035
1036         spin_unlock_irqrestore(&port->lock, flags);
1037
1038         return c;
1039 }
1040
1041 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1042 {
1043         unsigned long flags;
1044
1045         spin_lock_irqsave(&port->lock, flags);
1046
1047         /* Wait until FIFO is empty */
1048         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1049                 cpu_relax();
1050
1051         /* Write a character */
1052         writel(c, port->membase + CDNS_UART_FIFO);
1053
1054         /* Wait until FIFO is empty */
1055         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1056                 cpu_relax();
1057
1058         spin_unlock_irqrestore(&port->lock, flags);
1059
1060         return;
1061 }
1062 #endif
1063
1064 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1065                    unsigned int oldstate)
1066 {
1067         switch (state) {
1068         case UART_PM_STATE_OFF:
1069                 pm_runtime_mark_last_busy(port->dev);
1070                 pm_runtime_put_autosuspend(port->dev);
1071                 break;
1072         default:
1073                 pm_runtime_get_sync(port->dev);
1074                 break;
1075         }
1076 }
1077
1078 static const struct uart_ops cdns_uart_ops = {
1079         .set_mctrl      = cdns_uart_set_mctrl,
1080         .get_mctrl      = cdns_uart_get_mctrl,
1081         .start_tx       = cdns_uart_start_tx,
1082         .stop_tx        = cdns_uart_stop_tx,
1083         .stop_rx        = cdns_uart_stop_rx,
1084         .tx_empty       = cdns_uart_tx_empty,
1085         .break_ctl      = cdns_uart_break_ctl,
1086         .set_termios    = cdns_uart_set_termios,
1087         .startup        = cdns_uart_startup,
1088         .shutdown       = cdns_uart_shutdown,
1089         .pm             = cdns_uart_pm,
1090         .type           = cdns_uart_type,
1091         .verify_port    = cdns_uart_verify_port,
1092         .request_port   = cdns_uart_request_port,
1093         .release_port   = cdns_uart_release_port,
1094         .config_port    = cdns_uart_config_port,
1095 #ifdef CONFIG_CONSOLE_POLL
1096         .poll_get_char  = cdns_uart_poll_get_char,
1097         .poll_put_char  = cdns_uart_poll_put_char,
1098 #endif
1099 };
1100
1101 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1102 /**
1103  * cdns_uart_console_putchar - write the character to the FIFO buffer
1104  * @port: Handle to the uart port structure
1105  * @ch: Character to be written
1106  */
1107 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1108 {
1109         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1110                 cpu_relax();
1111         writel(ch, port->membase + CDNS_UART_FIFO);
1112 }
1113
1114 static void cdns_early_write(struct console *con, const char *s,
1115                                     unsigned n)
1116 {
1117         struct earlycon_device *dev = con->data;
1118
1119         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1120 }
1121
1122 static int __init cdns_early_console_setup(struct earlycon_device *device,
1123                                            const char *opt)
1124 {
1125         struct uart_port *port = &device->port;
1126
1127         if (!port->membase)
1128                 return -ENODEV;
1129
1130         /* initialise control register */
1131         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1132                port->membase + CDNS_UART_CR);
1133
1134         /* only set baud if specified on command line - otherwise
1135          * assume it has been initialized by a boot loader.
1136          */
1137         if (port->uartclk && device->baud) {
1138                 u32 cd = 0, bdiv = 0;
1139                 u32 mr;
1140                 int div8;
1141
1142                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1143                                          &bdiv, &cd, &div8);
1144                 mr = CDNS_UART_MR_PARITY_NONE;
1145                 if (div8)
1146                         mr |= CDNS_UART_MR_CLKSEL;
1147
1148                 writel(mr,   port->membase + CDNS_UART_MR);
1149                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1150                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1151         }
1152
1153         device->con->write = cdns_early_write;
1154
1155         return 0;
1156 }
1157 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1158 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1159 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1160 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1161
1162
1163 /* Static pointer to console port */
1164 static struct uart_port *console_port;
1165
1166 /**
1167  * cdns_uart_console_write - perform write operation
1168  * @co: Console handle
1169  * @s: Pointer to character array
1170  * @count: No of characters
1171  */
1172 static void cdns_uart_console_write(struct console *co, const char *s,
1173                                 unsigned int count)
1174 {
1175         struct uart_port *port = console_port;
1176         unsigned long flags;
1177         unsigned int imr, ctrl;
1178         int locked = 1;
1179
1180         if (port->sysrq)
1181                 locked = 0;
1182         else if (oops_in_progress)
1183                 locked = spin_trylock_irqsave(&port->lock, flags);
1184         else
1185                 spin_lock_irqsave(&port->lock, flags);
1186
1187         /* save and disable interrupt */
1188         imr = readl(port->membase + CDNS_UART_IMR);
1189         writel(imr, port->membase + CDNS_UART_IDR);
1190
1191         /*
1192          * Make sure that the tx part is enabled. Set the TX enable bit and
1193          * clear the TX disable bit to enable the transmitter.
1194          */
1195         ctrl = readl(port->membase + CDNS_UART_CR);
1196         ctrl &= ~CDNS_UART_CR_TX_DIS;
1197         ctrl |= CDNS_UART_CR_TX_EN;
1198         writel(ctrl, port->membase + CDNS_UART_CR);
1199
1200         uart_console_write(port, s, count, cdns_uart_console_putchar);
1201         while ((readl(port->membase + CDNS_UART_SR) &
1202                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1203                         CDNS_UART_SR_TXEMPTY)
1204                 cpu_relax();
1205
1206         /* restore interrupt state */
1207         writel(imr, port->membase + CDNS_UART_IER);
1208
1209         if (locked)
1210                 spin_unlock_irqrestore(&port->lock, flags);
1211 }
1212
1213 /**
1214  * cdns_uart_console_setup - Initialize the uart to default config
1215  * @co: Console handle
1216  * @options: Initial settings of uart
1217  *
1218  * Return: 0 on success, negative errno otherwise.
1219  */
1220 static int __init cdns_uart_console_setup(struct console *co, char *options)
1221 {
1222         struct uart_port *port = console_port;
1223
1224         int baud = 9600;
1225         int bits = 8;
1226         int parity = 'n';
1227         int flow = 'n';
1228
1229         if (!port->membase) {
1230                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1231                          co->index);
1232                 return -ENODEV;
1233         }
1234
1235         if (options)
1236                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1237
1238         return uart_set_options(port, co, baud, parity, bits, flow);
1239 }
1240
1241 static struct uart_driver cdns_uart_uart_driver;
1242
1243 static struct console cdns_uart_console = {
1244         .name   = CDNS_UART_TTY_NAME,
1245         .write  = cdns_uart_console_write,
1246         .device = uart_console_device,
1247         .setup  = cdns_uart_console_setup,
1248         .flags  = CON_PRINTBUFFER,
1249         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1250         .data   = &cdns_uart_uart_driver,
1251 };
1252 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1253
1254 static struct uart_driver cdns_uart_uart_driver = {
1255         .owner          = THIS_MODULE,
1256         .driver_name    = CDNS_UART_NAME,
1257         .dev_name       = CDNS_UART_TTY_NAME,
1258         .major          = CDNS_UART_MAJOR,
1259         .minor          = CDNS_UART_MINOR,
1260         .nr             = CDNS_UART_NR_PORTS,
1261 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1262         .cons           = &cdns_uart_console,
1263 #endif
1264 };
1265
1266 #ifdef CONFIG_PM_SLEEP
1267 /**
1268  * cdns_uart_suspend - suspend event
1269  * @device: Pointer to the device structure
1270  *
1271  * Return: 0
1272  */
1273 static int cdns_uart_suspend(struct device *device)
1274 {
1275         struct uart_port *port = dev_get_drvdata(device);
1276         struct tty_struct *tty;
1277         struct device *tty_dev;
1278         int may_wake = 0;
1279
1280         /* Get the tty which could be NULL so don't assume it's valid */
1281         tty = tty_port_tty_get(&port->state->port);
1282         if (tty) {
1283                 tty_dev = tty->dev;
1284                 may_wake = device_may_wakeup(tty_dev);
1285                 tty_kref_put(tty);
1286         }
1287
1288         /*
1289          * Call the API provided in serial_core.c file which handles
1290          * the suspend.
1291          */
1292         uart_suspend_port(&cdns_uart_uart_driver, port);
1293         if (!(console_suspend_enabled && !may_wake)) {
1294                 unsigned long flags = 0;
1295
1296                 spin_lock_irqsave(&port->lock, flags);
1297                 /* Empty the receive FIFO 1st before making changes */
1298                 while (!(readl(port->membase + CDNS_UART_SR) &
1299                                         CDNS_UART_SR_RXEMPTY))
1300                         readl(port->membase + CDNS_UART_FIFO);
1301                 /* set RX trigger level to 1 */
1302                 writel(1, port->membase + CDNS_UART_RXWM);
1303                 /* disable RX timeout interrups */
1304                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1305                 spin_unlock_irqrestore(&port->lock, flags);
1306         }
1307
1308         return 0;
1309 }
1310
1311 /**
1312  * cdns_uart_resume - Resume after a previous suspend
1313  * @device: Pointer to the device structure
1314  *
1315  * Return: 0
1316  */
1317 static int cdns_uart_resume(struct device *device)
1318 {
1319         struct uart_port *port = dev_get_drvdata(device);
1320         unsigned long flags = 0;
1321         u32 ctrl_reg;
1322         struct tty_struct *tty;
1323         struct device *tty_dev;
1324         int may_wake = 0;
1325
1326         /* Get the tty which could be NULL so don't assume it's valid */
1327         tty = tty_port_tty_get(&port->state->port);
1328         if (tty) {
1329                 tty_dev = tty->dev;
1330                 may_wake = device_may_wakeup(tty_dev);
1331                 tty_kref_put(tty);
1332         }
1333
1334         if (console_suspend_enabled && !may_wake) {
1335                 struct cdns_uart *cdns_uart = port->private_data;
1336
1337                 clk_enable(cdns_uart->pclk);
1338                 clk_enable(cdns_uart->uartclk);
1339
1340                 spin_lock_irqsave(&port->lock, flags);
1341
1342                 /* Set TX/RX Reset */
1343                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1344                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1345                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1346                 while (readl(port->membase + CDNS_UART_CR) &
1347                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1348                         cpu_relax();
1349
1350                 /* restore rx timeout value */
1351                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1352                 /* Enable Tx/Rx */
1353                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1354                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1355                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1356                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1357
1358                 clk_disable(cdns_uart->uartclk);
1359                 clk_disable(cdns_uart->pclk);
1360                 spin_unlock_irqrestore(&port->lock, flags);
1361         } else {
1362                 spin_lock_irqsave(&port->lock, flags);
1363                 /* restore original rx trigger level */
1364                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1365                 /* enable RX timeout interrupt */
1366                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1367                 spin_unlock_irqrestore(&port->lock, flags);
1368         }
1369
1370         return uart_resume_port(&cdns_uart_uart_driver, port);
1371 }
1372 #endif /* ! CONFIG_PM_SLEEP */
1373 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1374 {
1375         struct uart_port *port = dev_get_drvdata(dev);
1376         struct cdns_uart *cdns_uart = port->private_data;
1377
1378         clk_disable(cdns_uart->uartclk);
1379         clk_disable(cdns_uart->pclk);
1380         return 0;
1381 };
1382
1383 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1384 {
1385         struct uart_port *port = dev_get_drvdata(dev);
1386         struct cdns_uart *cdns_uart = port->private_data;
1387
1388         clk_enable(cdns_uart->pclk);
1389         clk_enable(cdns_uart->uartclk);
1390         return 0;
1391 };
1392
1393 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1394         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1395         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1396                            cdns_runtime_resume, NULL)
1397 };
1398
1399 static const struct cdns_platform_data zynqmp_uart_def = {
1400                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1401
1402 /* Match table for of_platform binding */
1403 static const struct of_device_id cdns_uart_of_match[] = {
1404         { .compatible = "xlnx,xuartps", },
1405         { .compatible = "cdns,uart-r1p8", },
1406         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1407         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1408         {}
1409 };
1410 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1411
1412 /**
1413  * cdns_uart_probe - Platform driver probe
1414  * @pdev: Pointer to the platform device structure
1415  *
1416  * Return: 0 on success, negative errno otherwise
1417  */
1418 static int cdns_uart_probe(struct platform_device *pdev)
1419 {
1420         int rc, id, irq;
1421         struct uart_port *port;
1422         struct resource *res;
1423         struct cdns_uart *cdns_uart_data;
1424         const struct of_device_id *match;
1425
1426         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1427                         GFP_KERNEL);
1428         if (!cdns_uart_data)
1429                 return -ENOMEM;
1430         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1431         if (!port)
1432                 return -ENOMEM;
1433
1434         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1435         if (match && match->data) {
1436                 const struct cdns_platform_data *data = match->data;
1437
1438                 cdns_uart_data->quirks = data->quirks;
1439         }
1440
1441         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1442         if (IS_ERR(cdns_uart_data->pclk)) {
1443                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1444                 if (!IS_ERR(cdns_uart_data->pclk))
1445                         dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1446         }
1447         if (IS_ERR(cdns_uart_data->pclk)) {
1448                 dev_err(&pdev->dev, "pclk clock not found.\n");
1449                 return PTR_ERR(cdns_uart_data->pclk);
1450         }
1451
1452         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1453         if (IS_ERR(cdns_uart_data->uartclk)) {
1454                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1455                 if (!IS_ERR(cdns_uart_data->uartclk))
1456                         dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1457         }
1458         if (IS_ERR(cdns_uart_data->uartclk)) {
1459                 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1460                 return PTR_ERR(cdns_uart_data->uartclk);
1461         }
1462
1463         rc = clk_prepare_enable(cdns_uart_data->pclk);
1464         if (rc) {
1465                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1466                 return rc;
1467         }
1468         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1469         if (rc) {
1470                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1471                 goto err_out_clk_dis_pclk;
1472         }
1473
1474         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1475         if (!res) {
1476                 rc = -ENODEV;
1477                 goto err_out_clk_disable;
1478         }
1479
1480         irq = platform_get_irq(pdev, 0);
1481         if (irq <= 0) {
1482                 rc = -ENXIO;
1483                 goto err_out_clk_disable;
1484         }
1485
1486 #ifdef CONFIG_COMMON_CLK
1487         cdns_uart_data->clk_rate_change_nb.notifier_call =
1488                         cdns_uart_clk_notifier_cb;
1489         if (clk_notifier_register(cdns_uart_data->uartclk,
1490                                 &cdns_uart_data->clk_rate_change_nb))
1491                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1492 #endif
1493         /* Look for a serialN alias */
1494         id = of_alias_get_id(pdev->dev.of_node, "serial");
1495         if (id < 0)
1496                 id = 0;
1497
1498         if (id >= CDNS_UART_NR_PORTS) {
1499                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1500                 rc = -ENODEV;
1501                 goto err_out_notif_unreg;
1502         }
1503
1504         /* At this point, we've got an empty uart_port struct, initialize it */
1505         spin_lock_init(&port->lock);
1506         port->membase   = NULL;
1507         port->irq       = 0;
1508         port->type      = PORT_UNKNOWN;
1509         port->iotype    = UPIO_MEM32;
1510         port->flags     = UPF_BOOT_AUTOCONF;
1511         port->ops       = &cdns_uart_ops;
1512         port->fifosize  = CDNS_UART_FIFO_SIZE;
1513         port->line      = id;
1514         port->dev       = NULL;
1515
1516         /*
1517          * Register the port.
1518          * This function also registers this device with the tty layer
1519          * and triggers invocation of the config_port() entry point.
1520          */
1521         port->mapbase = res->start;
1522         port->irq = irq;
1523         port->dev = &pdev->dev;
1524         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1525         port->private_data = cdns_uart_data;
1526         cdns_uart_data->port = port;
1527         platform_set_drvdata(pdev, port);
1528
1529         pm_runtime_use_autosuspend(&pdev->dev);
1530         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1531         pm_runtime_set_active(&pdev->dev);
1532         pm_runtime_enable(&pdev->dev);
1533
1534 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1535         /*
1536          * If console hasn't been found yet try to assign this port
1537          * because it is required to be assigned for console setup function.
1538          * If register_console() don't assign value, then console_port pointer
1539          * is cleanup.
1540          */
1541         if (cdns_uart_uart_driver.cons->index == -1)
1542                 console_port = port;
1543 #endif
1544
1545         rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1546         if (rc) {
1547                 dev_err(&pdev->dev,
1548                         "uart_add_one_port() failed; err=%i\n", rc);
1549                 goto err_out_pm_disable;
1550         }
1551
1552 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1553         /* This is not port which is used for console that's why clean it up */
1554         if (cdns_uart_uart_driver.cons->index == -1)
1555                 console_port = NULL;
1556 #endif
1557
1558         return 0;
1559
1560 err_out_pm_disable:
1561         pm_runtime_disable(&pdev->dev);
1562         pm_runtime_set_suspended(&pdev->dev);
1563         pm_runtime_dont_use_autosuspend(&pdev->dev);
1564 err_out_notif_unreg:
1565 #ifdef CONFIG_COMMON_CLK
1566         clk_notifier_unregister(cdns_uart_data->uartclk,
1567                         &cdns_uart_data->clk_rate_change_nb);
1568 #endif
1569 err_out_clk_disable:
1570         clk_disable_unprepare(cdns_uart_data->uartclk);
1571 err_out_clk_dis_pclk:
1572         clk_disable_unprepare(cdns_uart_data->pclk);
1573
1574         return rc;
1575 }
1576
1577 /**
1578  * cdns_uart_remove - called when the platform driver is unregistered
1579  * @pdev: Pointer to the platform device structure
1580  *
1581  * Return: 0 on success, negative errno otherwise
1582  */
1583 static int cdns_uart_remove(struct platform_device *pdev)
1584 {
1585         struct uart_port *port = platform_get_drvdata(pdev);
1586         struct cdns_uart *cdns_uart_data = port->private_data;
1587         int rc;
1588
1589         /* Remove the cdns_uart port from the serial core */
1590 #ifdef CONFIG_COMMON_CLK
1591         clk_notifier_unregister(cdns_uart_data->uartclk,
1592                         &cdns_uart_data->clk_rate_change_nb);
1593 #endif
1594         rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1595         port->mapbase = 0;
1596         clk_disable_unprepare(cdns_uart_data->uartclk);
1597         clk_disable_unprepare(cdns_uart_data->pclk);
1598         pm_runtime_disable(&pdev->dev);
1599         pm_runtime_set_suspended(&pdev->dev);
1600         pm_runtime_dont_use_autosuspend(&pdev->dev);
1601         return rc;
1602 }
1603
1604 static struct platform_driver cdns_uart_platform_driver = {
1605         .probe   = cdns_uart_probe,
1606         .remove  = cdns_uart_remove,
1607         .driver  = {
1608                 .name = CDNS_UART_NAME,
1609                 .of_match_table = cdns_uart_of_match,
1610                 .pm = &cdns_uart_dev_pm_ops,
1611                 },
1612 };
1613
1614 static int __init cdns_uart_init(void)
1615 {
1616         int retval = 0;
1617
1618         /* Register the cdns_uart driver with the serial core */
1619         retval = uart_register_driver(&cdns_uart_uart_driver);
1620         if (retval)
1621                 return retval;
1622
1623         /* Register the platform driver */
1624         retval = platform_driver_register(&cdns_uart_platform_driver);
1625         if (retval)
1626                 uart_unregister_driver(&cdns_uart_uart_driver);
1627
1628         return retval;
1629 }
1630
1631 static void __exit cdns_uart_exit(void)
1632 {
1633         /* Unregister the platform driver */
1634         platform_driver_unregister(&cdns_uart_platform_driver);
1635
1636         /* Unregister the cdns_uart driver */
1637         uart_unregister_driver(&cdns_uart_uart_driver);
1638 }
1639
1640 arch_initcall(cdns_uart_init);
1641 module_exit(cdns_uart_exit);
1642
1643 MODULE_DESCRIPTION("Driver for Cadence UART");
1644 MODULE_AUTHOR("Xilinx Inc.");
1645 MODULE_LICENSE("GPL");