drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/serial.h>
  18 #include <linux/console.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/clk.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #define CDNS_UART_TTY_NAME      "ttyPS"
  31 #define CDNS_UART_NAME          "xuartps"
  32 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
  33 #define CDNS_UART_MINOR         0       /* works best with devtmpfs */
  34 #define CDNS_UART_NR_PORTS      2
  35 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  36 #define CDNS_UART_REGISTER_SPACE        0x1000
  37
  38 /* Rx Trigger level */
  39 static int rx_trigger_level = 56;
  40 module_param(rx_trigger_level, uint, S_IRUGO);
  41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  42
  43 /* Rx Timeout */
  44 static int rx_timeout = 10;
  45 module_param(rx_timeout, uint, S_IRUGO);
  46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  47
  48 /* Register offsets for the UART. */
  49 #define CDNS_UART_CR            0x00  /* Control Register */
  50 #define CDNS_UART_MR            0x04  /* Mode Register */
  51 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  52 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  53 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  54 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  55 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  56 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  57 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  58 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  59 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  60 #define CDNS_UART_SR            0x2C  /* Channel Status */
  61 #define CDNS_UART_FIFO          0x30  /* FIFO */
  62 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  63 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  64 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  65 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  66 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  67 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  68
  69 /* Control Register Bit Definitions */
  70 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  71 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  72 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  73 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  74 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  75 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  76 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  77 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  78 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  79 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  80 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  81 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  82
  83 /*
  84  * Mode Register:
  85  * The mode register (MR) defines the mode of transfer as well as the data
  86  * format. If this register is modified during transmission or reception,
  87  * data validity cannot be guaranteed.
  88  */
  89 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  90 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  91 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  92 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  93
  94 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  95 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  96
  97 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  98 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  99 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
 100 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
 101 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
 102
 103 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 104 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 105 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 106
 107 /*
 108  * Interrupt Registers:
 109  * Interrupt control logic uses the interrupt enable register (IER) and the
 110  * interrupt disable register (IDR) to set the value of the bits in the
 111  * interrupt mask register (IMR). The IMR determines whether to pass an
 112  * interrupt to the interrupt status register (ISR).
 113  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 114  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 115  * Reading either IER or IDR returns 0x00.
 116  * All four registers have the same bit definitions.
 117  */
 118 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 119 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 120 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 121 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 122 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 123 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 124 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 125 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 126 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 127 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 128 #define CDNS_UART_IXR_MASK      0x00001FFF /* Valid bit mask */
 129
 130         /*
 131          * Do not enable parity error interrupt for the following
 132          * reason: When parity error interrupt is enabled, each Rx
 133          * parity error always results in 2 events. The first one
 134          * being parity error interrupt and the second one with a
 135          * proper Rx interrupt with the incoming data.  Disabling
 136          * parity error interrupt ensures better handling of parity
 137          * error events. With this change, for a parity error case, we
 138          * get a Rx interrupt with parity error set in ISR register
 139          * and we still handle parity errors in the desired way.
 140          */
 141
 142 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 143                                  CDNS_UART_IXR_OVERRUN | \
 144                                  CDNS_UART_IXR_RXTRIG |  \
 145                                  CDNS_UART_IXR_TOUT)
 146
 147 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 148 #define CDNS_UART_IXR_BRK       0x00002000
 149
 150 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 151 /*
 152  * Modem Control register:
 153  * The read/write Modem Control register controls the interface with the modem
 154  * or data set, or a peripheral device emulating a modem.
 155  */
 156 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 157 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 158 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 159
 160 /*
 161  * Channel Status Register:
 162  * The channel status register (CSR) is provided to enable the control logic
 163  * to monitor the status of bits in the channel interrupt status register,
 164  * even if these are masked out by the interrupt mask register.
 165  */
 166 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 167 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 168 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 169 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 170 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 171
 172 /* baud dividers min/max values */
 173 #define CDNS_UART_BDIV_MIN      4
 174 #define CDNS_UART_BDIV_MAX      255
 175 #define CDNS_UART_CD_MAX        65535
 176 #define UART_AUTOSUSPEND_TIMEOUT        3000
 177
 178 /**
 179  * struct cdns_uart - device data
 180  * @port:               Pointer to the UART port
 181  * @uartclk:            Reference clock
 182  * @pclk:               APB clock
 183  * @cdns_uart_driver:   Pointer to UART driver
 184  * @baud:               Current baud rate
 185  * @clk_rate_change_nb: Notifier block for clock changes
 186  * @quirks:             Flags for RXBS support.
 187  */
 188 struct cdns_uart {
 189         struct uart_port        *port;
 190         struct clk              *uartclk;
 191         struct clk              *pclk;
 192         struct uart_driver      *cdns_uart_driver;
 193         unsigned int            baud;
 194         struct notifier_block   clk_rate_change_nb;
 195         u32                     quirks;
 196 };
 197 struct cdns_platform_data {
 198         u32 quirks;
 199 };
 200 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 201                 clk_rate_change_nb);
 202
 203 /**
 204  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 205  * @dev_id: Id of the UART port
 206  * @isrstatus: The interrupt status register value as read
 207  * Return: None
 208  */
 209 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 210 {
 211         struct uart_port *port = (struct uart_port *)dev_id;
 212         struct cdns_uart *cdns_uart = port->private_data;
 213         unsigned int data;
 214         unsigned int rxbs_status = 0;
 215         unsigned int status_mask;
 216         unsigned int framerrprocessed = 0;
 217         char status = TTY_NORMAL;
 218         bool is_rxbs_support;
 219
 220         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 221
 222         while ((readl(port->membase + CDNS_UART_SR) &
 223                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 224                 if (is_rxbs_support)
 225                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 226                 data = readl(port->membase + CDNS_UART_FIFO);
 227                 port->icount.rx++;
 228                 /*
 229                  * There is no hardware break detection in Zynq, so we interpret
 230                  * framing error with all-zeros data as a break sequence.
 231                  * Most of the time, there's another non-zero byte at the
 232                  * end of the sequence.
 233                  */
 234                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 235                         if (!data) {
 236                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 237                                 framerrprocessed = 1;
 238                                 continue;
 239                         }
 240                 }
 241                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 242                         port->icount.brk++;
 243                         status = TTY_BREAK;
 244                         if (uart_handle_break(port))
 245                                 continue;
 246                 }
 247
 248                 isrstatus &= port->read_status_mask;
 249                 isrstatus &= ~port->ignore_status_mask;
 250                 status_mask = port->read_status_mask;
 251                 status_mask &= ~port->ignore_status_mask;
 252
 253                 if (data &&
 254                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 255                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 256                         port->icount.brk++;
 257                         if (uart_handle_break(port))
 258                                 continue;
 259                 }
 260
 261                 if (uart_handle_sysrq_char(port, data))
 262                         continue;
 263
 264                 if (is_rxbs_support) {
 265                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 266                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 267                                 port->icount.parity++;
 268                                 status = TTY_PARITY;
 269                         }
 270                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 271                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 272                                 port->icount.frame++;
 273                                 status = TTY_FRAME;
 274                         }
 275                 } else {
 276                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 277                                 port->icount.parity++;
 278                                 status = TTY_PARITY;
 279                         }
 280                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 281                             !framerrprocessed) {
 282                                 port->icount.frame++;
 283                                 status = TTY_FRAME;
 284                         }
 285                 }
 286                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 287                         port->icount.overrun++;
 288                         tty_insert_flip_char(&port->state->port, 0,
 289                                              TTY_OVERRUN);
 290                 }
 291                 tty_insert_flip_char(&port->state->port, data, status);
 292                 isrstatus = 0;
 293         }
 294         spin_unlock(&port->lock);
 295         tty_flip_buffer_push(&port->state->port);
 296         spin_lock(&port->lock);
 297 }
 298
 299 /**
 300  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 301  * @dev_id: Id of the UART port
 302  * Return: None
 303  */
 304 static void cdns_uart_handle_tx(void *dev_id)
 305 {
 306         struct uart_port *port = (struct uart_port *)dev_id;
 307         unsigned int numbytes;
 308
 309         if (uart_circ_empty(&port->state->xmit)) {
 310                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 311         } else {
 312                 numbytes = port->fifosize;
 313                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 314                        !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
 315                         /*
 316                          * Get the data from the UART circular buffer
 317                          * and write it to the cdns_uart's TX_FIFO
 318                          * register.
 319                          */
 320                         writel(
 321                                 port->state->xmit.buf[port->state->xmit.
 322                                 tail], port->membase + CDNS_UART_FIFO);
 323
 324                         port->icount.tx++;
 325
 326                         /*
 327                          * Adjust the tail of the UART buffer and wrap
 328                          * the buffer if it reaches limit.
 329                          */
 330                         port->state->xmit.tail =
 331                                 (port->state->xmit.tail + 1) &
 332                                         (UART_XMIT_SIZE - 1);
 333
 334                         numbytes--;
 335                 }
 336
 337                 if (uart_circ_chars_pending(
 338                                 &port->state->xmit) < WAKEUP_CHARS)
 339                         uart_write_wakeup(port);
 340         }
 341 }
 342
 343 /**
 344  * cdns_uart_isr - Interrupt handler
 345  * @irq: Irq number
 346  * @dev_id: Id of the port
 347  *
 348  * Return: IRQHANDLED
 349  */
 350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 351 {
 352         struct uart_port *port = (struct uart_port *)dev_id;
 353         unsigned int isrstatus;
 354
 355         spin_lock(&port->lock);
 356
 357         /* Read the interrupt status register to determine which
 358          * interrupt(s) is/are active and clear them.
 359          */
 360         isrstatus = readl(port->membase + CDNS_UART_ISR);
 361         writel(isrstatus, port->membase + CDNS_UART_ISR);
 362
 363         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 364                 cdns_uart_handle_tx(dev_id);
 365                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 366         }
 367         if (isrstatus & CDNS_UART_IXR_MASK)
 368                 cdns_uart_handle_rx(dev_id, isrstatus);
 369
 370         spin_unlock(&port->lock);
 371         return IRQ_HANDLED;
 372 }
 373
 374 /**
 375  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 376  * @clk: UART module input clock
 377  * @baud: Desired baud rate
 378  * @rbdiv: BDIV value (return value)
 379  * @rcd: CD value (return value)
 380  * @div8: Value for clk_sel bit in mod (return value)
 381  * Return: baud rate, requested baud when possible, or actual baud when there
 382  *      was too much error, zero if no valid divisors are found.
 383  *
 384  * Formula to obtain baud rate is
 385  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 386  *      input_clk = (Uart User Defined Clock or Apb Clock)
 387  *              depends on UCLKEN in MR Reg
 388  *      clk = input_clk or input_clk/8;
 389  *              depends on CLKS in MR reg
 390  *      CD and BDIV depends on values in
 391  *                      baud rate generate register
 392  *                      baud rate clock divisor register
 393  */
 394 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 395                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 396 {
 397         u32 cd, bdiv;
 398         unsigned int calc_baud;
 399         unsigned int bestbaud = 0;
 400         unsigned int bauderror;
 401         unsigned int besterror = ~0;
 402
 403         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 404                 *div8 = 1;
 405                 clk /= 8;
 406         } else {
 407                 *div8 = 0;
 408         }
 409
 410         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 411                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 412                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 413                         continue;
 414
 415                 calc_baud = clk / (cd * (bdiv + 1));
 416
 417                 if (baud > calc_baud)
 418                         bauderror = baud - calc_baud;
 419                 else
 420                         bauderror = calc_baud - baud;
 421
 422                 if (besterror > bauderror) {
 423                         *rbdiv = bdiv;
 424                         *rcd = cd;
 425                         bestbaud = calc_baud;
 426                         besterror = bauderror;
 427                 }
 428         }
 429         /* use the values when percent error is acceptable */
 430         if (((besterror * 100) / baud) < 3)
 431                 bestbaud = baud;
 432
 433         return bestbaud;
 434 }
 435
 436 /**
 437  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 438  * @port: Handle to the uart port structure
 439  * @baud: Baud rate to set
 440  * Return: baud rate, requested baud when possible, or actual baud when there
 441  *         was too much error, zero if no valid divisors are found.
 442  */
 443 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 444                 unsigned int baud)
 445 {
 446         unsigned int calc_baud;
 447         u32 cd = 0, bdiv = 0;
 448         u32 mreg;
 449         int div8;
 450         struct cdns_uart *cdns_uart = port->private_data;
 451
 452         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 453                         &div8);
 454
 455         /* Write new divisors to hardware */
 456         mreg = readl(port->membase + CDNS_UART_MR);
 457         if (div8)
 458                 mreg |= CDNS_UART_MR_CLKSEL;
 459         else
 460                 mreg &= ~CDNS_UART_MR_CLKSEL;
 461         writel(mreg, port->membase + CDNS_UART_MR);
 462         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 463         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 464         cdns_uart->baud = baud;
 465
 466         return calc_baud;
 467 }
 468
 469 #ifdef CONFIG_COMMON_CLK
 470 /**
 471  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 472  * @nb:         Notifier block
 473  * @event:      Notify event
 474  * @data:       Notifier data
 475  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 476  */
 477 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 478                 unsigned long event, void *data)
 479 {
 480         u32 ctrl_reg;
 481         struct uart_port *port;
 482         int locked = 0;
 483         struct clk_notifier_data *ndata = data;
 484         unsigned long flags = 0;
 485         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 486
 487         port = cdns_uart->port;
 488         if (port->suspended)
 489                 return NOTIFY_OK;
 490
 491         switch (event) {
 492         case PRE_RATE_CHANGE:
 493         {
 494                 u32 bdiv, cd;
 495                 int div8;
 496
 497                 /*
 498                  * Find out if current baud-rate can be achieved with new clock
 499                  * frequency.
 500                  */
 501                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 502                                         &bdiv, &cd, &div8)) {
 503                         dev_warn(port->dev, "clock rate change rejected\n");
 504                         return NOTIFY_BAD;
 505                 }
 506
 507                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 508
 509                 /* Disable the TX and RX to set baud rate */
 510                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 511                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 512                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 513
 514                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 515
 516                 return NOTIFY_OK;
 517         }
 518         case POST_RATE_CHANGE:
 519                 /*
 520                  * Set clk dividers to generate correct baud with new clock
 521                  * frequency.
 522                  */
 523
 524                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 525
 526                 locked = 1;
 527                 port->uartclk = ndata->new_rate;
 528
 529                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 530                                 cdns_uart->baud);
 531                 /* fall through */
 532         case ABORT_RATE_CHANGE:
 533                 if (!locked)
 534                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 535
 536                 /* Set TX/RX Reset */
 537                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 538                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 539                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 540
 541                 while (readl(port->membase + CDNS_UART_CR) &
 542                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 543                         cpu_relax();
 544
 545                 /*
 546                  * Clear the RX disable and TX disable bits and then set the TX
 547                  * enable bit and RX enable bit to enable the transmitter and
 548                  * receiver.
 549                  */
 550                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 551                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 552                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 553                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 554                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 555
 556                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 557
 558                 return NOTIFY_OK;
 559         default:
 560                 return NOTIFY_DONE;
 561         }
 562 }
 563 #endif
 564
 565 /**
 566  * cdns_uart_start_tx -  Start transmitting bytes
 567  * @port: Handle to the uart port structure
 568  */
 569 static void cdns_uart_start_tx(struct uart_port *port)
 570 {
 571         unsigned int status;
 572
 573         if (uart_tx_stopped(port))
 574                 return;
 575
 576         /*
 577          * Set the TX enable bit and clear the TX disable bit to enable the
 578          * transmitter.
 579          */
 580         status = readl(port->membase + CDNS_UART_CR);
 581         status &= ~CDNS_UART_CR_TX_DIS;
 582         status |= CDNS_UART_CR_TX_EN;
 583         writel(status, port->membase + CDNS_UART_CR);
 584
 585         if (uart_circ_empty(&port->state->xmit))
 586                 return;
 587
 588         cdns_uart_handle_tx(port);
 589
 590         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 591         /* Enable the TX Empty interrupt */
 592         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 593 }
 594
 595 /**
 596  * cdns_uart_stop_tx - Stop TX
 597  * @port: Handle to the uart port structure
 598  */
 599 static void cdns_uart_stop_tx(struct uart_port *port)
 600 {
 601         unsigned int regval;
 602
 603         regval = readl(port->membase + CDNS_UART_CR);
 604         regval |= CDNS_UART_CR_TX_DIS;
 605         /* Disable the transmitter */
 606         writel(regval, port->membase + CDNS_UART_CR);
 607 }
 608
 609 /**
 610  * cdns_uart_stop_rx - Stop RX
 611  * @port: Handle to the uart port structure
 612  */
 613 static void cdns_uart_stop_rx(struct uart_port *port)
 614 {
 615         unsigned int regval;
 616
 617         /* Disable RX IRQs */
 618         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 619
 620         /* Disable the receiver */
 621         regval = readl(port->membase + CDNS_UART_CR);
 622         regval |= CDNS_UART_CR_RX_DIS;
 623         writel(regval, port->membase + CDNS_UART_CR);
 624 }
 625
 626 /**
 627  * cdns_uart_tx_empty -  Check whether TX is empty
 628  * @port: Handle to the uart port structure
 629  *
 630  * Return: TIOCSER_TEMT on success, 0 otherwise
 631  */
 632 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 633 {
 634         unsigned int status;
 635
 636         status = readl(port->membase + CDNS_UART_SR) &
 637                                 CDNS_UART_SR_TXEMPTY;
 638         return status ? TIOCSER_TEMT : 0;
 639 }
 640
 641 /**
 642  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 643  *                      transmitting char breaks
 644  * @port: Handle to the uart port structure
 645  * @ctl: Value based on which start or stop decision is taken
 646  */
 647 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 648 {
 649         unsigned int status;
 650         unsigned long flags;
 651
 652         spin_lock_irqsave(&port->lock, flags);
 653
 654         status = readl(port->membase + CDNS_UART_CR);
 655
 656         if (ctl == -1)
 657                 writel(CDNS_UART_CR_STARTBRK | status,
 658                                 port->membase + CDNS_UART_CR);
 659         else {
 660                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 661                         writel(CDNS_UART_CR_STOPBRK | status,
 662                                         port->membase + CDNS_UART_CR);
 663         }
 664         spin_unlock_irqrestore(&port->lock, flags);
 665 }
 666
 667 /**
 668  * cdns_uart_set_termios - termios operations, handling data length, parity,
 669  *                              stop bits, flow control, baud rate
 670  * @port: Handle to the uart port structure
 671  * @termios: Handle to the input termios structure
 672  * @old: Values of the previously saved termios structure
 673  */
 674 static void cdns_uart_set_termios(struct uart_port *port,
 675                                 struct ktermios *termios, struct ktermios *old)
 676 {
 677         unsigned int cval = 0;
 678         unsigned int baud, minbaud, maxbaud;
 679         unsigned long flags;
 680         unsigned int ctrl_reg, mode_reg;
 681
 682         spin_lock_irqsave(&port->lock, flags);
 683
 684         /* Wait for the transmit FIFO to empty before making changes */
 685         if (!(readl(port->membase + CDNS_UART_CR) &
 686                                 CDNS_UART_CR_TX_DIS)) {
 687                 while (!(readl(port->membase + CDNS_UART_SR) &
 688                                 CDNS_UART_SR_TXEMPTY)) {
 689                         cpu_relax();
 690                 }
 691         }
 692
 693         /* Disable the TX and RX to set baud rate */
 694         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 695         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 696         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 697
 698         /*
 699          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 700          * min and max baud should be calculated here based on port->uartclk.
 701          * this way we get a valid baud and can safely call set_baud()
 702          */
 703         minbaud = port->uartclk /
 704                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 705         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 706         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 707         baud = cdns_uart_set_baud_rate(port, baud);
 708         if (tty_termios_baud_rate(termios))
 709                 tty_termios_encode_baud_rate(termios, baud, baud);
 710
 711         /* Update the per-port timeout. */
 712         uart_update_timeout(port, termios->c_cflag, baud);
 713
 714         /* Set TX/RX Reset */
 715         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 716         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 717         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 718
 719         while (readl(port->membase + CDNS_UART_CR) &
 720                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 721                 cpu_relax();
 722
 723         /*
 724          * Clear the RX disable and TX disable bits and then set the TX enable
 725          * bit and RX enable bit to enable the transmitter and receiver.
 726          */
 727         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 728         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 729         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 730         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 731
 732         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 733
 734         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 735                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 736         port->ignore_status_mask = 0;
 737
 738         if (termios->c_iflag & INPCK)
 739                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 740                 CDNS_UART_IXR_FRAMING;
 741
 742         if (termios->c_iflag & IGNPAR)
 743                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 744                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 745
 746         /* ignore all characters if CREAD is not set */
 747         if ((termios->c_cflag & CREAD) == 0)
 748                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 749                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 750                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 751
 752         mode_reg = readl(port->membase + CDNS_UART_MR);
 753
 754         /* Handling Data Size */
 755         switch (termios->c_cflag & CSIZE) {
 756         case CS6:
 757                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 758                 break;
 759         case CS7:
 760                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 761                 break;
 762         default:
 763         case CS8:
 764                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 765                 termios->c_cflag &= ~CSIZE;
 766                 termios->c_cflag |= CS8;
 767                 break;
 768         }
 769
 770         /* Handling Parity and Stop Bits length */
 771         if (termios->c_cflag & CSTOPB)
 772                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 773         else
 774                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 775
 776         if (termios->c_cflag & PARENB) {
 777                 /* Mark or Space parity */
 778                 if (termios->c_cflag & CMSPAR) {
 779                         if (termios->c_cflag & PARODD)
 780                                 cval |= CDNS_UART_MR_PARITY_MARK;
 781                         else
 782                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 783                 } else {
 784                         if (termios->c_cflag & PARODD)
 785                                 cval |= CDNS_UART_MR_PARITY_ODD;
 786                         else
 787                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 788                 }
 789         } else {
 790                 cval |= CDNS_UART_MR_PARITY_NONE;
 791         }
 792         cval |= mode_reg & 1;
 793         writel(cval, port->membase + CDNS_UART_MR);
 794
 795         spin_unlock_irqrestore(&port->lock, flags);
 796 }
 797
 798 /**
 799  * cdns_uart_startup - Called when an application opens a cdns_uart port
 800  * @port: Handle to the uart port structure
 801  *
 802  * Return: 0 on success, negative errno otherwise
 803  */
 804 static int cdns_uart_startup(struct uart_port *port)
 805 {
 806         struct cdns_uart *cdns_uart = port->private_data;
 807         bool is_brk_support;
 808         int ret;
 809         unsigned long flags;
 810         unsigned int status = 0;
 811
 812         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 813
 814         spin_lock_irqsave(&port->lock, flags);
 815
 816         /* Disable the TX and RX */
 817         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 818                         port->membase + CDNS_UART_CR);
 819
 820         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 821          * no break chars.
 822          */
 823         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 824                         port->membase + CDNS_UART_CR);
 825
 826         while (readl(port->membase + CDNS_UART_CR) &
 827                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 828                 cpu_relax();
 829
 830         /*
 831          * Clear the RX disable bit and then set the RX enable bit to enable
 832          * the receiver.
 833          */
 834         status = readl(port->membase + CDNS_UART_CR);
 835         status &= ~CDNS_UART_CR_RX_DIS;
 836         status |= CDNS_UART_CR_RX_EN;
 837         writel(status, port->membase + CDNS_UART_CR);
 838
 839         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 840          * no parity.
 841          */
 842         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 843                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 844                 port->membase + CDNS_UART_MR);
 845
 846         /*
 847          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 848          * can be tuned with a module parameter
 849          */
 850         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 851
 852         /*
 853          * Receive Timeout register is enabled but it
 854          * can be tuned with a module parameter
 855          */
 856         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 857
 858         /* Clear out any pending interrupts before enabling them */
 859         writel(readl(port->membase + CDNS_UART_ISR),
 860                         port->membase + CDNS_UART_ISR);
 861
 862         spin_unlock_irqrestore(&port->lock, flags);
 863
 864         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 865         if (ret) {
 866                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 867                         port->irq, ret);
 868                 return ret;
 869         }
 870
 871         /* Set the Interrupt Registers with desired interrupts */
 872         if (is_brk_support)
 873                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 874                                         port->membase + CDNS_UART_IER);
 875         else
 876                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 877
 878         return 0;
 879 }
 880
 881 /**
 882  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 883  * @port: Handle to the uart port structure
 884  */
 885 static void cdns_uart_shutdown(struct uart_port *port)
 886 {
 887         int status;
 888         unsigned long flags;
 889
 890         spin_lock_irqsave(&port->lock, flags);
 891
 892         /* Disable interrupts */
 893         status = readl(port->membase + CDNS_UART_IMR);
 894         writel(status, port->membase + CDNS_UART_IDR);
 895         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 896
 897         /* Disable the TX and RX */
 898         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 899                         port->membase + CDNS_UART_CR);
 900
 901         spin_unlock_irqrestore(&port->lock, flags);
 902
 903         free_irq(port->irq, port);
 904 }
 905
 906 /**
 907  * cdns_uart_type - Set UART type to cdns_uart port
 908  * @port: Handle to the uart port structure
 909  *
 910  * Return: string on success, NULL otherwise
 911  */
 912 static const char *cdns_uart_type(struct uart_port *port)
 913 {
 914         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 915 }
 916
 917 /**
 918  * cdns_uart_verify_port - Verify the port params
 919  * @port: Handle to the uart port structure
 920  * @ser: Handle to the structure whose members are compared
 921  *
 922  * Return: 0 on success, negative errno otherwise.
 923  */
 924 static int cdns_uart_verify_port(struct uart_port *port,
 925                                         struct serial_struct *ser)
 926 {
 927         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 928                 return -EINVAL;
 929         if (port->irq != ser->irq)
 930                 return -EINVAL;
 931         if (ser->io_type != UPIO_MEM)
 932                 return -EINVAL;
 933         if (port->iobase != ser->port)
 934                 return -EINVAL;
 935         if (ser->hub6 != 0)
 936                 return -EINVAL;
 937         return 0;
 938 }
 939
 940 /**
 941  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 942  *                              called when the driver adds a cdns_uart port via
 943  *                              uart_add_one_port()
 944  * @port: Handle to the uart port structure
 945  *
 946  * Return: 0 on success, negative errno otherwise.
 947  */
 948 static int cdns_uart_request_port(struct uart_port *port)
 949 {
 950         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 951                                          CDNS_UART_NAME)) {
 952                 return -ENOMEM;
 953         }
 954
 955         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 956         if (!port->membase) {
 957                 dev_err(port->dev, "Unable to map registers\n");
 958                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 959                 return -ENOMEM;
 960         }
 961         return 0;
 962 }
 963
 964 /**
 965  * cdns_uart_release_port - Release UART port
 966  * @port: Handle to the uart port structure
 967  *
 968  * Release the memory region attached to a cdns_uart port. Called when the
 969  * driver removes a cdns_uart port via uart_remove_one_port().
 970  */
 971 static void cdns_uart_release_port(struct uart_port *port)
 972 {
 973         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 974         iounmap(port->membase);
 975         port->membase = NULL;
 976 }
 977
 978 /**
 979  * cdns_uart_config_port - Configure UART port
 980  * @port: Handle to the uart port structure
 981  * @flags: If any
 982  */
 983 static void cdns_uart_config_port(struct uart_port *port, int flags)
 984 {
 985         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 986                 port->type = PORT_XUARTPS;
 987 }
 988
 989 /**
 990  * cdns_uart_get_mctrl - Get the modem control state
 991  * @port: Handle to the uart port structure
 992  *
 993  * Return: the modem control state
 994  */
 995 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
 996 {
 997         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 998 }
 999
1000 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1001 {
1002         u32 val;
1003         u32 mode_reg;
1004
1005         val = readl(port->membase + CDNS_UART_MODEMCR);
1006         mode_reg = readl(port->membase + CDNS_UART_MR);
1007
1008         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1009         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1010
1011         if (mctrl & TIOCM_RTS)
1012                 val |= CDNS_UART_MODEMCR_RTS;
1013         if (mctrl & TIOCM_DTR)
1014                 val |= CDNS_UART_MODEMCR_DTR;
1015         if (mctrl & TIOCM_LOOP)
1016                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1017         else
1018                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1019
1020         writel(val, port->membase + CDNS_UART_MODEMCR);
1021         writel(mode_reg, port->membase + CDNS_UART_MR);
1022 }
1023
1024 #ifdef CONFIG_CONSOLE_POLL
1025 static int cdns_uart_poll_get_char(struct uart_port *port)
1026 {
1027         int c;
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&port->lock, flags);
1031
1032         /* Check if FIFO is empty */
1033         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1034                 c = NO_POLL_CHAR;
1035         else /* Read a character */
1036                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1037
1038         spin_unlock_irqrestore(&port->lock, flags);
1039
1040         return c;
1041 }
1042
1043 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1044 {
1045         unsigned long flags;
1046
1047         spin_lock_irqsave(&port->lock, flags);
1048
1049         /* Wait until FIFO is empty */
1050         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1051                 cpu_relax();
1052
1053         /* Write a character */
1054         writel(c, port->membase + CDNS_UART_FIFO);
1055
1056         /* Wait until FIFO is empty */
1057         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1058                 cpu_relax();
1059
1060         spin_unlock_irqrestore(&port->lock, flags);
1061
1062         return;
1063 }
1064 #endif
1065
1066 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1067                    unsigned int oldstate)
1068 {
1069         switch (state) {
1070         case UART_PM_STATE_OFF:
1071                 pm_runtime_mark_last_busy(port->dev);
1072                 pm_runtime_put_autosuspend(port->dev);
1073                 break;
1074         default:
1075                 pm_runtime_get_sync(port->dev);
1076                 break;
1077         }
1078 }
1079
1080 static const struct uart_ops cdns_uart_ops = {
1081         .set_mctrl      = cdns_uart_set_mctrl,
1082         .get_mctrl      = cdns_uart_get_mctrl,
1083         .start_tx       = cdns_uart_start_tx,
1084         .stop_tx        = cdns_uart_stop_tx,
1085         .stop_rx        = cdns_uart_stop_rx,
1086         .tx_empty       = cdns_uart_tx_empty,
1087         .break_ctl      = cdns_uart_break_ctl,
1088         .set_termios    = cdns_uart_set_termios,
1089         .startup        = cdns_uart_startup,
1090         .shutdown       = cdns_uart_shutdown,
1091         .pm             = cdns_uart_pm,
1092         .type           = cdns_uart_type,
1093         .verify_port    = cdns_uart_verify_port,
1094         .request_port   = cdns_uart_request_port,
1095         .release_port   = cdns_uart_release_port,
1096         .config_port    = cdns_uart_config_port,
1097 #ifdef CONFIG_CONSOLE_POLL
1098         .poll_get_char  = cdns_uart_poll_get_char,
1099         .poll_put_char  = cdns_uart_poll_put_char,
1100 #endif
1101 };
1102
1103 static struct uart_driver cdns_uart_uart_driver;
1104
1105 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1106 /**
1107  * cdns_uart_console_putchar - write the character to the FIFO buffer
1108  * @port: Handle to the uart port structure
1109  * @ch: Character to be written
1110  */
1111 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1112 {
1113         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1114                 cpu_relax();
1115         writel(ch, port->membase + CDNS_UART_FIFO);
1116 }
1117
1118 static void cdns_early_write(struct console *con, const char *s,
1119                                     unsigned n)
1120 {
1121         struct earlycon_device *dev = con->data;
1122
1123         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1124 }
1125
1126 static int __init cdns_early_console_setup(struct earlycon_device *device,
1127                                            const char *opt)
1128 {
1129         struct uart_port *port = &device->port;
1130
1131         if (!port->membase)
1132                 return -ENODEV;
1133
1134         /* initialise control register */
1135         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1136                port->membase + CDNS_UART_CR);
1137
1138         /* only set baud if specified on command line - otherwise
1139          * assume it has been initialized by a boot loader.
1140          */
1141         if (port->uartclk && device->baud) {
1142                 u32 cd = 0, bdiv = 0;
1143                 u32 mr;
1144                 int div8;
1145
1146                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1147                                          &bdiv, &cd, &div8);
1148                 mr = CDNS_UART_MR_PARITY_NONE;
1149                 if (div8)
1150                         mr |= CDNS_UART_MR_CLKSEL;
1151
1152                 writel(mr,   port->membase + CDNS_UART_MR);
1153                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1154                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1155         }
1156
1157         device->con->write = cdns_early_write;
1158
1159         return 0;
1160 }
1161 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1162 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1163 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1164 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1165
1166
1167 /* Static pointer to console port */
1168 static struct uart_port *console_port;
1169
1170 /**
1171  * cdns_uart_console_write - perform write operation
1172  * @co: Console handle
1173  * @s: Pointer to character array
1174  * @count: No of characters
1175  */
1176 static void cdns_uart_console_write(struct console *co, const char *s,
1177                                 unsigned int count)
1178 {
1179         struct uart_port *port = console_port;
1180         unsigned long flags;
1181         unsigned int imr, ctrl;
1182         int locked = 1;
1183
1184         if (port->sysrq)
1185                 locked = 0;
1186         else if (oops_in_progress)
1187                 locked = spin_trylock_irqsave(&port->lock, flags);
1188         else
1189                 spin_lock_irqsave(&port->lock, flags);
1190
1191         /* save and disable interrupt */
1192         imr = readl(port->membase + CDNS_UART_IMR);
1193         writel(imr, port->membase + CDNS_UART_IDR);
1194
1195         /*
1196          * Make sure that the tx part is enabled. Set the TX enable bit and
1197          * clear the TX disable bit to enable the transmitter.
1198          */
1199         ctrl = readl(port->membase + CDNS_UART_CR);
1200         ctrl &= ~CDNS_UART_CR_TX_DIS;
1201         ctrl |= CDNS_UART_CR_TX_EN;
1202         writel(ctrl, port->membase + CDNS_UART_CR);
1203
1204         uart_console_write(port, s, count, cdns_uart_console_putchar);
1205         while ((readl(port->membase + CDNS_UART_SR) &
1206                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1207                         CDNS_UART_SR_TXEMPTY)
1208                 cpu_relax();
1209
1210         /* restore interrupt state */
1211         writel(imr, port->membase + CDNS_UART_IER);
1212
1213         if (locked)
1214                 spin_unlock_irqrestore(&port->lock, flags);
1215 }
1216
1217 /**
1218  * cdns_uart_console_setup - Initialize the uart to default config
1219  * @co: Console handle
1220  * @options: Initial settings of uart
1221  *
1222  * Return: 0 on success, negative errno otherwise.
1223  */
1224 static int cdns_uart_console_setup(struct console *co, char *options)
1225 {
1226         struct uart_port *port = console_port;
1227
1228         int baud = 9600;
1229         int bits = 8;
1230         int parity = 'n';
1231         int flow = 'n';
1232
1233         if (!port->membase) {
1234                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1235                          co->index);
1236                 return -ENODEV;
1237         }
1238
1239         if (options)
1240                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1241
1242         return uart_set_options(port, co, baud, parity, bits, flow);
1243 }
1244
1245 static struct console cdns_uart_console = {
1246         .name   = CDNS_UART_TTY_NAME,
1247         .write  = cdns_uart_console_write,
1248         .device = uart_console_device,
1249         .setup  = cdns_uart_console_setup,
1250         .flags  = CON_PRINTBUFFER,
1251         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1252         .data   = &cdns_uart_uart_driver,
1253 };
1254 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1255
1256 #ifdef CONFIG_PM_SLEEP
1257 /**
1258  * cdns_uart_suspend - suspend event
1259  * @device: Pointer to the device structure
1260  *
1261  * Return: 0
1262  */
1263 static int cdns_uart_suspend(struct device *device)
1264 {
1265         struct uart_port *port = dev_get_drvdata(device);
1266         struct cdns_uart *cdns_uart = port->private_data;
1267         int may_wake;
1268
1269         may_wake = device_may_wakeup(device);
1270
1271         if (console_suspend_enabled && may_wake) {
1272                 unsigned long flags = 0;
1273
1274                 spin_lock_irqsave(&port->lock, flags);
1275                 /* Empty the receive FIFO 1st before making changes */
1276                 while (!(readl(port->membase + CDNS_UART_SR) &
1277                                         CDNS_UART_SR_RXEMPTY))
1278                         readl(port->membase + CDNS_UART_FIFO);
1279                 /* set RX trigger level to 1 */
1280                 writel(1, port->membase + CDNS_UART_RXWM);
1281                 /* disable RX timeout interrups */
1282                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1283                 spin_unlock_irqrestore(&port->lock, flags);
1284         }
1285
1286         /*
1287          * Call the API provided in serial_core.c file which handles
1288          * the suspend.
1289          */
1290         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1291 }
1292
1293 /**
1294  * cdns_uart_resume - Resume after a previous suspend
1295  * @device: Pointer to the device structure
1296  *
1297  * Return: 0
1298  */
1299 static int cdns_uart_resume(struct device *device)
1300 {
1301         struct uart_port *port = dev_get_drvdata(device);
1302         struct cdns_uart *cdns_uart = port->private_data;
1303         unsigned long flags = 0;
1304         u32 ctrl_reg;
1305         int may_wake;
1306
1307         may_wake = device_may_wakeup(device);
1308
1309         if (console_suspend_enabled && !may_wake) {
1310                 clk_enable(cdns_uart->pclk);
1311                 clk_enable(cdns_uart->uartclk);
1312
1313                 spin_lock_irqsave(&port->lock, flags);
1314
1315                 /* Set TX/RX Reset */
1316                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1317                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1318                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1319                 while (readl(port->membase + CDNS_UART_CR) &
1320                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1321                         cpu_relax();
1322
1323                 /* restore rx timeout value */
1324                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1325                 /* Enable Tx/Rx */
1326                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1327                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1328                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1329                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1330
1331                 clk_disable(cdns_uart->uartclk);
1332                 clk_disable(cdns_uart->pclk);
1333                 spin_unlock_irqrestore(&port->lock, flags);
1334         } else {
1335                 spin_lock_irqsave(&port->lock, flags);
1336                 /* restore original rx trigger level */
1337                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1338                 /* enable RX timeout interrupt */
1339                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1340                 spin_unlock_irqrestore(&port->lock, flags);
1341         }
1342
1343         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1344 }
1345 #endif /* ! CONFIG_PM_SLEEP */
1346 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1347 {
1348         struct uart_port *port = dev_get_drvdata(dev);
1349         struct cdns_uart *cdns_uart = port->private_data;
1350
1351         clk_disable(cdns_uart->uartclk);
1352         clk_disable(cdns_uart->pclk);
1353         return 0;
1354 };
1355
1356 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1357 {
1358         struct uart_port *port = dev_get_drvdata(dev);
1359         struct cdns_uart *cdns_uart = port->private_data;
1360
1361         clk_enable(cdns_uart->pclk);
1362         clk_enable(cdns_uart->uartclk);
1363         return 0;
1364 };
1365
1366 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1367         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1368         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1369                            cdns_runtime_resume, NULL)
1370 };
1371
1372 static const struct cdns_platform_data zynqmp_uart_def = {
1373                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1374
1375 /* Match table for of_platform binding */
1376 static const struct of_device_id cdns_uart_of_match[] = {
1377         { .compatible = "xlnx,xuartps", },
1378         { .compatible = "cdns,uart-r1p8", },
1379         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1380         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1381         {}
1382 };
1383 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1384
1385 /* Temporary variable for storing number of instances */
1386 static int instances;
1387
1388 /**
1389  * cdns_uart_probe - Platform driver probe
1390  * @pdev: Pointer to the platform device structure
1391  *
1392  * Return: 0 on success, negative errno otherwise
1393  */
1394 static int cdns_uart_probe(struct platform_device *pdev)
1395 {
1396         int rc, id, irq;
1397         struct uart_port *port;
1398         struct resource *res;
1399         struct cdns_uart *cdns_uart_data;
1400         const struct of_device_id *match;
1401
1402         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1403                         GFP_KERNEL);
1404         if (!cdns_uart_data)
1405                 return -ENOMEM;
1406         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1407         if (!port)
1408                 return -ENOMEM;
1409
1410         /* Look for a serialN alias */
1411         id = of_alias_get_id(pdev->dev.of_node, "serial");
1412         if (id < 0)
1413                 id = 0;
1414
1415         if (id >= CDNS_UART_NR_PORTS) {
1416                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1417                 return -ENODEV;
1418         }
1419
1420         if (!cdns_uart_uart_driver.state) {
1421                 cdns_uart_uart_driver.owner = THIS_MODULE;
1422                 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1423                 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1424                 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1425                 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1426                 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1427 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1428                 cdns_uart_uart_driver.cons = &cdns_uart_console;
1429 #endif
1430
1431                 rc = uart_register_driver(&cdns_uart_uart_driver);
1432                 if (rc < 0) {
1433                         dev_err(&pdev->dev, "Failed to register driver\n");
1434                         return rc;
1435                 }
1436         }
1437
1438         cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1439
1440         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1441         if (match && match->data) {
1442                 const struct cdns_platform_data *data = match->data;
1443
1444                 cdns_uart_data->quirks = data->quirks;
1445         }
1446
1447         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1448         if (IS_ERR(cdns_uart_data->pclk)) {
1449                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1450                 if (!IS_ERR(cdns_uart_data->pclk))
1451                         dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1452         }
1453         if (IS_ERR(cdns_uart_data->pclk)) {
1454                 dev_err(&pdev->dev, "pclk clock not found.\n");
1455                 rc = PTR_ERR(cdns_uart_data->pclk);
1456                 goto err_out_unregister_driver;
1457         }
1458
1459         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1460         if (IS_ERR(cdns_uart_data->uartclk)) {
1461                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1462                 if (!IS_ERR(cdns_uart_data->uartclk))
1463                         dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1464         }
1465         if (IS_ERR(cdns_uart_data->uartclk)) {
1466                 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1467                 rc = PTR_ERR(cdns_uart_data->uartclk);
1468                 goto err_out_unregister_driver;
1469         }
1470
1471         rc = clk_prepare_enable(cdns_uart_data->pclk);
1472         if (rc) {
1473                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1474                 goto err_out_unregister_driver;
1475         }
1476         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1477         if (rc) {
1478                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1479                 goto err_out_clk_dis_pclk;
1480         }
1481
1482         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1483         if (!res) {
1484                 rc = -ENODEV;
1485                 goto err_out_clk_disable;
1486         }
1487
1488         irq = platform_get_irq(pdev, 0);
1489         if (irq <= 0) {
1490                 rc = -ENXIO;
1491                 goto err_out_clk_disable;
1492         }
1493
1494 #ifdef CONFIG_COMMON_CLK
1495         cdns_uart_data->clk_rate_change_nb.notifier_call =
1496                         cdns_uart_clk_notifier_cb;
1497         if (clk_notifier_register(cdns_uart_data->uartclk,
1498                                 &cdns_uart_data->clk_rate_change_nb))
1499                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1500 #endif
1501
1502         /* At this point, we've got an empty uart_port struct, initialize it */
1503         spin_lock_init(&port->lock);
1504         port->type      = PORT_UNKNOWN;
1505         port->iotype    = UPIO_MEM32;
1506         port->flags     = UPF_BOOT_AUTOCONF;
1507         port->ops       = &cdns_uart_ops;
1508         port->fifosize  = CDNS_UART_FIFO_SIZE;
1509         port->line      = id;
1510
1511         /*
1512          * Register the port.
1513          * This function also registers this device with the tty layer
1514          * and triggers invocation of the config_port() entry point.
1515          */
1516         port->mapbase = res->start;
1517         port->irq = irq;
1518         port->dev = &pdev->dev;
1519         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1520         port->private_data = cdns_uart_data;
1521         cdns_uart_data->port = port;
1522         platform_set_drvdata(pdev, port);
1523
1524         pm_runtime_use_autosuspend(&pdev->dev);
1525         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1526         pm_runtime_set_active(&pdev->dev);
1527         pm_runtime_enable(&pdev->dev);
1528
1529 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1530         /*
1531          * If console hasn't been found yet try to assign this port
1532          * because it is required to be assigned for console setup function.
1533          * If register_console() don't assign value, then console_port pointer
1534          * is cleanup.
1535          */
1536         if (!console_port)
1537                 console_port = port;
1538 #endif
1539
1540         rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1541         if (rc) {
1542                 dev_err(&pdev->dev,
1543                         "uart_add_one_port() failed; err=%i\n", rc);
1544                 goto err_out_pm_disable;
1545         }
1546
1547 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1548         /* This is not port which is used for console that's why clean it up */
1549         if (console_port == port &&
1550             !(cdns_uart_uart_driver.cons->flags & CON_ENABLED))
1551                 console_port = NULL;
1552 #endif
1553
1554         instances++;
1555         return 0;
1556
1557 err_out_pm_disable:
1558         pm_runtime_disable(&pdev->dev);
1559         pm_runtime_set_suspended(&pdev->dev);
1560         pm_runtime_dont_use_autosuspend(&pdev->dev);
1561 #ifdef CONFIG_COMMON_CLK
1562         clk_notifier_unregister(cdns_uart_data->uartclk,
1563                         &cdns_uart_data->clk_rate_change_nb);
1564 #endif
1565 err_out_clk_disable:
1566         clk_disable_unprepare(cdns_uart_data->uartclk);
1567 err_out_clk_dis_pclk:
1568         clk_disable_unprepare(cdns_uart_data->pclk);
1569 err_out_unregister_driver:
1570         if (!instances)
1571                 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1572         return rc;
1573 }
1574
1575 /**
1576  * cdns_uart_remove - called when the platform driver is unregistered
1577  * @pdev: Pointer to the platform device structure
1578  *
1579  * Return: 0 on success, negative errno otherwise
1580  */
1581 static int cdns_uart_remove(struct platform_device *pdev)
1582 {
1583         struct uart_port *port = platform_get_drvdata(pdev);
1584         struct cdns_uart *cdns_uart_data = port->private_data;
1585         int rc;
1586
1587         /* Remove the cdns_uart port from the serial core */
1588 #ifdef CONFIG_COMMON_CLK
1589         clk_notifier_unregister(cdns_uart_data->uartclk,
1590                         &cdns_uart_data->clk_rate_change_nb);
1591 #endif
1592         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1593         port->mapbase = 0;
1594         clk_disable_unprepare(cdns_uart_data->uartclk);
1595         clk_disable_unprepare(cdns_uart_data->pclk);
1596         pm_runtime_disable(&pdev->dev);
1597         pm_runtime_set_suspended(&pdev->dev);
1598         pm_runtime_dont_use_autosuspend(&pdev->dev);
1599
1600 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1601         if (console_port == port)
1602                 console_port = NULL;
1603 #endif
1604
1605         if (!--instances)
1606                 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1607         return rc;
1608 }
1609
1610 static struct platform_driver cdns_uart_platform_driver = {
1611         .probe   = cdns_uart_probe,
1612         .remove  = cdns_uart_remove,
1613         .driver  = {
1614                 .name = CDNS_UART_NAME,
1615                 .of_match_table = cdns_uart_of_match,
1616                 .pm = &cdns_uart_dev_pm_ops,
1617                 },
1618 };
1619
1620 static int __init cdns_uart_init(void)
1621 {
1622         /* Register the platform driver */
1623         return platform_driver_register(&cdns_uart_platform_driver);
1624 }
1625
1626 static void __exit cdns_uart_exit(void)
1627 {
1628         /* Unregister the platform driver */
1629         platform_driver_unregister(&cdns_uart_platform_driver);
1630 }
1631
1632 arch_initcall(cdns_uart_init);
1633 module_exit(cdns_uart_exit);
1634
1635 MODULE_DESCRIPTION("Driver for Cadence UART");
1636 MODULE_AUTHOR("Xilinx Inc.");
1637 MODULE_LICENSE("GPL");