1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/scatterlist.h>
41 #include <linux/serial.h>
42 #include <linux/serial_sci.h>
43 #include <linux/sh_dma.h>
44 #include <linux/slab.h>
45 #include <linux/string.h>
46 #include <linux/sysrq.h>
47 #include <linux/timer.h>
48 #include <linux/tty.h>
49 #include <linux/tty_flip.h>
52 #include <asm/sh_bios.h>
53 #include <asm/platform_early.h>
56 #include "serial_mctrl_gpio.h"
59 /* Offsets into the sci_port->irqs array */
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79 SCI_FCK, /* Functional Clock */
80 SCI_SCK, /* Optional External Clock */
81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 /* Bit x set means sampling rate x + 1 is supported */
87 #define SCI_SR(x) BIT((x) - 1)
88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
94 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
95 #define max_sr(_port) fls((_port)->sampling_rate_mask)
97 /* Iterate over all supported sampling rates, from high to low */
98 #define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102 struct plat_sci_reg {
106 struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
117 struct uart_port port;
119 /* Platform configuration */
120 const struct sci_port_params *params;
121 const struct plat_sci_port *cfg;
122 unsigned int sampling_rate_mask;
123 resource_size_t reg_size;
124 struct mctrl_gpios *gpios;
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
130 int irqs[SCIx_NR_IRQS];
131 char *irqstr[SCIx_NR_IRQS];
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
136 #ifdef CONFIG_SERIAL_SH_SCI_DMA
137 struct dma_chan *chan_tx_saved;
138 struct dma_chan *chan_rx_saved;
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
147 struct work_struct work_tx;
148 struct hrtimer rx_timer;
149 unsigned int rx_timeout; /* microseconds */
151 unsigned int rx_frame;
153 struct timer_list rx_fifo_timer;
161 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163 static struct sci_port sci_ports[SCI_NPORTS];
164 static unsigned long sci_ports_in_use;
165 static struct uart_driver sci_uart_driver;
167 static inline struct sci_port *
168 to_sci_port(struct uart_port *uart)
170 return container_of(uart, struct sci_port, port);
173 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 * Common SCI definitions, dependent on the port's regshift
178 [SCIx_SCI_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCI_ORER,
190 .sampling_rate_mask = SCI_SR(32),
191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 * Common definitions for legacy IrDA ports.
198 [SCIx_IRDA_REGTYPE] = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x02, 8 },
202 [SCSCR] = { 0x04, 8 },
203 [SCxTDR] = { 0x06, 8 },
204 [SCxSR] = { 0x08, 16 },
205 [SCxRDR] = { 0x0a, 8 },
206 [SCFCR] = { 0x0c, 8 },
207 [SCFDR] = { 0x0e, 16 },
210 .overrun_reg = SCxSR,
211 .overrun_mask = SCI_ORER,
212 .sampling_rate_mask = SCI_SR(32),
213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 * Common SCIFA definitions.
220 [SCIx_SCIFA_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x20, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x24, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = { 0x1c, 16 },
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
234 .overrun_reg = SCxSR,
235 .overrun_mask = SCIFA_ORER,
236 .sampling_rate_mask = SCI_SR_SCIFAB,
237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 * Common SCIFB definitions.
244 [SCIx_SCIFB_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCTFDR] = { 0x38, 16 },
254 [SCRFDR] = { 0x3c, 16 },
255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
259 .overrun_reg = SCxSR,
260 .overrun_mask = SCIFA_ORER,
261 .sampling_rate_mask = SCI_SR_SCIFAB,
262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 * Common SH-2(A) SCIF definitions for ports with FIFO data
270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
284 .overrun_reg = SCLSR,
285 .overrun_mask = SCLSR_ORER,
286 .sampling_rate_mask = SCI_SR(32),
287 .error_mask = SCIF_DEFAULT_ERROR_MASK,
288 .error_clear = SCIF_ERROR_CLEAR,
292 * The "SCIFA" that is in RZ/T and RZ/A2.
293 * It looks like a normal SCIF with FIFO data, but with a
294 * compressed address space. Also, the break out of interrupts
295 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 [SCIx_RZ_SCIFA_REGTYPE] = {
299 [SCSMR] = { 0x00, 16 },
300 [SCBRR] = { 0x02, 8 },
301 [SCSCR] = { 0x04, 16 },
302 [SCxTDR] = { 0x06, 8 },
303 [SCxSR] = { 0x08, 16 },
304 [SCxRDR] = { 0x0A, 8 },
305 [SCFCR] = { 0x0C, 16 },
306 [SCFDR] = { 0x0E, 16 },
307 [SCSPTR] = { 0x10, 16 },
308 [SCLSR] = { 0x12, 16 },
311 .overrun_reg = SCLSR,
312 .overrun_mask = SCLSR_ORER,
313 .sampling_rate_mask = SCI_SR(32),
314 .error_mask = SCIF_DEFAULT_ERROR_MASK,
315 .error_clear = SCIF_ERROR_CLEAR,
319 * Common SH-3 SCIF definitions.
321 [SCIx_SH3_SCIF_REGTYPE] = {
323 [SCSMR] = { 0x00, 8 },
324 [SCBRR] = { 0x02, 8 },
325 [SCSCR] = { 0x04, 8 },
326 [SCxTDR] = { 0x06, 8 },
327 [SCxSR] = { 0x08, 16 },
328 [SCxRDR] = { 0x0a, 8 },
329 [SCFCR] = { 0x0c, 8 },
330 [SCFDR] = { 0x0e, 16 },
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
341 * Common SH-4(A) SCIF(B) definitions.
343 [SCIx_SH4_SCIF_REGTYPE] = {
345 [SCSMR] = { 0x00, 16 },
346 [SCBRR] = { 0x04, 8 },
347 [SCSCR] = { 0x08, 16 },
348 [SCxTDR] = { 0x0c, 8 },
349 [SCxSR] = { 0x10, 16 },
350 [SCxRDR] = { 0x14, 8 },
351 [SCFCR] = { 0x18, 16 },
352 [SCFDR] = { 0x1c, 16 },
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
357 .overrun_reg = SCLSR,
358 .overrun_mask = SCLSR_ORER,
359 .sampling_rate_mask = SCI_SR(32),
360 .error_mask = SCIF_DEFAULT_ERROR_MASK,
361 .error_clear = SCIF_ERROR_CLEAR,
365 * Common SCIF definitions for ports with a Baud Rate Generator for
366 * External Clock (BRG).
368 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR(32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
392 * Common HSCIF definitions.
394 [SCIx_HSCIF_REGTYPE] = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCSPTR] = { 0x20, 16 },
405 [SCLSR] = { 0x24, 16 },
406 [HSSRR] = { 0x40, 16 },
407 [SCDL] = { 0x30, 16 },
408 [SCCKS] = { 0x34, 16 },
409 [HSRTRGR] = { 0x54, 16 },
410 [HSTTRGR] = { 0x58, 16 },
413 .overrun_reg = SCLSR,
414 .overrun_mask = SCLSR_ORER,
415 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
416 .error_mask = SCIF_DEFAULT_ERROR_MASK,
417 .error_clear = SCIF_ERROR_CLEAR,
421 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
426 [SCSMR] = { 0x00, 16 },
427 [SCBRR] = { 0x04, 8 },
428 [SCSCR] = { 0x08, 16 },
429 [SCxTDR] = { 0x0c, 8 },
430 [SCxSR] = { 0x10, 16 },
431 [SCxRDR] = { 0x14, 8 },
432 [SCFCR] = { 0x18, 16 },
433 [SCFDR] = { 0x1c, 16 },
434 [SCLSR] = { 0x24, 16 },
437 .overrun_reg = SCLSR,
438 .overrun_mask = SCLSR_ORER,
439 .sampling_rate_mask = SCI_SR(32),
440 .error_mask = SCIF_DEFAULT_ERROR_MASK,
441 .error_clear = SCIF_ERROR_CLEAR,
445 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
450 [SCSMR] = { 0x00, 16 },
451 [SCBRR] = { 0x04, 8 },
452 [SCSCR] = { 0x08, 16 },
453 [SCxTDR] = { 0x0c, 8 },
454 [SCxSR] = { 0x10, 16 },
455 [SCxRDR] = { 0x14, 8 },
456 [SCFCR] = { 0x18, 16 },
457 [SCFDR] = { 0x1c, 16 },
458 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
459 [SCRFDR] = { 0x20, 16 },
460 [SCSPTR] = { 0x24, 16 },
461 [SCLSR] = { 0x28, 16 },
464 .overrun_reg = SCLSR,
465 .overrun_mask = SCLSR_ORER,
466 .sampling_rate_mask = SCI_SR(32),
467 .error_mask = SCIF_DEFAULT_ERROR_MASK,
468 .error_clear = SCIF_ERROR_CLEAR,
472 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 [SCIx_SH7705_SCIF_REGTYPE] = {
477 [SCSMR] = { 0x00, 16 },
478 [SCBRR] = { 0x04, 8 },
479 [SCSCR] = { 0x08, 16 },
480 [SCxTDR] = { 0x20, 8 },
481 [SCxSR] = { 0x14, 16 },
482 [SCxRDR] = { 0x24, 8 },
483 [SCFCR] = { 0x18, 16 },
484 [SCFDR] = { 0x1c, 16 },
487 .overrun_reg = SCxSR,
488 .overrun_mask = SCIFA_ORER,
489 .sampling_rate_mask = SCI_SR(16),
490 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
491 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498 * The "offset" here is rather misleading, in that it refers to an enum
499 * value relative to the port mapping rather than the fixed offset
500 * itself, which needs to be manually retrieved from the platform's
501 * register map for the given port.
503 static unsigned int sci_serial_in(struct uart_port *p, int offset)
505 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508 return ioread8(p->membase + (reg->offset << p->regshift));
509 else if (reg->size == 16)
510 return ioread16(p->membase + (reg->offset << p->regshift));
512 WARN(1, "Invalid register access\n");
517 static void sci_serial_out(struct uart_port *p, int offset, int value)
519 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522 iowrite8(value, p->membase + (reg->offset << p->regshift));
523 else if (reg->size == 16)
524 iowrite16(value, p->membase + (reg->offset << p->regshift));
526 WARN(1, "Invalid register access\n");
529 static void sci_port_enable(struct sci_port *sci_port)
533 if (!sci_port->port.dev)
536 pm_runtime_get_sync(sci_port->port.dev);
538 for (i = 0; i < SCI_NUM_CLKS; i++) {
539 clk_prepare_enable(sci_port->clks[i]);
540 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
542 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545 static void sci_port_disable(struct sci_port *sci_port)
549 if (!sci_port->port.dev)
552 for (i = SCI_NUM_CLKS; i-- > 0; )
553 clk_disable_unprepare(sci_port->clks[i]);
555 pm_runtime_put_sync(sci_port->port.dev);
558 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561 * Not all ports (such as SCIFA) will support REIE. Rather than
562 * special-casing the port type, we check the port initialization
563 * IRQ enable mask to see whether the IRQ is desired at all. If
564 * it's unset, it's logically inferred that there's no point in
567 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570 static void sci_start_tx(struct uart_port *port)
572 struct sci_port *s = to_sci_port(port);
575 #ifdef CONFIG_SERIAL_SH_SCI_DMA
576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 u16 new, scr = serial_port_in(port, SCSCR);
579 new = scr | SCSCR_TDRQE;
581 new = scr & ~SCSCR_TDRQE;
583 serial_port_out(port, SCSCR, new);
586 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
587 dma_submit_error(s->cookie_tx)) {
589 schedule_work(&s->work_tx);
593 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
594 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
595 ctrl = serial_port_in(port, SCSCR);
596 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 static void sci_stop_tx(struct uart_port *port)
604 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
605 ctrl = serial_port_in(port, SCSCR);
607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
608 ctrl &= ~SCSCR_TDRQE;
612 serial_port_out(port, SCSCR, ctrl);
615 static void sci_start_rx(struct uart_port *port)
619 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
621 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
622 ctrl &= ~SCSCR_RDRQE;
624 serial_port_out(port, SCSCR, ctrl);
627 static void sci_stop_rx(struct uart_port *port)
631 ctrl = serial_port_in(port, SCSCR);
633 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
634 ctrl &= ~SCSCR_RDRQE;
636 ctrl &= ~port_rx_irq_mask(port);
638 serial_port_out(port, SCSCR, ctrl);
641 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
643 if (port->type == PORT_SCI) {
644 /* Just store the mask */
645 serial_port_out(port, SCxSR, mask);
646 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
647 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
648 /* Only clear the status bits we want to clear */
649 serial_port_out(port, SCxSR,
650 serial_port_in(port, SCxSR) & mask);
652 /* Store the mask, clear parity/framing errors */
653 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
658 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
660 #ifdef CONFIG_CONSOLE_POLL
661 static int sci_poll_get_char(struct uart_port *port)
663 unsigned short status;
667 status = serial_port_in(port, SCxSR);
668 if (status & SCxSR_ERRORS(port)) {
669 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
675 if (!(status & SCxSR_RDxF(port)))
678 c = serial_port_in(port, SCxRDR);
681 serial_port_in(port, SCxSR);
682 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
688 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
690 unsigned short status;
693 status = serial_port_in(port, SCxSR);
694 } while (!(status & SCxSR_TDxE(port)));
696 serial_port_out(port, SCxTDR, c);
697 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
699 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
700 CONFIG_SERIAL_SH_SCI_EARLYCON */
702 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
704 struct sci_port *s = to_sci_port(port);
707 * Use port-specific handler if provided.
709 if (s->cfg->ops && s->cfg->ops->init_pins) {
710 s->cfg->ops->init_pins(port, cflag);
714 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
715 u16 data = serial_port_in(port, SCPDR);
716 u16 ctrl = serial_port_in(port, SCPCR);
718 /* Enable RXD and TXD pin functions */
719 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
720 if (to_sci_port(port)->has_rtscts) {
721 /* RTS# is output, active low, unless autorts */
722 if (!(port->mctrl & TIOCM_RTS)) {
725 } else if (!s->autorts) {
729 /* Enable RTS# pin function */
732 /* Enable CTS# pin function */
735 serial_port_out(port, SCPDR, data);
736 serial_port_out(port, SCPCR, ctrl);
737 } else if (sci_getreg(port, SCSPTR)->size) {
738 u16 status = serial_port_in(port, SCSPTR);
740 /* RTS# is always output; and active low, unless autorts */
741 status |= SCSPTR_RTSIO;
742 if (!(port->mctrl & TIOCM_RTS))
743 status |= SCSPTR_RTSDT;
744 else if (!s->autorts)
745 status &= ~SCSPTR_RTSDT;
746 /* CTS# and SCK are inputs */
747 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
748 serial_port_out(port, SCSPTR, status);
752 static int sci_txfill(struct uart_port *port)
754 struct sci_port *s = to_sci_port(port);
755 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
756 const struct plat_sci_reg *reg;
758 reg = sci_getreg(port, SCTFDR);
760 return serial_port_in(port, SCTFDR) & fifo_mask;
762 reg = sci_getreg(port, SCFDR);
764 return serial_port_in(port, SCFDR) >> 8;
766 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
769 static int sci_txroom(struct uart_port *port)
771 return port->fifosize - sci_txfill(port);
774 static int sci_rxfill(struct uart_port *port)
776 struct sci_port *s = to_sci_port(port);
777 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
778 const struct plat_sci_reg *reg;
780 reg = sci_getreg(port, SCRFDR);
782 return serial_port_in(port, SCRFDR) & fifo_mask;
784 reg = sci_getreg(port, SCFDR);
786 return serial_port_in(port, SCFDR) & fifo_mask;
788 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
791 /* ********************************************************************** *
792 * the interrupt related routines *
793 * ********************************************************************** */
795 static void sci_transmit_chars(struct uart_port *port)
797 struct circ_buf *xmit = &port->state->xmit;
798 unsigned int stopped = uart_tx_stopped(port);
799 unsigned short status;
803 status = serial_port_in(port, SCxSR);
804 if (!(status & SCxSR_TDxE(port))) {
805 ctrl = serial_port_in(port, SCSCR);
806 if (uart_circ_empty(xmit))
810 serial_port_out(port, SCSCR, ctrl);
814 count = sci_txroom(port);
822 } else if (!uart_circ_empty(xmit) && !stopped) {
823 c = xmit->buf[xmit->tail];
824 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
829 serial_port_out(port, SCxTDR, c);
832 } while (--count > 0);
834 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
836 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
837 uart_write_wakeup(port);
838 if (uart_circ_empty(xmit))
843 /* On SH3, SCIF may read end-of-break as a space->mark char */
844 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
846 static void sci_receive_chars(struct uart_port *port)
848 struct tty_port *tport = &port->state->port;
849 int i, count, copied = 0;
850 unsigned short status;
853 status = serial_port_in(port, SCxSR);
854 if (!(status & SCxSR_RDxF(port)))
858 /* Don't copy more bytes than there is room for in the buffer */
859 count = tty_buffer_request_room(tport, sci_rxfill(port));
861 /* If for any reason we can't copy more data, we're done! */
865 if (port->type == PORT_SCI) {
866 char c = serial_port_in(port, SCxRDR);
867 if (uart_handle_sysrq_char(port, c))
870 tty_insert_flip_char(tport, c, TTY_NORMAL);
872 for (i = 0; i < count; i++) {
875 if (port->type == PORT_SCIF ||
876 port->type == PORT_HSCIF) {
877 status = serial_port_in(port, SCxSR);
878 c = serial_port_in(port, SCxRDR);
880 c = serial_port_in(port, SCxRDR);
881 status = serial_port_in(port, SCxSR);
883 if (uart_handle_sysrq_char(port, c)) {
888 /* Store data and status */
889 if (status & SCxSR_FER(port)) {
891 port->icount.frame++;
892 dev_notice(port->dev, "frame error\n");
893 } else if (status & SCxSR_PER(port)) {
895 port->icount.parity++;
896 dev_notice(port->dev, "parity error\n");
900 tty_insert_flip_char(tport, c, flag);
904 serial_port_in(port, SCxSR); /* dummy read */
905 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
908 port->icount.rx += count;
912 /* Tell the rest of the system the news. New characters! */
913 tty_flip_buffer_push(tport);
915 /* TTY buffers full; read from RX reg to prevent lockup */
916 serial_port_in(port, SCxRDR);
917 serial_port_in(port, SCxSR); /* dummy read */
918 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
922 static int sci_handle_errors(struct uart_port *port)
925 unsigned short status = serial_port_in(port, SCxSR);
926 struct tty_port *tport = &port->state->port;
927 struct sci_port *s = to_sci_port(port);
929 /* Handle overruns */
930 if (status & s->params->overrun_mask) {
931 port->icount.overrun++;
934 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
937 dev_notice(port->dev, "overrun error\n");
940 if (status & SCxSR_FER(port)) {
942 port->icount.frame++;
944 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
947 dev_notice(port->dev, "frame error\n");
950 if (status & SCxSR_PER(port)) {
952 port->icount.parity++;
954 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
957 dev_notice(port->dev, "parity error\n");
961 tty_flip_buffer_push(tport);
966 static int sci_handle_fifo_overrun(struct uart_port *port)
968 struct tty_port *tport = &port->state->port;
969 struct sci_port *s = to_sci_port(port);
970 const struct plat_sci_reg *reg;
974 reg = sci_getreg(port, s->params->overrun_reg);
978 status = serial_port_in(port, s->params->overrun_reg);
979 if (status & s->params->overrun_mask) {
980 status &= ~s->params->overrun_mask;
981 serial_port_out(port, s->params->overrun_reg, status);
983 port->icount.overrun++;
985 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
986 tty_flip_buffer_push(tport);
988 dev_dbg(port->dev, "overrun error\n");
995 static int sci_handle_breaks(struct uart_port *port)
998 unsigned short status = serial_port_in(port, SCxSR);
999 struct tty_port *tport = &port->state->port;
1001 if (uart_handle_break(port))
1004 if (status & SCxSR_BRK(port)) {
1007 /* Notify of BREAK */
1008 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1011 dev_dbg(port->dev, "BREAK detected\n");
1015 tty_flip_buffer_push(tport);
1017 copied += sci_handle_fifo_overrun(port);
1022 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1028 if (rx_trig >= port->fifosize)
1029 rx_trig = port->fifosize;
1031 /* HSCIF can be set to an arbitrary level. */
1032 if (sci_getreg(port, HSRTRGR)->size) {
1033 serial_port_out(port, HSRTRGR, rx_trig);
1037 switch (port->type) {
1042 } else if (rx_trig < 8) {
1045 } else if (rx_trig < 14) {
1049 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1058 } else if (rx_trig < 32) {
1061 } else if (rx_trig < 48) {
1065 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1070 WARN(1, "unknown FIFO configuration");
1074 serial_port_out(port, SCFCR,
1075 (serial_port_in(port, SCFCR) &
1076 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1081 static int scif_rtrg_enabled(struct uart_port *port)
1083 if (sci_getreg(port, HSRTRGR)->size)
1084 return serial_port_in(port, HSRTRGR) != 0;
1086 return (serial_port_in(port, SCFCR) &
1087 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1090 static void rx_fifo_timer_fn(struct timer_list *t)
1092 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1093 struct uart_port *port = &s->port;
1095 dev_dbg(port->dev, "Rx timed out\n");
1096 scif_set_rtrg(port, 1);
1099 static ssize_t rx_fifo_trigger_show(struct device *dev,
1100 struct device_attribute *attr, char *buf)
1102 struct uart_port *port = dev_get_drvdata(dev);
1103 struct sci_port *sci = to_sci_port(port);
1105 return sprintf(buf, "%d\n", sci->rx_trigger);
1108 static ssize_t rx_fifo_trigger_store(struct device *dev,
1109 struct device_attribute *attr,
1110 const char *buf, size_t count)
1112 struct uart_port *port = dev_get_drvdata(dev);
1113 struct sci_port *sci = to_sci_port(port);
1117 ret = kstrtol(buf, 0, &r);
1121 sci->rx_trigger = scif_set_rtrg(port, r);
1122 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1123 scif_set_rtrg(port, 1);
1128 static DEVICE_ATTR_RW(rx_fifo_trigger);
1130 static ssize_t rx_fifo_timeout_show(struct device *dev,
1131 struct device_attribute *attr,
1134 struct uart_port *port = dev_get_drvdata(dev);
1135 struct sci_port *sci = to_sci_port(port);
1138 if (port->type == PORT_HSCIF)
1139 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1141 v = sci->rx_fifo_timeout;
1143 return sprintf(buf, "%d\n", v);
1146 static ssize_t rx_fifo_timeout_store(struct device *dev,
1147 struct device_attribute *attr,
1151 struct uart_port *port = dev_get_drvdata(dev);
1152 struct sci_port *sci = to_sci_port(port);
1156 ret = kstrtol(buf, 0, &r);
1160 if (port->type == PORT_HSCIF) {
1163 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1165 sci->rx_fifo_timeout = r;
1166 scif_set_rtrg(port, 1);
1168 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1174 static DEVICE_ATTR_RW(rx_fifo_timeout);
1177 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1178 static void sci_dma_tx_complete(void *arg)
1180 struct sci_port *s = arg;
1181 struct uart_port *port = &s->port;
1182 struct circ_buf *xmit = &port->state->xmit;
1183 unsigned long flags;
1185 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1187 spin_lock_irqsave(&port->lock, flags);
1189 xmit->tail += s->tx_dma_len;
1190 xmit->tail &= UART_XMIT_SIZE - 1;
1192 port->icount.tx += s->tx_dma_len;
1194 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1195 uart_write_wakeup(port);
1197 if (!uart_circ_empty(xmit)) {
1199 schedule_work(&s->work_tx);
1201 s->cookie_tx = -EINVAL;
1202 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1203 u16 ctrl = serial_port_in(port, SCSCR);
1204 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1208 spin_unlock_irqrestore(&port->lock, flags);
1211 /* Locking: called with port lock held */
1212 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1214 struct uart_port *port = &s->port;
1215 struct tty_port *tport = &port->state->port;
1218 copied = tty_insert_flip_string(tport, buf, count);
1220 port->icount.buf_overrun++;
1222 port->icount.rx += copied;
1227 static int sci_dma_rx_find_active(struct sci_port *s)
1231 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1232 if (s->active_rx == s->cookie_rx[i])
1238 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1243 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1244 s->cookie_rx[i] = -EINVAL;
1248 static void sci_dma_rx_release(struct sci_port *s)
1250 struct dma_chan *chan = s->chan_rx_saved;
1252 s->chan_rx_saved = NULL;
1253 sci_dma_rx_chan_invalidate(s);
1254 dmaengine_terminate_sync(chan);
1255 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1256 sg_dma_address(&s->sg_rx[0]));
1257 dma_release_channel(chan);
1260 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1262 long sec = usec / 1000000;
1263 long nsec = (usec % 1000000) * 1000;
1264 ktime_t t = ktime_set(sec, nsec);
1266 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1269 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1271 struct uart_port *port = &s->port;
1274 /* Direct new serial port interrupts back to CPU */
1275 scr = serial_port_in(port, SCSCR);
1276 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1277 scr &= ~SCSCR_RDRQE;
1278 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1280 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1283 static void sci_dma_rx_complete(void *arg)
1285 struct sci_port *s = arg;
1286 struct dma_chan *chan = s->chan_rx;
1287 struct uart_port *port = &s->port;
1288 struct dma_async_tx_descriptor *desc;
1289 unsigned long flags;
1290 int active, count = 0;
1292 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1295 spin_lock_irqsave(&port->lock, flags);
1297 active = sci_dma_rx_find_active(s);
1299 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1301 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1304 tty_flip_buffer_push(&port->state->port);
1306 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 desc->callback = sci_dma_rx_complete;
1313 desc->callback_param = s;
1314 s->cookie_rx[active] = dmaengine_submit(desc);
1315 if (dma_submit_error(s->cookie_rx[active]))
1318 s->active_rx = s->cookie_rx[!active];
1320 dma_async_issue_pending(chan);
1322 spin_unlock_irqrestore(&port->lock, flags);
1323 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1324 __func__, s->cookie_rx[active], active, s->active_rx);
1328 spin_unlock_irqrestore(&port->lock, flags);
1329 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1331 spin_lock_irqsave(&port->lock, flags);
1332 dmaengine_terminate_async(chan);
1333 sci_dma_rx_chan_invalidate(s);
1334 sci_dma_rx_reenable_irq(s);
1335 spin_unlock_irqrestore(&port->lock, flags);
1338 static void sci_dma_tx_release(struct sci_port *s)
1340 struct dma_chan *chan = s->chan_tx_saved;
1342 cancel_work_sync(&s->work_tx);
1343 s->chan_tx_saved = s->chan_tx = NULL;
1344 s->cookie_tx = -EINVAL;
1345 dmaengine_terminate_sync(chan);
1346 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1348 dma_release_channel(chan);
1351 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1353 struct dma_chan *chan = s->chan_rx;
1354 struct uart_port *port = &s->port;
1355 unsigned long flags;
1358 for (i = 0; i < 2; i++) {
1359 struct scatterlist *sg = &s->sg_rx[i];
1360 struct dma_async_tx_descriptor *desc;
1362 desc = dmaengine_prep_slave_sg(chan,
1363 sg, 1, DMA_DEV_TO_MEM,
1364 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1368 desc->callback = sci_dma_rx_complete;
1369 desc->callback_param = s;
1370 s->cookie_rx[i] = dmaengine_submit(desc);
1371 if (dma_submit_error(s->cookie_rx[i]))
1376 s->active_rx = s->cookie_rx[0];
1378 dma_async_issue_pending(chan);
1383 if (!port_lock_held)
1384 spin_lock_irqsave(&port->lock, flags);
1386 dmaengine_terminate_async(chan);
1387 sci_dma_rx_chan_invalidate(s);
1389 if (!port_lock_held)
1390 spin_unlock_irqrestore(&port->lock, flags);
1394 static void sci_dma_tx_work_fn(struct work_struct *work)
1396 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1397 struct dma_async_tx_descriptor *desc;
1398 struct dma_chan *chan = s->chan_tx;
1399 struct uart_port *port = &s->port;
1400 struct circ_buf *xmit = &port->state->xmit;
1401 unsigned long flags;
1407 * Port xmit buffer is already mapped, and it is one page... Just adjust
1408 * offsets and lengths. Since it is a circular buffer, we have to
1409 * transmit till the end, and then the rest. Take the port lock to get a
1410 * consistent xmit buffer state.
1412 spin_lock_irq(&port->lock);
1415 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1416 s->tx_dma_len = min_t(unsigned int,
1417 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1418 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1419 if (!s->tx_dma_len) {
1420 /* Transmit buffer has been flushed */
1421 spin_unlock_irq(&port->lock);
1425 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1427 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1429 spin_unlock_irq(&port->lock);
1430 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1434 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1437 desc->callback = sci_dma_tx_complete;
1438 desc->callback_param = s;
1439 s->cookie_tx = dmaengine_submit(desc);
1440 if (dma_submit_error(s->cookie_tx)) {
1441 spin_unlock_irq(&port->lock);
1442 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1446 spin_unlock_irq(&port->lock);
1447 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1448 __func__, xmit->buf, tail, head, s->cookie_tx);
1450 dma_async_issue_pending(chan);
1454 spin_lock_irqsave(&port->lock, flags);
1457 spin_unlock_irqrestore(&port->lock, flags);
1461 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1463 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1464 struct dma_chan *chan = s->chan_rx;
1465 struct uart_port *port = &s->port;
1466 struct dma_tx_state state;
1467 enum dma_status status;
1468 unsigned long flags;
1472 dev_dbg(port->dev, "DMA Rx timed out\n");
1474 spin_lock_irqsave(&port->lock, flags);
1476 active = sci_dma_rx_find_active(s);
1478 spin_unlock_irqrestore(&port->lock, flags);
1479 return HRTIMER_NORESTART;
1482 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1483 if (status == DMA_COMPLETE) {
1484 spin_unlock_irqrestore(&port->lock, flags);
1485 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1486 s->active_rx, active);
1488 /* Let packet complete handler take care of the packet */
1489 return HRTIMER_NORESTART;
1492 dmaengine_pause(chan);
1495 * sometimes DMA transfer doesn't stop even if it is stopped and
1496 * data keeps on coming until transaction is complete so check
1497 * for DMA_COMPLETE again
1498 * Let packet complete handler take care of the packet
1500 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1501 if (status == DMA_COMPLETE) {
1502 spin_unlock_irqrestore(&port->lock, flags);
1503 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1504 return HRTIMER_NORESTART;
1507 /* Handle incomplete DMA receive */
1508 dmaengine_terminate_async(s->chan_rx);
1509 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1512 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1514 tty_flip_buffer_push(&port->state->port);
1517 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1518 sci_dma_rx_submit(s, true);
1520 sci_dma_rx_reenable_irq(s);
1522 spin_unlock_irqrestore(&port->lock, flags);
1524 return HRTIMER_NORESTART;
1527 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1528 enum dma_transfer_direction dir)
1530 struct dma_chan *chan;
1531 struct dma_slave_config cfg;
1534 chan = dma_request_slave_channel(port->dev,
1535 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1537 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1541 memset(&cfg, 0, sizeof(cfg));
1542 cfg.direction = dir;
1543 if (dir == DMA_MEM_TO_DEV) {
1544 cfg.dst_addr = port->mapbase +
1545 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1546 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1548 cfg.src_addr = port->mapbase +
1549 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1550 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1553 ret = dmaengine_slave_config(chan, &cfg);
1555 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1556 dma_release_channel(chan);
1563 static void sci_request_dma(struct uart_port *port)
1565 struct sci_port *s = to_sci_port(port);
1566 struct dma_chan *chan;
1568 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1571 * DMA on console may interfere with Kernel log messages which use
1572 * plain putchar(). So, simply don't use it with a console.
1574 if (uart_console(port))
1577 if (!port->dev->of_node)
1580 s->cookie_tx = -EINVAL;
1583 * Don't request a dma channel if no channel was specified
1584 * in the device tree.
1586 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1589 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1590 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1592 /* UART circular tx buffer is an aligned page. */
1593 s->tx_dma_addr = dma_map_single(chan->device->dev,
1594 port->state->xmit.buf,
1597 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1598 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1599 dma_release_channel(chan);
1601 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1602 __func__, UART_XMIT_SIZE,
1603 port->state->xmit.buf, &s->tx_dma_addr);
1605 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1606 s->chan_tx_saved = s->chan_tx = chan;
1610 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1611 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1617 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1618 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1622 "Failed to allocate Rx dma buffer, using PIO\n");
1623 dma_release_channel(chan);
1627 for (i = 0; i < 2; i++) {
1628 struct scatterlist *sg = &s->sg_rx[i];
1630 sg_init_table(sg, 1);
1632 sg_dma_address(sg) = dma;
1633 sg_dma_len(sg) = s->buf_len_rx;
1635 buf += s->buf_len_rx;
1636 dma += s->buf_len_rx;
1639 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1640 s->rx_timer.function = sci_dma_rx_timer_fn;
1642 s->chan_rx_saved = s->chan_rx = chan;
1644 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1645 sci_dma_rx_submit(s, false);
1649 static void sci_free_dma(struct uart_port *port)
1651 struct sci_port *s = to_sci_port(port);
1653 if (s->chan_tx_saved)
1654 sci_dma_tx_release(s);
1655 if (s->chan_rx_saved)
1656 sci_dma_rx_release(s);
1659 static void sci_flush_buffer(struct uart_port *port)
1661 struct sci_port *s = to_sci_port(port);
1664 * In uart_flush_buffer(), the xmit circular buffer has just been
1665 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1670 dmaengine_terminate_async(s->chan_tx);
1671 s->cookie_tx = -EINVAL;
1674 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1675 static inline void sci_request_dma(struct uart_port *port)
1679 static inline void sci_free_dma(struct uart_port *port)
1683 #define sci_flush_buffer NULL
1684 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1686 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1688 struct uart_port *port = ptr;
1689 struct sci_port *s = to_sci_port(port);
1691 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1693 u16 scr = serial_port_in(port, SCSCR);
1694 u16 ssr = serial_port_in(port, SCxSR);
1696 /* Disable future Rx interrupts */
1697 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1698 disable_irq_nosync(irq);
1701 if (sci_dma_rx_submit(s, false) < 0)
1706 serial_port_out(port, SCSCR, scr);
1707 /* Clear current interrupt */
1708 serial_port_out(port, SCxSR,
1709 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1710 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1711 jiffies, s->rx_timeout);
1712 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1720 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1721 if (!scif_rtrg_enabled(port))
1722 scif_set_rtrg(port, s->rx_trigger);
1724 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1725 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1728 /* I think sci_receive_chars has to be called irrespective
1729 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1732 sci_receive_chars(port);
1737 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1739 struct uart_port *port = ptr;
1740 unsigned long flags;
1742 spin_lock_irqsave(&port->lock, flags);
1743 sci_transmit_chars(port);
1744 spin_unlock_irqrestore(&port->lock, flags);
1749 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1751 struct uart_port *port = ptr;
1754 sci_handle_breaks(port);
1755 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1760 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1762 struct uart_port *port = ptr;
1763 struct sci_port *s = to_sci_port(port);
1765 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1766 /* Break and Error interrupts are muxed */
1767 unsigned short ssr_status = serial_port_in(port, SCxSR);
1769 /* Break Interrupt */
1770 if (ssr_status & SCxSR_BRK(port))
1771 sci_br_interrupt(irq, ptr);
1774 if (!(ssr_status & SCxSR_ERRORS(port)))
1779 if (port->type == PORT_SCI) {
1780 if (sci_handle_errors(port)) {
1781 /* discard character in rx buffer */
1782 serial_port_in(port, SCxSR);
1783 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1786 sci_handle_fifo_overrun(port);
1788 sci_receive_chars(port);
1791 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1793 /* Kick the transmission */
1795 sci_tx_interrupt(irq, ptr);
1800 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1802 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1803 struct uart_port *port = ptr;
1804 struct sci_port *s = to_sci_port(port);
1805 irqreturn_t ret = IRQ_NONE;
1807 ssr_status = serial_port_in(port, SCxSR);
1808 scr_status = serial_port_in(port, SCSCR);
1809 if (s->params->overrun_reg == SCxSR)
1810 orer_status = ssr_status;
1811 else if (sci_getreg(port, s->params->overrun_reg)->size)
1812 orer_status = serial_port_in(port, s->params->overrun_reg);
1814 err_enabled = scr_status & port_rx_irq_mask(port);
1817 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1819 ret = sci_tx_interrupt(irq, ptr);
1822 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1825 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1826 (scr_status & SCSCR_RIE))
1827 ret = sci_rx_interrupt(irq, ptr);
1829 /* Error Interrupt */
1830 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1831 ret = sci_er_interrupt(irq, ptr);
1833 /* Break Interrupt */
1834 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1835 ret = sci_br_interrupt(irq, ptr);
1837 /* Overrun Interrupt */
1838 if (orer_status & s->params->overrun_mask) {
1839 sci_handle_fifo_overrun(port);
1846 static const struct sci_irq_desc {
1848 irq_handler_t handler;
1849 } sci_irq_desc[] = {
1851 * Split out handlers, the default case.
1855 .handler = sci_er_interrupt,
1860 .handler = sci_rx_interrupt,
1865 .handler = sci_tx_interrupt,
1870 .handler = sci_br_interrupt,
1875 .handler = sci_rx_interrupt,
1880 .handler = sci_tx_interrupt,
1884 * Special muxed handler.
1888 .handler = sci_mpxed_interrupt,
1892 static int sci_request_irq(struct sci_port *port)
1894 struct uart_port *up = &port->port;
1895 int i, j, w, ret = 0;
1897 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1898 const struct sci_irq_desc *desc;
1901 /* Check if already registered (muxed) */
1902 for (w = 0; w < i; w++)
1903 if (port->irqs[w] == port->irqs[i])
1908 if (SCIx_IRQ_IS_MUXED(port)) {
1912 irq = port->irqs[i];
1915 * Certain port types won't support all of the
1916 * available interrupt sources.
1918 if (unlikely(irq < 0))
1922 desc = sci_irq_desc + i;
1923 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1924 dev_name(up->dev), desc->desc);
1925 if (!port->irqstr[j]) {
1930 ret = request_irq(irq, desc->handler, up->irqflags,
1931 port->irqstr[j], port);
1932 if (unlikely(ret)) {
1933 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1942 free_irq(port->irqs[i], port);
1946 kfree(port->irqstr[j]);
1951 static void sci_free_irq(struct sci_port *port)
1956 * Intentionally in reverse order so we iterate over the muxed
1959 for (i = 0; i < SCIx_NR_IRQS; i++) {
1960 int irq = port->irqs[i];
1963 * Certain port types won't support all of the available
1964 * interrupt sources.
1966 if (unlikely(irq < 0))
1969 /* Check if already freed (irq was muxed) */
1970 for (j = 0; j < i; j++)
1971 if (port->irqs[j] == irq)
1976 free_irq(port->irqs[i], port);
1977 kfree(port->irqstr[i]);
1979 if (SCIx_IRQ_IS_MUXED(port)) {
1980 /* If there's only one IRQ, we're done. */
1986 static unsigned int sci_tx_empty(struct uart_port *port)
1988 unsigned short status = serial_port_in(port, SCxSR);
1989 unsigned short in_tx_fifo = sci_txfill(port);
1991 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1994 static void sci_set_rts(struct uart_port *port, bool state)
1996 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1997 u16 data = serial_port_in(port, SCPDR);
2001 data &= ~SCPDR_RTSD;
2004 serial_port_out(port, SCPDR, data);
2006 /* RTS# is output */
2007 serial_port_out(port, SCPCR,
2008 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2009 } else if (sci_getreg(port, SCSPTR)->size) {
2010 u16 ctrl = serial_port_in(port, SCSPTR);
2014 ctrl &= ~SCSPTR_RTSDT;
2016 ctrl |= SCSPTR_RTSDT;
2017 serial_port_out(port, SCSPTR, ctrl);
2021 static bool sci_get_cts(struct uart_port *port)
2023 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2025 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2026 } else if (sci_getreg(port, SCSPTR)->size) {
2028 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2035 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2036 * CTS/RTS is supported in hardware by at least one port and controlled
2037 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2038 * handled via the ->init_pins() op, which is a bit of a one-way street,
2039 * lacking any ability to defer pin control -- this will later be
2040 * converted over to the GPIO framework).
2042 * Other modes (such as loopback) are supported generically on certain
2043 * port types, but not others. For these it's sufficient to test for the
2044 * existence of the support register and simply ignore the port type.
2046 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2048 struct sci_port *s = to_sci_port(port);
2050 if (mctrl & TIOCM_LOOP) {
2051 const struct plat_sci_reg *reg;
2054 * Standard loopback mode for SCFCR ports.
2056 reg = sci_getreg(port, SCFCR);
2058 serial_port_out(port, SCFCR,
2059 serial_port_in(port, SCFCR) |
2063 mctrl_gpio_set(s->gpios, mctrl);
2068 if (!(mctrl & TIOCM_RTS)) {
2069 /* Disable Auto RTS */
2070 serial_port_out(port, SCFCR,
2071 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2074 sci_set_rts(port, 0);
2075 } else if (s->autorts) {
2076 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2077 /* Enable RTS# pin function */
2078 serial_port_out(port, SCPCR,
2079 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2082 /* Enable Auto RTS */
2083 serial_port_out(port, SCFCR,
2084 serial_port_in(port, SCFCR) | SCFCR_MCE);
2087 sci_set_rts(port, 1);
2091 static unsigned int sci_get_mctrl(struct uart_port *port)
2093 struct sci_port *s = to_sci_port(port);
2094 struct mctrl_gpios *gpios = s->gpios;
2095 unsigned int mctrl = 0;
2097 mctrl_gpio_get(gpios, &mctrl);
2100 * CTS/RTS is handled in hardware when supported, while nothing
2104 if (sci_get_cts(port))
2106 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2109 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2111 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2117 static void sci_enable_ms(struct uart_port *port)
2119 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2122 static void sci_break_ctl(struct uart_port *port, int break_state)
2124 unsigned short scscr, scsptr;
2125 unsigned long flags;
2127 /* check whether the port has SCSPTR */
2128 if (!sci_getreg(port, SCSPTR)->size) {
2130 * Not supported by hardware. Most parts couple break and rx
2131 * interrupts together, with break detection always enabled.
2136 spin_lock_irqsave(&port->lock, flags);
2137 scsptr = serial_port_in(port, SCSPTR);
2138 scscr = serial_port_in(port, SCSCR);
2140 if (break_state == -1) {
2141 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2144 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2148 serial_port_out(port, SCSPTR, scsptr);
2149 serial_port_out(port, SCSCR, scscr);
2150 spin_unlock_irqrestore(&port->lock, flags);
2153 static int sci_startup(struct uart_port *port)
2155 struct sci_port *s = to_sci_port(port);
2158 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2160 sci_request_dma(port);
2162 ret = sci_request_irq(s);
2163 if (unlikely(ret < 0)) {
2171 static void sci_shutdown(struct uart_port *port)
2173 struct sci_port *s = to_sci_port(port);
2174 unsigned long flags;
2177 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2180 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2182 spin_lock_irqsave(&port->lock, flags);
2186 * Stop RX and TX, disable related interrupts, keep clock source
2187 * and HSCIF TOT bits
2189 scr = serial_port_in(port, SCSCR);
2190 serial_port_out(port, SCSCR, scr &
2191 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2192 spin_unlock_irqrestore(&port->lock, flags);
2194 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2195 if (s->chan_rx_saved) {
2196 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2198 hrtimer_cancel(&s->rx_timer);
2202 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2203 del_timer_sync(&s->rx_fifo_timer);
2208 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2211 unsigned long freq = s->clk_rates[SCI_SCK];
2212 int err, min_err = INT_MAX;
2215 if (s->port.type != PORT_HSCIF)
2218 for_each_sr(sr, s) {
2219 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2220 if (abs(err) >= abs(min_err))
2230 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2235 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2236 unsigned long freq, unsigned int *dlr,
2239 int err, min_err = INT_MAX;
2240 unsigned int sr, dl;
2242 if (s->port.type != PORT_HSCIF)
2245 for_each_sr(sr, s) {
2246 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2247 dl = clamp(dl, 1U, 65535U);
2249 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2250 if (abs(err) >= abs(min_err))
2261 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2262 min_err, *dlr, *srr + 1);
2266 /* calculate sample rate, BRR, and clock select */
2267 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2268 unsigned int *brr, unsigned int *srr,
2271 unsigned long freq = s->clk_rates[SCI_FCK];
2272 unsigned int sr, br, prediv, scrate, c;
2273 int err, min_err = INT_MAX;
2275 if (s->port.type != PORT_HSCIF)
2279 * Find the combination of sample rate and clock select with the
2280 * smallest deviation from the desired baud rate.
2281 * Prefer high sample rates to maximise the receive margin.
2283 * M: Receive margin (%)
2284 * N: Ratio of bit rate to clock (N = sampling rate)
2285 * D: Clock duty (D = 0 to 1.0)
2286 * L: Frame length (L = 9 to 12)
2287 * F: Absolute value of clock frequency deviation
2289 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2290 * (|D - 0.5| / N * (1 + F))|
2291 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2293 for_each_sr(sr, s) {
2294 for (c = 0; c <= 3; c++) {
2295 /* integerized formulas from HSCIF documentation */
2296 prediv = sr * (1 << (2 * c + 1));
2299 * We need to calculate:
2301 * br = freq / (prediv * bps) clamped to [1..256]
2302 * err = freq / (br * prediv) - bps
2304 * Watch out for overflow when calculating the desired
2305 * sampling clock rate!
2307 if (bps > UINT_MAX / prediv)
2310 scrate = prediv * bps;
2311 br = DIV_ROUND_CLOSEST(freq, scrate);
2312 br = clamp(br, 1U, 256U);
2314 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2315 if (abs(err) >= abs(min_err))
2329 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2330 min_err, *brr, *srr + 1, *cks);
2334 static void sci_reset(struct uart_port *port)
2336 const struct plat_sci_reg *reg;
2337 unsigned int status;
2338 struct sci_port *s = to_sci_port(port);
2340 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2342 reg = sci_getreg(port, SCFCR);
2344 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2346 sci_clear_SCxSR(port,
2347 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2348 SCxSR_BREAK_CLEAR(port));
2349 if (sci_getreg(port, SCLSR)->size) {
2350 status = serial_port_in(port, SCLSR);
2351 status &= ~(SCLSR_TO | SCLSR_ORER);
2352 serial_port_out(port, SCLSR, status);
2355 if (s->rx_trigger > 1) {
2356 if (s->rx_fifo_timeout) {
2357 scif_set_rtrg(port, 1);
2358 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2360 if (port->type == PORT_SCIFA ||
2361 port->type == PORT_SCIFB)
2362 scif_set_rtrg(port, 1);
2364 scif_set_rtrg(port, s->rx_trigger);
2369 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2370 struct ktermios *old)
2372 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2373 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2374 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2375 struct sci_port *s = to_sci_port(port);
2376 const struct plat_sci_reg *reg;
2377 int min_err = INT_MAX, err;
2378 unsigned long max_freq = 0;
2380 unsigned long flags;
2382 if ((termios->c_cflag & CSIZE) == CS7)
2383 smr_val |= SCSMR_CHR;
2384 if (termios->c_cflag & PARENB)
2385 smr_val |= SCSMR_PE;
2386 if (termios->c_cflag & PARODD)
2387 smr_val |= SCSMR_PE | SCSMR_ODD;
2388 if (termios->c_cflag & CSTOPB)
2389 smr_val |= SCSMR_STOP;
2392 * earlyprintk comes here early on with port->uartclk set to zero.
2393 * the clock framework is not up and running at this point so here
2394 * we assume that 115200 is the maximum baud rate. please note that
2395 * the baud rate is not programmed during earlyprintk - it is assumed
2396 * that the previous boot loader has enabled required clocks and
2397 * setup the baud rate generator hardware for us already.
2399 if (!port->uartclk) {
2400 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2404 for (i = 0; i < SCI_NUM_CLKS; i++)
2405 max_freq = max(max_freq, s->clk_rates[i]);
2407 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2412 * There can be multiple sources for the sampling clock. Find the one
2413 * that gives us the smallest deviation from the desired baud rate.
2416 /* Optional Undivided External Clock */
2417 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2418 port->type != PORT_SCIFB) {
2419 err = sci_sck_calc(s, baud, &srr1);
2420 if (abs(err) < abs(min_err)) {
2422 scr_val = SCSCR_CKE1;
2431 /* Optional BRG Frequency Divided External Clock */
2432 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2433 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2435 if (abs(err) < abs(min_err)) {
2436 best_clk = SCI_SCIF_CLK;
2437 scr_val = SCSCR_CKE1;
2447 /* Optional BRG Frequency Divided Internal Clock */
2448 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2449 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2451 if (abs(err) < abs(min_err)) {
2452 best_clk = SCI_BRG_INT;
2453 scr_val = SCSCR_CKE1;
2463 /* Divided Functional Clock using standard Bit Rate Register */
2464 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2465 if (abs(err) < abs(min_err)) {
2476 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2477 s->clks[best_clk], baud, min_err);
2482 * Program the optional External Baud Rate Generator (BRG) first.
2483 * It controls the mux to select (H)SCK or frequency divided clock.
2485 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2486 serial_port_out(port, SCDL, dl);
2487 serial_port_out(port, SCCKS, sccks);
2490 spin_lock_irqsave(&port->lock, flags);
2494 uart_update_timeout(port, termios->c_cflag, baud);
2496 /* byte size and parity */
2497 switch (termios->c_cflag & CSIZE) {
2512 if (termios->c_cflag & CSTOPB)
2514 if (termios->c_cflag & PARENB)
2517 if (best_clk >= 0) {
2518 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2520 case 5: smr_val |= SCSMR_SRC_5; break;
2521 case 7: smr_val |= SCSMR_SRC_7; break;
2522 case 11: smr_val |= SCSMR_SRC_11; break;
2523 case 13: smr_val |= SCSMR_SRC_13; break;
2524 case 16: smr_val |= SCSMR_SRC_16; break;
2525 case 17: smr_val |= SCSMR_SRC_17; break;
2526 case 19: smr_val |= SCSMR_SRC_19; break;
2527 case 27: smr_val |= SCSMR_SRC_27; break;
2530 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2531 serial_port_out(port, SCSMR, smr_val);
2532 serial_port_out(port, SCBRR, brr);
2533 if (sci_getreg(port, HSSRR)->size) {
2534 unsigned int hssrr = srr | HSCIF_SRE;
2535 /* Calculate deviation from intended rate at the
2536 * center of the last stop bit in sampling clocks.
2538 int last_stop = bits * 2 - 1;
2539 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2543 if (abs(deviation) >= 2) {
2544 /* At least two sampling clocks off at the
2545 * last stop bit; we can increase the error
2546 * margin by shifting the sampling point.
2548 int shift = clamp(deviation / 2, -8, 7);
2550 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2552 hssrr |= HSCIF_SRDE;
2554 serial_port_out(port, HSSRR, hssrr);
2557 /* Wait one bit interval */
2558 udelay((1000000 + (baud - 1)) / baud);
2560 /* Don't touch the bit rate configuration */
2561 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2562 smr_val |= serial_port_in(port, SCSMR) &
2563 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2564 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2565 serial_port_out(port, SCSMR, smr_val);
2568 sci_init_pins(port, termios->c_cflag);
2570 port->status &= ~UPSTAT_AUTOCTS;
2572 reg = sci_getreg(port, SCFCR);
2574 unsigned short ctrl = serial_port_in(port, SCFCR);
2576 if ((port->flags & UPF_HARD_FLOW) &&
2577 (termios->c_cflag & CRTSCTS)) {
2578 /* There is no CTS interrupt to restart the hardware */
2579 port->status |= UPSTAT_AUTOCTS;
2580 /* MCE is enabled when RTS is raised */
2585 * As we've done a sci_reset() above, ensure we don't
2586 * interfere with the FIFOs while toggling MCE. As the
2587 * reset values could still be set, simply mask them out.
2589 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2591 serial_port_out(port, SCFCR, ctrl);
2593 if (port->flags & UPF_HARD_FLOW) {
2594 /* Refresh (Auto) RTS */
2595 sci_set_mctrl(port, port->mctrl);
2598 scr_val |= SCSCR_RE | SCSCR_TE |
2599 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2600 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2601 if ((srr + 1 == 5) &&
2602 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2604 * In asynchronous mode, when the sampling rate is 1/5, first
2605 * received data may become invalid on some SCIFA and SCIFB.
2606 * To avoid this problem wait more than 1 serial data time (1
2607 * bit time x serial data number) after setting SCSCR.RE = 1.
2609 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2612 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2613 s->rx_frame = (10000 * bits) / (baud / 100);
2614 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2615 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2618 if ((termios->c_cflag & CREAD) != 0)
2621 spin_unlock_irqrestore(&port->lock, flags);
2623 sci_port_disable(s);
2625 if (UART_ENABLE_MS(port, termios->c_cflag))
2626 sci_enable_ms(port);
2629 static void sci_pm(struct uart_port *port, unsigned int state,
2630 unsigned int oldstate)
2632 struct sci_port *sci_port = to_sci_port(port);
2635 case UART_PM_STATE_OFF:
2636 sci_port_disable(sci_port);
2639 sci_port_enable(sci_port);
2644 static const char *sci_type(struct uart_port *port)
2646 switch (port->type) {
2664 static int sci_remap_port(struct uart_port *port)
2666 struct sci_port *sport = to_sci_port(port);
2669 * Nothing to do if there's already an established membase.
2674 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2675 port->membase = ioremap(port->mapbase, sport->reg_size);
2676 if (unlikely(!port->membase)) {
2677 dev_err(port->dev, "can't remap port#%d\n", port->line);
2682 * For the simple (and majority of) cases where we don't
2683 * need to do any remapping, just cast the cookie
2686 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2692 static void sci_release_port(struct uart_port *port)
2694 struct sci_port *sport = to_sci_port(port);
2696 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2697 iounmap(port->membase);
2698 port->membase = NULL;
2701 release_mem_region(port->mapbase, sport->reg_size);
2704 static int sci_request_port(struct uart_port *port)
2706 struct resource *res;
2707 struct sci_port *sport = to_sci_port(port);
2710 res = request_mem_region(port->mapbase, sport->reg_size,
2711 dev_name(port->dev));
2712 if (unlikely(res == NULL)) {
2713 dev_err(port->dev, "request_mem_region failed.");
2717 ret = sci_remap_port(port);
2718 if (unlikely(ret != 0)) {
2719 release_resource(res);
2726 static void sci_config_port(struct uart_port *port, int flags)
2728 if (flags & UART_CONFIG_TYPE) {
2729 struct sci_port *sport = to_sci_port(port);
2731 port->type = sport->cfg->type;
2732 sci_request_port(port);
2736 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2738 if (ser->baud_base < 2400)
2739 /* No paper tape reader for Mitch.. */
2745 static const struct uart_ops sci_uart_ops = {
2746 .tx_empty = sci_tx_empty,
2747 .set_mctrl = sci_set_mctrl,
2748 .get_mctrl = sci_get_mctrl,
2749 .start_tx = sci_start_tx,
2750 .stop_tx = sci_stop_tx,
2751 .stop_rx = sci_stop_rx,
2752 .enable_ms = sci_enable_ms,
2753 .break_ctl = sci_break_ctl,
2754 .startup = sci_startup,
2755 .shutdown = sci_shutdown,
2756 .flush_buffer = sci_flush_buffer,
2757 .set_termios = sci_set_termios,
2760 .release_port = sci_release_port,
2761 .request_port = sci_request_port,
2762 .config_port = sci_config_port,
2763 .verify_port = sci_verify_port,
2764 #ifdef CONFIG_CONSOLE_POLL
2765 .poll_get_char = sci_poll_get_char,
2766 .poll_put_char = sci_poll_put_char,
2770 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2772 const char *clk_names[] = {
2775 [SCI_BRG_INT] = "brg_int",
2776 [SCI_SCIF_CLK] = "scif_clk",
2781 if (sci_port->cfg->type == PORT_HSCIF)
2782 clk_names[SCI_SCK] = "hsck";
2784 for (i = 0; i < SCI_NUM_CLKS; i++) {
2785 clk = devm_clk_get(dev, clk_names[i]);
2786 if (PTR_ERR(clk) == -EPROBE_DEFER)
2787 return -EPROBE_DEFER;
2789 if (IS_ERR(clk) && i == SCI_FCK) {
2791 * "fck" used to be called "sci_ick", and we need to
2792 * maintain DT backward compatibility.
2794 clk = devm_clk_get(dev, "sci_ick");
2795 if (PTR_ERR(clk) == -EPROBE_DEFER)
2796 return -EPROBE_DEFER;
2802 * Not all SH platforms declare a clock lookup entry
2803 * for SCI devices, in which case we need to get the
2804 * global "peripheral_clk" clock.
2806 clk = devm_clk_get(dev, "peripheral_clk");
2810 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2812 return PTR_ERR(clk);
2817 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2820 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2821 clk, clk_get_rate(clk));
2822 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2827 static const struct sci_port_params *
2828 sci_probe_regmap(const struct plat_sci_port *cfg)
2830 unsigned int regtype;
2832 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2833 return &sci_port_params[cfg->regtype];
2835 switch (cfg->type) {
2837 regtype = SCIx_SCI_REGTYPE;
2840 regtype = SCIx_IRDA_REGTYPE;
2843 regtype = SCIx_SCIFA_REGTYPE;
2846 regtype = SCIx_SCIFB_REGTYPE;
2850 * The SH-4 is a bit of a misnomer here, although that's
2851 * where this particular port layout originated. This
2852 * configuration (or some slight variation thereof)
2853 * remains the dominant model for all SCIFs.
2855 regtype = SCIx_SH4_SCIF_REGTYPE;
2858 regtype = SCIx_HSCIF_REGTYPE;
2861 pr_err("Can't probe register map for given port\n");
2865 return &sci_port_params[regtype];
2868 static int sci_init_single(struct platform_device *dev,
2869 struct sci_port *sci_port, unsigned int index,
2870 const struct plat_sci_port *p, bool early)
2872 struct uart_port *port = &sci_port->port;
2873 const struct resource *res;
2879 port->ops = &sci_uart_ops;
2880 port->iotype = UPIO_MEM;
2882 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2884 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2888 port->mapbase = res->start;
2889 sci_port->reg_size = resource_size(res);
2891 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2893 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2895 sci_port->irqs[i] = platform_get_irq(dev, i);
2898 /* The SCI generates several interrupts. They can be muxed together or
2899 * connected to different interrupt lines. In the muxed case only one
2900 * interrupt resource is specified as there is only one interrupt ID.
2901 * In the non-muxed case, up to 6 interrupt signals might be generated
2902 * from the SCI, however those signals might have their own individual
2903 * interrupt ID numbers, or muxed together with another interrupt.
2905 if (sci_port->irqs[0] < 0)
2908 if (sci_port->irqs[1] < 0)
2909 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2910 sci_port->irqs[i] = sci_port->irqs[0];
2912 sci_port->params = sci_probe_regmap(p);
2913 if (unlikely(sci_port->params == NULL))
2918 sci_port->rx_trigger = 48;
2921 sci_port->rx_trigger = 64;
2924 sci_port->rx_trigger = 32;
2927 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2928 /* RX triggering not implemented for this IP */
2929 sci_port->rx_trigger = 1;
2931 sci_port->rx_trigger = 8;
2934 sci_port->rx_trigger = 1;
2938 sci_port->rx_fifo_timeout = 0;
2939 sci_port->hscif_tot = 0;
2941 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2942 * match the SoC datasheet, this should be investigated. Let platform
2943 * data override the sampling rate for now.
2945 sci_port->sampling_rate_mask = p->sampling_rate
2946 ? SCI_SR(p->sampling_rate)
2947 : sci_port->params->sampling_rate_mask;
2950 ret = sci_init_clocks(sci_port, &dev->dev);
2954 port->dev = &dev->dev;
2956 pm_runtime_enable(&dev->dev);
2959 port->type = p->type;
2960 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2961 port->fifosize = sci_port->params->fifosize;
2963 if (port->type == PORT_SCI) {
2964 if (sci_port->reg_size >= 0x20)
2971 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2972 * for the multi-IRQ ports, which is where we are primarily
2973 * concerned with the shutdown path synchronization.
2975 * For the muxed case there's nothing more to do.
2977 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2980 port->serial_in = sci_serial_in;
2981 port->serial_out = sci_serial_out;
2986 static void sci_cleanup_single(struct sci_port *port)
2988 pm_runtime_disable(port->port.dev);
2991 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2992 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2993 static void serial_console_putchar(struct uart_port *port, int ch)
2995 sci_poll_put_char(port, ch);
2999 * Print a string to the serial port trying not to disturb
3000 * any possible real use of the port...
3002 static void serial_console_write(struct console *co, const char *s,
3005 struct sci_port *sci_port = &sci_ports[co->index];
3006 struct uart_port *port = &sci_port->port;
3007 unsigned short bits, ctrl, ctrl_temp;
3008 unsigned long flags;
3013 else if (oops_in_progress)
3014 locked = spin_trylock_irqsave(&port->lock, flags);
3016 spin_lock_irqsave(&port->lock, flags);
3018 /* first save SCSCR then disable interrupts, keep clock source */
3019 ctrl = serial_port_in(port, SCSCR);
3020 ctrl_temp = SCSCR_RE | SCSCR_TE |
3021 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3022 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3023 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3025 uart_console_write(port, s, count, serial_console_putchar);
3027 /* wait until fifo is empty and last bit has been transmitted */
3028 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3029 while ((serial_port_in(port, SCxSR) & bits) != bits)
3032 /* restore the SCSCR */
3033 serial_port_out(port, SCSCR, ctrl);
3036 spin_unlock_irqrestore(&port->lock, flags);
3039 static int serial_console_setup(struct console *co, char *options)
3041 struct sci_port *sci_port;
3042 struct uart_port *port;
3050 * Refuse to handle any bogus ports.
3052 if (co->index < 0 || co->index >= SCI_NPORTS)
3055 sci_port = &sci_ports[co->index];
3056 port = &sci_port->port;
3059 * Refuse to handle uninitialized ports.
3064 ret = sci_remap_port(port);
3065 if (unlikely(ret != 0))
3069 uart_parse_options(options, &baud, &parity, &bits, &flow);
3071 return uart_set_options(port, co, baud, parity, bits, flow);
3074 static struct console serial_console = {
3076 .device = uart_console_device,
3077 .write = serial_console_write,
3078 .setup = serial_console_setup,
3079 .flags = CON_PRINTBUFFER,
3081 .data = &sci_uart_driver,
3084 #ifdef CONFIG_SUPERH
3085 static struct console early_serial_console = {
3086 .name = "early_ttySC",
3087 .write = serial_console_write,
3088 .flags = CON_PRINTBUFFER,
3092 static char early_serial_buf[32];
3094 static int sci_probe_earlyprintk(struct platform_device *pdev)
3096 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3098 if (early_serial_console.data)
3101 early_serial_console.index = pdev->id;
3103 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3105 serial_console_setup(&early_serial_console, early_serial_buf);
3107 if (!strstr(early_serial_buf, "keep"))
3108 early_serial_console.flags |= CON_BOOT;
3110 register_console(&early_serial_console);
3115 #define SCI_CONSOLE (&serial_console)
3118 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3123 #define SCI_CONSOLE NULL
3125 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3127 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3129 static DEFINE_MUTEX(sci_uart_registration_lock);
3130 static struct uart_driver sci_uart_driver = {
3131 .owner = THIS_MODULE,
3132 .driver_name = "sci",
3133 .dev_name = "ttySC",
3135 .minor = SCI_MINOR_START,
3137 .cons = SCI_CONSOLE,
3140 static int sci_remove(struct platform_device *dev)
3142 struct sci_port *port = platform_get_drvdata(dev);
3143 unsigned int type = port->port.type; /* uart_remove_... clears it */
3145 sci_ports_in_use &= ~BIT(port->port.line);
3146 uart_remove_one_port(&sci_uart_driver, &port->port);
3148 sci_cleanup_single(port);
3150 if (port->port.fifosize > 1)
3151 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3152 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3153 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3159 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3160 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3161 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3163 static const struct of_device_id of_sci_match[] = {
3164 /* SoC-specific types */
3166 .compatible = "renesas,scif-r7s72100",
3167 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3170 .compatible = "renesas,scif-r7s9210",
3171 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3173 /* Family-specific types */
3175 .compatible = "renesas,rcar-gen1-scif",
3176 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3178 .compatible = "renesas,rcar-gen2-scif",
3179 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3181 .compatible = "renesas,rcar-gen3-scif",
3182 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3186 .compatible = "renesas,scif",
3187 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3189 .compatible = "renesas,scifa",
3190 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3192 .compatible = "renesas,scifb",
3193 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3195 .compatible = "renesas,hscif",
3196 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3198 .compatible = "renesas,sci",
3199 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3204 MODULE_DEVICE_TABLE(of, of_sci_match);
3206 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3207 unsigned int *dev_id)
3209 struct device_node *np = pdev->dev.of_node;
3210 struct plat_sci_port *p;
3211 struct sci_port *sp;
3215 if (!IS_ENABLED(CONFIG_OF) || !np)
3218 data = of_device_get_match_data(&pdev->dev);
3220 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3224 /* Get the line number from the aliases node. */
3225 id = of_alias_get_id(np, "serial");
3226 if (id < 0 && ~sci_ports_in_use)
3227 id = ffz(sci_ports_in_use);
3229 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3232 if (id >= ARRAY_SIZE(sci_ports)) {
3233 dev_err(&pdev->dev, "serial%d out of range\n", id);
3237 sp = &sci_ports[id];
3240 p->type = SCI_OF_TYPE(data);
3241 p->regtype = SCI_OF_REGTYPE(data);
3243 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3248 static int sci_probe_single(struct platform_device *dev,
3250 struct plat_sci_port *p,
3251 struct sci_port *sciport)
3256 if (unlikely(index >= SCI_NPORTS)) {
3257 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3258 index+1, SCI_NPORTS);
3259 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3262 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3263 if (sci_ports_in_use & BIT(index))
3266 mutex_lock(&sci_uart_registration_lock);
3267 if (!sci_uart_driver.state) {
3268 ret = uart_register_driver(&sci_uart_driver);
3270 mutex_unlock(&sci_uart_registration_lock);
3274 mutex_unlock(&sci_uart_registration_lock);
3276 ret = sci_init_single(dev, sciport, index, p, false);
3280 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3281 if (IS_ERR(sciport->gpios))
3282 return PTR_ERR(sciport->gpios);
3284 if (sciport->has_rtscts) {
3285 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3286 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3287 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3290 sciport->port.flags |= UPF_HARD_FLOW;
3293 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3295 sci_cleanup_single(sciport);
3302 static int sci_probe(struct platform_device *dev)
3304 struct plat_sci_port *p;
3305 struct sci_port *sp;
3306 unsigned int dev_id;
3310 * If we've come here via earlyprintk initialization, head off to
3311 * the special early probe. We don't have sufficient device state
3312 * to make it beyond this yet.
3314 #ifdef CONFIG_SUPERH
3315 if (is_sh_early_platform_device(dev))
3316 return sci_probe_earlyprintk(dev);
3319 if (dev->dev.of_node) {
3320 p = sci_parse_dt(dev, &dev_id);
3324 p = dev->dev.platform_data;
3326 dev_err(&dev->dev, "no platform data supplied\n");
3333 sp = &sci_ports[dev_id];
3334 platform_set_drvdata(dev, sp);
3336 ret = sci_probe_single(dev, dev_id, p, sp);
3340 if (sp->port.fifosize > 1) {
3341 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3345 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3346 sp->port.type == PORT_HSCIF) {
3347 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3349 if (sp->port.fifosize > 1) {
3350 device_remove_file(&dev->dev,
3351 &dev_attr_rx_fifo_trigger);
3357 #ifdef CONFIG_SH_STANDARD_BIOS
3358 sh_bios_gdb_detach();
3361 sci_ports_in_use |= BIT(dev_id);
3365 static __maybe_unused int sci_suspend(struct device *dev)
3367 struct sci_port *sport = dev_get_drvdata(dev);
3370 uart_suspend_port(&sci_uart_driver, &sport->port);
3375 static __maybe_unused int sci_resume(struct device *dev)
3377 struct sci_port *sport = dev_get_drvdata(dev);
3380 uart_resume_port(&sci_uart_driver, &sport->port);
3385 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3387 static struct platform_driver sci_driver = {
3389 .remove = sci_remove,
3392 .pm = &sci_dev_pm_ops,
3393 .of_match_table = of_match_ptr(of_sci_match),
3397 static int __init sci_init(void)
3399 pr_info("%s\n", banner);
3401 return platform_driver_register(&sci_driver);
3404 static void __exit sci_exit(void)
3406 platform_driver_unregister(&sci_driver);
3408 if (sci_uart_driver.state)
3409 uart_unregister_driver(&sci_uart_driver);
3412 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3413 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3414 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3416 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3417 static struct plat_sci_port port_cfg __initdata;
3419 static int __init early_console_setup(struct earlycon_device *device,
3422 if (!device->port.membase)
3425 device->port.serial_in = sci_serial_in;
3426 device->port.serial_out = sci_serial_out;
3427 device->port.type = type;
3428 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3429 port_cfg.type = type;
3430 sci_ports[0].cfg = &port_cfg;
3431 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3432 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3433 sci_serial_out(&sci_ports[0].port, SCSCR,
3434 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3436 device->con->write = serial_console_write;
3439 static int __init sci_early_console_setup(struct earlycon_device *device,
3442 return early_console_setup(device, PORT_SCI);
3444 static int __init scif_early_console_setup(struct earlycon_device *device,
3447 return early_console_setup(device, PORT_SCIF);
3449 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3452 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3453 return early_console_setup(device, PORT_SCIF);
3455 static int __init scifa_early_console_setup(struct earlycon_device *device,
3458 return early_console_setup(device, PORT_SCIFA);
3460 static int __init scifb_early_console_setup(struct earlycon_device *device,
3463 return early_console_setup(device, PORT_SCIFB);
3465 static int __init hscif_early_console_setup(struct earlycon_device *device,
3468 return early_console_setup(device, PORT_HSCIF);
3471 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3472 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3473 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3474 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3475 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3476 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3477 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3479 module_init(sci_init);
3480 module_exit(sci_exit);
3482 MODULE_LICENSE("GPL");
3483 MODULE_ALIAS("platform:sh-sci");
3484 MODULE_AUTHOR("Paul Mundt");
3485 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");