2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
42 #include <linux/notifier.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/scatterlist.h>
47 #include <linux/serial.h>
48 #include <linux/serial_sci.h>
49 #include <linux/sh_dma.h>
50 #include <linux/slab.h>
51 #include <linux/string.h>
52 #include <linux/sysrq.h>
53 #include <linux/timer.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
58 #include <asm/sh_bios.h>
63 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
86 struct uart_port port;
88 /* Platform configuration */
89 struct plat_sci_port *cfg;
90 unsigned int overrun_reg;
91 unsigned int overrun_mask;
92 unsigned int error_mask;
93 unsigned int error_clear;
94 unsigned int sampling_rate;
95 resource_size_t reg_size;
98 struct timer_list break_timer;
102 struct clk *clks[SCI_NUM_CLKS];
103 unsigned long clk_rates[SCI_NUM_CLKS];
105 int irqs[SCIx_NR_IRQS];
106 char *irqstr[SCIx_NR_IRQS];
108 struct dma_chan *chan_tx;
109 struct dma_chan *chan_rx;
111 #ifdef CONFIG_SERIAL_SH_SCI_DMA
112 dma_cookie_t cookie_tx;
113 dma_cookie_t cookie_rx[2];
114 dma_cookie_t active_rx;
115 dma_addr_t tx_dma_addr;
116 unsigned int tx_dma_len;
117 struct scatterlist sg_rx[2];
120 struct work_struct work_tx;
121 struct timer_list rx_timer;
122 unsigned int rx_timeout;
125 struct notifier_block freq_transition;
128 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
130 static struct sci_port sci_ports[SCI_NPORTS];
131 static struct uart_driver sci_uart_driver;
133 static inline struct sci_port *
134 to_sci_port(struct uart_port *uart)
136 return container_of(uart, struct sci_port, port);
139 struct plat_sci_reg {
143 /* Helper for invalidating specific entries of an inherited map. */
144 #define sci_reg_invalid { .offset = 0, .size = 0 }
146 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
147 [SCIx_PROBE_REGTYPE] = {
148 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
152 * Common SCI definitions, dependent on the port's regshift
155 [SCIx_SCI_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = sci_reg_invalid,
163 [SCFDR] = sci_reg_invalid,
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 [HSSRR] = sci_reg_invalid,
169 [SCPCR] = sci_reg_invalid,
170 [SCPDR] = sci_reg_invalid,
171 [SCDL] = sci_reg_invalid,
172 [SCCKS] = sci_reg_invalid,
176 * Common definitions for legacy IrDA ports, dependent on
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 [HSSRR] = sci_reg_invalid,
193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
195 [SCDL] = sci_reg_invalid,
196 [SCCKS] = sci_reg_invalid,
200 * Common SCIFA definitions.
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
215 [HSSRR] = sci_reg_invalid,
216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
218 [SCDL] = sci_reg_invalid,
219 [SCCKS] = sci_reg_invalid,
223 * Common SCIFB definitions.
225 [SCIx_SCIFB_REGTYPE] = {
226 [SCSMR] = { 0x00, 16 },
227 [SCBRR] = { 0x04, 8 },
228 [SCSCR] = { 0x08, 16 },
229 [SCxTDR] = { 0x40, 8 },
230 [SCxSR] = { 0x14, 16 },
231 [SCxRDR] = { 0x60, 8 },
232 [SCFCR] = { 0x18, 16 },
233 [SCFDR] = sci_reg_invalid,
234 [SCTFDR] = { 0x38, 16 },
235 [SCRFDR] = { 0x3c, 16 },
236 [SCSPTR] = sci_reg_invalid,
237 [SCLSR] = sci_reg_invalid,
238 [HSSRR] = sci_reg_invalid,
239 [SCPCR] = { 0x30, 16 },
240 [SCPDR] = { 0x34, 16 },
241 [SCDL] = sci_reg_invalid,
242 [SCCKS] = sci_reg_invalid,
246 * Common SH-2(A) SCIF definitions for ports with FIFO data
249 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = { 0x20, 16 },
261 [SCLSR] = { 0x24, 16 },
262 [HSSRR] = sci_reg_invalid,
263 [SCPCR] = sci_reg_invalid,
264 [SCPDR] = sci_reg_invalid,
265 [SCDL] = sci_reg_invalid,
266 [SCCKS] = sci_reg_invalid,
270 * Common SH-3 SCIF definitions.
272 [SCIx_SH3_SCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 8 },
274 [SCBRR] = { 0x02, 8 },
275 [SCSCR] = { 0x04, 8 },
276 [SCxTDR] = { 0x06, 8 },
277 [SCxSR] = { 0x08, 16 },
278 [SCxRDR] = { 0x0a, 8 },
279 [SCFCR] = { 0x0c, 8 },
280 [SCFDR] = { 0x0e, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = sci_reg_invalid,
284 [SCLSR] = sci_reg_invalid,
285 [HSSRR] = sci_reg_invalid,
286 [SCPCR] = sci_reg_invalid,
287 [SCPDR] = sci_reg_invalid,
288 [SCDL] = sci_reg_invalid,
289 [SCCKS] = sci_reg_invalid,
293 * Common SH-4(A) SCIF(B) definitions.
295 [SCIx_SH4_SCIF_REGTYPE] = {
296 [SCSMR] = { 0x00, 16 },
297 [SCBRR] = { 0x04, 8 },
298 [SCSCR] = { 0x08, 16 },
299 [SCxTDR] = { 0x0c, 8 },
300 [SCxSR] = { 0x10, 16 },
301 [SCxRDR] = { 0x14, 8 },
302 [SCFCR] = { 0x18, 16 },
303 [SCFDR] = { 0x1c, 16 },
304 [SCTFDR] = sci_reg_invalid,
305 [SCRFDR] = sci_reg_invalid,
306 [SCSPTR] = { 0x20, 16 },
307 [SCLSR] = { 0x24, 16 },
308 [HSSRR] = sci_reg_invalid,
309 [SCPCR] = sci_reg_invalid,
310 [SCPDR] = sci_reg_invalid,
311 [SCDL] = sci_reg_invalid,
312 [SCCKS] = sci_reg_invalid,
316 * Common SCIF definitions for ports with a Baud Rate Generator for
317 * External Clock (BRG).
319 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x04, 8 },
322 [SCSCR] = { 0x08, 16 },
323 [SCxTDR] = { 0x0c, 8 },
324 [SCxSR] = { 0x10, 16 },
325 [SCxRDR] = { 0x14, 8 },
326 [SCFCR] = { 0x18, 16 },
327 [SCFDR] = { 0x1c, 16 },
328 [SCTFDR] = sci_reg_invalid,
329 [SCRFDR] = sci_reg_invalid,
330 [SCSPTR] = { 0x20, 16 },
331 [SCLSR] = { 0x24, 16 },
332 [HSSRR] = sci_reg_invalid,
333 [SCPCR] = sci_reg_invalid,
334 [SCPDR] = sci_reg_invalid,
335 [SCDL] = { 0x30, 16 },
336 [SCCKS] = { 0x34, 16 },
340 * Common HSCIF definitions.
342 [SCIx_HSCIF_REGTYPE] = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCTFDR] = sci_reg_invalid,
352 [SCRFDR] = sci_reg_invalid,
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
355 [HSSRR] = { 0x40, 16 },
356 [SCPCR] = sci_reg_invalid,
357 [SCPDR] = sci_reg_invalid,
358 [SCDL] = { 0x30, 16 },
359 [SCCKS] = { 0x34, 16 },
363 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
366 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCTFDR] = sci_reg_invalid,
376 [SCRFDR] = sci_reg_invalid,
377 [SCSPTR] = sci_reg_invalid,
378 [SCLSR] = { 0x24, 16 },
379 [HSSRR] = sci_reg_invalid,
380 [SCPCR] = sci_reg_invalid,
381 [SCPDR] = sci_reg_invalid,
382 [SCDL] = sci_reg_invalid,
383 [SCCKS] = sci_reg_invalid,
387 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
390 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
391 [SCSMR] = { 0x00, 16 },
392 [SCBRR] = { 0x04, 8 },
393 [SCSCR] = { 0x08, 16 },
394 [SCxTDR] = { 0x0c, 8 },
395 [SCxSR] = { 0x10, 16 },
396 [SCxRDR] = { 0x14, 8 },
397 [SCFCR] = { 0x18, 16 },
398 [SCFDR] = { 0x1c, 16 },
399 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
400 [SCRFDR] = { 0x20, 16 },
401 [SCSPTR] = { 0x24, 16 },
402 [SCLSR] = { 0x28, 16 },
403 [HSSRR] = sci_reg_invalid,
404 [SCPCR] = sci_reg_invalid,
405 [SCPDR] = sci_reg_invalid,
406 [SCDL] = sci_reg_invalid,
407 [SCCKS] = sci_reg_invalid,
411 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
414 [SCIx_SH7705_SCIF_REGTYPE] = {
415 [SCSMR] = { 0x00, 16 },
416 [SCBRR] = { 0x04, 8 },
417 [SCSCR] = { 0x08, 16 },
418 [SCxTDR] = { 0x20, 8 },
419 [SCxSR] = { 0x14, 16 },
420 [SCxRDR] = { 0x24, 8 },
421 [SCFCR] = { 0x18, 16 },
422 [SCFDR] = { 0x1c, 16 },
423 [SCTFDR] = sci_reg_invalid,
424 [SCRFDR] = sci_reg_invalid,
425 [SCSPTR] = sci_reg_invalid,
426 [SCLSR] = sci_reg_invalid,
427 [HSSRR] = sci_reg_invalid,
428 [SCPCR] = sci_reg_invalid,
429 [SCPDR] = sci_reg_invalid,
430 [SCDL] = sci_reg_invalid,
431 [SCCKS] = sci_reg_invalid,
435 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
438 * The "offset" here is rather misleading, in that it refers to an enum
439 * value relative to the port mapping rather than the fixed offset
440 * itself, which needs to be manually retrieved from the platform's
441 * register map for the given port.
443 static unsigned int sci_serial_in(struct uart_port *p, int offset)
445 const struct plat_sci_reg *reg = sci_getreg(p, offset);
448 return ioread8(p->membase + (reg->offset << p->regshift));
449 else if (reg->size == 16)
450 return ioread16(p->membase + (reg->offset << p->regshift));
452 WARN(1, "Invalid register access\n");
457 static void sci_serial_out(struct uart_port *p, int offset, int value)
459 const struct plat_sci_reg *reg = sci_getreg(p, offset);
462 iowrite8(value, p->membase + (reg->offset << p->regshift));
463 else if (reg->size == 16)
464 iowrite16(value, p->membase + (reg->offset << p->regshift));
466 WARN(1, "Invalid register access\n");
469 static int sci_probe_regmap(struct plat_sci_port *cfg)
473 cfg->regtype = SCIx_SCI_REGTYPE;
476 cfg->regtype = SCIx_IRDA_REGTYPE;
479 cfg->regtype = SCIx_SCIFA_REGTYPE;
482 cfg->regtype = SCIx_SCIFB_REGTYPE;
486 * The SH-4 is a bit of a misnomer here, although that's
487 * where this particular port layout originated. This
488 * configuration (or some slight variation thereof)
489 * remains the dominant model for all SCIFs.
491 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
494 cfg->regtype = SCIx_HSCIF_REGTYPE;
497 pr_err("Can't probe register map for given port\n");
504 static void sci_port_enable(struct sci_port *sci_port)
508 if (!sci_port->port.dev)
511 pm_runtime_get_sync(sci_port->port.dev);
513 for (i = 0; i < SCI_NUM_CLKS; i++) {
514 clk_prepare_enable(sci_port->clks[i]);
515 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
517 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
520 static void sci_port_disable(struct sci_port *sci_port)
524 if (!sci_port->port.dev)
527 /* Cancel the break timer to ensure that the timer handler will not try
528 * to access the hardware with clocks and power disabled. Reset the
529 * break flag to make the break debouncing state machine ready for the
532 del_timer_sync(&sci_port->break_timer);
533 sci_port->break_flag = 0;
535 for (i = SCI_NUM_CLKS; i-- > 0; )
536 clk_disable_unprepare(sci_port->clks[i]);
538 pm_runtime_put_sync(sci_port->port.dev);
541 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
544 * Not all ports (such as SCIFA) will support REIE. Rather than
545 * special-casing the port type, we check the port initialization
546 * IRQ enable mask to see whether the IRQ is desired at all. If
547 * it's unset, it's logically inferred that there's no point in
550 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
553 static void sci_start_tx(struct uart_port *port)
555 struct sci_port *s = to_sci_port(port);
558 #ifdef CONFIG_SERIAL_SH_SCI_DMA
559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
560 u16 new, scr = serial_port_in(port, SCSCR);
562 new = scr | SCSCR_TDRQE;
564 new = scr & ~SCSCR_TDRQE;
566 serial_port_out(port, SCSCR, new);
569 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
570 dma_submit_error(s->cookie_tx)) {
572 schedule_work(&s->work_tx);
576 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
578 ctrl = serial_port_in(port, SCSCR);
579 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
583 static void sci_stop_tx(struct uart_port *port)
587 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
588 ctrl = serial_port_in(port, SCSCR);
590 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
591 ctrl &= ~SCSCR_TDRQE;
595 serial_port_out(port, SCSCR, ctrl);
598 static void sci_start_rx(struct uart_port *port)
602 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
607 serial_port_out(port, SCSCR, ctrl);
610 static void sci_stop_rx(struct uart_port *port)
614 ctrl = serial_port_in(port, SCSCR);
616 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
617 ctrl &= ~SCSCR_RDRQE;
619 ctrl &= ~port_rx_irq_mask(port);
621 serial_port_out(port, SCSCR, ctrl);
624 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
626 if (port->type == PORT_SCI) {
627 /* Just store the mask */
628 serial_port_out(port, SCxSR, mask);
629 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
630 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
631 /* Only clear the status bits we want to clear */
632 serial_port_out(port, SCxSR,
633 serial_port_in(port, SCxSR) & mask);
635 /* Store the mask, clear parity/framing errors */
636 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
640 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
642 #ifdef CONFIG_CONSOLE_POLL
643 static int sci_poll_get_char(struct uart_port *port)
645 unsigned short status;
649 status = serial_port_in(port, SCxSR);
650 if (status & SCxSR_ERRORS(port)) {
651 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
657 if (!(status & SCxSR_RDxF(port)))
660 c = serial_port_in(port, SCxRDR);
663 serial_port_in(port, SCxSR);
664 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
670 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
672 unsigned short status;
675 status = serial_port_in(port, SCxSR);
676 } while (!(status & SCxSR_TDxE(port)));
678 serial_port_out(port, SCxTDR, c);
679 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
681 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
683 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
685 struct sci_port *s = to_sci_port(port);
686 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
689 * Use port-specific handler if provided.
691 if (s->cfg->ops && s->cfg->ops->init_pins) {
692 s->cfg->ops->init_pins(port, cflag);
697 * For the generic path SCSPTR is necessary. Bail out if that's
703 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
704 ((!(cflag & CRTSCTS)))) {
705 unsigned short status;
707 status = serial_port_in(port, SCSPTR);
708 status &= ~SCSPTR_CTSIO;
709 status |= SCSPTR_RTSIO;
710 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
714 static int sci_txfill(struct uart_port *port)
716 const struct plat_sci_reg *reg;
718 reg = sci_getreg(port, SCTFDR);
720 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
722 reg = sci_getreg(port, SCFDR);
724 return serial_port_in(port, SCFDR) >> 8;
726 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
729 static int sci_txroom(struct uart_port *port)
731 return port->fifosize - sci_txfill(port);
734 static int sci_rxfill(struct uart_port *port)
736 const struct plat_sci_reg *reg;
738 reg = sci_getreg(port, SCRFDR);
740 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
742 reg = sci_getreg(port, SCFDR);
744 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
746 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
750 * SCI helper for checking the state of the muxed port/RXD pins.
752 static inline int sci_rxd_in(struct uart_port *port)
754 struct sci_port *s = to_sci_port(port);
756 if (s->cfg->port_reg <= 0)
759 /* Cast for ARM damage */
760 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
763 /* ********************************************************************** *
764 * the interrupt related routines *
765 * ********************************************************************** */
767 static void sci_transmit_chars(struct uart_port *port)
769 struct circ_buf *xmit = &port->state->xmit;
770 unsigned int stopped = uart_tx_stopped(port);
771 unsigned short status;
775 status = serial_port_in(port, SCxSR);
776 if (!(status & SCxSR_TDxE(port))) {
777 ctrl = serial_port_in(port, SCSCR);
778 if (uart_circ_empty(xmit))
782 serial_port_out(port, SCSCR, ctrl);
786 count = sci_txroom(port);
794 } else if (!uart_circ_empty(xmit) && !stopped) {
795 c = xmit->buf[xmit->tail];
796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
801 serial_port_out(port, SCxTDR, c);
804 } while (--count > 0);
806 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809 uart_write_wakeup(port);
810 if (uart_circ_empty(xmit)) {
813 ctrl = serial_port_in(port, SCSCR);
815 if (port->type != PORT_SCI) {
816 serial_port_in(port, SCxSR); /* Dummy read */
817 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
821 serial_port_out(port, SCSCR, ctrl);
825 /* On SH3, SCIF may read end-of-break as a space->mark char */
826 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
828 static void sci_receive_chars(struct uart_port *port)
830 struct sci_port *sci_port = to_sci_port(port);
831 struct tty_port *tport = &port->state->port;
832 int i, count, copied = 0;
833 unsigned short status;
836 status = serial_port_in(port, SCxSR);
837 if (!(status & SCxSR_RDxF(port)))
841 /* Don't copy more bytes than there is room for in the buffer */
842 count = tty_buffer_request_room(tport, sci_rxfill(port));
844 /* If for any reason we can't copy more data, we're done! */
848 if (port->type == PORT_SCI) {
849 char c = serial_port_in(port, SCxRDR);
850 if (uart_handle_sysrq_char(port, c) ||
851 sci_port->break_flag)
854 tty_insert_flip_char(tport, c, TTY_NORMAL);
856 for (i = 0; i < count; i++) {
857 char c = serial_port_in(port, SCxRDR);
859 status = serial_port_in(port, SCxSR);
860 #if defined(CONFIG_CPU_SH3)
861 /* Skip "chars" during break */
862 if (sci_port->break_flag) {
864 (status & SCxSR_FER(port))) {
869 /* Nonzero => end-of-break */
870 dev_dbg(port->dev, "debounce<%02x>\n", c);
871 sci_port->break_flag = 0;
878 #endif /* CONFIG_CPU_SH3 */
879 if (uart_handle_sysrq_char(port, c)) {
884 /* Store data and status */
885 if (status & SCxSR_FER(port)) {
887 port->icount.frame++;
888 dev_notice(port->dev, "frame error\n");
889 } else if (status & SCxSR_PER(port)) {
891 port->icount.parity++;
892 dev_notice(port->dev, "parity error\n");
896 tty_insert_flip_char(tport, c, flag);
900 serial_port_in(port, SCxSR); /* dummy read */
901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
904 port->icount.rx += count;
908 /* Tell the rest of the system the news. New characters! */
909 tty_flip_buffer_push(tport);
911 serial_port_in(port, SCxSR); /* dummy read */
912 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
916 #define SCI_BREAK_JIFFIES (HZ/20)
919 * The sci generates interrupts during the break,
920 * 1 per millisecond or so during the break period, for 9600 baud.
921 * So dont bother disabling interrupts.
922 * But dont want more than 1 break event.
923 * Use a kernel timer to periodically poll the rx line until
924 * the break is finished.
926 static inline void sci_schedule_break_timer(struct sci_port *port)
928 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
931 /* Ensure that two consecutive samples find the break over. */
932 static void sci_break_timer(unsigned long data)
934 struct sci_port *port = (struct sci_port *)data;
936 if (sci_rxd_in(&port->port) == 0) {
937 port->break_flag = 1;
938 sci_schedule_break_timer(port);
939 } else if (port->break_flag == 1) {
941 port->break_flag = 2;
942 sci_schedule_break_timer(port);
944 port->break_flag = 0;
947 static int sci_handle_errors(struct uart_port *port)
950 unsigned short status = serial_port_in(port, SCxSR);
951 struct tty_port *tport = &port->state->port;
952 struct sci_port *s = to_sci_port(port);
954 /* Handle overruns */
955 if (status & s->overrun_mask) {
956 port->icount.overrun++;
959 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
962 dev_notice(port->dev, "overrun error\n");
965 if (status & SCxSR_FER(port)) {
966 if (sci_rxd_in(port) == 0) {
967 /* Notify of BREAK */
968 struct sci_port *sci_port = to_sci_port(port);
970 if (!sci_port->break_flag) {
973 sci_port->break_flag = 1;
974 sci_schedule_break_timer(sci_port);
976 /* Do sysrq handling. */
977 if (uart_handle_break(port))
980 dev_dbg(port->dev, "BREAK detected\n");
982 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
988 port->icount.frame++;
990 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
993 dev_notice(port->dev, "frame error\n");
997 if (status & SCxSR_PER(port)) {
999 port->icount.parity++;
1001 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1004 dev_notice(port->dev, "parity error\n");
1008 tty_flip_buffer_push(tport);
1013 static int sci_handle_fifo_overrun(struct uart_port *port)
1015 struct tty_port *tport = &port->state->port;
1016 struct sci_port *s = to_sci_port(port);
1017 const struct plat_sci_reg *reg;
1021 reg = sci_getreg(port, s->overrun_reg);
1025 status = serial_port_in(port, s->overrun_reg);
1026 if (status & s->overrun_mask) {
1027 status &= ~s->overrun_mask;
1028 serial_port_out(port, s->overrun_reg, status);
1030 port->icount.overrun++;
1032 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1033 tty_flip_buffer_push(tport);
1035 dev_dbg(port->dev, "overrun error\n");
1042 static int sci_handle_breaks(struct uart_port *port)
1045 unsigned short status = serial_port_in(port, SCxSR);
1046 struct tty_port *tport = &port->state->port;
1047 struct sci_port *s = to_sci_port(port);
1049 if (uart_handle_break(port))
1052 if (!s->break_flag && status & SCxSR_BRK(port)) {
1053 #if defined(CONFIG_CPU_SH3)
1054 /* Debounce break */
1060 /* Notify of BREAK */
1061 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1064 dev_dbg(port->dev, "BREAK detected\n");
1068 tty_flip_buffer_push(tport);
1070 copied += sci_handle_fifo_overrun(port);
1075 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1076 static void sci_dma_tx_complete(void *arg)
1078 struct sci_port *s = arg;
1079 struct uart_port *port = &s->port;
1080 struct circ_buf *xmit = &port->state->xmit;
1081 unsigned long flags;
1083 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1085 spin_lock_irqsave(&port->lock, flags);
1087 xmit->tail += s->tx_dma_len;
1088 xmit->tail &= UART_XMIT_SIZE - 1;
1090 port->icount.tx += s->tx_dma_len;
1092 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1093 uart_write_wakeup(port);
1095 if (!uart_circ_empty(xmit)) {
1097 schedule_work(&s->work_tx);
1099 s->cookie_tx = -EINVAL;
1100 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1101 u16 ctrl = serial_port_in(port, SCSCR);
1102 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1106 spin_unlock_irqrestore(&port->lock, flags);
1109 /* Locking: called with port lock held */
1110 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1112 struct uart_port *port = &s->port;
1113 struct tty_port *tport = &port->state->port;
1116 copied = tty_insert_flip_string(tport, buf, count);
1117 if (copied < count) {
1118 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1120 port->icount.buf_overrun++;
1123 port->icount.rx += copied;
1128 static int sci_dma_rx_find_active(struct sci_port *s)
1132 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1133 if (s->active_rx == s->cookie_rx[i])
1136 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1141 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1143 struct dma_chan *chan = s->chan_rx;
1144 struct uart_port *port = &s->port;
1145 unsigned long flags;
1147 spin_lock_irqsave(&port->lock, flags);
1149 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1150 spin_unlock_irqrestore(&port->lock, flags);
1151 dmaengine_terminate_all(chan);
1152 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1153 sg_dma_address(&s->sg_rx[0]));
1154 dma_release_channel(chan);
1159 static void sci_dma_rx_complete(void *arg)
1161 struct sci_port *s = arg;
1162 struct dma_chan *chan = s->chan_rx;
1163 struct uart_port *port = &s->port;
1164 struct dma_async_tx_descriptor *desc;
1165 unsigned long flags;
1166 int active, count = 0;
1168 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1171 spin_lock_irqsave(&port->lock, flags);
1173 active = sci_dma_rx_find_active(s);
1175 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1177 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1180 tty_flip_buffer_push(&port->state->port);
1182 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1184 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1188 desc->callback = sci_dma_rx_complete;
1189 desc->callback_param = s;
1190 s->cookie_rx[active] = dmaengine_submit(desc);
1191 if (dma_submit_error(s->cookie_rx[active]))
1194 s->active_rx = s->cookie_rx[!active];
1196 dma_async_issue_pending(chan);
1198 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1199 __func__, s->cookie_rx[active], active, s->active_rx);
1200 spin_unlock_irqrestore(&port->lock, flags);
1204 spin_unlock_irqrestore(&port->lock, flags);
1205 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1206 sci_rx_dma_release(s, true);
1209 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1211 struct dma_chan *chan = s->chan_tx;
1212 struct uart_port *port = &s->port;
1213 unsigned long flags;
1215 spin_lock_irqsave(&port->lock, flags);
1217 s->cookie_tx = -EINVAL;
1218 spin_unlock_irqrestore(&port->lock, flags);
1219 dmaengine_terminate_all(chan);
1220 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1222 dma_release_channel(chan);
1227 static void sci_submit_rx(struct sci_port *s)
1229 struct dma_chan *chan = s->chan_rx;
1232 for (i = 0; i < 2; i++) {
1233 struct scatterlist *sg = &s->sg_rx[i];
1234 struct dma_async_tx_descriptor *desc;
1236 desc = dmaengine_prep_slave_sg(chan,
1237 sg, 1, DMA_DEV_TO_MEM,
1238 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1242 desc->callback = sci_dma_rx_complete;
1243 desc->callback_param = s;
1244 s->cookie_rx[i] = dmaengine_submit(desc);
1245 if (dma_submit_error(s->cookie_rx[i]))
1248 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1249 s->cookie_rx[i], i);
1252 s->active_rx = s->cookie_rx[0];
1254 dma_async_issue_pending(chan);
1259 dmaengine_terminate_all(chan);
1260 for (i = 0; i < 2; i++)
1261 s->cookie_rx[i] = -EINVAL;
1262 s->active_rx = -EINVAL;
1263 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1264 sci_rx_dma_release(s, true);
1267 static void work_fn_tx(struct work_struct *work)
1269 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1270 struct dma_async_tx_descriptor *desc;
1271 struct dma_chan *chan = s->chan_tx;
1272 struct uart_port *port = &s->port;
1273 struct circ_buf *xmit = &port->state->xmit;
1278 * Port xmit buffer is already mapped, and it is one page... Just adjust
1279 * offsets and lengths. Since it is a circular buffer, we have to
1280 * transmit till the end, and then the rest. Take the port lock to get a
1281 * consistent xmit buffer state.
1283 spin_lock_irq(&port->lock);
1284 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1285 s->tx_dma_len = min_t(unsigned int,
1286 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1287 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1288 spin_unlock_irq(&port->lock);
1290 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1294 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1296 sci_tx_dma_release(s, true);
1300 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1303 spin_lock_irq(&port->lock);
1304 desc->callback = sci_dma_tx_complete;
1305 desc->callback_param = s;
1306 spin_unlock_irq(&port->lock);
1307 s->cookie_tx = dmaengine_submit(desc);
1308 if (dma_submit_error(s->cookie_tx)) {
1309 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1311 sci_tx_dma_release(s, true);
1315 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1316 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1318 dma_async_issue_pending(chan);
1321 static void rx_timer_fn(unsigned long arg)
1323 struct sci_port *s = (struct sci_port *)arg;
1324 struct dma_chan *chan = s->chan_rx;
1325 struct uart_port *port = &s->port;
1326 struct dma_tx_state state;
1327 enum dma_status status;
1328 unsigned long flags;
1333 spin_lock_irqsave(&port->lock, flags);
1335 dev_dbg(port->dev, "DMA Rx timed out\n");
1337 active = sci_dma_rx_find_active(s);
1339 spin_unlock_irqrestore(&port->lock, flags);
1343 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1344 if (status == DMA_COMPLETE) {
1345 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1346 s->active_rx, active);
1347 spin_unlock_irqrestore(&port->lock, flags);
1349 /* Let packet complete handler take care of the packet */
1353 dmaengine_pause(chan);
1356 * sometimes DMA transfer doesn't stop even if it is stopped and
1357 * data keeps on coming until transaction is complete so check
1358 * for DMA_COMPLETE again
1359 * Let packet complete handler take care of the packet
1361 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1362 if (status == DMA_COMPLETE) {
1363 spin_unlock_irqrestore(&port->lock, flags);
1364 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1368 /* Handle incomplete DMA receive */
1369 dmaengine_terminate_all(s->chan_rx);
1370 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1371 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1375 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1377 tty_flip_buffer_push(&port->state->port);
1380 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1383 /* Direct new serial port interrupts back to CPU */
1384 scr = serial_port_in(port, SCSCR);
1385 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1386 scr &= ~SCSCR_RDRQE;
1387 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1389 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1391 spin_unlock_irqrestore(&port->lock, flags);
1394 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1395 enum dma_transfer_direction dir,
1398 dma_cap_mask_t mask;
1399 struct dma_chan *chan;
1400 struct dma_slave_config cfg;
1404 dma_cap_set(DMA_SLAVE, mask);
1406 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1407 (void *)(unsigned long)id, port->dev,
1408 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1411 "dma_request_slave_channel_compat failed\n");
1415 memset(&cfg, 0, sizeof(cfg));
1416 cfg.direction = dir;
1417 if (dir == DMA_MEM_TO_DEV) {
1418 cfg.dst_addr = port->mapbase +
1419 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1420 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1422 cfg.src_addr = port->mapbase +
1423 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1424 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1427 ret = dmaengine_slave_config(chan, &cfg);
1429 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1430 dma_release_channel(chan);
1437 static void sci_request_dma(struct uart_port *port)
1439 struct sci_port *s = to_sci_port(port);
1440 struct dma_chan *chan;
1442 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1444 if (!port->dev->of_node &&
1445 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1448 s->cookie_tx = -EINVAL;
1449 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1450 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1453 /* UART circular tx buffer is an aligned page. */
1454 s->tx_dma_addr = dma_map_single(chan->device->dev,
1455 port->state->xmit.buf,
1458 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1459 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1460 dma_release_channel(chan);
1463 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1464 __func__, UART_XMIT_SIZE,
1465 port->state->xmit.buf, &s->tx_dma_addr);
1468 INIT_WORK(&s->work_tx, work_fn_tx);
1471 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1472 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1480 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1481 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1485 "Failed to allocate Rx dma buffer, using PIO\n");
1486 dma_release_channel(chan);
1491 for (i = 0; i < 2; i++) {
1492 struct scatterlist *sg = &s->sg_rx[i];
1494 sg_init_table(sg, 1);
1496 sg_dma_address(sg) = dma;
1497 sg->length = s->buf_len_rx;
1499 buf += s->buf_len_rx;
1500 dma += s->buf_len_rx;
1503 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1510 static void sci_free_dma(struct uart_port *port)
1512 struct sci_port *s = to_sci_port(port);
1515 sci_tx_dma_release(s, false);
1517 sci_rx_dma_release(s, false);
1520 static inline void sci_request_dma(struct uart_port *port)
1524 static inline void sci_free_dma(struct uart_port *port)
1529 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1531 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1532 struct uart_port *port = ptr;
1533 struct sci_port *s = to_sci_port(port);
1536 u16 scr = serial_port_in(port, SCSCR);
1537 u16 ssr = serial_port_in(port, SCxSR);
1539 /* Disable future Rx interrupts */
1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1541 disable_irq_nosync(irq);
1547 serial_port_out(port, SCSCR, scr);
1548 /* Clear current interrupt */
1549 serial_port_out(port, SCxSR,
1550 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1551 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1552 jiffies, s->rx_timeout);
1553 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1559 /* I think sci_receive_chars has to be called irrespective
1560 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1563 sci_receive_chars(ptr);
1568 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1570 struct uart_port *port = ptr;
1571 unsigned long flags;
1573 spin_lock_irqsave(&port->lock, flags);
1574 sci_transmit_chars(port);
1575 spin_unlock_irqrestore(&port->lock, flags);
1580 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1582 struct uart_port *port = ptr;
1583 struct sci_port *s = to_sci_port(port);
1586 if (port->type == PORT_SCI) {
1587 if (sci_handle_errors(port)) {
1588 /* discard character in rx buffer */
1589 serial_port_in(port, SCxSR);
1590 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1593 sci_handle_fifo_overrun(port);
1595 sci_receive_chars(ptr);
1598 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1600 /* Kick the transmission */
1602 sci_tx_interrupt(irq, ptr);
1607 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1609 struct uart_port *port = ptr;
1612 sci_handle_breaks(port);
1613 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1618 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1620 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1621 struct uart_port *port = ptr;
1622 struct sci_port *s = to_sci_port(port);
1623 irqreturn_t ret = IRQ_NONE;
1625 ssr_status = serial_port_in(port, SCxSR);
1626 scr_status = serial_port_in(port, SCSCR);
1627 if (s->overrun_reg == SCxSR)
1628 orer_status = ssr_status;
1630 if (sci_getreg(port, s->overrun_reg)->size)
1631 orer_status = serial_port_in(port, s->overrun_reg);
1634 err_enabled = scr_status & port_rx_irq_mask(port);
1637 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1639 ret = sci_tx_interrupt(irq, ptr);
1642 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1645 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1646 (scr_status & SCSCR_RIE))
1647 ret = sci_rx_interrupt(irq, ptr);
1649 /* Error Interrupt */
1650 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1651 ret = sci_er_interrupt(irq, ptr);
1653 /* Break Interrupt */
1654 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1655 ret = sci_br_interrupt(irq, ptr);
1657 /* Overrun Interrupt */
1658 if (orer_status & s->overrun_mask) {
1659 sci_handle_fifo_overrun(port);
1667 * Here we define a transition notifier so that we can update all of our
1668 * ports' baud rate when the peripheral clock changes.
1670 static int sci_notifier(struct notifier_block *self,
1671 unsigned long phase, void *p)
1673 struct sci_port *sci_port;
1674 unsigned long flags;
1677 sci_port = container_of(self, struct sci_port, freq_transition);
1679 if (phase == CPUFREQ_POSTCHANGE) {
1680 struct uart_port *port = &sci_port->port;
1682 spin_lock_irqsave(&port->lock, flags);
1683 for (i = 0; i < SCI_NUM_CLKS; i++)
1684 sci_port->clk_rates[i] =
1685 clk_get_rate(sci_port->clks[i]);
1686 spin_unlock_irqrestore(&port->lock, flags);
1692 static const struct sci_irq_desc {
1694 irq_handler_t handler;
1695 } sci_irq_desc[] = {
1697 * Split out handlers, the default case.
1701 .handler = sci_er_interrupt,
1706 .handler = sci_rx_interrupt,
1711 .handler = sci_tx_interrupt,
1716 .handler = sci_br_interrupt,
1720 * Special muxed handler.
1724 .handler = sci_mpxed_interrupt,
1728 static int sci_request_irq(struct sci_port *port)
1730 struct uart_port *up = &port->port;
1733 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1734 const struct sci_irq_desc *desc;
1737 if (SCIx_IRQ_IS_MUXED(port)) {
1741 irq = port->irqs[i];
1744 * Certain port types won't support all of the
1745 * available interrupt sources.
1747 if (unlikely(irq < 0))
1751 desc = sci_irq_desc + i;
1752 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1753 dev_name(up->dev), desc->desc);
1754 if (!port->irqstr[j])
1757 ret = request_irq(irq, desc->handler, up->irqflags,
1758 port->irqstr[j], port);
1759 if (unlikely(ret)) {
1760 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1769 free_irq(port->irqs[i], port);
1773 kfree(port->irqstr[j]);
1778 static void sci_free_irq(struct sci_port *port)
1783 * Intentionally in reverse order so we iterate over the muxed
1786 for (i = 0; i < SCIx_NR_IRQS; i++) {
1787 int irq = port->irqs[i];
1790 * Certain port types won't support all of the available
1791 * interrupt sources.
1793 if (unlikely(irq < 0))
1796 free_irq(port->irqs[i], port);
1797 kfree(port->irqstr[i]);
1799 if (SCIx_IRQ_IS_MUXED(port)) {
1800 /* If there's only one IRQ, we're done. */
1806 static unsigned int sci_tx_empty(struct uart_port *port)
1808 unsigned short status = serial_port_in(port, SCxSR);
1809 unsigned short in_tx_fifo = sci_txfill(port);
1811 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1815 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1816 * CTS/RTS is supported in hardware by at least one port and controlled
1817 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1818 * handled via the ->init_pins() op, which is a bit of a one-way street,
1819 * lacking any ability to defer pin control -- this will later be
1820 * converted over to the GPIO framework).
1822 * Other modes (such as loopback) are supported generically on certain
1823 * port types, but not others. For these it's sufficient to test for the
1824 * existence of the support register and simply ignore the port type.
1826 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1828 if (mctrl & TIOCM_LOOP) {
1829 const struct plat_sci_reg *reg;
1832 * Standard loopback mode for SCFCR ports.
1834 reg = sci_getreg(port, SCFCR);
1836 serial_port_out(port, SCFCR,
1837 serial_port_in(port, SCFCR) |
1842 static unsigned int sci_get_mctrl(struct uart_port *port)
1845 * CTS/RTS is handled in hardware when supported, while nothing
1846 * else is wired up. Keep it simple and simply assert DSR/CAR.
1848 return TIOCM_DSR | TIOCM_CAR;
1851 static void sci_break_ctl(struct uart_port *port, int break_state)
1853 struct sci_port *s = to_sci_port(port);
1854 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1855 unsigned short scscr, scsptr;
1857 /* check wheter the port has SCSPTR */
1860 * Not supported by hardware. Most parts couple break and rx
1861 * interrupts together, with break detection always enabled.
1866 scsptr = serial_port_in(port, SCSPTR);
1867 scscr = serial_port_in(port, SCSCR);
1869 if (break_state == -1) {
1870 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1873 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1877 serial_port_out(port, SCSPTR, scsptr);
1878 serial_port_out(port, SCSCR, scscr);
1881 static int sci_startup(struct uart_port *port)
1883 struct sci_port *s = to_sci_port(port);
1884 unsigned long flags;
1887 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1889 ret = sci_request_irq(s);
1890 if (unlikely(ret < 0))
1893 sci_request_dma(port);
1895 spin_lock_irqsave(&port->lock, flags);
1898 spin_unlock_irqrestore(&port->lock, flags);
1903 static void sci_shutdown(struct uart_port *port)
1905 struct sci_port *s = to_sci_port(port);
1906 unsigned long flags;
1908 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1910 spin_lock_irqsave(&port->lock, flags);
1913 spin_unlock_irqrestore(&port->lock, flags);
1915 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1917 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1919 del_timer_sync(&s->rx_timer);
1927 /* calculate sample rate, BRR, and clock select */
1928 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1929 unsigned int *brr, unsigned int *srr,
1932 unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
1933 unsigned long freq = s->clk_rates[SCI_FCK];
1934 int err, min_err = INT_MAX;
1936 if (s->sampling_rate) {
1937 min_sr = max_sr = s->sampling_rate;
1940 /* HSCIF has a variable sample rate */
1947 * Find the combination of sample rate and clock select with the
1948 * smallest deviation from the desired baud rate.
1949 * Prefer high sample rates to maximise the receive margin.
1951 * M: Receive margin (%)
1952 * N: Ratio of bit rate to clock (N = sampling rate)
1953 * D: Clock duty (D = 0 to 1.0)
1954 * L: Frame length (L = 9 to 12)
1955 * F: Absolute value of clock frequency deviation
1957 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1958 * (|D - 0.5| / N * (1 + F))|
1959 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
1961 for (sr = max_sr; sr >= min_sr; sr--) {
1962 for (c = 0; c <= 3; c++) {
1963 /* integerized formulas from HSCIF documentation */
1964 prediv = sr * (1 << (2 * c + shift));
1967 * We need to calculate:
1969 * br = freq / (prediv * bps) clamped to [1..256]
1970 * err = freq / (br * prediv) - bps
1972 * Watch out for overflow when calculating the desired
1973 * sampling clock rate!
1975 if (bps > UINT_MAX / prediv)
1978 scrate = prediv * bps;
1979 br = DIV_ROUND_CLOSEST(freq, scrate);
1980 br = clamp(br, 1U, 256U);
1982 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
1983 if (abs(err) >= abs(min_err))
1997 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
1998 min_err, *brr, *srr + 1, *cks);
2002 static void sci_reset(struct uart_port *port)
2004 const struct plat_sci_reg *reg;
2005 unsigned int status;
2008 status = serial_port_in(port, SCxSR);
2009 } while (!(status & SCxSR_TEND(port)));
2011 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2013 reg = sci_getreg(port, SCFCR);
2015 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2018 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2019 struct ktermios *old)
2021 unsigned int baud, smr_val = 0, scr_val = 0, i;
2022 unsigned int brr = 255, cks = 0, srr = 15;
2023 unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
2024 struct sci_port *s = to_sci_port(port);
2025 const struct plat_sci_reg *reg;
2026 int min_err = INT_MAX, err;
2027 unsigned long max_freq = 0;
2030 if ((termios->c_cflag & CSIZE) == CS7)
2031 smr_val |= SCSMR_CHR;
2032 if (termios->c_cflag & PARENB)
2033 smr_val |= SCSMR_PE;
2034 if (termios->c_cflag & PARODD)
2035 smr_val |= SCSMR_PE | SCSMR_ODD;
2036 if (termios->c_cflag & CSTOPB)
2037 smr_val |= SCSMR_STOP;
2040 * earlyprintk comes here early on with port->uartclk set to zero.
2041 * the clock framework is not up and running at this point so here
2042 * we assume that 115200 is the maximum baud rate. please note that
2043 * the baud rate is not programmed during earlyprintk - it is assumed
2044 * that the previous boot loader has enabled required clocks and
2045 * setup the baud rate generator hardware for us already.
2047 if (!port->uartclk) {
2048 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2052 for (i = 0; i < SCI_NUM_CLKS; i++)
2053 max_freq = max(max_freq, s->clk_rates[i]);
2055 baud = uart_get_baud_rate(port, termios, old, 0,
2056 max_freq / max(s->sampling_rate, 8U));
2061 * There can be multiple sources for the sampling clock. Find the one
2062 * that gives us the smallest deviation from the desired baud rate.
2065 /* Divided Functional Clock using standard Bit Rate Register */
2066 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2067 if (abs(err) < abs(min_err)) {
2077 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2078 s->clks[best_clk], baud, min_err);
2084 uart_update_timeout(port, termios->c_cflag, baud);
2086 if (best_clk >= 0) {
2088 dev_dbg(port->dev, "SMR 0x%x BRR %u SRR %u\n", smr_val, brr,
2090 serial_port_out(port, SCSMR, smr_val);
2091 serial_port_out(port, SCBRR, brr);
2092 if (sci_getreg(port, HSSRR)->size)
2093 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2095 /* Wait one bit interval */
2096 udelay((1000000 + (baud - 1)) / baud);
2098 /* Don't touch the bit rate configuration */
2099 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2100 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2101 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2102 serial_port_out(port, SCSCR, scr_val);
2103 serial_port_out(port, SCSMR, smr_val);
2106 sci_init_pins(port, termios->c_cflag);
2108 reg = sci_getreg(port, SCFCR);
2110 unsigned short ctrl = serial_port_in(port, SCFCR);
2112 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2113 if (termios->c_cflag & CRTSCTS)
2120 * As we've done a sci_reset() above, ensure we don't
2121 * interfere with the FIFOs while toggling MCE. As the
2122 * reset values could still be set, simply mask them out.
2124 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2126 serial_port_out(port, SCFCR, ctrl);
2129 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2130 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2131 serial_port_out(port, SCSCR, scr_val);
2133 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2135 * Calculate delay for 2 DMA buffers (4 FIFO).
2136 * See serial_core.c::uart_update_timeout().
2137 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2138 * function calculates 1 jiffie for the data plus 5 jiffies for the
2139 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2140 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2141 * value obtained by this formula is too small. Therefore, if the value
2142 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2147 /* byte size and parity */
2148 switch (termios->c_cflag & CSIZE) {
2163 if (termios->c_cflag & CSTOPB)
2165 if (termios->c_cflag & PARENB)
2167 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2169 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2170 s->rx_timeout * 1000 / HZ, port->timeout);
2171 if (s->rx_timeout < msecs_to_jiffies(20))
2172 s->rx_timeout = msecs_to_jiffies(20);
2176 if ((termios->c_cflag & CREAD) != 0)
2179 sci_port_disable(s);
2182 static void sci_pm(struct uart_port *port, unsigned int state,
2183 unsigned int oldstate)
2185 struct sci_port *sci_port = to_sci_port(port);
2188 case UART_PM_STATE_OFF:
2189 sci_port_disable(sci_port);
2192 sci_port_enable(sci_port);
2197 static const char *sci_type(struct uart_port *port)
2199 switch (port->type) {
2217 static int sci_remap_port(struct uart_port *port)
2219 struct sci_port *sport = to_sci_port(port);
2222 * Nothing to do if there's already an established membase.
2227 if (port->flags & UPF_IOREMAP) {
2228 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2229 if (unlikely(!port->membase)) {
2230 dev_err(port->dev, "can't remap port#%d\n", port->line);
2235 * For the simple (and majority of) cases where we don't
2236 * need to do any remapping, just cast the cookie
2239 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2245 static void sci_release_port(struct uart_port *port)
2247 struct sci_port *sport = to_sci_port(port);
2249 if (port->flags & UPF_IOREMAP) {
2250 iounmap(port->membase);
2251 port->membase = NULL;
2254 release_mem_region(port->mapbase, sport->reg_size);
2257 static int sci_request_port(struct uart_port *port)
2259 struct resource *res;
2260 struct sci_port *sport = to_sci_port(port);
2263 res = request_mem_region(port->mapbase, sport->reg_size,
2264 dev_name(port->dev));
2265 if (unlikely(res == NULL)) {
2266 dev_err(port->dev, "request_mem_region failed.");
2270 ret = sci_remap_port(port);
2271 if (unlikely(ret != 0)) {
2272 release_resource(res);
2279 static void sci_config_port(struct uart_port *port, int flags)
2281 if (flags & UART_CONFIG_TYPE) {
2282 struct sci_port *sport = to_sci_port(port);
2284 port->type = sport->cfg->type;
2285 sci_request_port(port);
2289 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2291 if (ser->baud_base < 2400)
2292 /* No paper tape reader for Mitch.. */
2298 static struct uart_ops sci_uart_ops = {
2299 .tx_empty = sci_tx_empty,
2300 .set_mctrl = sci_set_mctrl,
2301 .get_mctrl = sci_get_mctrl,
2302 .start_tx = sci_start_tx,
2303 .stop_tx = sci_stop_tx,
2304 .stop_rx = sci_stop_rx,
2305 .break_ctl = sci_break_ctl,
2306 .startup = sci_startup,
2307 .shutdown = sci_shutdown,
2308 .set_termios = sci_set_termios,
2311 .release_port = sci_release_port,
2312 .request_port = sci_request_port,
2313 .config_port = sci_config_port,
2314 .verify_port = sci_verify_port,
2315 #ifdef CONFIG_CONSOLE_POLL
2316 .poll_get_char = sci_poll_get_char,
2317 .poll_put_char = sci_poll_put_char,
2321 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2323 const char *clk_names[] = {
2329 for (i = 0; i < SCI_NUM_CLKS; i++) {
2330 clk = devm_clk_get(dev, clk_names[i]);
2331 if (PTR_ERR(clk) == -EPROBE_DEFER)
2332 return -EPROBE_DEFER;
2334 if (IS_ERR(clk) && i == SCI_FCK) {
2336 * "fck" used to be called "sci_ick", and we need to
2337 * maintain DT backward compatibility.
2339 clk = devm_clk_get(dev, "sci_ick");
2340 if (PTR_ERR(clk) == -EPROBE_DEFER)
2341 return -EPROBE_DEFER;
2346 /* SH has historically named the clock "sci_fck". */
2347 clk = devm_clk_get(dev, "sci_fck");
2352 * Not all SH platforms declare a clock lookup entry
2353 * for SCI devices, in which case we need to get the
2354 * global "peripheral_clk" clock.
2356 clk = devm_clk_get(dev, "peripheral_clk");
2360 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2362 return PTR_ERR(clk);
2367 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2370 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2372 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2377 static int sci_init_single(struct platform_device *dev,
2378 struct sci_port *sci_port, unsigned int index,
2379 struct plat_sci_port *p, bool early)
2381 struct uart_port *port = &sci_port->port;
2382 const struct resource *res;
2388 port->ops = &sci_uart_ops;
2389 port->iotype = UPIO_MEM;
2392 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2396 port->mapbase = res->start;
2397 sci_port->reg_size = resource_size(res);
2399 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2400 sci_port->irqs[i] = platform_get_irq(dev, i);
2402 /* The SCI generates several interrupts. They can be muxed together or
2403 * connected to different interrupt lines. In the muxed case only one
2404 * interrupt resource is specified. In the non-muxed case three or four
2405 * interrupt resources are specified, as the BRI interrupt is optional.
2407 if (sci_port->irqs[0] < 0)
2410 if (sci_port->irqs[1] < 0) {
2411 sci_port->irqs[1] = sci_port->irqs[0];
2412 sci_port->irqs[2] = sci_port->irqs[0];
2413 sci_port->irqs[3] = sci_port->irqs[0];
2416 if (p->regtype == SCIx_PROBE_REGTYPE) {
2417 ret = sci_probe_regmap(p);
2424 port->fifosize = 256;
2425 sci_port->overrun_reg = SCxSR;
2426 sci_port->overrun_mask = SCIFA_ORER;
2427 sci_port->sampling_rate = 16;
2430 port->fifosize = 128;
2431 sci_port->overrun_reg = SCLSR;
2432 sci_port->overrun_mask = SCLSR_ORER;
2433 sci_port->sampling_rate = 0;
2436 port->fifosize = 64;
2437 sci_port->overrun_reg = SCxSR;
2438 sci_port->overrun_mask = SCIFA_ORER;
2439 sci_port->sampling_rate = 16;
2442 port->fifosize = 16;
2443 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2444 sci_port->overrun_reg = SCxSR;
2445 sci_port->overrun_mask = SCIFA_ORER;
2446 sci_port->sampling_rate = 16;
2448 sci_port->overrun_reg = SCLSR;
2449 sci_port->overrun_mask = SCLSR_ORER;
2450 sci_port->sampling_rate = 32;
2455 sci_port->overrun_reg = SCxSR;
2456 sci_port->overrun_mask = SCI_ORER;
2457 sci_port->sampling_rate = 32;
2461 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2462 * match the SoC datasheet, this should be investigated. Let platform
2463 * data override the sampling rate for now.
2465 if (p->sampling_rate)
2466 sci_port->sampling_rate = p->sampling_rate;
2469 ret = sci_init_clocks(sci_port, &dev->dev);
2473 port->dev = &dev->dev;
2475 pm_runtime_enable(&dev->dev);
2478 sci_port->break_timer.data = (unsigned long)sci_port;
2479 sci_port->break_timer.function = sci_break_timer;
2480 init_timer(&sci_port->break_timer);
2483 * Establish some sensible defaults for the error detection.
2485 if (p->type == PORT_SCI) {
2486 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2487 sci_port->error_clear = SCI_ERROR_CLEAR;
2489 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2490 sci_port->error_clear = SCIF_ERROR_CLEAR;
2494 * Make the error mask inclusive of overrun detection, if
2497 if (sci_port->overrun_reg == SCxSR) {
2498 sci_port->error_mask |= sci_port->overrun_mask;
2499 sci_port->error_clear &= ~sci_port->overrun_mask;
2502 port->type = p->type;
2503 port->flags = UPF_FIXED_PORT | p->flags;
2504 port->regshift = p->regshift;
2507 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2508 * for the multi-IRQ ports, which is where we are primarily
2509 * concerned with the shutdown path synchronization.
2511 * For the muxed case there's nothing more to do.
2513 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2516 port->serial_in = sci_serial_in;
2517 port->serial_out = sci_serial_out;
2519 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2520 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2521 p->dma_slave_tx, p->dma_slave_rx);
2526 static void sci_cleanup_single(struct sci_port *port)
2528 pm_runtime_disable(port->port.dev);
2531 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2532 static void serial_console_putchar(struct uart_port *port, int ch)
2534 sci_poll_put_char(port, ch);
2538 * Print a string to the serial port trying not to disturb
2539 * any possible real use of the port...
2541 static void serial_console_write(struct console *co, const char *s,
2544 struct sci_port *sci_port = &sci_ports[co->index];
2545 struct uart_port *port = &sci_port->port;
2546 unsigned short bits, ctrl, ctrl_temp;
2547 unsigned long flags;
2550 local_irq_save(flags);
2553 else if (oops_in_progress)
2554 locked = spin_trylock(&port->lock);
2556 spin_lock(&port->lock);
2558 /* first save SCSCR then disable interrupts, keep clock source */
2559 ctrl = serial_port_in(port, SCSCR);
2560 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2561 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2562 serial_port_out(port, SCSCR, ctrl_temp);
2564 uart_console_write(port, s, count, serial_console_putchar);
2566 /* wait until fifo is empty and last bit has been transmitted */
2567 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2568 while ((serial_port_in(port, SCxSR) & bits) != bits)
2571 /* restore the SCSCR */
2572 serial_port_out(port, SCSCR, ctrl);
2575 spin_unlock(&port->lock);
2576 local_irq_restore(flags);
2579 static int serial_console_setup(struct console *co, char *options)
2581 struct sci_port *sci_port;
2582 struct uart_port *port;
2590 * Refuse to handle any bogus ports.
2592 if (co->index < 0 || co->index >= SCI_NPORTS)
2595 sci_port = &sci_ports[co->index];
2596 port = &sci_port->port;
2599 * Refuse to handle uninitialized ports.
2604 ret = sci_remap_port(port);
2605 if (unlikely(ret != 0))
2609 uart_parse_options(options, &baud, &parity, &bits, &flow);
2611 return uart_set_options(port, co, baud, parity, bits, flow);
2614 static struct console serial_console = {
2616 .device = uart_console_device,
2617 .write = serial_console_write,
2618 .setup = serial_console_setup,
2619 .flags = CON_PRINTBUFFER,
2621 .data = &sci_uart_driver,
2624 static struct console early_serial_console = {
2625 .name = "early_ttySC",
2626 .write = serial_console_write,
2627 .flags = CON_PRINTBUFFER,
2631 static char early_serial_buf[32];
2633 static int sci_probe_earlyprintk(struct platform_device *pdev)
2635 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2637 if (early_serial_console.data)
2640 early_serial_console.index = pdev->id;
2642 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2644 serial_console_setup(&early_serial_console, early_serial_buf);
2646 if (!strstr(early_serial_buf, "keep"))
2647 early_serial_console.flags |= CON_BOOT;
2649 register_console(&early_serial_console);
2653 #define SCI_CONSOLE (&serial_console)
2656 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2661 #define SCI_CONSOLE NULL
2663 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2665 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2667 static struct uart_driver sci_uart_driver = {
2668 .owner = THIS_MODULE,
2669 .driver_name = "sci",
2670 .dev_name = "ttySC",
2672 .minor = SCI_MINOR_START,
2674 .cons = SCI_CONSOLE,
2677 static int sci_remove(struct platform_device *dev)
2679 struct sci_port *port = platform_get_drvdata(dev);
2681 cpufreq_unregister_notifier(&port->freq_transition,
2682 CPUFREQ_TRANSITION_NOTIFIER);
2684 uart_remove_one_port(&sci_uart_driver, &port->port);
2686 sci_cleanup_single(port);
2692 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2693 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2694 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2696 static const struct of_device_id of_sci_match[] = {
2697 /* SoC-specific types */
2699 .compatible = "renesas,scif-r7s72100",
2700 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2702 /* Family-specific types */
2704 .compatible = "renesas,rcar-gen1-scif",
2705 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2707 .compatible = "renesas,rcar-gen2-scif",
2708 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2710 .compatible = "renesas,rcar-gen3-scif",
2711 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2715 .compatible = "renesas,scif",
2716 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2718 .compatible = "renesas,scifa",
2719 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2721 .compatible = "renesas,scifb",
2722 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2724 .compatible = "renesas,hscif",
2725 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2727 .compatible = "renesas,sci",
2728 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2733 MODULE_DEVICE_TABLE(of, of_sci_match);
2735 static struct plat_sci_port *
2736 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2738 struct device_node *np = pdev->dev.of_node;
2739 const struct of_device_id *match;
2740 struct plat_sci_port *p;
2743 if (!IS_ENABLED(CONFIG_OF) || !np)
2746 match = of_match_node(of_sci_match, np);
2750 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2754 /* Get the line number from the aliases node. */
2755 id = of_alias_get_id(np, "serial");
2757 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2763 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2764 p->type = SCI_OF_TYPE(match->data);
2765 p->regtype = SCI_OF_REGTYPE(match->data);
2766 p->scscr = SCSCR_RE | SCSCR_TE;
2771 static int sci_probe_single(struct platform_device *dev,
2773 struct plat_sci_port *p,
2774 struct sci_port *sciport)
2779 if (unlikely(index >= SCI_NPORTS)) {
2780 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2781 index+1, SCI_NPORTS);
2782 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2786 ret = sci_init_single(dev, sciport, index, p, false);
2790 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2792 sci_cleanup_single(sciport);
2799 static int sci_probe(struct platform_device *dev)
2801 struct plat_sci_port *p;
2802 struct sci_port *sp;
2803 unsigned int dev_id;
2807 * If we've come here via earlyprintk initialization, head off to
2808 * the special early probe. We don't have sufficient device state
2809 * to make it beyond this yet.
2811 if (is_early_platform_device(dev))
2812 return sci_probe_earlyprintk(dev);
2814 if (dev->dev.of_node) {
2815 p = sci_parse_dt(dev, &dev_id);
2819 p = dev->dev.platform_data;
2821 dev_err(&dev->dev, "no platform data supplied\n");
2828 sp = &sci_ports[dev_id];
2829 platform_set_drvdata(dev, sp);
2831 ret = sci_probe_single(dev, dev_id, p, sp);
2835 sp->freq_transition.notifier_call = sci_notifier;
2837 ret = cpufreq_register_notifier(&sp->freq_transition,
2838 CPUFREQ_TRANSITION_NOTIFIER);
2839 if (unlikely(ret < 0)) {
2840 uart_remove_one_port(&sci_uart_driver, &sp->port);
2841 sci_cleanup_single(sp);
2845 #ifdef CONFIG_SH_STANDARD_BIOS
2846 sh_bios_gdb_detach();
2852 static __maybe_unused int sci_suspend(struct device *dev)
2854 struct sci_port *sport = dev_get_drvdata(dev);
2857 uart_suspend_port(&sci_uart_driver, &sport->port);
2862 static __maybe_unused int sci_resume(struct device *dev)
2864 struct sci_port *sport = dev_get_drvdata(dev);
2867 uart_resume_port(&sci_uart_driver, &sport->port);
2872 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2874 static struct platform_driver sci_driver = {
2876 .remove = sci_remove,
2879 .pm = &sci_dev_pm_ops,
2880 .of_match_table = of_match_ptr(of_sci_match),
2884 static int __init sci_init(void)
2888 pr_info("%s\n", banner);
2890 ret = uart_register_driver(&sci_uart_driver);
2891 if (likely(ret == 0)) {
2892 ret = platform_driver_register(&sci_driver);
2894 uart_unregister_driver(&sci_uart_driver);
2900 static void __exit sci_exit(void)
2902 platform_driver_unregister(&sci_driver);
2903 uart_unregister_driver(&sci_uart_driver);
2906 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2907 early_platform_init_buffer("earlyprintk", &sci_driver,
2908 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2910 module_init(sci_init);
2911 module_exit(sci_exit);
2913 MODULE_LICENSE("GPL");
2914 MODULE_ALIAS("platform:sh-sci");
2915 MODULE_AUTHOR("Paul Mundt");
2916 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");