2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
98 int irqs[SCIx_NR_IRQS];
99 char *irqstr[SCIx_NR_IRQS];
101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 dma_cookie_t cookie_tx;
106 dma_cookie_t cookie_rx[2];
107 dma_cookie_t active_rx;
108 dma_addr_t tx_dma_addr;
109 unsigned int tx_dma_len;
110 struct scatterlist sg_rx[2];
113 struct work_struct work_tx;
114 struct timer_list rx_timer;
115 unsigned int rx_timeout;
118 struct notifier_block freq_transition;
121 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
123 static struct sci_port sci_ports[SCI_NPORTS];
124 static struct uart_driver sci_uart_driver;
126 static inline struct sci_port *
127 to_sci_port(struct uart_port *uart)
129 return container_of(uart, struct sci_port, port);
132 struct plat_sci_reg {
136 /* Helper for invalidating specific entries of an inherited map. */
137 #define sci_reg_invalid { .offset = 0, .size = 0 }
139 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
140 [SCIx_PROBE_REGTYPE] = {
141 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
145 * Common SCI definitions, dependent on the port's regshift
148 [SCIx_SCI_REGTYPE] = {
149 [SCSMR] = { 0x00, 8 },
150 [SCBRR] = { 0x01, 8 },
151 [SCSCR] = { 0x02, 8 },
152 [SCxTDR] = { 0x03, 8 },
153 [SCxSR] = { 0x04, 8 },
154 [SCxRDR] = { 0x05, 8 },
155 [SCFCR] = sci_reg_invalid,
156 [SCFDR] = sci_reg_invalid,
157 [SCTFDR] = sci_reg_invalid,
158 [SCRFDR] = sci_reg_invalid,
159 [SCSPTR] = sci_reg_invalid,
160 [SCLSR] = sci_reg_invalid,
161 [HSSRR] = sci_reg_invalid,
162 [SCPCR] = sci_reg_invalid,
163 [SCPDR] = sci_reg_invalid,
164 [SCDL] = sci_reg_invalid,
165 [SCCKS] = sci_reg_invalid,
169 * Common definitions for legacy IrDA ports, dependent on
172 [SCIx_IRDA_REGTYPE] = {
173 [SCSMR] = { 0x00, 8 },
174 [SCBRR] = { 0x01, 8 },
175 [SCSCR] = { 0x02, 8 },
176 [SCxTDR] = { 0x03, 8 },
177 [SCxSR] = { 0x04, 8 },
178 [SCxRDR] = { 0x05, 8 },
179 [SCFCR] = { 0x06, 8 },
180 [SCFDR] = { 0x07, 16 },
181 [SCTFDR] = sci_reg_invalid,
182 [SCRFDR] = sci_reg_invalid,
183 [SCSPTR] = sci_reg_invalid,
184 [SCLSR] = sci_reg_invalid,
185 [HSSRR] = sci_reg_invalid,
186 [SCPCR] = sci_reg_invalid,
187 [SCPDR] = sci_reg_invalid,
188 [SCDL] = sci_reg_invalid,
189 [SCCKS] = sci_reg_invalid,
193 * Common SCIFA definitions.
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
211 [SCDL] = sci_reg_invalid,
212 [SCCKS] = sci_reg_invalid,
216 * Common SCIFB definitions.
218 [SCIx_SCIFB_REGTYPE] = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x40, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x60, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = sci_reg_invalid,
227 [SCTFDR] = { 0x38, 16 },
228 [SCRFDR] = { 0x3c, 16 },
229 [SCSPTR] = sci_reg_invalid,
230 [SCLSR] = sci_reg_invalid,
231 [HSSRR] = sci_reg_invalid,
232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
234 [SCDL] = sci_reg_invalid,
235 [SCCKS] = sci_reg_invalid,
239 * Common SH-2(A) SCIF definitions for ports with FIFO data
242 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x0c, 8 },
247 [SCxSR] = { 0x10, 16 },
248 [SCxRDR] = { 0x14, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCTFDR] = sci_reg_invalid,
252 [SCRFDR] = sci_reg_invalid,
253 [SCSPTR] = { 0x20, 16 },
254 [SCLSR] = { 0x24, 16 },
255 [HSSRR] = sci_reg_invalid,
256 [SCPCR] = sci_reg_invalid,
257 [SCPDR] = sci_reg_invalid,
258 [SCDL] = sci_reg_invalid,
259 [SCCKS] = sci_reg_invalid,
263 * Common SH-3 SCIF definitions.
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
278 [HSSRR] = sci_reg_invalid,
279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
281 [SCDL] = sci_reg_invalid,
282 [SCCKS] = sci_reg_invalid,
286 * Common SH-4(A) SCIF(B) definitions.
288 [SCIx_SH4_SCIF_REGTYPE] = {
289 [SCSMR] = { 0x00, 16 },
290 [SCBRR] = { 0x04, 8 },
291 [SCSCR] = { 0x08, 16 },
292 [SCxTDR] = { 0x0c, 8 },
293 [SCxSR] = { 0x10, 16 },
294 [SCxRDR] = { 0x14, 8 },
295 [SCFCR] = { 0x18, 16 },
296 [SCFDR] = { 0x1c, 16 },
297 [SCTFDR] = sci_reg_invalid,
298 [SCRFDR] = sci_reg_invalid,
299 [SCSPTR] = { 0x20, 16 },
300 [SCLSR] = { 0x24, 16 },
301 [HSSRR] = sci_reg_invalid,
302 [SCPCR] = sci_reg_invalid,
303 [SCPDR] = sci_reg_invalid,
304 [SCDL] = sci_reg_invalid,
305 [SCCKS] = sci_reg_invalid,
309 * Common SCIF definitions for ports with a Baud Rate Generator for
310 * External Clock (BRG).
312 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = sci_reg_invalid,
322 [SCRFDR] = sci_reg_invalid,
323 [SCSPTR] = { 0x20, 16 },
324 [SCLSR] = { 0x24, 16 },
325 [HSSRR] = sci_reg_invalid,
326 [SCPCR] = sci_reg_invalid,
327 [SCPDR] = sci_reg_invalid,
328 [SCDL] = { 0x30, 16 },
329 [SCCKS] = { 0x34, 16 },
333 * Common HSCIF definitions.
335 [SCIx_HSCIF_REGTYPE] = {
336 [SCSMR] = { 0x00, 16 },
337 [SCBRR] = { 0x04, 8 },
338 [SCSCR] = { 0x08, 16 },
339 [SCxTDR] = { 0x0c, 8 },
340 [SCxSR] = { 0x10, 16 },
341 [SCxRDR] = { 0x14, 8 },
342 [SCFCR] = { 0x18, 16 },
343 [SCFDR] = { 0x1c, 16 },
344 [SCTFDR] = sci_reg_invalid,
345 [SCRFDR] = sci_reg_invalid,
346 [SCSPTR] = { 0x20, 16 },
347 [SCLSR] = { 0x24, 16 },
348 [HSSRR] = { 0x40, 16 },
349 [SCPCR] = sci_reg_invalid,
350 [SCPDR] = sci_reg_invalid,
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
356 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
359 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
360 [SCSMR] = { 0x00, 16 },
361 [SCBRR] = { 0x04, 8 },
362 [SCSCR] = { 0x08, 16 },
363 [SCxTDR] = { 0x0c, 8 },
364 [SCxSR] = { 0x10, 16 },
365 [SCxRDR] = { 0x14, 8 },
366 [SCFCR] = { 0x18, 16 },
367 [SCFDR] = { 0x1c, 16 },
368 [SCTFDR] = sci_reg_invalid,
369 [SCRFDR] = sci_reg_invalid,
370 [SCSPTR] = sci_reg_invalid,
371 [SCLSR] = { 0x24, 16 },
372 [HSSRR] = sci_reg_invalid,
373 [SCPCR] = sci_reg_invalid,
374 [SCPDR] = sci_reg_invalid,
375 [SCDL] = sci_reg_invalid,
376 [SCCKS] = sci_reg_invalid,
380 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
383 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
384 [SCSMR] = { 0x00, 16 },
385 [SCBRR] = { 0x04, 8 },
386 [SCSCR] = { 0x08, 16 },
387 [SCxTDR] = { 0x0c, 8 },
388 [SCxSR] = { 0x10, 16 },
389 [SCxRDR] = { 0x14, 8 },
390 [SCFCR] = { 0x18, 16 },
391 [SCFDR] = { 0x1c, 16 },
392 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
393 [SCRFDR] = { 0x20, 16 },
394 [SCSPTR] = { 0x24, 16 },
395 [SCLSR] = { 0x28, 16 },
396 [HSSRR] = sci_reg_invalid,
397 [SCPCR] = sci_reg_invalid,
398 [SCPDR] = sci_reg_invalid,
399 [SCDL] = sci_reg_invalid,
400 [SCCKS] = sci_reg_invalid,
404 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
407 [SCIx_SH7705_SCIF_REGTYPE] = {
408 [SCSMR] = { 0x00, 16 },
409 [SCBRR] = { 0x04, 8 },
410 [SCSCR] = { 0x08, 16 },
411 [SCxTDR] = { 0x20, 8 },
412 [SCxSR] = { 0x14, 16 },
413 [SCxRDR] = { 0x24, 8 },
414 [SCFCR] = { 0x18, 16 },
415 [SCFDR] = { 0x1c, 16 },
416 [SCTFDR] = sci_reg_invalid,
417 [SCRFDR] = sci_reg_invalid,
418 [SCSPTR] = sci_reg_invalid,
419 [SCLSR] = sci_reg_invalid,
420 [HSSRR] = sci_reg_invalid,
421 [SCPCR] = sci_reg_invalid,
422 [SCPDR] = sci_reg_invalid,
423 [SCDL] = sci_reg_invalid,
424 [SCCKS] = sci_reg_invalid,
428 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
431 * The "offset" here is rather misleading, in that it refers to an enum
432 * value relative to the port mapping rather than the fixed offset
433 * itself, which needs to be manually retrieved from the platform's
434 * register map for the given port.
436 static unsigned int sci_serial_in(struct uart_port *p, int offset)
438 const struct plat_sci_reg *reg = sci_getreg(p, offset);
441 return ioread8(p->membase + (reg->offset << p->regshift));
442 else if (reg->size == 16)
443 return ioread16(p->membase + (reg->offset << p->regshift));
445 WARN(1, "Invalid register access\n");
450 static void sci_serial_out(struct uart_port *p, int offset, int value)
452 const struct plat_sci_reg *reg = sci_getreg(p, offset);
455 iowrite8(value, p->membase + (reg->offset << p->regshift));
456 else if (reg->size == 16)
457 iowrite16(value, p->membase + (reg->offset << p->regshift));
459 WARN(1, "Invalid register access\n");
462 static int sci_probe_regmap(struct plat_sci_port *cfg)
466 cfg->regtype = SCIx_SCI_REGTYPE;
469 cfg->regtype = SCIx_IRDA_REGTYPE;
472 cfg->regtype = SCIx_SCIFA_REGTYPE;
475 cfg->regtype = SCIx_SCIFB_REGTYPE;
479 * The SH-4 is a bit of a misnomer here, although that's
480 * where this particular port layout originated. This
481 * configuration (or some slight variation thereof)
482 * remains the dominant model for all SCIFs.
484 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
487 cfg->regtype = SCIx_HSCIF_REGTYPE;
490 pr_err("Can't probe register map for given port\n");
497 static void sci_port_enable(struct sci_port *sci_port)
499 if (!sci_port->port.dev)
502 pm_runtime_get_sync(sci_port->port.dev);
504 clk_prepare_enable(sci_port->fclk);
505 sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
508 static void sci_port_disable(struct sci_port *sci_port)
510 if (!sci_port->port.dev)
513 /* Cancel the break timer to ensure that the timer handler will not try
514 * to access the hardware with clocks and power disabled. Reset the
515 * break flag to make the break debouncing state machine ready for the
518 del_timer_sync(&sci_port->break_timer);
519 sci_port->break_flag = 0;
521 clk_disable_unprepare(sci_port->fclk);
523 pm_runtime_put_sync(sci_port->port.dev);
526 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
529 * Not all ports (such as SCIFA) will support REIE. Rather than
530 * special-casing the port type, we check the port initialization
531 * IRQ enable mask to see whether the IRQ is desired at all. If
532 * it's unset, it's logically inferred that there's no point in
535 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
538 static void sci_start_tx(struct uart_port *port)
540 struct sci_port *s = to_sci_port(port);
543 #ifdef CONFIG_SERIAL_SH_SCI_DMA
544 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
545 u16 new, scr = serial_port_in(port, SCSCR);
547 new = scr | SCSCR_TDRQE;
549 new = scr & ~SCSCR_TDRQE;
551 serial_port_out(port, SCSCR, new);
554 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
555 dma_submit_error(s->cookie_tx)) {
557 schedule_work(&s->work_tx);
561 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
562 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
563 ctrl = serial_port_in(port, SCSCR);
564 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 static void sci_stop_tx(struct uart_port *port)
572 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
573 ctrl = serial_port_in(port, SCSCR);
575 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
576 ctrl &= ~SCSCR_TDRQE;
580 serial_port_out(port, SCSCR, ctrl);
583 static void sci_start_rx(struct uart_port *port)
587 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
589 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
590 ctrl &= ~SCSCR_RDRQE;
592 serial_port_out(port, SCSCR, ctrl);
595 static void sci_stop_rx(struct uart_port *port)
599 ctrl = serial_port_in(port, SCSCR);
601 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
602 ctrl &= ~SCSCR_RDRQE;
604 ctrl &= ~port_rx_irq_mask(port);
606 serial_port_out(port, SCSCR, ctrl);
609 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
611 if (port->type == PORT_SCI) {
612 /* Just store the mask */
613 serial_port_out(port, SCxSR, mask);
614 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
615 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
616 /* Only clear the status bits we want to clear */
617 serial_port_out(port, SCxSR,
618 serial_port_in(port, SCxSR) & mask);
620 /* Store the mask, clear parity/framing errors */
621 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
627 #ifdef CONFIG_CONSOLE_POLL
628 static int sci_poll_get_char(struct uart_port *port)
630 unsigned short status;
634 status = serial_port_in(port, SCxSR);
635 if (status & SCxSR_ERRORS(port)) {
636 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
642 if (!(status & SCxSR_RDxF(port)))
645 c = serial_port_in(port, SCxRDR);
648 serial_port_in(port, SCxSR);
649 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
655 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
657 unsigned short status;
660 status = serial_port_in(port, SCxSR);
661 } while (!(status & SCxSR_TDxE(port)));
663 serial_port_out(port, SCxTDR, c);
664 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
666 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
668 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
670 struct sci_port *s = to_sci_port(port);
671 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
674 * Use port-specific handler if provided.
676 if (s->cfg->ops && s->cfg->ops->init_pins) {
677 s->cfg->ops->init_pins(port, cflag);
682 * For the generic path SCSPTR is necessary. Bail out if that's
688 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
689 ((!(cflag & CRTSCTS)))) {
690 unsigned short status;
692 status = serial_port_in(port, SCSPTR);
693 status &= ~SCSPTR_CTSIO;
694 status |= SCSPTR_RTSIO;
695 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
699 static int sci_txfill(struct uart_port *port)
701 const struct plat_sci_reg *reg;
703 reg = sci_getreg(port, SCTFDR);
705 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
707 reg = sci_getreg(port, SCFDR);
709 return serial_port_in(port, SCFDR) >> 8;
711 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
714 static int sci_txroom(struct uart_port *port)
716 return port->fifosize - sci_txfill(port);
719 static int sci_rxfill(struct uart_port *port)
721 const struct plat_sci_reg *reg;
723 reg = sci_getreg(port, SCRFDR);
725 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
727 reg = sci_getreg(port, SCFDR);
729 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
731 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
735 * SCI helper for checking the state of the muxed port/RXD pins.
737 static inline int sci_rxd_in(struct uart_port *port)
739 struct sci_port *s = to_sci_port(port);
741 if (s->cfg->port_reg <= 0)
744 /* Cast for ARM damage */
745 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
748 /* ********************************************************************** *
749 * the interrupt related routines *
750 * ********************************************************************** */
752 static void sci_transmit_chars(struct uart_port *port)
754 struct circ_buf *xmit = &port->state->xmit;
755 unsigned int stopped = uart_tx_stopped(port);
756 unsigned short status;
760 status = serial_port_in(port, SCxSR);
761 if (!(status & SCxSR_TDxE(port))) {
762 ctrl = serial_port_in(port, SCSCR);
763 if (uart_circ_empty(xmit))
767 serial_port_out(port, SCSCR, ctrl);
771 count = sci_txroom(port);
779 } else if (!uart_circ_empty(xmit) && !stopped) {
780 c = xmit->buf[xmit->tail];
781 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
786 serial_port_out(port, SCxTDR, c);
789 } while (--count > 0);
791 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
793 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
794 uart_write_wakeup(port);
795 if (uart_circ_empty(xmit)) {
798 ctrl = serial_port_in(port, SCSCR);
800 if (port->type != PORT_SCI) {
801 serial_port_in(port, SCxSR); /* Dummy read */
802 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
806 serial_port_out(port, SCSCR, ctrl);
810 /* On SH3, SCIF may read end-of-break as a space->mark char */
811 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
813 static void sci_receive_chars(struct uart_port *port)
815 struct sci_port *sci_port = to_sci_port(port);
816 struct tty_port *tport = &port->state->port;
817 int i, count, copied = 0;
818 unsigned short status;
821 status = serial_port_in(port, SCxSR);
822 if (!(status & SCxSR_RDxF(port)))
826 /* Don't copy more bytes than there is room for in the buffer */
827 count = tty_buffer_request_room(tport, sci_rxfill(port));
829 /* If for any reason we can't copy more data, we're done! */
833 if (port->type == PORT_SCI) {
834 char c = serial_port_in(port, SCxRDR);
835 if (uart_handle_sysrq_char(port, c) ||
836 sci_port->break_flag)
839 tty_insert_flip_char(tport, c, TTY_NORMAL);
841 for (i = 0; i < count; i++) {
842 char c = serial_port_in(port, SCxRDR);
844 status = serial_port_in(port, SCxSR);
845 #if defined(CONFIG_CPU_SH3)
846 /* Skip "chars" during break */
847 if (sci_port->break_flag) {
849 (status & SCxSR_FER(port))) {
854 /* Nonzero => end-of-break */
855 dev_dbg(port->dev, "debounce<%02x>\n", c);
856 sci_port->break_flag = 0;
863 #endif /* CONFIG_CPU_SH3 */
864 if (uart_handle_sysrq_char(port, c)) {
869 /* Store data and status */
870 if (status & SCxSR_FER(port)) {
872 port->icount.frame++;
873 dev_notice(port->dev, "frame error\n");
874 } else if (status & SCxSR_PER(port)) {
876 port->icount.parity++;
877 dev_notice(port->dev, "parity error\n");
881 tty_insert_flip_char(tport, c, flag);
885 serial_port_in(port, SCxSR); /* dummy read */
886 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
889 port->icount.rx += count;
893 /* Tell the rest of the system the news. New characters! */
894 tty_flip_buffer_push(tport);
896 serial_port_in(port, SCxSR); /* dummy read */
897 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
901 #define SCI_BREAK_JIFFIES (HZ/20)
904 * The sci generates interrupts during the break,
905 * 1 per millisecond or so during the break period, for 9600 baud.
906 * So dont bother disabling interrupts.
907 * But dont want more than 1 break event.
908 * Use a kernel timer to periodically poll the rx line until
909 * the break is finished.
911 static inline void sci_schedule_break_timer(struct sci_port *port)
913 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
916 /* Ensure that two consecutive samples find the break over. */
917 static void sci_break_timer(unsigned long data)
919 struct sci_port *port = (struct sci_port *)data;
921 if (sci_rxd_in(&port->port) == 0) {
922 port->break_flag = 1;
923 sci_schedule_break_timer(port);
924 } else if (port->break_flag == 1) {
926 port->break_flag = 2;
927 sci_schedule_break_timer(port);
929 port->break_flag = 0;
932 static int sci_handle_errors(struct uart_port *port)
935 unsigned short status = serial_port_in(port, SCxSR);
936 struct tty_port *tport = &port->state->port;
937 struct sci_port *s = to_sci_port(port);
939 /* Handle overruns */
940 if (status & s->overrun_mask) {
941 port->icount.overrun++;
944 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
947 dev_notice(port->dev, "overrun error\n");
950 if (status & SCxSR_FER(port)) {
951 if (sci_rxd_in(port) == 0) {
952 /* Notify of BREAK */
953 struct sci_port *sci_port = to_sci_port(port);
955 if (!sci_port->break_flag) {
958 sci_port->break_flag = 1;
959 sci_schedule_break_timer(sci_port);
961 /* Do sysrq handling. */
962 if (uart_handle_break(port))
965 dev_dbg(port->dev, "BREAK detected\n");
967 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
973 port->icount.frame++;
975 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
978 dev_notice(port->dev, "frame error\n");
982 if (status & SCxSR_PER(port)) {
984 port->icount.parity++;
986 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
989 dev_notice(port->dev, "parity error\n");
993 tty_flip_buffer_push(tport);
998 static int sci_handle_fifo_overrun(struct uart_port *port)
1000 struct tty_port *tport = &port->state->port;
1001 struct sci_port *s = to_sci_port(port);
1002 const struct plat_sci_reg *reg;
1006 reg = sci_getreg(port, s->overrun_reg);
1010 status = serial_port_in(port, s->overrun_reg);
1011 if (status & s->overrun_mask) {
1012 status &= ~s->overrun_mask;
1013 serial_port_out(port, s->overrun_reg, status);
1015 port->icount.overrun++;
1017 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1018 tty_flip_buffer_push(tport);
1020 dev_dbg(port->dev, "overrun error\n");
1027 static int sci_handle_breaks(struct uart_port *port)
1030 unsigned short status = serial_port_in(port, SCxSR);
1031 struct tty_port *tport = &port->state->port;
1032 struct sci_port *s = to_sci_port(port);
1034 if (uart_handle_break(port))
1037 if (!s->break_flag && status & SCxSR_BRK(port)) {
1038 #if defined(CONFIG_CPU_SH3)
1039 /* Debounce break */
1045 /* Notify of BREAK */
1046 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1049 dev_dbg(port->dev, "BREAK detected\n");
1053 tty_flip_buffer_push(tport);
1055 copied += sci_handle_fifo_overrun(port);
1060 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1061 static void sci_dma_tx_complete(void *arg)
1063 struct sci_port *s = arg;
1064 struct uart_port *port = &s->port;
1065 struct circ_buf *xmit = &port->state->xmit;
1066 unsigned long flags;
1068 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1070 spin_lock_irqsave(&port->lock, flags);
1072 xmit->tail += s->tx_dma_len;
1073 xmit->tail &= UART_XMIT_SIZE - 1;
1075 port->icount.tx += s->tx_dma_len;
1077 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1078 uart_write_wakeup(port);
1080 if (!uart_circ_empty(xmit)) {
1082 schedule_work(&s->work_tx);
1084 s->cookie_tx = -EINVAL;
1085 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1086 u16 ctrl = serial_port_in(port, SCSCR);
1087 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1091 spin_unlock_irqrestore(&port->lock, flags);
1094 /* Locking: called with port lock held */
1095 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1097 struct uart_port *port = &s->port;
1098 struct tty_port *tport = &port->state->port;
1101 copied = tty_insert_flip_string(tport, buf, count);
1102 if (copied < count) {
1103 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1105 port->icount.buf_overrun++;
1108 port->icount.rx += copied;
1113 static int sci_dma_rx_find_active(struct sci_port *s)
1117 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1118 if (s->active_rx == s->cookie_rx[i])
1121 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1126 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1128 struct dma_chan *chan = s->chan_rx;
1129 struct uart_port *port = &s->port;
1130 unsigned long flags;
1132 spin_lock_irqsave(&port->lock, flags);
1134 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1135 spin_unlock_irqrestore(&port->lock, flags);
1136 dmaengine_terminate_all(chan);
1137 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1138 sg_dma_address(&s->sg_rx[0]));
1139 dma_release_channel(chan);
1144 static void sci_dma_rx_complete(void *arg)
1146 struct sci_port *s = arg;
1147 struct dma_chan *chan = s->chan_rx;
1148 struct uart_port *port = &s->port;
1149 struct dma_async_tx_descriptor *desc;
1150 unsigned long flags;
1151 int active, count = 0;
1153 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1156 spin_lock_irqsave(&port->lock, flags);
1158 active = sci_dma_rx_find_active(s);
1160 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1162 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1165 tty_flip_buffer_push(&port->state->port);
1167 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1173 desc->callback = sci_dma_rx_complete;
1174 desc->callback_param = s;
1175 s->cookie_rx[active] = dmaengine_submit(desc);
1176 if (dma_submit_error(s->cookie_rx[active]))
1179 s->active_rx = s->cookie_rx[!active];
1181 dma_async_issue_pending(chan);
1183 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1184 __func__, s->cookie_rx[active], active, s->active_rx);
1185 spin_unlock_irqrestore(&port->lock, flags);
1189 spin_unlock_irqrestore(&port->lock, flags);
1190 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1191 sci_rx_dma_release(s, true);
1194 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1196 struct dma_chan *chan = s->chan_tx;
1197 struct uart_port *port = &s->port;
1198 unsigned long flags;
1200 spin_lock_irqsave(&port->lock, flags);
1202 s->cookie_tx = -EINVAL;
1203 spin_unlock_irqrestore(&port->lock, flags);
1204 dmaengine_terminate_all(chan);
1205 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1207 dma_release_channel(chan);
1212 static void sci_submit_rx(struct sci_port *s)
1214 struct dma_chan *chan = s->chan_rx;
1217 for (i = 0; i < 2; i++) {
1218 struct scatterlist *sg = &s->sg_rx[i];
1219 struct dma_async_tx_descriptor *desc;
1221 desc = dmaengine_prep_slave_sg(chan,
1222 sg, 1, DMA_DEV_TO_MEM,
1223 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1227 desc->callback = sci_dma_rx_complete;
1228 desc->callback_param = s;
1229 s->cookie_rx[i] = dmaengine_submit(desc);
1230 if (dma_submit_error(s->cookie_rx[i]))
1233 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1234 s->cookie_rx[i], i);
1237 s->active_rx = s->cookie_rx[0];
1239 dma_async_issue_pending(chan);
1244 dmaengine_terminate_all(chan);
1245 for (i = 0; i < 2; i++)
1246 s->cookie_rx[i] = -EINVAL;
1247 s->active_rx = -EINVAL;
1248 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1249 sci_rx_dma_release(s, true);
1252 static void work_fn_tx(struct work_struct *work)
1254 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1255 struct dma_async_tx_descriptor *desc;
1256 struct dma_chan *chan = s->chan_tx;
1257 struct uart_port *port = &s->port;
1258 struct circ_buf *xmit = &port->state->xmit;
1263 * Port xmit buffer is already mapped, and it is one page... Just adjust
1264 * offsets and lengths. Since it is a circular buffer, we have to
1265 * transmit till the end, and then the rest. Take the port lock to get a
1266 * consistent xmit buffer state.
1268 spin_lock_irq(&port->lock);
1269 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1270 s->tx_dma_len = min_t(unsigned int,
1271 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1272 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1273 spin_unlock_irq(&port->lock);
1275 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1277 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1279 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1281 sci_tx_dma_release(s, true);
1285 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1288 spin_lock_irq(&port->lock);
1289 desc->callback = sci_dma_tx_complete;
1290 desc->callback_param = s;
1291 spin_unlock_irq(&port->lock);
1292 s->cookie_tx = dmaengine_submit(desc);
1293 if (dma_submit_error(s->cookie_tx)) {
1294 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1296 sci_tx_dma_release(s, true);
1300 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1301 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1303 dma_async_issue_pending(chan);
1306 static void rx_timer_fn(unsigned long arg)
1308 struct sci_port *s = (struct sci_port *)arg;
1309 struct dma_chan *chan = s->chan_rx;
1310 struct uart_port *port = &s->port;
1311 struct dma_tx_state state;
1312 enum dma_status status;
1313 unsigned long flags;
1318 spin_lock_irqsave(&port->lock, flags);
1320 dev_dbg(port->dev, "DMA Rx timed out\n");
1322 active = sci_dma_rx_find_active(s);
1324 spin_unlock_irqrestore(&port->lock, flags);
1328 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1329 if (status == DMA_COMPLETE) {
1330 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1331 s->active_rx, active);
1332 spin_unlock_irqrestore(&port->lock, flags);
1334 /* Let packet complete handler take care of the packet */
1338 dmaengine_pause(chan);
1341 * sometimes DMA transfer doesn't stop even if it is stopped and
1342 * data keeps on coming until transaction is complete so check
1343 * for DMA_COMPLETE again
1344 * Let packet complete handler take care of the packet
1346 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1347 if (status == DMA_COMPLETE) {
1348 spin_unlock_irqrestore(&port->lock, flags);
1349 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1353 /* Handle incomplete DMA receive */
1354 dmaengine_terminate_all(s->chan_rx);
1355 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1356 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1360 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1362 tty_flip_buffer_push(&port->state->port);
1365 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1368 /* Direct new serial port interrupts back to CPU */
1369 scr = serial_port_in(port, SCSCR);
1370 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1371 scr &= ~SCSCR_RDRQE;
1372 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1374 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1376 spin_unlock_irqrestore(&port->lock, flags);
1379 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1380 enum dma_transfer_direction dir,
1383 dma_cap_mask_t mask;
1384 struct dma_chan *chan;
1385 struct dma_slave_config cfg;
1389 dma_cap_set(DMA_SLAVE, mask);
1391 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1392 (void *)(unsigned long)id, port->dev,
1393 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1396 "dma_request_slave_channel_compat failed\n");
1400 memset(&cfg, 0, sizeof(cfg));
1401 cfg.direction = dir;
1402 if (dir == DMA_MEM_TO_DEV) {
1403 cfg.dst_addr = port->mapbase +
1404 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1405 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1407 cfg.src_addr = port->mapbase +
1408 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1409 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1412 ret = dmaengine_slave_config(chan, &cfg);
1414 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1415 dma_release_channel(chan);
1422 static void sci_request_dma(struct uart_port *port)
1424 struct sci_port *s = to_sci_port(port);
1425 struct dma_chan *chan;
1427 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1429 if (!port->dev->of_node &&
1430 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1433 s->cookie_tx = -EINVAL;
1434 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1435 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1438 /* UART circular tx buffer is an aligned page. */
1439 s->tx_dma_addr = dma_map_single(chan->device->dev,
1440 port->state->xmit.buf,
1443 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1444 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1445 dma_release_channel(chan);
1448 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1449 __func__, UART_XMIT_SIZE,
1450 port->state->xmit.buf, &s->tx_dma_addr);
1453 INIT_WORK(&s->work_tx, work_fn_tx);
1456 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1457 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1465 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1466 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1470 "Failed to allocate Rx dma buffer, using PIO\n");
1471 dma_release_channel(chan);
1476 for (i = 0; i < 2; i++) {
1477 struct scatterlist *sg = &s->sg_rx[i];
1479 sg_init_table(sg, 1);
1481 sg_dma_address(sg) = dma;
1482 sg->length = s->buf_len_rx;
1484 buf += s->buf_len_rx;
1485 dma += s->buf_len_rx;
1488 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1490 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1495 static void sci_free_dma(struct uart_port *port)
1497 struct sci_port *s = to_sci_port(port);
1500 sci_tx_dma_release(s, false);
1502 sci_rx_dma_release(s, false);
1505 static inline void sci_request_dma(struct uart_port *port)
1509 static inline void sci_free_dma(struct uart_port *port)
1514 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1516 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1517 struct uart_port *port = ptr;
1518 struct sci_port *s = to_sci_port(port);
1521 u16 scr = serial_port_in(port, SCSCR);
1522 u16 ssr = serial_port_in(port, SCxSR);
1524 /* Disable future Rx interrupts */
1525 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1526 disable_irq_nosync(irq);
1532 serial_port_out(port, SCSCR, scr);
1533 /* Clear current interrupt */
1534 serial_port_out(port, SCxSR,
1535 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1536 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1537 jiffies, s->rx_timeout);
1538 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1544 /* I think sci_receive_chars has to be called irrespective
1545 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1548 sci_receive_chars(ptr);
1553 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1555 struct uart_port *port = ptr;
1556 unsigned long flags;
1558 spin_lock_irqsave(&port->lock, flags);
1559 sci_transmit_chars(port);
1560 spin_unlock_irqrestore(&port->lock, flags);
1565 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1567 struct uart_port *port = ptr;
1568 struct sci_port *s = to_sci_port(port);
1571 if (port->type == PORT_SCI) {
1572 if (sci_handle_errors(port)) {
1573 /* discard character in rx buffer */
1574 serial_port_in(port, SCxSR);
1575 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1578 sci_handle_fifo_overrun(port);
1580 sci_receive_chars(ptr);
1583 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1585 /* Kick the transmission */
1587 sci_tx_interrupt(irq, ptr);
1592 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1594 struct uart_port *port = ptr;
1597 sci_handle_breaks(port);
1598 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1603 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1605 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1606 struct uart_port *port = ptr;
1607 struct sci_port *s = to_sci_port(port);
1608 irqreturn_t ret = IRQ_NONE;
1610 ssr_status = serial_port_in(port, SCxSR);
1611 scr_status = serial_port_in(port, SCSCR);
1612 if (s->overrun_reg == SCxSR)
1613 orer_status = ssr_status;
1615 if (sci_getreg(port, s->overrun_reg)->size)
1616 orer_status = serial_port_in(port, s->overrun_reg);
1619 err_enabled = scr_status & port_rx_irq_mask(port);
1622 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1624 ret = sci_tx_interrupt(irq, ptr);
1627 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1630 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1631 (scr_status & SCSCR_RIE))
1632 ret = sci_rx_interrupt(irq, ptr);
1634 /* Error Interrupt */
1635 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1636 ret = sci_er_interrupt(irq, ptr);
1638 /* Break Interrupt */
1639 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1640 ret = sci_br_interrupt(irq, ptr);
1642 /* Overrun Interrupt */
1643 if (orer_status & s->overrun_mask) {
1644 sci_handle_fifo_overrun(port);
1652 * Here we define a transition notifier so that we can update all of our
1653 * ports' baud rate when the peripheral clock changes.
1655 static int sci_notifier(struct notifier_block *self,
1656 unsigned long phase, void *p)
1658 struct sci_port *sci_port;
1659 unsigned long flags;
1661 sci_port = container_of(self, struct sci_port, freq_transition);
1663 if (phase == CPUFREQ_POSTCHANGE) {
1664 struct uart_port *port = &sci_port->port;
1666 spin_lock_irqsave(&port->lock, flags);
1667 port->uartclk = clk_get_rate(sci_port->fclk);
1668 spin_unlock_irqrestore(&port->lock, flags);
1674 static const struct sci_irq_desc {
1676 irq_handler_t handler;
1677 } sci_irq_desc[] = {
1679 * Split out handlers, the default case.
1683 .handler = sci_er_interrupt,
1688 .handler = sci_rx_interrupt,
1693 .handler = sci_tx_interrupt,
1698 .handler = sci_br_interrupt,
1702 * Special muxed handler.
1706 .handler = sci_mpxed_interrupt,
1710 static int sci_request_irq(struct sci_port *port)
1712 struct uart_port *up = &port->port;
1715 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1716 const struct sci_irq_desc *desc;
1719 if (SCIx_IRQ_IS_MUXED(port)) {
1723 irq = port->irqs[i];
1726 * Certain port types won't support all of the
1727 * available interrupt sources.
1729 if (unlikely(irq < 0))
1733 desc = sci_irq_desc + i;
1734 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1735 dev_name(up->dev), desc->desc);
1736 if (!port->irqstr[j])
1739 ret = request_irq(irq, desc->handler, up->irqflags,
1740 port->irqstr[j], port);
1741 if (unlikely(ret)) {
1742 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1751 free_irq(port->irqs[i], port);
1755 kfree(port->irqstr[j]);
1760 static void sci_free_irq(struct sci_port *port)
1765 * Intentionally in reverse order so we iterate over the muxed
1768 for (i = 0; i < SCIx_NR_IRQS; i++) {
1769 int irq = port->irqs[i];
1772 * Certain port types won't support all of the available
1773 * interrupt sources.
1775 if (unlikely(irq < 0))
1778 free_irq(port->irqs[i], port);
1779 kfree(port->irqstr[i]);
1781 if (SCIx_IRQ_IS_MUXED(port)) {
1782 /* If there's only one IRQ, we're done. */
1788 static unsigned int sci_tx_empty(struct uart_port *port)
1790 unsigned short status = serial_port_in(port, SCxSR);
1791 unsigned short in_tx_fifo = sci_txfill(port);
1793 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1797 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1798 * CTS/RTS is supported in hardware by at least one port and controlled
1799 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1800 * handled via the ->init_pins() op, which is a bit of a one-way street,
1801 * lacking any ability to defer pin control -- this will later be
1802 * converted over to the GPIO framework).
1804 * Other modes (such as loopback) are supported generically on certain
1805 * port types, but not others. For these it's sufficient to test for the
1806 * existence of the support register and simply ignore the port type.
1808 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1810 if (mctrl & TIOCM_LOOP) {
1811 const struct plat_sci_reg *reg;
1814 * Standard loopback mode for SCFCR ports.
1816 reg = sci_getreg(port, SCFCR);
1818 serial_port_out(port, SCFCR,
1819 serial_port_in(port, SCFCR) |
1824 static unsigned int sci_get_mctrl(struct uart_port *port)
1827 * CTS/RTS is handled in hardware when supported, while nothing
1828 * else is wired up. Keep it simple and simply assert DSR/CAR.
1830 return TIOCM_DSR | TIOCM_CAR;
1833 static void sci_break_ctl(struct uart_port *port, int break_state)
1835 struct sci_port *s = to_sci_port(port);
1836 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1837 unsigned short scscr, scsptr;
1839 /* check wheter the port has SCSPTR */
1842 * Not supported by hardware. Most parts couple break and rx
1843 * interrupts together, with break detection always enabled.
1848 scsptr = serial_port_in(port, SCSPTR);
1849 scscr = serial_port_in(port, SCSCR);
1851 if (break_state == -1) {
1852 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1855 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1859 serial_port_out(port, SCSPTR, scsptr);
1860 serial_port_out(port, SCSCR, scscr);
1863 static int sci_startup(struct uart_port *port)
1865 struct sci_port *s = to_sci_port(port);
1866 unsigned long flags;
1869 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1871 ret = sci_request_irq(s);
1872 if (unlikely(ret < 0))
1875 sci_request_dma(port);
1877 spin_lock_irqsave(&port->lock, flags);
1880 spin_unlock_irqrestore(&port->lock, flags);
1885 static void sci_shutdown(struct uart_port *port)
1887 struct sci_port *s = to_sci_port(port);
1888 unsigned long flags;
1890 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1892 spin_lock_irqsave(&port->lock, flags);
1895 spin_unlock_irqrestore(&port->lock, flags);
1897 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1899 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1901 del_timer_sync(&s->rx_timer);
1909 /* calculate sample rate, BRR, and clock select */
1910 static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1911 unsigned long freq, int *brr, unsigned int *srr,
1914 unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
1915 int err, min_err = INT_MAX;
1917 if (s->sampling_rate) {
1918 min_sr = max_sr = s->sampling_rate;
1921 /* HSCIF has a variable sample rate */
1928 * Find the combination of sample rate and clock select with the
1929 * smallest deviation from the desired baud rate.
1930 * Prefer high sample rates to maximise the receive margin.
1932 * M: Receive margin (%)
1933 * N: Ratio of bit rate to clock (N = sampling rate)
1934 * D: Clock duty (D = 0 to 1.0)
1935 * L: Frame length (L = 9 to 12)
1936 * F: Absolute value of clock frequency deviation
1938 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1939 * (|D - 0.5| / N * (1 + F))|
1940 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
1942 for (sr = max_sr; sr >= min_sr; sr--) {
1943 for (c = 0; c <= 3; c++) {
1944 /* integerized formulas from HSCIF documentation */
1945 prediv = sr * (1 << (2 * c + shift));
1948 * We need to calculate:
1950 * br = freq / (prediv * bps) clamped to [1..256]
1951 * err = freq / (br * prediv) - bps
1953 * Watch out for overflow when calculating the desired
1954 * sampling clock rate!
1956 if (bps > UINT_MAX / prediv)
1959 scrate = prediv * bps;
1960 br = DIV_ROUND_CLOSEST(freq, scrate);
1961 br = clamp(br, 1U, 256U);
1963 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
1964 if (abs(err) >= abs(min_err))
1978 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
1979 min_err, *brr, *srr + 1, *cks);
1982 static void sci_reset(struct uart_port *port)
1984 const struct plat_sci_reg *reg;
1985 unsigned int status;
1988 status = serial_port_in(port, SCxSR);
1989 } while (!(status & SCxSR_TEND(port)));
1991 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1993 reg = sci_getreg(port, SCFCR);
1995 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1998 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1999 struct ktermios *old)
2001 struct sci_port *s = to_sci_port(port);
2002 const struct plat_sci_reg *reg;
2003 unsigned int baud, smr_val = 0, max_baud, cks = 0;
2005 unsigned int srr = 15;
2007 if ((termios->c_cflag & CSIZE) == CS7)
2008 smr_val |= SCSMR_CHR;
2009 if (termios->c_cflag & PARENB)
2010 smr_val |= SCSMR_PE;
2011 if (termios->c_cflag & PARODD)
2012 smr_val |= SCSMR_PE | SCSMR_ODD;
2013 if (termios->c_cflag & CSTOPB)
2014 smr_val |= SCSMR_STOP;
2017 * earlyprintk comes here early on with port->uartclk set to zero.
2018 * the clock framework is not up and running at this point so here
2019 * we assume that 115200 is the maximum baud rate. please note that
2020 * the baud rate is not programmed during earlyprintk - it is assumed
2021 * that the previous boot loader has enabled required clocks and
2022 * setup the baud rate generator hardware for us already.
2025 max_baud = port->uartclk / max(s->sampling_rate, 8U);
2029 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
2030 if (likely(baud && port->uartclk))
2031 sci_scbrr_calc(s, baud, port->uartclk, &t, &srr, &cks);
2037 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2039 uart_update_timeout(port, termios->c_cflag, baud);
2041 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2042 __func__, smr_val, cks, t, s->cfg->scscr);
2045 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
2046 serial_port_out(port, SCBRR, t);
2047 reg = sci_getreg(port, HSSRR);
2049 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2050 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2052 serial_port_out(port, SCSMR, smr_val);
2054 sci_init_pins(port, termios->c_cflag);
2056 reg = sci_getreg(port, SCFCR);
2058 unsigned short ctrl = serial_port_in(port, SCFCR);
2060 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2061 if (termios->c_cflag & CRTSCTS)
2068 * As we've done a sci_reset() above, ensure we don't
2069 * interfere with the FIFOs while toggling MCE. As the
2070 * reset values could still be set, simply mask them out.
2072 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2074 serial_port_out(port, SCFCR, ctrl);
2077 serial_port_out(port, SCSCR, s->cfg->scscr);
2079 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2081 * Calculate delay for 2 DMA buffers (4 FIFO).
2082 * See serial_core.c::uart_update_timeout().
2083 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2084 * function calculates 1 jiffie for the data plus 5 jiffies for the
2085 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2086 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2087 * value obtained by this formula is too small. Therefore, if the value
2088 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2093 /* byte size and parity */
2094 switch (termios->c_cflag & CSIZE) {
2109 if (termios->c_cflag & CSTOPB)
2111 if (termios->c_cflag & PARENB)
2113 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2115 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2116 s->rx_timeout * 1000 / HZ, port->timeout);
2117 if (s->rx_timeout < msecs_to_jiffies(20))
2118 s->rx_timeout = msecs_to_jiffies(20);
2122 if ((termios->c_cflag & CREAD) != 0)
2125 sci_port_disable(s);
2128 static void sci_pm(struct uart_port *port, unsigned int state,
2129 unsigned int oldstate)
2131 struct sci_port *sci_port = to_sci_port(port);
2134 case UART_PM_STATE_OFF:
2135 sci_port_disable(sci_port);
2138 sci_port_enable(sci_port);
2143 static const char *sci_type(struct uart_port *port)
2145 switch (port->type) {
2163 static int sci_remap_port(struct uart_port *port)
2165 struct sci_port *sport = to_sci_port(port);
2168 * Nothing to do if there's already an established membase.
2173 if (port->flags & UPF_IOREMAP) {
2174 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2175 if (unlikely(!port->membase)) {
2176 dev_err(port->dev, "can't remap port#%d\n", port->line);
2181 * For the simple (and majority of) cases where we don't
2182 * need to do any remapping, just cast the cookie
2185 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2191 static void sci_release_port(struct uart_port *port)
2193 struct sci_port *sport = to_sci_port(port);
2195 if (port->flags & UPF_IOREMAP) {
2196 iounmap(port->membase);
2197 port->membase = NULL;
2200 release_mem_region(port->mapbase, sport->reg_size);
2203 static int sci_request_port(struct uart_port *port)
2205 struct resource *res;
2206 struct sci_port *sport = to_sci_port(port);
2209 res = request_mem_region(port->mapbase, sport->reg_size,
2210 dev_name(port->dev));
2211 if (unlikely(res == NULL)) {
2212 dev_err(port->dev, "request_mem_region failed.");
2216 ret = sci_remap_port(port);
2217 if (unlikely(ret != 0)) {
2218 release_resource(res);
2225 static void sci_config_port(struct uart_port *port, int flags)
2227 if (flags & UART_CONFIG_TYPE) {
2228 struct sci_port *sport = to_sci_port(port);
2230 port->type = sport->cfg->type;
2231 sci_request_port(port);
2235 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2237 if (ser->baud_base < 2400)
2238 /* No paper tape reader for Mitch.. */
2244 static struct uart_ops sci_uart_ops = {
2245 .tx_empty = sci_tx_empty,
2246 .set_mctrl = sci_set_mctrl,
2247 .get_mctrl = sci_get_mctrl,
2248 .start_tx = sci_start_tx,
2249 .stop_tx = sci_stop_tx,
2250 .stop_rx = sci_stop_rx,
2251 .break_ctl = sci_break_ctl,
2252 .startup = sci_startup,
2253 .shutdown = sci_shutdown,
2254 .set_termios = sci_set_termios,
2257 .release_port = sci_release_port,
2258 .request_port = sci_request_port,
2259 .config_port = sci_config_port,
2260 .verify_port = sci_verify_port,
2261 #ifdef CONFIG_CONSOLE_POLL
2262 .poll_get_char = sci_poll_get_char,
2263 .poll_put_char = sci_poll_put_char,
2267 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2269 /* Get the SCI functional clock. It's called "fck" on ARM. */
2270 sci_port->fclk = devm_clk_get(dev, "fck");
2271 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2272 return -EPROBE_DEFER;
2273 if (!IS_ERR(sci_port->fclk))
2277 * But it used to be called "sci_ick", and we need to maintain DT
2278 * backward compatibility.
2280 sci_port->fclk = devm_clk_get(dev, "sci_ick");
2281 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2282 return -EPROBE_DEFER;
2283 if (!IS_ERR(sci_port->fclk))
2286 /* SH has historically named the clock "sci_fck". */
2287 sci_port->fclk = devm_clk_get(dev, "sci_fck");
2288 if (!IS_ERR(sci_port->fclk))
2292 * Not all SH platforms declare a clock lookup entry for SCI devices,
2293 * in which case we need to get the global "peripheral_clk" clock.
2295 sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
2296 if (!IS_ERR(sci_port->fclk))
2299 dev_err(dev, "failed to get functional clock\n");
2300 return PTR_ERR(sci_port->fclk);
2303 static int sci_init_single(struct platform_device *dev,
2304 struct sci_port *sci_port, unsigned int index,
2305 struct plat_sci_port *p, bool early)
2307 struct uart_port *port = &sci_port->port;
2308 const struct resource *res;
2314 port->ops = &sci_uart_ops;
2315 port->iotype = UPIO_MEM;
2318 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2322 port->mapbase = res->start;
2323 sci_port->reg_size = resource_size(res);
2325 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2326 sci_port->irqs[i] = platform_get_irq(dev, i);
2328 /* The SCI generates several interrupts. They can be muxed together or
2329 * connected to different interrupt lines. In the muxed case only one
2330 * interrupt resource is specified. In the non-muxed case three or four
2331 * interrupt resources are specified, as the BRI interrupt is optional.
2333 if (sci_port->irqs[0] < 0)
2336 if (sci_port->irqs[1] < 0) {
2337 sci_port->irqs[1] = sci_port->irqs[0];
2338 sci_port->irqs[2] = sci_port->irqs[0];
2339 sci_port->irqs[3] = sci_port->irqs[0];
2342 if (p->regtype == SCIx_PROBE_REGTYPE) {
2343 ret = sci_probe_regmap(p);
2350 port->fifosize = 256;
2351 sci_port->overrun_reg = SCxSR;
2352 sci_port->overrun_mask = SCIFA_ORER;
2353 sci_port->sampling_rate = 16;
2356 port->fifosize = 128;
2357 sci_port->overrun_reg = SCLSR;
2358 sci_port->overrun_mask = SCLSR_ORER;
2359 sci_port->sampling_rate = 0;
2362 port->fifosize = 64;
2363 sci_port->overrun_reg = SCxSR;
2364 sci_port->overrun_mask = SCIFA_ORER;
2365 sci_port->sampling_rate = 16;
2368 port->fifosize = 16;
2369 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2370 sci_port->overrun_reg = SCxSR;
2371 sci_port->overrun_mask = SCIFA_ORER;
2372 sci_port->sampling_rate = 16;
2374 sci_port->overrun_reg = SCLSR;
2375 sci_port->overrun_mask = SCLSR_ORER;
2376 sci_port->sampling_rate = 32;
2381 sci_port->overrun_reg = SCxSR;
2382 sci_port->overrun_mask = SCI_ORER;
2383 sci_port->sampling_rate = 32;
2387 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2388 * match the SoC datasheet, this should be investigated. Let platform
2389 * data override the sampling rate for now.
2391 if (p->sampling_rate)
2392 sci_port->sampling_rate = p->sampling_rate;
2395 ret = sci_init_clocks(sci_port, &dev->dev);
2399 port->dev = &dev->dev;
2401 pm_runtime_enable(&dev->dev);
2404 sci_port->break_timer.data = (unsigned long)sci_port;
2405 sci_port->break_timer.function = sci_break_timer;
2406 init_timer(&sci_port->break_timer);
2409 * Establish some sensible defaults for the error detection.
2411 if (p->type == PORT_SCI) {
2412 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2413 sci_port->error_clear = SCI_ERROR_CLEAR;
2415 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2416 sci_port->error_clear = SCIF_ERROR_CLEAR;
2420 * Make the error mask inclusive of overrun detection, if
2423 if (sci_port->overrun_reg == SCxSR) {
2424 sci_port->error_mask |= sci_port->overrun_mask;
2425 sci_port->error_clear &= ~sci_port->overrun_mask;
2428 port->type = p->type;
2429 port->flags = UPF_FIXED_PORT | p->flags;
2430 port->regshift = p->regshift;
2433 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2434 * for the multi-IRQ ports, which is where we are primarily
2435 * concerned with the shutdown path synchronization.
2437 * For the muxed case there's nothing more to do.
2439 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2442 port->serial_in = sci_serial_in;
2443 port->serial_out = sci_serial_out;
2445 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2446 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2447 p->dma_slave_tx, p->dma_slave_rx);
2452 static void sci_cleanup_single(struct sci_port *port)
2454 pm_runtime_disable(port->port.dev);
2457 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2458 static void serial_console_putchar(struct uart_port *port, int ch)
2460 sci_poll_put_char(port, ch);
2464 * Print a string to the serial port trying not to disturb
2465 * any possible real use of the port...
2467 static void serial_console_write(struct console *co, const char *s,
2470 struct sci_port *sci_port = &sci_ports[co->index];
2471 struct uart_port *port = &sci_port->port;
2472 unsigned short bits, ctrl, ctrl_temp;
2473 unsigned long flags;
2476 local_irq_save(flags);
2479 else if (oops_in_progress)
2480 locked = spin_trylock(&port->lock);
2482 spin_lock(&port->lock);
2484 /* first save SCSCR then disable interrupts, keep clock source */
2485 ctrl = serial_port_in(port, SCSCR);
2486 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2487 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2488 serial_port_out(port, SCSCR, ctrl_temp);
2490 uart_console_write(port, s, count, serial_console_putchar);
2492 /* wait until fifo is empty and last bit has been transmitted */
2493 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2494 while ((serial_port_in(port, SCxSR) & bits) != bits)
2497 /* restore the SCSCR */
2498 serial_port_out(port, SCSCR, ctrl);
2501 spin_unlock(&port->lock);
2502 local_irq_restore(flags);
2505 static int serial_console_setup(struct console *co, char *options)
2507 struct sci_port *sci_port;
2508 struct uart_port *port;
2516 * Refuse to handle any bogus ports.
2518 if (co->index < 0 || co->index >= SCI_NPORTS)
2521 sci_port = &sci_ports[co->index];
2522 port = &sci_port->port;
2525 * Refuse to handle uninitialized ports.
2530 ret = sci_remap_port(port);
2531 if (unlikely(ret != 0))
2535 uart_parse_options(options, &baud, &parity, &bits, &flow);
2537 return uart_set_options(port, co, baud, parity, bits, flow);
2540 static struct console serial_console = {
2542 .device = uart_console_device,
2543 .write = serial_console_write,
2544 .setup = serial_console_setup,
2545 .flags = CON_PRINTBUFFER,
2547 .data = &sci_uart_driver,
2550 static struct console early_serial_console = {
2551 .name = "early_ttySC",
2552 .write = serial_console_write,
2553 .flags = CON_PRINTBUFFER,
2557 static char early_serial_buf[32];
2559 static int sci_probe_earlyprintk(struct platform_device *pdev)
2561 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2563 if (early_serial_console.data)
2566 early_serial_console.index = pdev->id;
2568 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2570 serial_console_setup(&early_serial_console, early_serial_buf);
2572 if (!strstr(early_serial_buf, "keep"))
2573 early_serial_console.flags |= CON_BOOT;
2575 register_console(&early_serial_console);
2579 #define SCI_CONSOLE (&serial_console)
2582 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2587 #define SCI_CONSOLE NULL
2589 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2591 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2593 static struct uart_driver sci_uart_driver = {
2594 .owner = THIS_MODULE,
2595 .driver_name = "sci",
2596 .dev_name = "ttySC",
2598 .minor = SCI_MINOR_START,
2600 .cons = SCI_CONSOLE,
2603 static int sci_remove(struct platform_device *dev)
2605 struct sci_port *port = platform_get_drvdata(dev);
2607 cpufreq_unregister_notifier(&port->freq_transition,
2608 CPUFREQ_TRANSITION_NOTIFIER);
2610 uart_remove_one_port(&sci_uart_driver, &port->port);
2612 sci_cleanup_single(port);
2618 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2619 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2620 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2622 static const struct of_device_id of_sci_match[] = {
2623 /* SoC-specific types */
2625 .compatible = "renesas,scif-r7s72100",
2626 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2628 /* Family-specific types */
2630 .compatible = "renesas,rcar-gen1-scif",
2631 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2633 .compatible = "renesas,rcar-gen2-scif",
2634 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2636 .compatible = "renesas,rcar-gen3-scif",
2637 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2641 .compatible = "renesas,scif",
2642 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2644 .compatible = "renesas,scifa",
2645 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2647 .compatible = "renesas,scifb",
2648 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2650 .compatible = "renesas,hscif",
2651 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2653 .compatible = "renesas,sci",
2654 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2659 MODULE_DEVICE_TABLE(of, of_sci_match);
2661 static struct plat_sci_port *
2662 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2664 struct device_node *np = pdev->dev.of_node;
2665 const struct of_device_id *match;
2666 struct plat_sci_port *p;
2669 if (!IS_ENABLED(CONFIG_OF) || !np)
2672 match = of_match_node(of_sci_match, np);
2676 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2680 /* Get the line number from the aliases node. */
2681 id = of_alias_get_id(np, "serial");
2683 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2689 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2690 p->type = SCI_OF_TYPE(match->data);
2691 p->regtype = SCI_OF_REGTYPE(match->data);
2692 p->scscr = SCSCR_RE | SCSCR_TE;
2697 static int sci_probe_single(struct platform_device *dev,
2699 struct plat_sci_port *p,
2700 struct sci_port *sciport)
2705 if (unlikely(index >= SCI_NPORTS)) {
2706 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2707 index+1, SCI_NPORTS);
2708 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2712 ret = sci_init_single(dev, sciport, index, p, false);
2716 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2718 sci_cleanup_single(sciport);
2725 static int sci_probe(struct platform_device *dev)
2727 struct plat_sci_port *p;
2728 struct sci_port *sp;
2729 unsigned int dev_id;
2733 * If we've come here via earlyprintk initialization, head off to
2734 * the special early probe. We don't have sufficient device state
2735 * to make it beyond this yet.
2737 if (is_early_platform_device(dev))
2738 return sci_probe_earlyprintk(dev);
2740 if (dev->dev.of_node) {
2741 p = sci_parse_dt(dev, &dev_id);
2745 p = dev->dev.platform_data;
2747 dev_err(&dev->dev, "no platform data supplied\n");
2754 sp = &sci_ports[dev_id];
2755 platform_set_drvdata(dev, sp);
2757 ret = sci_probe_single(dev, dev_id, p, sp);
2761 sp->freq_transition.notifier_call = sci_notifier;
2763 ret = cpufreq_register_notifier(&sp->freq_transition,
2764 CPUFREQ_TRANSITION_NOTIFIER);
2765 if (unlikely(ret < 0)) {
2766 uart_remove_one_port(&sci_uart_driver, &sp->port);
2767 sci_cleanup_single(sp);
2771 #ifdef CONFIG_SH_STANDARD_BIOS
2772 sh_bios_gdb_detach();
2778 static __maybe_unused int sci_suspend(struct device *dev)
2780 struct sci_port *sport = dev_get_drvdata(dev);
2783 uart_suspend_port(&sci_uart_driver, &sport->port);
2788 static __maybe_unused int sci_resume(struct device *dev)
2790 struct sci_port *sport = dev_get_drvdata(dev);
2793 uart_resume_port(&sci_uart_driver, &sport->port);
2798 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2800 static struct platform_driver sci_driver = {
2802 .remove = sci_remove,
2805 .pm = &sci_dev_pm_ops,
2806 .of_match_table = of_match_ptr(of_sci_match),
2810 static int __init sci_init(void)
2814 pr_info("%s\n", banner);
2816 ret = uart_register_driver(&sci_uart_driver);
2817 if (likely(ret == 0)) {
2818 ret = platform_driver_register(&sci_driver);
2820 uart_unregister_driver(&sci_uart_driver);
2826 static void __exit sci_exit(void)
2828 platform_driver_unregister(&sci_driver);
2829 uart_unregister_driver(&sci_uart_driver);
2832 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2833 early_platform_init_buffer("earlyprintk", &sci_driver,
2834 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2836 module_init(sci_init);
2837 module_exit(sci_exit);
2839 MODULE_LICENSE("GPL");
2840 MODULE_ALIAS("platform:sh-sci");
2841 MODULE_AUTHOR("Paul Mundt");
2842 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");