1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
59 #include "serial_mctrl_gpio.h"
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
98 /* Iterate over all supported sampling rates, from high to low */
99 #define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103 struct plat_sci_reg {
107 struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
118 struct uart_port port;
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
137 #ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
152 unsigned int rx_frame;
154 struct timer_list rx_fifo_timer;
162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
164 static struct sci_port sci_ports[SCI_NPORTS];
165 static unsigned long sci_ports_in_use;
166 static struct uart_driver sci_uart_driver;
168 static inline struct sci_port *
169 to_sci_port(struct uart_port *uart)
171 return container_of(uart, struct sci_port, port);
174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
176 * Common SCI definitions, dependent on the port's regshift
179 [SCIx_SCI_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
197 * Common definitions for legacy IrDA ports.
199 [SCIx_IRDA_REGTYPE] = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
219 * Common SCIFA definitions.
221 [SCIx_SCIFA_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
243 * Common SCIFB definitions.
245 [SCIx_SCIFB_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
293 * Common SH-3 SCIF definitions.
295 [SCIx_SH3_SCIF_REGTYPE] = {
297 [SCSMR] = { 0x00, 8 },
298 [SCBRR] = { 0x02, 8 },
299 [SCSCR] = { 0x04, 8 },
300 [SCxTDR] = { 0x06, 8 },
301 [SCxSR] = { 0x08, 16 },
302 [SCxRDR] = { 0x0a, 8 },
303 [SCFCR] = { 0x0c, 8 },
304 [SCFDR] = { 0x0e, 16 },
307 .overrun_reg = SCLSR,
308 .overrun_mask = SCLSR_ORER,
309 .sampling_rate_mask = SCI_SR(32),
310 .error_mask = SCIF_DEFAULT_ERROR_MASK,
311 .error_clear = SCIF_ERROR_CLEAR,
315 * Common SH-4(A) SCIF(B) definitions.
317 [SCIx_SH4_SCIF_REGTYPE] = {
319 [SCSMR] = { 0x00, 16 },
320 [SCBRR] = { 0x04, 8 },
321 [SCSCR] = { 0x08, 16 },
322 [SCxTDR] = { 0x0c, 8 },
323 [SCxSR] = { 0x10, 16 },
324 [SCxRDR] = { 0x14, 8 },
325 [SCFCR] = { 0x18, 16 },
326 [SCFDR] = { 0x1c, 16 },
327 [SCSPTR] = { 0x20, 16 },
328 [SCLSR] = { 0x24, 16 },
331 .overrun_reg = SCLSR,
332 .overrun_mask = SCLSR_ORER,
333 .sampling_rate_mask = SCI_SR(32),
334 .error_mask = SCIF_DEFAULT_ERROR_MASK,
335 .error_clear = SCIF_ERROR_CLEAR,
339 * Common SCIF definitions for ports with a Baud Rate Generator for
340 * External Clock (BRG).
342 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
344 [SCSMR] = { 0x00, 16 },
345 [SCBRR] = { 0x04, 8 },
346 [SCSCR] = { 0x08, 16 },
347 [SCxTDR] = { 0x0c, 8 },
348 [SCxSR] = { 0x10, 16 },
349 [SCxRDR] = { 0x14, 8 },
350 [SCFCR] = { 0x18, 16 },
351 [SCFDR] = { 0x1c, 16 },
352 [SCSPTR] = { 0x20, 16 },
353 [SCLSR] = { 0x24, 16 },
354 [SCDL] = { 0x30, 16 },
355 [SCCKS] = { 0x34, 16 },
358 .overrun_reg = SCLSR,
359 .overrun_mask = SCLSR_ORER,
360 .sampling_rate_mask = SCI_SR(32),
361 .error_mask = SCIF_DEFAULT_ERROR_MASK,
362 .error_clear = SCIF_ERROR_CLEAR,
366 * Common HSCIF definitions.
368 [SCIx_HSCIF_REGTYPE] = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [HSSRR] = { 0x40, 16 },
381 [SCDL] = { 0x30, 16 },
382 [SCCKS] = { 0x34, 16 },
383 [HSRTRGR] = { 0x54, 16 },
384 [HSTTRGR] = { 0x58, 16 },
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
395 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
398 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
400 [SCSMR] = { 0x00, 16 },
401 [SCBRR] = { 0x04, 8 },
402 [SCSCR] = { 0x08, 16 },
403 [SCxTDR] = { 0x0c, 8 },
404 [SCxSR] = { 0x10, 16 },
405 [SCxRDR] = { 0x14, 8 },
406 [SCFCR] = { 0x18, 16 },
407 [SCFDR] = { 0x1c, 16 },
408 [SCLSR] = { 0x24, 16 },
411 .overrun_reg = SCLSR,
412 .overrun_mask = SCLSR_ORER,
413 .sampling_rate_mask = SCI_SR(32),
414 .error_mask = SCIF_DEFAULT_ERROR_MASK,
415 .error_clear = SCIF_ERROR_CLEAR,
419 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
422 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
424 [SCSMR] = { 0x00, 16 },
425 [SCBRR] = { 0x04, 8 },
426 [SCSCR] = { 0x08, 16 },
427 [SCxTDR] = { 0x0c, 8 },
428 [SCxSR] = { 0x10, 16 },
429 [SCxRDR] = { 0x14, 8 },
430 [SCFCR] = { 0x18, 16 },
431 [SCFDR] = { 0x1c, 16 },
432 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
433 [SCRFDR] = { 0x20, 16 },
434 [SCSPTR] = { 0x24, 16 },
435 [SCLSR] = { 0x28, 16 },
438 .overrun_reg = SCLSR,
439 .overrun_mask = SCLSR_ORER,
440 .sampling_rate_mask = SCI_SR(32),
441 .error_mask = SCIF_DEFAULT_ERROR_MASK,
442 .error_clear = SCIF_ERROR_CLEAR,
446 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
449 [SCIx_SH7705_SCIF_REGTYPE] = {
451 [SCSMR] = { 0x00, 16 },
452 [SCBRR] = { 0x04, 8 },
453 [SCSCR] = { 0x08, 16 },
454 [SCxTDR] = { 0x20, 8 },
455 [SCxSR] = { 0x14, 16 },
456 [SCxRDR] = { 0x24, 8 },
457 [SCFCR] = { 0x18, 16 },
458 [SCFDR] = { 0x1c, 16 },
461 .overrun_reg = SCxSR,
462 .overrun_mask = SCIFA_ORER,
463 .sampling_rate_mask = SCI_SR(16),
464 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
465 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
469 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
472 * The "offset" here is rather misleading, in that it refers to an enum
473 * value relative to the port mapping rather than the fixed offset
474 * itself, which needs to be manually retrieved from the platform's
475 * register map for the given port.
477 static unsigned int sci_serial_in(struct uart_port *p, int offset)
479 const struct plat_sci_reg *reg = sci_getreg(p, offset);
482 return ioread8(p->membase + (reg->offset << p->regshift));
483 else if (reg->size == 16)
484 return ioread16(p->membase + (reg->offset << p->regshift));
486 WARN(1, "Invalid register access\n");
491 static void sci_serial_out(struct uart_port *p, int offset, int value)
493 const struct plat_sci_reg *reg = sci_getreg(p, offset);
496 iowrite8(value, p->membase + (reg->offset << p->regshift));
497 else if (reg->size == 16)
498 iowrite16(value, p->membase + (reg->offset << p->regshift));
500 WARN(1, "Invalid register access\n");
503 static void sci_port_enable(struct sci_port *sci_port)
507 if (!sci_port->port.dev)
510 pm_runtime_get_sync(sci_port->port.dev);
512 for (i = 0; i < SCI_NUM_CLKS; i++) {
513 clk_prepare_enable(sci_port->clks[i]);
514 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
516 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
519 static void sci_port_disable(struct sci_port *sci_port)
523 if (!sci_port->port.dev)
526 for (i = SCI_NUM_CLKS; i-- > 0; )
527 clk_disable_unprepare(sci_port->clks[i]);
529 pm_runtime_put_sync(sci_port->port.dev);
532 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
535 * Not all ports (such as SCIFA) will support REIE. Rather than
536 * special-casing the port type, we check the port initialization
537 * IRQ enable mask to see whether the IRQ is desired at all. If
538 * it's unset, it's logically inferred that there's no point in
541 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
544 static void sci_start_tx(struct uart_port *port)
546 struct sci_port *s = to_sci_port(port);
549 #ifdef CONFIG_SERIAL_SH_SCI_DMA
550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
551 u16 new, scr = serial_port_in(port, SCSCR);
553 new = scr | SCSCR_TDRQE;
555 new = scr & ~SCSCR_TDRQE;
557 serial_port_out(port, SCSCR, new);
560 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
561 dma_submit_error(s->cookie_tx)) {
563 schedule_work(&s->work_tx);
567 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
568 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
569 ctrl = serial_port_in(port, SCSCR);
570 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
574 static void sci_stop_tx(struct uart_port *port)
578 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
579 ctrl = serial_port_in(port, SCSCR);
581 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
582 ctrl &= ~SCSCR_TDRQE;
586 serial_port_out(port, SCSCR, ctrl);
589 static void sci_start_rx(struct uart_port *port)
593 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
595 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
596 ctrl &= ~SCSCR_RDRQE;
598 serial_port_out(port, SCSCR, ctrl);
601 static void sci_stop_rx(struct uart_port *port)
605 ctrl = serial_port_in(port, SCSCR);
607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
608 ctrl &= ~SCSCR_RDRQE;
610 ctrl &= ~port_rx_irq_mask(port);
612 serial_port_out(port, SCSCR, ctrl);
615 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
617 if (port->type == PORT_SCI) {
618 /* Just store the mask */
619 serial_port_out(port, SCxSR, mask);
620 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
621 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
622 /* Only clear the status bits we want to clear */
623 serial_port_out(port, SCxSR,
624 serial_port_in(port, SCxSR) & mask);
626 /* Store the mask, clear parity/framing errors */
627 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
631 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
632 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
634 #ifdef CONFIG_CONSOLE_POLL
635 static int sci_poll_get_char(struct uart_port *port)
637 unsigned short status;
641 status = serial_port_in(port, SCxSR);
642 if (status & SCxSR_ERRORS(port)) {
643 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
649 if (!(status & SCxSR_RDxF(port)))
652 c = serial_port_in(port, SCxRDR);
655 serial_port_in(port, SCxSR);
656 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
662 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
664 unsigned short status;
667 status = serial_port_in(port, SCxSR);
668 } while (!(status & SCxSR_TDxE(port)));
670 serial_port_out(port, SCxTDR, c);
671 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
673 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
674 CONFIG_SERIAL_SH_SCI_EARLYCON */
676 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
678 struct sci_port *s = to_sci_port(port);
681 * Use port-specific handler if provided.
683 if (s->cfg->ops && s->cfg->ops->init_pins) {
684 s->cfg->ops->init_pins(port, cflag);
688 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
689 u16 data = serial_port_in(port, SCPDR);
690 u16 ctrl = serial_port_in(port, SCPCR);
692 /* Enable RXD and TXD pin functions */
693 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
694 if (to_sci_port(port)->has_rtscts) {
695 /* RTS# is output, active low, unless autorts */
696 if (!(port->mctrl & TIOCM_RTS)) {
699 } else if (!s->autorts) {
703 /* Enable RTS# pin function */
706 /* Enable CTS# pin function */
709 serial_port_out(port, SCPDR, data);
710 serial_port_out(port, SCPCR, ctrl);
711 } else if (sci_getreg(port, SCSPTR)->size) {
712 u16 status = serial_port_in(port, SCSPTR);
714 /* RTS# is always output; and active low, unless autorts */
715 status |= SCSPTR_RTSIO;
716 if (!(port->mctrl & TIOCM_RTS))
717 status |= SCSPTR_RTSDT;
718 else if (!s->autorts)
719 status &= ~SCSPTR_RTSDT;
720 /* CTS# and SCK are inputs */
721 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
722 serial_port_out(port, SCSPTR, status);
726 static int sci_txfill(struct uart_port *port)
728 struct sci_port *s = to_sci_port(port);
729 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
730 const struct plat_sci_reg *reg;
732 reg = sci_getreg(port, SCTFDR);
734 return serial_port_in(port, SCTFDR) & fifo_mask;
736 reg = sci_getreg(port, SCFDR);
738 return serial_port_in(port, SCFDR) >> 8;
740 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
743 static int sci_txroom(struct uart_port *port)
745 return port->fifosize - sci_txfill(port);
748 static int sci_rxfill(struct uart_port *port)
750 struct sci_port *s = to_sci_port(port);
751 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
752 const struct plat_sci_reg *reg;
754 reg = sci_getreg(port, SCRFDR);
756 return serial_port_in(port, SCRFDR) & fifo_mask;
758 reg = sci_getreg(port, SCFDR);
760 return serial_port_in(port, SCFDR) & fifo_mask;
762 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
765 /* ********************************************************************** *
766 * the interrupt related routines *
767 * ********************************************************************** */
769 static void sci_transmit_chars(struct uart_port *port)
771 struct circ_buf *xmit = &port->state->xmit;
772 unsigned int stopped = uart_tx_stopped(port);
773 unsigned short status;
777 status = serial_port_in(port, SCxSR);
778 if (!(status & SCxSR_TDxE(port))) {
779 ctrl = serial_port_in(port, SCSCR);
780 if (uart_circ_empty(xmit))
784 serial_port_out(port, SCSCR, ctrl);
788 count = sci_txroom(port);
796 } else if (!uart_circ_empty(xmit) && !stopped) {
797 c = xmit->buf[xmit->tail];
798 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
803 serial_port_out(port, SCxTDR, c);
806 } while (--count > 0);
808 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
812 if (uart_circ_empty(xmit)) {
815 ctrl = serial_port_in(port, SCSCR);
817 if (port->type != PORT_SCI) {
818 serial_port_in(port, SCxSR); /* Dummy read */
819 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
823 serial_port_out(port, SCSCR, ctrl);
827 /* On SH3, SCIF may read end-of-break as a space->mark char */
828 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
830 static void sci_receive_chars(struct uart_port *port)
832 struct tty_port *tport = &port->state->port;
833 int i, count, copied = 0;
834 unsigned short status;
837 status = serial_port_in(port, SCxSR);
838 if (!(status & SCxSR_RDxF(port)))
842 /* Don't copy more bytes than there is room for in the buffer */
843 count = tty_buffer_request_room(tport, sci_rxfill(port));
845 /* If for any reason we can't copy more data, we're done! */
849 if (port->type == PORT_SCI) {
850 char c = serial_port_in(port, SCxRDR);
851 if (uart_handle_sysrq_char(port, c))
854 tty_insert_flip_char(tport, c, TTY_NORMAL);
856 for (i = 0; i < count; i++) {
857 char c = serial_port_in(port, SCxRDR);
859 status = serial_port_in(port, SCxSR);
860 if (uart_handle_sysrq_char(port, c)) {
865 /* Store data and status */
866 if (status & SCxSR_FER(port)) {
868 port->icount.frame++;
869 dev_notice(port->dev, "frame error\n");
870 } else if (status & SCxSR_PER(port)) {
872 port->icount.parity++;
873 dev_notice(port->dev, "parity error\n");
877 tty_insert_flip_char(tport, c, flag);
881 serial_port_in(port, SCxSR); /* dummy read */
882 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
885 port->icount.rx += count;
889 /* Tell the rest of the system the news. New characters! */
890 tty_flip_buffer_push(tport);
892 /* TTY buffers full; read from RX reg to prevent lockup */
893 serial_port_in(port, SCxRDR);
894 serial_port_in(port, SCxSR); /* dummy read */
895 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
899 static int sci_handle_errors(struct uart_port *port)
902 unsigned short status = serial_port_in(port, SCxSR);
903 struct tty_port *tport = &port->state->port;
904 struct sci_port *s = to_sci_port(port);
906 /* Handle overruns */
907 if (status & s->params->overrun_mask) {
908 port->icount.overrun++;
911 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
914 dev_notice(port->dev, "overrun error\n");
917 if (status & SCxSR_FER(port)) {
919 port->icount.frame++;
921 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
924 dev_notice(port->dev, "frame error\n");
927 if (status & SCxSR_PER(port)) {
929 port->icount.parity++;
931 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
934 dev_notice(port->dev, "parity error\n");
938 tty_flip_buffer_push(tport);
943 static int sci_handle_fifo_overrun(struct uart_port *port)
945 struct tty_port *tport = &port->state->port;
946 struct sci_port *s = to_sci_port(port);
947 const struct plat_sci_reg *reg;
951 reg = sci_getreg(port, s->params->overrun_reg);
955 status = serial_port_in(port, s->params->overrun_reg);
956 if (status & s->params->overrun_mask) {
957 status &= ~s->params->overrun_mask;
958 serial_port_out(port, s->params->overrun_reg, status);
960 port->icount.overrun++;
962 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
963 tty_flip_buffer_push(tport);
965 dev_dbg(port->dev, "overrun error\n");
972 static int sci_handle_breaks(struct uart_port *port)
975 unsigned short status = serial_port_in(port, SCxSR);
976 struct tty_port *tport = &port->state->port;
978 if (uart_handle_break(port))
981 if (status & SCxSR_BRK(port)) {
984 /* Notify of BREAK */
985 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
988 dev_dbg(port->dev, "BREAK detected\n");
992 tty_flip_buffer_push(tport);
994 copied += sci_handle_fifo_overrun(port);
999 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1005 if (rx_trig >= port->fifosize)
1006 rx_trig = port->fifosize;
1008 /* HSCIF can be set to an arbitrary level. */
1009 if (sci_getreg(port, HSRTRGR)->size) {
1010 serial_port_out(port, HSRTRGR, rx_trig);
1014 switch (port->type) {
1019 } else if (rx_trig < 8) {
1022 } else if (rx_trig < 14) {
1026 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1035 } else if (rx_trig < 32) {
1038 } else if (rx_trig < 48) {
1042 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1047 WARN(1, "unknown FIFO configuration");
1051 serial_port_out(port, SCFCR,
1052 (serial_port_in(port, SCFCR) &
1053 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1058 static int scif_rtrg_enabled(struct uart_port *port)
1060 if (sci_getreg(port, HSRTRGR)->size)
1061 return serial_port_in(port, HSRTRGR) != 0;
1063 return (serial_port_in(port, SCFCR) &
1064 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1067 static void rx_fifo_timer_fn(struct timer_list *t)
1069 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1070 struct uart_port *port = &s->port;
1072 dev_dbg(port->dev, "Rx timed out\n");
1073 scif_set_rtrg(port, 1);
1076 static ssize_t rx_trigger_show(struct device *dev,
1077 struct device_attribute *attr,
1080 struct uart_port *port = dev_get_drvdata(dev);
1081 struct sci_port *sci = to_sci_port(port);
1083 return sprintf(buf, "%d\n", sci->rx_trigger);
1086 static ssize_t rx_trigger_store(struct device *dev,
1087 struct device_attribute *attr,
1091 struct uart_port *port = dev_get_drvdata(dev);
1092 struct sci_port *sci = to_sci_port(port);
1096 ret = kstrtol(buf, 0, &r);
1100 sci->rx_trigger = scif_set_rtrg(port, r);
1101 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1102 scif_set_rtrg(port, 1);
1107 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1109 static ssize_t rx_fifo_timeout_show(struct device *dev,
1110 struct device_attribute *attr,
1113 struct uart_port *port = dev_get_drvdata(dev);
1114 struct sci_port *sci = to_sci_port(port);
1117 if (port->type == PORT_HSCIF)
1118 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1120 v = sci->rx_fifo_timeout;
1122 return sprintf(buf, "%d\n", v);
1125 static ssize_t rx_fifo_timeout_store(struct device *dev,
1126 struct device_attribute *attr,
1130 struct uart_port *port = dev_get_drvdata(dev);
1131 struct sci_port *sci = to_sci_port(port);
1135 ret = kstrtol(buf, 0, &r);
1139 if (port->type == PORT_HSCIF) {
1142 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1144 sci->rx_fifo_timeout = r;
1145 scif_set_rtrg(port, 1);
1147 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1153 static DEVICE_ATTR_RW(rx_fifo_timeout);
1156 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1157 static void sci_dma_tx_complete(void *arg)
1159 struct sci_port *s = arg;
1160 struct uart_port *port = &s->port;
1161 struct circ_buf *xmit = &port->state->xmit;
1162 unsigned long flags;
1164 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1166 spin_lock_irqsave(&port->lock, flags);
1168 xmit->tail += s->tx_dma_len;
1169 xmit->tail &= UART_XMIT_SIZE - 1;
1171 port->icount.tx += s->tx_dma_len;
1173 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1174 uart_write_wakeup(port);
1176 if (!uart_circ_empty(xmit)) {
1178 schedule_work(&s->work_tx);
1180 s->cookie_tx = -EINVAL;
1181 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1182 u16 ctrl = serial_port_in(port, SCSCR);
1183 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1187 spin_unlock_irqrestore(&port->lock, flags);
1190 /* Locking: called with port lock held */
1191 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1193 struct uart_port *port = &s->port;
1194 struct tty_port *tport = &port->state->port;
1197 copied = tty_insert_flip_string(tport, buf, count);
1199 port->icount.buf_overrun++;
1201 port->icount.rx += copied;
1206 static int sci_dma_rx_find_active(struct sci_port *s)
1210 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1211 if (s->active_rx == s->cookie_rx[i])
1217 static void sci_rx_dma_release(struct sci_port *s)
1219 struct dma_chan *chan = s->chan_rx_saved;
1221 s->chan_rx_saved = s->chan_rx = NULL;
1222 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1223 dmaengine_terminate_sync(chan);
1224 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1225 sg_dma_address(&s->sg_rx[0]));
1226 dma_release_channel(chan);
1229 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1231 long sec = usec / 1000000;
1232 long nsec = (usec % 1000000) * 1000;
1233 ktime_t t = ktime_set(sec, nsec);
1235 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1238 static void sci_dma_rx_complete(void *arg)
1240 struct sci_port *s = arg;
1241 struct dma_chan *chan = s->chan_rx;
1242 struct uart_port *port = &s->port;
1243 struct dma_async_tx_descriptor *desc;
1244 unsigned long flags;
1245 int active, count = 0;
1247 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1250 spin_lock_irqsave(&port->lock, flags);
1252 active = sci_dma_rx_find_active(s);
1254 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1256 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1259 tty_flip_buffer_push(&port->state->port);
1261 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1263 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1267 desc->callback = sci_dma_rx_complete;
1268 desc->callback_param = s;
1269 s->cookie_rx[active] = dmaengine_submit(desc);
1270 if (dma_submit_error(s->cookie_rx[active]))
1273 s->active_rx = s->cookie_rx[!active];
1275 dma_async_issue_pending(chan);
1277 spin_unlock_irqrestore(&port->lock, flags);
1278 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1279 __func__, s->cookie_rx[active], active, s->active_rx);
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1286 spin_lock_irqsave(&port->lock, flags);
1289 spin_unlock_irqrestore(&port->lock, flags);
1292 static void sci_tx_dma_release(struct sci_port *s)
1294 struct dma_chan *chan = s->chan_tx_saved;
1296 cancel_work_sync(&s->work_tx);
1297 s->chan_tx_saved = s->chan_tx = NULL;
1298 s->cookie_tx = -EINVAL;
1299 dmaengine_terminate_sync(chan);
1300 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1302 dma_release_channel(chan);
1305 static void sci_submit_rx(struct sci_port *s)
1307 struct dma_chan *chan = s->chan_rx;
1308 struct uart_port *port = &s->port;
1309 unsigned long flags;
1312 for (i = 0; i < 2; i++) {
1313 struct scatterlist *sg = &s->sg_rx[i];
1314 struct dma_async_tx_descriptor *desc;
1316 desc = dmaengine_prep_slave_sg(chan,
1317 sg, 1, DMA_DEV_TO_MEM,
1318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1322 desc->callback = sci_dma_rx_complete;
1323 desc->callback_param = s;
1324 s->cookie_rx[i] = dmaengine_submit(desc);
1325 if (dma_submit_error(s->cookie_rx[i]))
1330 s->active_rx = s->cookie_rx[0];
1332 dma_async_issue_pending(chan);
1337 dmaengine_terminate_async(chan);
1338 for (i = 0; i < 2; i++)
1339 s->cookie_rx[i] = -EINVAL;
1340 s->active_rx = -EINVAL;
1342 spin_lock_irqsave(&port->lock, flags);
1345 spin_unlock_irqrestore(&port->lock, flags);
1348 static void work_fn_tx(struct work_struct *work)
1350 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1351 struct dma_async_tx_descriptor *desc;
1352 struct dma_chan *chan = s->chan_tx;
1353 struct uart_port *port = &s->port;
1354 struct circ_buf *xmit = &port->state->xmit;
1355 unsigned long flags;
1360 * Port xmit buffer is already mapped, and it is one page... Just adjust
1361 * offsets and lengths. Since it is a circular buffer, we have to
1362 * transmit till the end, and then the rest. Take the port lock to get a
1363 * consistent xmit buffer state.
1365 spin_lock_irq(&port->lock);
1366 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1367 s->tx_dma_len = min_t(unsigned int,
1368 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1369 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1370 spin_unlock_irq(&port->lock);
1372 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1374 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1376 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1380 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1383 spin_lock_irq(&port->lock);
1384 desc->callback = sci_dma_tx_complete;
1385 desc->callback_param = s;
1386 spin_unlock_irq(&port->lock);
1387 s->cookie_tx = dmaengine_submit(desc);
1388 if (dma_submit_error(s->cookie_tx)) {
1389 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1393 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1394 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1396 dma_async_issue_pending(chan);
1400 spin_lock_irqsave(&port->lock, flags);
1403 spin_unlock_irqrestore(&port->lock, flags);
1407 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1409 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1410 struct dma_chan *chan = s->chan_rx;
1411 struct uart_port *port = &s->port;
1412 struct dma_tx_state state;
1413 enum dma_status status;
1414 unsigned long flags;
1419 dev_dbg(port->dev, "DMA Rx timed out\n");
1421 spin_lock_irqsave(&port->lock, flags);
1423 active = sci_dma_rx_find_active(s);
1425 spin_unlock_irqrestore(&port->lock, flags);
1426 return HRTIMER_NORESTART;
1429 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1430 if (status == DMA_COMPLETE) {
1431 spin_unlock_irqrestore(&port->lock, flags);
1432 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1433 s->active_rx, active);
1435 /* Let packet complete handler take care of the packet */
1436 return HRTIMER_NORESTART;
1439 dmaengine_pause(chan);
1442 * sometimes DMA transfer doesn't stop even if it is stopped and
1443 * data keeps on coming until transaction is complete so check
1444 * for DMA_COMPLETE again
1445 * Let packet complete handler take care of the packet
1447 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1448 if (status == DMA_COMPLETE) {
1449 spin_unlock_irqrestore(&port->lock, flags);
1450 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1451 return HRTIMER_NORESTART;
1454 /* Handle incomplete DMA receive */
1455 dmaengine_terminate_async(s->chan_rx);
1456 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1459 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1461 tty_flip_buffer_push(&port->state->port);
1464 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1467 /* Direct new serial port interrupts back to CPU */
1468 scr = serial_port_in(port, SCSCR);
1469 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1470 scr &= ~SCSCR_RDRQE;
1471 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1473 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1475 spin_unlock_irqrestore(&port->lock, flags);
1477 return HRTIMER_NORESTART;
1480 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1481 enum dma_transfer_direction dir)
1483 struct dma_chan *chan;
1484 struct dma_slave_config cfg;
1487 chan = dma_request_slave_channel(port->dev,
1488 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1490 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1494 memset(&cfg, 0, sizeof(cfg));
1495 cfg.direction = dir;
1496 if (dir == DMA_MEM_TO_DEV) {
1497 cfg.dst_addr = port->mapbase +
1498 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1499 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1501 cfg.src_addr = port->mapbase +
1502 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1503 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1506 ret = dmaengine_slave_config(chan, &cfg);
1508 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1509 dma_release_channel(chan);
1516 static void sci_request_dma(struct uart_port *port)
1518 struct sci_port *s = to_sci_port(port);
1519 struct dma_chan *chan;
1521 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1523 if (!port->dev->of_node)
1526 s->cookie_tx = -EINVAL;
1529 * Don't request a dma channel if no channel was specified
1530 * in the device tree.
1532 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1535 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1536 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1538 /* UART circular tx buffer is an aligned page. */
1539 s->tx_dma_addr = dma_map_single(chan->device->dev,
1540 port->state->xmit.buf,
1543 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1544 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1545 dma_release_channel(chan);
1548 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1549 __func__, UART_XMIT_SIZE,
1550 port->state->xmit.buf, &s->tx_dma_addr);
1552 INIT_WORK(&s->work_tx, work_fn_tx);
1553 s->chan_tx_saved = s->chan_tx = chan;
1557 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1558 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1564 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1565 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1569 "Failed to allocate Rx dma buffer, using PIO\n");
1570 dma_release_channel(chan);
1574 for (i = 0; i < 2; i++) {
1575 struct scatterlist *sg = &s->sg_rx[i];
1577 sg_init_table(sg, 1);
1579 sg_dma_address(sg) = dma;
1580 sg_dma_len(sg) = s->buf_len_rx;
1582 buf += s->buf_len_rx;
1583 dma += s->buf_len_rx;
1586 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1587 s->rx_timer.function = rx_timer_fn;
1589 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1592 s->chan_rx_saved = s->chan_rx = chan;
1596 static void sci_free_dma(struct uart_port *port)
1598 struct sci_port *s = to_sci_port(port);
1600 if (s->chan_tx_saved)
1601 sci_tx_dma_release(s);
1602 if (s->chan_rx_saved)
1603 sci_rx_dma_release(s);
1606 static void sci_flush_buffer(struct uart_port *port)
1609 * In uart_flush_buffer(), the xmit circular buffer has just been
1610 * cleared, so we have to reset tx_dma_len accordingly.
1612 to_sci_port(port)->tx_dma_len = 0;
1614 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1615 static inline void sci_request_dma(struct uart_port *port)
1619 static inline void sci_free_dma(struct uart_port *port)
1623 #define sci_flush_buffer NULL
1624 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1626 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1628 struct uart_port *port = ptr;
1629 struct sci_port *s = to_sci_port(port);
1631 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1633 u16 scr = serial_port_in(port, SCSCR);
1634 u16 ssr = serial_port_in(port, SCxSR);
1636 /* Disable future Rx interrupts */
1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1638 disable_irq_nosync(irq);
1644 serial_port_out(port, SCSCR, scr);
1645 /* Clear current interrupt */
1646 serial_port_out(port, SCxSR,
1647 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1648 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1649 jiffies, s->rx_timeout);
1650 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1656 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1657 if (!scif_rtrg_enabled(port))
1658 scif_set_rtrg(port, s->rx_trigger);
1660 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1661 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1664 /* I think sci_receive_chars has to be called irrespective
1665 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1668 sci_receive_chars(ptr);
1673 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1675 struct uart_port *port = ptr;
1676 unsigned long flags;
1678 spin_lock_irqsave(&port->lock, flags);
1679 sci_transmit_chars(port);
1680 spin_unlock_irqrestore(&port->lock, flags);
1685 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1687 struct uart_port *port = ptr;
1688 struct sci_port *s = to_sci_port(port);
1691 if (port->type == PORT_SCI) {
1692 if (sci_handle_errors(port)) {
1693 /* discard character in rx buffer */
1694 serial_port_in(port, SCxSR);
1695 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1698 sci_handle_fifo_overrun(port);
1700 sci_receive_chars(ptr);
1703 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1705 /* Kick the transmission */
1707 sci_tx_interrupt(irq, ptr);
1712 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1714 struct uart_port *port = ptr;
1717 sci_handle_breaks(port);
1718 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1723 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1725 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1726 struct uart_port *port = ptr;
1727 struct sci_port *s = to_sci_port(port);
1728 irqreturn_t ret = IRQ_NONE;
1730 ssr_status = serial_port_in(port, SCxSR);
1731 scr_status = serial_port_in(port, SCSCR);
1732 if (s->params->overrun_reg == SCxSR)
1733 orer_status = ssr_status;
1734 else if (sci_getreg(port, s->params->overrun_reg)->size)
1735 orer_status = serial_port_in(port, s->params->overrun_reg);
1737 err_enabled = scr_status & port_rx_irq_mask(port);
1740 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1742 ret = sci_tx_interrupt(irq, ptr);
1745 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1748 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1749 (scr_status & SCSCR_RIE))
1750 ret = sci_rx_interrupt(irq, ptr);
1752 /* Error Interrupt */
1753 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1754 ret = sci_er_interrupt(irq, ptr);
1756 /* Break Interrupt */
1757 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1758 ret = sci_br_interrupt(irq, ptr);
1760 /* Overrun Interrupt */
1761 if (orer_status & s->params->overrun_mask) {
1762 sci_handle_fifo_overrun(port);
1769 static const struct sci_irq_desc {
1771 irq_handler_t handler;
1772 } sci_irq_desc[] = {
1774 * Split out handlers, the default case.
1778 .handler = sci_er_interrupt,
1783 .handler = sci_rx_interrupt,
1788 .handler = sci_tx_interrupt,
1793 .handler = sci_br_interrupt,
1797 * Special muxed handler.
1801 .handler = sci_mpxed_interrupt,
1805 static int sci_request_irq(struct sci_port *port)
1807 struct uart_port *up = &port->port;
1810 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1811 const struct sci_irq_desc *desc;
1814 if (SCIx_IRQ_IS_MUXED(port)) {
1818 irq = port->irqs[i];
1821 * Certain port types won't support all of the
1822 * available interrupt sources.
1824 if (unlikely(irq < 0))
1828 desc = sci_irq_desc + i;
1829 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1830 dev_name(up->dev), desc->desc);
1831 if (!port->irqstr[j]) {
1836 ret = request_irq(irq, desc->handler, up->irqflags,
1837 port->irqstr[j], port);
1838 if (unlikely(ret)) {
1839 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1848 free_irq(port->irqs[i], port);
1852 kfree(port->irqstr[j]);
1857 static void sci_free_irq(struct sci_port *port)
1862 * Intentionally in reverse order so we iterate over the muxed
1865 for (i = 0; i < SCIx_NR_IRQS; i++) {
1866 int irq = port->irqs[i];
1869 * Certain port types won't support all of the available
1870 * interrupt sources.
1872 if (unlikely(irq < 0))
1875 free_irq(port->irqs[i], port);
1876 kfree(port->irqstr[i]);
1878 if (SCIx_IRQ_IS_MUXED(port)) {
1879 /* If there's only one IRQ, we're done. */
1885 static unsigned int sci_tx_empty(struct uart_port *port)
1887 unsigned short status = serial_port_in(port, SCxSR);
1888 unsigned short in_tx_fifo = sci_txfill(port);
1890 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1893 static void sci_set_rts(struct uart_port *port, bool state)
1895 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1896 u16 data = serial_port_in(port, SCPDR);
1900 data &= ~SCPDR_RTSD;
1903 serial_port_out(port, SCPDR, data);
1905 /* RTS# is output */
1906 serial_port_out(port, SCPCR,
1907 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1908 } else if (sci_getreg(port, SCSPTR)->size) {
1909 u16 ctrl = serial_port_in(port, SCSPTR);
1913 ctrl &= ~SCSPTR_RTSDT;
1915 ctrl |= SCSPTR_RTSDT;
1916 serial_port_out(port, SCSPTR, ctrl);
1920 static bool sci_get_cts(struct uart_port *port)
1922 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1924 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1925 } else if (sci_getreg(port, SCSPTR)->size) {
1927 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1934 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1935 * CTS/RTS is supported in hardware by at least one port and controlled
1936 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1937 * handled via the ->init_pins() op, which is a bit of a one-way street,
1938 * lacking any ability to defer pin control -- this will later be
1939 * converted over to the GPIO framework).
1941 * Other modes (such as loopback) are supported generically on certain
1942 * port types, but not others. For these it's sufficient to test for the
1943 * existence of the support register and simply ignore the port type.
1945 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1947 struct sci_port *s = to_sci_port(port);
1949 if (mctrl & TIOCM_LOOP) {
1950 const struct plat_sci_reg *reg;
1953 * Standard loopback mode for SCFCR ports.
1955 reg = sci_getreg(port, SCFCR);
1957 serial_port_out(port, SCFCR,
1958 serial_port_in(port, SCFCR) |
1962 mctrl_gpio_set(s->gpios, mctrl);
1967 if (!(mctrl & TIOCM_RTS)) {
1968 /* Disable Auto RTS */
1969 serial_port_out(port, SCFCR,
1970 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1973 sci_set_rts(port, 0);
1974 } else if (s->autorts) {
1975 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1976 /* Enable RTS# pin function */
1977 serial_port_out(port, SCPCR,
1978 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1981 /* Enable Auto RTS */
1982 serial_port_out(port, SCFCR,
1983 serial_port_in(port, SCFCR) | SCFCR_MCE);
1986 sci_set_rts(port, 1);
1990 static unsigned int sci_get_mctrl(struct uart_port *port)
1992 struct sci_port *s = to_sci_port(port);
1993 struct mctrl_gpios *gpios = s->gpios;
1994 unsigned int mctrl = 0;
1996 mctrl_gpio_get(gpios, &mctrl);
1999 * CTS/RTS is handled in hardware when supported, while nothing
2003 if (sci_get_cts(port))
2005 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2008 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2010 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2016 static void sci_enable_ms(struct uart_port *port)
2018 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2021 static void sci_break_ctl(struct uart_port *port, int break_state)
2023 unsigned short scscr, scsptr;
2024 unsigned long flags;
2026 /* check wheter the port has SCSPTR */
2027 if (!sci_getreg(port, SCSPTR)->size) {
2029 * Not supported by hardware. Most parts couple break and rx
2030 * interrupts together, with break detection always enabled.
2035 spin_lock_irqsave(&port->lock, flags);
2036 scsptr = serial_port_in(port, SCSPTR);
2037 scscr = serial_port_in(port, SCSCR);
2039 if (break_state == -1) {
2040 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2043 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2047 serial_port_out(port, SCSPTR, scsptr);
2048 serial_port_out(port, SCSCR, scscr);
2049 spin_unlock_irqrestore(&port->lock, flags);
2052 static int sci_startup(struct uart_port *port)
2054 struct sci_port *s = to_sci_port(port);
2057 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2059 sci_request_dma(port);
2061 ret = sci_request_irq(s);
2062 if (unlikely(ret < 0)) {
2070 static void sci_shutdown(struct uart_port *port)
2072 struct sci_port *s = to_sci_port(port);
2073 unsigned long flags;
2076 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2079 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2081 spin_lock_irqsave(&port->lock, flags);
2085 * Stop RX and TX, disable related interrupts, keep clock source
2086 * and HSCIF TOT bits
2088 scr = serial_port_in(port, SCSCR);
2089 serial_port_out(port, SCSCR, scr &
2090 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2091 spin_unlock_irqrestore(&port->lock, flags);
2093 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2094 if (s->chan_rx_saved) {
2095 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2097 hrtimer_cancel(&s->rx_timer);
2101 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2102 del_timer_sync(&s->rx_fifo_timer);
2107 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2110 unsigned long freq = s->clk_rates[SCI_SCK];
2111 int err, min_err = INT_MAX;
2114 if (s->port.type != PORT_HSCIF)
2117 for_each_sr(sr, s) {
2118 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2119 if (abs(err) >= abs(min_err))
2129 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2134 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2135 unsigned long freq, unsigned int *dlr,
2138 int err, min_err = INT_MAX;
2139 unsigned int sr, dl;
2141 if (s->port.type != PORT_HSCIF)
2144 for_each_sr(sr, s) {
2145 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2146 dl = clamp(dl, 1U, 65535U);
2148 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2149 if (abs(err) >= abs(min_err))
2160 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2161 min_err, *dlr, *srr + 1);
2165 /* calculate sample rate, BRR, and clock select */
2166 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2167 unsigned int *brr, unsigned int *srr,
2170 unsigned long freq = s->clk_rates[SCI_FCK];
2171 unsigned int sr, br, prediv, scrate, c;
2172 int err, min_err = INT_MAX;
2174 if (s->port.type != PORT_HSCIF)
2178 * Find the combination of sample rate and clock select with the
2179 * smallest deviation from the desired baud rate.
2180 * Prefer high sample rates to maximise the receive margin.
2182 * M: Receive margin (%)
2183 * N: Ratio of bit rate to clock (N = sampling rate)
2184 * D: Clock duty (D = 0 to 1.0)
2185 * L: Frame length (L = 9 to 12)
2186 * F: Absolute value of clock frequency deviation
2188 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2189 * (|D - 0.5| / N * (1 + F))|
2190 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2192 for_each_sr(sr, s) {
2193 for (c = 0; c <= 3; c++) {
2194 /* integerized formulas from HSCIF documentation */
2195 prediv = sr * (1 << (2 * c + 1));
2198 * We need to calculate:
2200 * br = freq / (prediv * bps) clamped to [1..256]
2201 * err = freq / (br * prediv) - bps
2203 * Watch out for overflow when calculating the desired
2204 * sampling clock rate!
2206 if (bps > UINT_MAX / prediv)
2209 scrate = prediv * bps;
2210 br = DIV_ROUND_CLOSEST(freq, scrate);
2211 br = clamp(br, 1U, 256U);
2213 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2214 if (abs(err) >= abs(min_err))
2228 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2229 min_err, *brr, *srr + 1, *cks);
2233 static void sci_reset(struct uart_port *port)
2235 const struct plat_sci_reg *reg;
2236 unsigned int status;
2237 struct sci_port *s = to_sci_port(port);
2239 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2241 reg = sci_getreg(port, SCFCR);
2243 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2245 sci_clear_SCxSR(port,
2246 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2247 SCxSR_BREAK_CLEAR(port));
2248 if (sci_getreg(port, SCLSR)->size) {
2249 status = serial_port_in(port, SCLSR);
2250 status &= ~(SCLSR_TO | SCLSR_ORER);
2251 serial_port_out(port, SCLSR, status);
2254 if (s->rx_trigger > 1) {
2255 if (s->rx_fifo_timeout) {
2256 scif_set_rtrg(port, 1);
2257 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2259 if (port->type == PORT_SCIFA ||
2260 port->type == PORT_SCIFB)
2261 scif_set_rtrg(port, 1);
2263 scif_set_rtrg(port, s->rx_trigger);
2268 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2269 struct ktermios *old)
2271 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2272 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2273 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2274 struct sci_port *s = to_sci_port(port);
2275 const struct plat_sci_reg *reg;
2276 int min_err = INT_MAX, err;
2277 unsigned long max_freq = 0;
2279 unsigned long flags;
2281 if ((termios->c_cflag & CSIZE) == CS7)
2282 smr_val |= SCSMR_CHR;
2283 if (termios->c_cflag & PARENB)
2284 smr_val |= SCSMR_PE;
2285 if (termios->c_cflag & PARODD)
2286 smr_val |= SCSMR_PE | SCSMR_ODD;
2287 if (termios->c_cflag & CSTOPB)
2288 smr_val |= SCSMR_STOP;
2291 * earlyprintk comes here early on with port->uartclk set to zero.
2292 * the clock framework is not up and running at this point so here
2293 * we assume that 115200 is the maximum baud rate. please note that
2294 * the baud rate is not programmed during earlyprintk - it is assumed
2295 * that the previous boot loader has enabled required clocks and
2296 * setup the baud rate generator hardware for us already.
2298 if (!port->uartclk) {
2299 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2303 for (i = 0; i < SCI_NUM_CLKS; i++)
2304 max_freq = max(max_freq, s->clk_rates[i]);
2306 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2311 * There can be multiple sources for the sampling clock. Find the one
2312 * that gives us the smallest deviation from the desired baud rate.
2315 /* Optional Undivided External Clock */
2316 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2317 port->type != PORT_SCIFB) {
2318 err = sci_sck_calc(s, baud, &srr1);
2319 if (abs(err) < abs(min_err)) {
2321 scr_val = SCSCR_CKE1;
2330 /* Optional BRG Frequency Divided External Clock */
2331 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2332 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2334 if (abs(err) < abs(min_err)) {
2335 best_clk = SCI_SCIF_CLK;
2336 scr_val = SCSCR_CKE1;
2346 /* Optional BRG Frequency Divided Internal Clock */
2347 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2348 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2350 if (abs(err) < abs(min_err)) {
2351 best_clk = SCI_BRG_INT;
2352 scr_val = SCSCR_CKE1;
2362 /* Divided Functional Clock using standard Bit Rate Register */
2363 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2364 if (abs(err) < abs(min_err)) {
2375 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2376 s->clks[best_clk], baud, min_err);
2381 * Program the optional External Baud Rate Generator (BRG) first.
2382 * It controls the mux to select (H)SCK or frequency divided clock.
2384 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2385 serial_port_out(port, SCDL, dl);
2386 serial_port_out(port, SCCKS, sccks);
2389 spin_lock_irqsave(&port->lock, flags);
2393 uart_update_timeout(port, termios->c_cflag, baud);
2395 /* byte size and parity */
2396 switch (termios->c_cflag & CSIZE) {
2411 if (termios->c_cflag & CSTOPB)
2413 if (termios->c_cflag & PARENB)
2416 if (best_clk >= 0) {
2417 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2419 case 5: smr_val |= SCSMR_SRC_5; break;
2420 case 7: smr_val |= SCSMR_SRC_7; break;
2421 case 11: smr_val |= SCSMR_SRC_11; break;
2422 case 13: smr_val |= SCSMR_SRC_13; break;
2423 case 16: smr_val |= SCSMR_SRC_16; break;
2424 case 17: smr_val |= SCSMR_SRC_17; break;
2425 case 19: smr_val |= SCSMR_SRC_19; break;
2426 case 27: smr_val |= SCSMR_SRC_27; break;
2429 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2430 serial_port_out(port, SCSMR, smr_val);
2431 serial_port_out(port, SCBRR, brr);
2432 if (sci_getreg(port, HSSRR)->size) {
2433 unsigned int hssrr = srr | HSCIF_SRE;
2434 /* Calculate deviation from intended rate at the
2435 * center of the last stop bit in sampling clocks.
2437 int last_stop = bits * 2 - 1;
2438 int deviation = min_err * srr * last_stop / 2 / baud;
2440 if (abs(deviation) >= 2) {
2441 /* At least two sampling clocks off at the
2442 * last stop bit; we can increase the error
2443 * margin by shifting the sampling point.
2445 int shift = min(-8, max(7, deviation / 2));
2447 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2449 hssrr |= HSCIF_SRDE;
2451 serial_port_out(port, HSSRR, hssrr);
2454 /* Wait one bit interval */
2455 udelay((1000000 + (baud - 1)) / baud);
2457 /* Don't touch the bit rate configuration */
2458 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2459 smr_val |= serial_port_in(port, SCSMR) &
2460 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2461 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2462 serial_port_out(port, SCSMR, smr_val);
2465 sci_init_pins(port, termios->c_cflag);
2467 port->status &= ~UPSTAT_AUTOCTS;
2469 reg = sci_getreg(port, SCFCR);
2471 unsigned short ctrl = serial_port_in(port, SCFCR);
2473 if ((port->flags & UPF_HARD_FLOW) &&
2474 (termios->c_cflag & CRTSCTS)) {
2475 /* There is no CTS interrupt to restart the hardware */
2476 port->status |= UPSTAT_AUTOCTS;
2477 /* MCE is enabled when RTS is raised */
2482 * As we've done a sci_reset() above, ensure we don't
2483 * interfere with the FIFOs while toggling MCE. As the
2484 * reset values could still be set, simply mask them out.
2486 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2488 serial_port_out(port, SCFCR, ctrl);
2490 if (port->flags & UPF_HARD_FLOW) {
2491 /* Refresh (Auto) RTS */
2492 sci_set_mctrl(port, port->mctrl);
2495 scr_val |= SCSCR_RE | SCSCR_TE |
2496 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2497 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2498 if ((srr + 1 == 5) &&
2499 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2501 * In asynchronous mode, when the sampling rate is 1/5, first
2502 * received data may become invalid on some SCIFA and SCIFB.
2503 * To avoid this problem wait more than 1 serial data time (1
2504 * bit time x serial data number) after setting SCSCR.RE = 1.
2506 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2510 * Calculate delay for 2 DMA buffers (4 FIFO).
2511 * See serial_core.c::uart_update_timeout().
2512 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2513 * function calculates 1 jiffie for the data plus 5 jiffies for the
2514 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2515 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2516 * value obtained by this formula is too small. Therefore, if the value
2517 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2519 s->rx_frame = (10000 * bits) / (baud / 100);
2520 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2521 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2522 if (s->rx_timeout < 20)
2526 if ((termios->c_cflag & CREAD) != 0)
2529 spin_unlock_irqrestore(&port->lock, flags);
2531 sci_port_disable(s);
2533 if (UART_ENABLE_MS(port, termios->c_cflag))
2534 sci_enable_ms(port);
2537 static void sci_pm(struct uart_port *port, unsigned int state,
2538 unsigned int oldstate)
2540 struct sci_port *sci_port = to_sci_port(port);
2543 case UART_PM_STATE_OFF:
2544 sci_port_disable(sci_port);
2547 sci_port_enable(sci_port);
2552 static const char *sci_type(struct uart_port *port)
2554 switch (port->type) {
2572 static int sci_remap_port(struct uart_port *port)
2574 struct sci_port *sport = to_sci_port(port);
2577 * Nothing to do if there's already an established membase.
2582 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2583 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2584 if (unlikely(!port->membase)) {
2585 dev_err(port->dev, "can't remap port#%d\n", port->line);
2590 * For the simple (and majority of) cases where we don't
2591 * need to do any remapping, just cast the cookie
2594 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2600 static void sci_release_port(struct uart_port *port)
2602 struct sci_port *sport = to_sci_port(port);
2604 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2605 iounmap(port->membase);
2606 port->membase = NULL;
2609 release_mem_region(port->mapbase, sport->reg_size);
2612 static int sci_request_port(struct uart_port *port)
2614 struct resource *res;
2615 struct sci_port *sport = to_sci_port(port);
2618 res = request_mem_region(port->mapbase, sport->reg_size,
2619 dev_name(port->dev));
2620 if (unlikely(res == NULL)) {
2621 dev_err(port->dev, "request_mem_region failed.");
2625 ret = sci_remap_port(port);
2626 if (unlikely(ret != 0)) {
2627 release_resource(res);
2634 static void sci_config_port(struct uart_port *port, int flags)
2636 if (flags & UART_CONFIG_TYPE) {
2637 struct sci_port *sport = to_sci_port(port);
2639 port->type = sport->cfg->type;
2640 sci_request_port(port);
2644 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2646 if (ser->baud_base < 2400)
2647 /* No paper tape reader for Mitch.. */
2653 static const struct uart_ops sci_uart_ops = {
2654 .tx_empty = sci_tx_empty,
2655 .set_mctrl = sci_set_mctrl,
2656 .get_mctrl = sci_get_mctrl,
2657 .start_tx = sci_start_tx,
2658 .stop_tx = sci_stop_tx,
2659 .stop_rx = sci_stop_rx,
2660 .enable_ms = sci_enable_ms,
2661 .break_ctl = sci_break_ctl,
2662 .startup = sci_startup,
2663 .shutdown = sci_shutdown,
2664 .flush_buffer = sci_flush_buffer,
2665 .set_termios = sci_set_termios,
2668 .release_port = sci_release_port,
2669 .request_port = sci_request_port,
2670 .config_port = sci_config_port,
2671 .verify_port = sci_verify_port,
2672 #ifdef CONFIG_CONSOLE_POLL
2673 .poll_get_char = sci_poll_get_char,
2674 .poll_put_char = sci_poll_put_char,
2678 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2680 const char *clk_names[] = {
2683 [SCI_BRG_INT] = "brg_int",
2684 [SCI_SCIF_CLK] = "scif_clk",
2689 if (sci_port->cfg->type == PORT_HSCIF)
2690 clk_names[SCI_SCK] = "hsck";
2692 for (i = 0; i < SCI_NUM_CLKS; i++) {
2693 clk = devm_clk_get(dev, clk_names[i]);
2694 if (PTR_ERR(clk) == -EPROBE_DEFER)
2695 return -EPROBE_DEFER;
2697 if (IS_ERR(clk) && i == SCI_FCK) {
2699 * "fck" used to be called "sci_ick", and we need to
2700 * maintain DT backward compatibility.
2702 clk = devm_clk_get(dev, "sci_ick");
2703 if (PTR_ERR(clk) == -EPROBE_DEFER)
2704 return -EPROBE_DEFER;
2710 * Not all SH platforms declare a clock lookup entry
2711 * for SCI devices, in which case we need to get the
2712 * global "peripheral_clk" clock.
2714 clk = devm_clk_get(dev, "peripheral_clk");
2718 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2720 return PTR_ERR(clk);
2725 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2728 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2729 clk, clk_get_rate(clk));
2730 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2735 static const struct sci_port_params *
2736 sci_probe_regmap(const struct plat_sci_port *cfg)
2738 unsigned int regtype;
2740 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2741 return &sci_port_params[cfg->regtype];
2743 switch (cfg->type) {
2745 regtype = SCIx_SCI_REGTYPE;
2748 regtype = SCIx_IRDA_REGTYPE;
2751 regtype = SCIx_SCIFA_REGTYPE;
2754 regtype = SCIx_SCIFB_REGTYPE;
2758 * The SH-4 is a bit of a misnomer here, although that's
2759 * where this particular port layout originated. This
2760 * configuration (or some slight variation thereof)
2761 * remains the dominant model for all SCIFs.
2763 regtype = SCIx_SH4_SCIF_REGTYPE;
2766 regtype = SCIx_HSCIF_REGTYPE;
2769 pr_err("Can't probe register map for given port\n");
2773 return &sci_port_params[regtype];
2776 static int sci_init_single(struct platform_device *dev,
2777 struct sci_port *sci_port, unsigned int index,
2778 const struct plat_sci_port *p, bool early)
2780 struct uart_port *port = &sci_port->port;
2781 const struct resource *res;
2787 port->ops = &sci_uart_ops;
2788 port->iotype = UPIO_MEM;
2791 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2795 port->mapbase = res->start;
2796 sci_port->reg_size = resource_size(res);
2798 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2799 sci_port->irqs[i] = platform_get_irq(dev, i);
2801 /* The SCI generates several interrupts. They can be muxed together or
2802 * connected to different interrupt lines. In the muxed case only one
2803 * interrupt resource is specified. In the non-muxed case three or four
2804 * interrupt resources are specified, as the BRI interrupt is optional.
2806 if (sci_port->irqs[0] < 0)
2809 if (sci_port->irqs[1] < 0) {
2810 sci_port->irqs[1] = sci_port->irqs[0];
2811 sci_port->irqs[2] = sci_port->irqs[0];
2812 sci_port->irqs[3] = sci_port->irqs[0];
2815 sci_port->params = sci_probe_regmap(p);
2816 if (unlikely(sci_port->params == NULL))
2821 sci_port->rx_trigger = 48;
2824 sci_port->rx_trigger = 64;
2827 sci_port->rx_trigger = 32;
2830 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2831 /* RX triggering not implemented for this IP */
2832 sci_port->rx_trigger = 1;
2834 sci_port->rx_trigger = 8;
2837 sci_port->rx_trigger = 1;
2841 sci_port->rx_fifo_timeout = 0;
2842 sci_port->hscif_tot = 0;
2844 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2845 * match the SoC datasheet, this should be investigated. Let platform
2846 * data override the sampling rate for now.
2848 sci_port->sampling_rate_mask = p->sampling_rate
2849 ? SCI_SR(p->sampling_rate)
2850 : sci_port->params->sampling_rate_mask;
2853 ret = sci_init_clocks(sci_port, &dev->dev);
2857 port->dev = &dev->dev;
2859 pm_runtime_enable(&dev->dev);
2862 port->type = p->type;
2863 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2864 port->fifosize = sci_port->params->fifosize;
2866 if (port->type == PORT_SCI) {
2867 if (sci_port->reg_size >= 0x20)
2874 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2875 * for the multi-IRQ ports, which is where we are primarily
2876 * concerned with the shutdown path synchronization.
2878 * For the muxed case there's nothing more to do.
2880 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2883 port->serial_in = sci_serial_in;
2884 port->serial_out = sci_serial_out;
2889 static void sci_cleanup_single(struct sci_port *port)
2891 pm_runtime_disable(port->port.dev);
2894 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2895 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2896 static void serial_console_putchar(struct uart_port *port, int ch)
2898 sci_poll_put_char(port, ch);
2902 * Print a string to the serial port trying not to disturb
2903 * any possible real use of the port...
2905 static void serial_console_write(struct console *co, const char *s,
2908 struct sci_port *sci_port = &sci_ports[co->index];
2909 struct uart_port *port = &sci_port->port;
2910 unsigned short bits, ctrl, ctrl_temp;
2911 unsigned long flags;
2914 #if defined(SUPPORT_SYSRQ)
2919 if (oops_in_progress)
2920 locked = spin_trylock_irqsave(&port->lock, flags);
2922 spin_lock_irqsave(&port->lock, flags);
2924 /* first save SCSCR then disable interrupts, keep clock source */
2925 ctrl = serial_port_in(port, SCSCR);
2926 ctrl_temp = SCSCR_RE | SCSCR_TE |
2927 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2928 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2929 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2931 uart_console_write(port, s, count, serial_console_putchar);
2933 /* wait until fifo is empty and last bit has been transmitted */
2934 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2935 while ((serial_port_in(port, SCxSR) & bits) != bits)
2938 /* restore the SCSCR */
2939 serial_port_out(port, SCSCR, ctrl);
2942 spin_unlock_irqrestore(&port->lock, flags);
2945 static int serial_console_setup(struct console *co, char *options)
2947 struct sci_port *sci_port;
2948 struct uart_port *port;
2956 * Refuse to handle any bogus ports.
2958 if (co->index < 0 || co->index >= SCI_NPORTS)
2961 sci_port = &sci_ports[co->index];
2962 port = &sci_port->port;
2965 * Refuse to handle uninitialized ports.
2970 ret = sci_remap_port(port);
2971 if (unlikely(ret != 0))
2975 uart_parse_options(options, &baud, &parity, &bits, &flow);
2977 return uart_set_options(port, co, baud, parity, bits, flow);
2980 static struct console serial_console = {
2982 .device = uart_console_device,
2983 .write = serial_console_write,
2984 .setup = serial_console_setup,
2985 .flags = CON_PRINTBUFFER,
2987 .data = &sci_uart_driver,
2990 static struct console early_serial_console = {
2991 .name = "early_ttySC",
2992 .write = serial_console_write,
2993 .flags = CON_PRINTBUFFER,
2997 static char early_serial_buf[32];
2999 static int sci_probe_earlyprintk(struct platform_device *pdev)
3001 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3003 if (early_serial_console.data)
3006 early_serial_console.index = pdev->id;
3008 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3010 serial_console_setup(&early_serial_console, early_serial_buf);
3012 if (!strstr(early_serial_buf, "keep"))
3013 early_serial_console.flags |= CON_BOOT;
3015 register_console(&early_serial_console);
3019 #define SCI_CONSOLE (&serial_console)
3022 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3027 #define SCI_CONSOLE NULL
3029 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3031 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3033 static DEFINE_MUTEX(sci_uart_registration_lock);
3034 static struct uart_driver sci_uart_driver = {
3035 .owner = THIS_MODULE,
3036 .driver_name = "sci",
3037 .dev_name = "ttySC",
3039 .minor = SCI_MINOR_START,
3041 .cons = SCI_CONSOLE,
3044 static int sci_remove(struct platform_device *dev)
3046 struct sci_port *port = platform_get_drvdata(dev);
3048 sci_ports_in_use &= ~BIT(port->port.line);
3049 uart_remove_one_port(&sci_uart_driver, &port->port);
3051 sci_cleanup_single(port);
3053 if (port->port.fifosize > 1) {
3054 sysfs_remove_file(&dev->dev.kobj,
3055 &dev_attr_rx_fifo_trigger.attr);
3057 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3058 port->port.type == PORT_HSCIF) {
3059 sysfs_remove_file(&dev->dev.kobj,
3060 &dev_attr_rx_fifo_timeout.attr);
3067 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3068 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3069 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3071 static const struct of_device_id of_sci_match[] = {
3072 /* SoC-specific types */
3074 .compatible = "renesas,scif-r7s72100",
3075 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3077 /* Family-specific types */
3079 .compatible = "renesas,rcar-gen1-scif",
3080 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3082 .compatible = "renesas,rcar-gen2-scif",
3083 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3085 .compatible = "renesas,rcar-gen3-scif",
3086 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3090 .compatible = "renesas,scif",
3091 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3093 .compatible = "renesas,scifa",
3094 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3096 .compatible = "renesas,scifb",
3097 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3099 .compatible = "renesas,hscif",
3100 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3102 .compatible = "renesas,sci",
3103 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3108 MODULE_DEVICE_TABLE(of, of_sci_match);
3110 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3111 unsigned int *dev_id)
3113 struct device_node *np = pdev->dev.of_node;
3114 struct plat_sci_port *p;
3115 struct sci_port *sp;
3119 if (!IS_ENABLED(CONFIG_OF) || !np)
3122 data = of_device_get_match_data(&pdev->dev);
3124 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3128 /* Get the line number from the aliases node. */
3129 id = of_alias_get_id(np, "serial");
3130 if (id < 0 && ~sci_ports_in_use)
3131 id = ffz(sci_ports_in_use);
3133 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3136 if (id >= ARRAY_SIZE(sci_ports)) {
3137 dev_err(&pdev->dev, "serial%d out of range\n", id);
3141 sp = &sci_ports[id];
3144 p->type = SCI_OF_TYPE(data);
3145 p->regtype = SCI_OF_REGTYPE(data);
3147 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3152 static int sci_probe_single(struct platform_device *dev,
3154 struct plat_sci_port *p,
3155 struct sci_port *sciport)
3160 if (unlikely(index >= SCI_NPORTS)) {
3161 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3162 index+1, SCI_NPORTS);
3163 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3166 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3167 if (sci_ports_in_use & BIT(index))
3170 mutex_lock(&sci_uart_registration_lock);
3171 if (!sci_uart_driver.state) {
3172 ret = uart_register_driver(&sci_uart_driver);
3174 mutex_unlock(&sci_uart_registration_lock);
3178 mutex_unlock(&sci_uart_registration_lock);
3180 ret = sci_init_single(dev, sciport, index, p, false);
3184 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3185 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3186 return PTR_ERR(sciport->gpios);
3188 if (sciport->has_rtscts) {
3189 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3191 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3193 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3196 sciport->port.flags |= UPF_HARD_FLOW;
3199 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3201 sci_cleanup_single(sciport);
3208 static int sci_probe(struct platform_device *dev)
3210 struct plat_sci_port *p;
3211 struct sci_port *sp;
3212 unsigned int dev_id;
3216 * If we've come here via earlyprintk initialization, head off to
3217 * the special early probe. We don't have sufficient device state
3218 * to make it beyond this yet.
3220 if (is_early_platform_device(dev))
3221 return sci_probe_earlyprintk(dev);
3223 if (dev->dev.of_node) {
3224 p = sci_parse_dt(dev, &dev_id);
3228 p = dev->dev.platform_data;
3230 dev_err(&dev->dev, "no platform data supplied\n");
3237 sp = &sci_ports[dev_id];
3238 platform_set_drvdata(dev, sp);
3240 ret = sci_probe_single(dev, dev_id, p, sp);
3244 if (sp->port.fifosize > 1) {
3245 ret = sysfs_create_file(&dev->dev.kobj,
3246 &dev_attr_rx_fifo_trigger.attr);
3250 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3251 sp->port.type == PORT_HSCIF) {
3252 ret = sysfs_create_file(&dev->dev.kobj,
3253 &dev_attr_rx_fifo_timeout.attr);
3255 if (sp->port.fifosize > 1) {
3256 sysfs_remove_file(&dev->dev.kobj,
3257 &dev_attr_rx_fifo_trigger.attr);
3263 #ifdef CONFIG_SH_STANDARD_BIOS
3264 sh_bios_gdb_detach();
3267 sci_ports_in_use |= BIT(dev_id);
3271 static __maybe_unused int sci_suspend(struct device *dev)
3273 struct sci_port *sport = dev_get_drvdata(dev);
3276 uart_suspend_port(&sci_uart_driver, &sport->port);
3281 static __maybe_unused int sci_resume(struct device *dev)
3283 struct sci_port *sport = dev_get_drvdata(dev);
3286 uart_resume_port(&sci_uart_driver, &sport->port);
3291 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3293 static struct platform_driver sci_driver = {
3295 .remove = sci_remove,
3298 .pm = &sci_dev_pm_ops,
3299 .of_match_table = of_match_ptr(of_sci_match),
3303 static int __init sci_init(void)
3305 pr_info("%s\n", banner);
3307 return platform_driver_register(&sci_driver);
3310 static void __exit sci_exit(void)
3312 platform_driver_unregister(&sci_driver);
3314 if (sci_uart_driver.state)
3315 uart_unregister_driver(&sci_uart_driver);
3318 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3319 early_platform_init_buffer("earlyprintk", &sci_driver,
3320 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3322 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3323 static struct plat_sci_port port_cfg __initdata;
3325 static int __init early_console_setup(struct earlycon_device *device,
3328 if (!device->port.membase)
3331 device->port.serial_in = sci_serial_in;
3332 device->port.serial_out = sci_serial_out;
3333 device->port.type = type;
3334 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3335 port_cfg.type = type;
3336 sci_ports[0].cfg = &port_cfg;
3337 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3338 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3339 sci_serial_out(&sci_ports[0].port, SCSCR,
3340 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3342 device->con->write = serial_console_write;
3345 static int __init sci_early_console_setup(struct earlycon_device *device,
3348 return early_console_setup(device, PORT_SCI);
3350 static int __init scif_early_console_setup(struct earlycon_device *device,
3353 return early_console_setup(device, PORT_SCIF);
3355 static int __init scifa_early_console_setup(struct earlycon_device *device,
3358 return early_console_setup(device, PORT_SCIFA);
3360 static int __init scifb_early_console_setup(struct earlycon_device *device,
3363 return early_console_setup(device, PORT_SCIFB);
3365 static int __init hscif_early_console_setup(struct earlycon_device *device,
3368 return early_console_setup(device, PORT_HSCIF);
3371 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3372 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3373 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3374 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3375 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3376 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3378 module_init(sci_init);
3379 module_exit(sci_exit);
3381 MODULE_LICENSE("GPL");
3382 MODULE_ALIAS("platform:sh-sci");
3383 MODULE_AUTHOR("Paul Mundt");
3384 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");