1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <uapi/linux/sched/types.h>
29 #define SC16IS7XX_NAME "sc16is7xx"
30 #define SC16IS7XX_MAX_DEVS 8
32 /* SC16IS7XX register definitions */
33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67 /* Enhanced Register set: Only if (LCR == 0xBF) */
68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74 /* IER register bits */
75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
83 /* IER register bits - write only if (EFR[4] == 1) */
84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89 /* FCR register bits */
90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96 /* FCR register bits - write only if (EFR[4] == 1) */
97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100 /* IIR register bits */
101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
118 /* LCR register bits */
119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 * Word length bits table:
128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 * STOP length bit table:
132 * 1 -> 1-1.5 stop bits if
134 * 2 stop bits otherwise
136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
150 /* MCR register bits */
151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 /* LSR register bits */
171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181 /* MSR register bits */
182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237 /* IOControl register bits (Only 750/760) */
238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242 /* EFCR register bits */
243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
252 * 1 = rate upto 1.152 Mbit/s
256 /* EFR register bits */
257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
270 * 01 -> transmitter generates
272 * 10 -> transmitter generates
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
284 * 01 -> receiver compares
286 * 10 -> receiver compares
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
293 /* Misc definitions */
294 #define SC16IS7XX_FIFO_SIZE (64)
295 #define SC16IS7XX_REG_SHIFT 2
297 struct sc16is7xx_devtype {
303 #define SC16IS7XX_RECONF_MD (1 << 0)
304 #define SC16IS7XX_RECONF_IER (1 << 1)
305 #define SC16IS7XX_RECONF_RS485 (1 << 2)
307 struct sc16is7xx_one_config {
312 struct sc16is7xx_one {
313 struct uart_port port;
315 struct kthread_work tx_work;
316 struct kthread_work reg_work;
317 struct sc16is7xx_one_config config;
321 struct sc16is7xx_port {
322 const struct sc16is7xx_devtype *devtype;
323 struct regmap *regmap;
325 #ifdef CONFIG_GPIOLIB
326 struct gpio_chip gpio;
328 unsigned char buf[SC16IS7XX_FIFO_SIZE];
329 struct kthread_worker kworker;
330 struct task_struct *kworker_task;
331 struct mutex efr_lock;
332 struct sc16is7xx_one p[];
335 static unsigned long sc16is7xx_lines;
337 static struct uart_driver sc16is7xx_uart = {
338 .owner = THIS_MODULE,
340 .nr = SC16IS7XX_MAX_DEVS,
343 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
344 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
346 static int sc16is7xx_line(struct uart_port *port)
348 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
353 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
355 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
356 unsigned int val = 0;
357 const u8 line = sc16is7xx_line(port);
359 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
364 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
366 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
367 const u8 line = sc16is7xx_line(port);
369 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
372 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
374 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
375 const u8 line = sc16is7xx_line(port);
376 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
378 regcache_cache_bypass(s->regmap, true);
379 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
380 regcache_cache_bypass(s->regmap, false);
383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
385 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
386 const u8 line = sc16is7xx_line(port);
387 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
390 * Don't send zero-length data, at least on SPI it confuses the chip
391 * delivering wrong TXLVL data.
393 if (unlikely(!to_send))
396 regcache_cache_bypass(s->regmap, true);
397 regmap_raw_write(s->regmap, addr, s->buf, to_send);
398 regcache_cache_bypass(s->regmap, false);
401 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
404 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
405 const u8 line = sc16is7xx_line(port);
407 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
411 static int sc16is7xx_alloc_line(void)
415 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
417 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
418 if (!test_and_set_bit(i, &sc16is7xx_lines))
424 static void sc16is7xx_power(struct uart_port *port, int on)
426 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
427 SC16IS7XX_IER_SLEEP_BIT,
428 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
431 static const struct sc16is7xx_devtype sc16is74x_devtype = {
437 static const struct sc16is7xx_devtype sc16is750_devtype = {
443 static const struct sc16is7xx_devtype sc16is752_devtype = {
449 static const struct sc16is7xx_devtype sc16is760_devtype = {
455 static const struct sc16is7xx_devtype sc16is762_devtype = {
461 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
463 switch (reg >> SC16IS7XX_REG_SHIFT) {
464 case SC16IS7XX_RHR_REG:
465 case SC16IS7XX_IIR_REG:
466 case SC16IS7XX_LSR_REG:
467 case SC16IS7XX_MSR_REG:
468 case SC16IS7XX_TXLVL_REG:
469 case SC16IS7XX_RXLVL_REG:
470 case SC16IS7XX_IOSTATE_REG:
479 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
481 switch (reg >> SC16IS7XX_REG_SHIFT) {
482 case SC16IS7XX_RHR_REG:
491 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
493 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
496 unsigned long clk = port->uartclk, div = clk / 16 / baud;
499 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
503 /* In an amazing feat of design, the Enhanced Features Register shares
504 * the address of the Interrupt Identification Register, and is
505 * switched in by writing a magic value (0xbf) to the Line Control
506 * Register. Any interrupt firing during this time will see the EFR
507 * where it expects the IIR to be, leading to "Unexpected interrupt"
510 * Prevent this possibility by claiming a mutex while accessing the
511 * EFR, and claiming the same mutex from within the interrupt handler.
512 * This is similar to disabling the interrupt, but that doesn't work
513 * because the bulk of the interrupt processing is run as a workqueue
514 * job in thread context.
516 mutex_lock(&s->efr_lock);
518 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
520 /* Open the LCR divisors for configuration */
521 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
522 SC16IS7XX_LCR_CONF_MODE_B);
524 /* Enable enhanced features */
525 regcache_cache_bypass(s->regmap, true);
526 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
527 SC16IS7XX_EFR_ENABLE_BIT);
528 regcache_cache_bypass(s->regmap, false);
530 /* Put LCR back to the normal mode */
531 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
533 mutex_unlock(&s->efr_lock);
535 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
536 SC16IS7XX_MCR_CLKSEL_BIT,
539 /* Open the LCR divisors for configuration */
540 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
541 SC16IS7XX_LCR_CONF_MODE_A);
543 /* Write the new divisor */
544 regcache_cache_bypass(s->regmap, true);
545 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
546 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
547 regcache_cache_bypass(s->regmap, false);
549 /* Put LCR back to the normal mode */
550 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
552 return DIV_ROUND_CLOSEST(clk / 16, div);
555 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
558 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
559 unsigned int lsr = 0, ch, flag, bytes_read, i;
560 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
562 if (unlikely(rxlen >= sizeof(s->buf))) {
563 dev_warn_ratelimited(port->dev,
564 "ttySC%i: Possible RX FIFO overrun: %d\n",
566 port->icount.buf_overrun++;
567 /* Ensure sanity of RX level */
568 rxlen = sizeof(s->buf);
572 /* Only read lsr if there are possible errors in FIFO */
574 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
575 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
576 read_lsr = false; /* No errors left in FIFO */
581 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
584 sc16is7xx_fifo_read(port, rxlen);
588 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
594 if (lsr & SC16IS7XX_LSR_BI_BIT) {
596 if (uart_handle_break(port))
598 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
599 port->icount.parity++;
600 else if (lsr & SC16IS7XX_LSR_FE_BIT)
601 port->icount.frame++;
602 else if (lsr & SC16IS7XX_LSR_OE_BIT)
603 port->icount.overrun++;
605 lsr &= port->read_status_mask;
606 if (lsr & SC16IS7XX_LSR_BI_BIT)
608 else if (lsr & SC16IS7XX_LSR_PE_BIT)
610 else if (lsr & SC16IS7XX_LSR_FE_BIT)
612 else if (lsr & SC16IS7XX_LSR_OE_BIT)
616 for (i = 0; i < bytes_read; ++i) {
618 if (uart_handle_sysrq_char(port, ch))
621 if (lsr & port->ignore_status_mask)
624 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
630 tty_flip_buffer_push(&port->state->port);
633 static void sc16is7xx_handle_tx(struct uart_port *port)
635 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
636 struct circ_buf *xmit = &port->state->xmit;
637 unsigned int txlen, to_send, i;
639 if (unlikely(port->x_char)) {
640 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
646 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
649 /* Get length of data pending in circular buffer */
650 to_send = uart_circ_chars_pending(xmit);
651 if (likely(to_send)) {
652 /* Limit to size of TX FIFO */
653 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
654 if (txlen > SC16IS7XX_FIFO_SIZE) {
655 dev_err_ratelimited(port->dev,
656 "chip reports %d free bytes in TX fifo, but it only has %d",
657 txlen, SC16IS7XX_FIFO_SIZE);
660 to_send = (to_send > txlen) ? txlen : to_send;
662 /* Add data to send */
663 port->icount.tx += to_send;
665 /* Convert to linear buffer */
666 for (i = 0; i < to_send; ++i) {
667 s->buf[i] = xmit->buf[xmit->tail];
668 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
671 sc16is7xx_fifo_write(port, to_send);
674 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
675 uart_write_wakeup(port);
678 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
680 struct uart_port *port = &s->p[portno].port;
683 unsigned int iir, rxlen;
685 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
686 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
689 iir &= SC16IS7XX_IIR_ID_MASK;
692 case SC16IS7XX_IIR_RDI_SRC:
693 case SC16IS7XX_IIR_RLSE_SRC:
694 case SC16IS7XX_IIR_RTOI_SRC:
695 case SC16IS7XX_IIR_XOFFI_SRC:
696 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
698 sc16is7xx_handle_rx(port, rxlen, iir);
700 case SC16IS7XX_IIR_THRI_SRC:
701 sc16is7xx_handle_tx(port);
704 dev_err_ratelimited(port->dev,
705 "ttySC%i: Unexpected interrupt: %x",
713 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
715 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
717 mutex_lock(&s->efr_lock);
720 bool keep_polling = false;
723 for (i = 0; i < s->devtype->nr_uart; ++i)
724 keep_polling |= sc16is7xx_port_irq(s, i);
729 mutex_unlock(&s->efr_lock);
734 static void sc16is7xx_tx_proc(struct kthread_work *ws)
736 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
737 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
739 if ((port->rs485.flags & SER_RS485_ENABLED) &&
740 (port->rs485.delay_rts_before_send > 0))
741 msleep(port->rs485.delay_rts_before_send);
743 mutex_lock(&s->efr_lock);
744 sc16is7xx_handle_tx(port);
745 mutex_unlock(&s->efr_lock);
748 static void sc16is7xx_reconf_rs485(struct uart_port *port)
750 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
751 SC16IS7XX_EFCR_RTS_INVERT_BIT;
753 struct serial_rs485 *rs485 = &port->rs485;
754 unsigned long irqflags;
756 spin_lock_irqsave(&port->lock, irqflags);
757 if (rs485->flags & SER_RS485_ENABLED) {
758 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
760 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
761 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
763 spin_unlock_irqrestore(&port->lock, irqflags);
765 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
768 static void sc16is7xx_reg_proc(struct kthread_work *ws)
770 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
771 struct sc16is7xx_one_config config;
772 unsigned long irqflags;
774 spin_lock_irqsave(&one->port.lock, irqflags);
775 config = one->config;
776 memset(&one->config, 0, sizeof(one->config));
777 spin_unlock_irqrestore(&one->port.lock, irqflags);
779 if (config.flags & SC16IS7XX_RECONF_MD) {
780 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
781 SC16IS7XX_MCR_LOOP_BIT,
782 (one->port.mctrl & TIOCM_LOOP) ?
783 SC16IS7XX_MCR_LOOP_BIT : 0);
784 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
785 SC16IS7XX_MCR_RTS_BIT,
786 (one->port.mctrl & TIOCM_RTS) ?
787 SC16IS7XX_MCR_RTS_BIT : 0);
788 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
789 SC16IS7XX_MCR_DTR_BIT,
790 (one->port.mctrl & TIOCM_DTR) ?
791 SC16IS7XX_MCR_DTR_BIT : 0);
793 if (config.flags & SC16IS7XX_RECONF_IER)
794 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
795 config.ier_clear, 0);
797 if (config.flags & SC16IS7XX_RECONF_RS485)
798 sc16is7xx_reconf_rs485(&one->port);
801 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
803 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
804 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
806 one->config.flags |= SC16IS7XX_RECONF_IER;
807 one->config.ier_clear |= bit;
808 kthread_queue_work(&s->kworker, &one->reg_work);
811 static void sc16is7xx_stop_tx(struct uart_port *port)
813 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
816 static void sc16is7xx_stop_rx(struct uart_port *port)
818 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
821 static void sc16is7xx_start_tx(struct uart_port *port)
823 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
824 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
826 kthread_queue_work(&s->kworker, &one->tx_work);
829 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
833 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
835 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
838 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
840 /* DCD and DSR are not wired and CTS/RTS is handled automatically
841 * so just indicate DSR and CAR asserted
843 return TIOCM_DSR | TIOCM_CAR;
846 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
848 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
849 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
851 one->config.flags |= SC16IS7XX_RECONF_MD;
852 kthread_queue_work(&s->kworker, &one->reg_work);
855 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
857 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
858 SC16IS7XX_LCR_TXBREAK_BIT,
859 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
862 static void sc16is7xx_set_termios(struct uart_port *port,
863 struct ktermios *termios,
864 struct ktermios *old)
866 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
867 unsigned int lcr, flow = 0;
870 /* Mask termios capabilities we don't support */
871 termios->c_cflag &= ~CMSPAR;
874 switch (termios->c_cflag & CSIZE) {
876 lcr = SC16IS7XX_LCR_WORD_LEN_5;
879 lcr = SC16IS7XX_LCR_WORD_LEN_6;
882 lcr = SC16IS7XX_LCR_WORD_LEN_7;
885 lcr = SC16IS7XX_LCR_WORD_LEN_8;
888 lcr = SC16IS7XX_LCR_WORD_LEN_8;
889 termios->c_cflag &= ~CSIZE;
890 termios->c_cflag |= CS8;
895 if (termios->c_cflag & PARENB) {
896 lcr |= SC16IS7XX_LCR_PARITY_BIT;
897 if (!(termios->c_cflag & PARODD))
898 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
902 if (termios->c_cflag & CSTOPB)
903 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
905 /* Set read status mask */
906 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
907 if (termios->c_iflag & INPCK)
908 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
909 SC16IS7XX_LSR_FE_BIT;
910 if (termios->c_iflag & (BRKINT | PARMRK))
911 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
913 /* Set status ignore mask */
914 port->ignore_status_mask = 0;
915 if (termios->c_iflag & IGNBRK)
916 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
917 if (!(termios->c_cflag & CREAD))
918 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
920 /* As above, claim the mutex while accessing the EFR. */
921 mutex_lock(&s->efr_lock);
923 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
924 SC16IS7XX_LCR_CONF_MODE_B);
926 /* Configure flow control */
927 regcache_cache_bypass(s->regmap, true);
928 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
929 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
930 if (termios->c_cflag & CRTSCTS)
931 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
932 SC16IS7XX_EFR_AUTORTS_BIT;
933 if (termios->c_iflag & IXON)
934 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
935 if (termios->c_iflag & IXOFF)
936 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
938 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
939 regcache_cache_bypass(s->regmap, false);
941 /* Update LCR register */
942 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
944 mutex_unlock(&s->efr_lock);
946 /* Get baud rate generator configuration */
947 baud = uart_get_baud_rate(port, termios, old,
948 port->uartclk / 16 / 4 / 0xffff,
951 /* Setup baudrate generator */
952 baud = sc16is7xx_set_baud(port, baud);
954 /* Update timeout according to new baud rate */
955 uart_update_timeout(port, termios->c_cflag, baud);
958 static int sc16is7xx_config_rs485(struct uart_port *port,
959 struct serial_rs485 *rs485)
961 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
962 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
964 if (rs485->flags & SER_RS485_ENABLED) {
965 bool rts_during_rx, rts_during_tx;
967 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
968 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
970 if (rts_during_rx == rts_during_tx)
972 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
973 rts_during_tx, rts_during_rx);
976 * RTS signal is handled by HW, it's timing can't be influenced.
977 * However, it's sometimes useful to delay TX even without RTS
978 * control therefore we try to handle .delay_rts_before_send.
980 if (rs485->delay_rts_after_send)
984 port->rs485 = *rs485;
985 one->config.flags |= SC16IS7XX_RECONF_RS485;
986 kthread_queue_work(&s->kworker, &one->reg_work);
991 static int sc16is7xx_startup(struct uart_port *port)
993 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
994 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
997 sc16is7xx_power(port, 1);
1000 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1001 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1003 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1004 SC16IS7XX_FCR_FIFO_BIT);
1007 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1008 SC16IS7XX_LCR_CONF_MODE_B);
1010 regcache_cache_bypass(s->regmap, true);
1012 /* Enable write access to enhanced features and internal clock div */
1013 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1014 SC16IS7XX_EFR_ENABLE_BIT);
1016 /* Enable TCR/TLR */
1017 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1018 SC16IS7XX_MCR_TCRTLR_BIT,
1019 SC16IS7XX_MCR_TCRTLR_BIT);
1021 /* Configure flow control levels */
1022 /* Flow control halt level 48, resume level 24 */
1023 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1024 SC16IS7XX_TCR_RX_RESUME(24) |
1025 SC16IS7XX_TCR_RX_HALT(48));
1027 regcache_cache_bypass(s->regmap, false);
1029 /* Now, initialize the UART */
1030 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1032 /* Enable IrDA mode if requested in DT */
1033 /* This bit must be written with LCR[7] = 0 */
1034 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1035 SC16IS7XX_MCR_IRDA_BIT,
1037 SC16IS7XX_MCR_IRDA_BIT : 0);
1039 /* Enable the Rx and Tx FIFO */
1040 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1041 SC16IS7XX_EFCR_RXDISABLE_BIT |
1042 SC16IS7XX_EFCR_TXDISABLE_BIT,
1045 /* Enable RX, TX interrupts */
1046 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1047 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1052 static void sc16is7xx_shutdown(struct uart_port *port)
1054 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1056 /* Disable all interrupts */
1057 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1059 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1060 SC16IS7XX_EFCR_RXDISABLE_BIT |
1061 SC16IS7XX_EFCR_TXDISABLE_BIT,
1062 SC16IS7XX_EFCR_RXDISABLE_BIT |
1063 SC16IS7XX_EFCR_TXDISABLE_BIT);
1065 sc16is7xx_power(port, 0);
1067 kthread_flush_worker(&s->kworker);
1070 static const char *sc16is7xx_type(struct uart_port *port)
1072 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1074 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1077 static int sc16is7xx_request_port(struct uart_port *port)
1083 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1085 if (flags & UART_CONFIG_TYPE)
1086 port->type = PORT_SC16IS7XX;
1089 static int sc16is7xx_verify_port(struct uart_port *port,
1090 struct serial_struct *s)
1092 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1094 if (s->irq != port->irq)
1100 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1101 unsigned int oldstate)
1103 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1106 static void sc16is7xx_null_void(struct uart_port *port)
1111 static const struct uart_ops sc16is7xx_ops = {
1112 .tx_empty = sc16is7xx_tx_empty,
1113 .set_mctrl = sc16is7xx_set_mctrl,
1114 .get_mctrl = sc16is7xx_get_mctrl,
1115 .stop_tx = sc16is7xx_stop_tx,
1116 .start_tx = sc16is7xx_start_tx,
1117 .stop_rx = sc16is7xx_stop_rx,
1118 .break_ctl = sc16is7xx_break_ctl,
1119 .startup = sc16is7xx_startup,
1120 .shutdown = sc16is7xx_shutdown,
1121 .set_termios = sc16is7xx_set_termios,
1122 .type = sc16is7xx_type,
1123 .request_port = sc16is7xx_request_port,
1124 .release_port = sc16is7xx_null_void,
1125 .config_port = sc16is7xx_config_port,
1126 .verify_port = sc16is7xx_verify_port,
1130 #ifdef CONFIG_GPIOLIB
1131 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1134 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1135 struct uart_port *port = &s->p[0].port;
1137 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1139 return !!(val & BIT(offset));
1142 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1144 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1145 struct uart_port *port = &s->p[0].port;
1147 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1148 val ? BIT(offset) : 0);
1151 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1154 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1155 struct uart_port *port = &s->p[0].port;
1157 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1162 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1163 unsigned offset, int val)
1165 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1166 struct uart_port *port = &s->p[0].port;
1167 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1170 state |= BIT(offset);
1172 state &= ~BIT(offset);
1173 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1174 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1181 static int sc16is7xx_probe(struct device *dev,
1182 const struct sc16is7xx_devtype *devtype,
1183 struct regmap *regmap, int irq)
1185 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1189 struct sc16is7xx_port *s;
1192 return PTR_ERR(regmap);
1195 * This device does not have an identification register that would
1196 * tell us if we are really connected to the correct device.
1197 * The best we can do is to check if communication is at all possible.
1199 ret = regmap_read(regmap,
1200 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1202 return -EPROBE_DEFER;
1204 /* Alloc port structure */
1205 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1207 dev_err(dev, "Error allocating port structure\n");
1211 /* Always ask for fixed clock rate from a property. */
1212 device_property_read_u32(dev, "clock-frequency", &uartclk);
1214 s->clk = devm_clk_get_optional(dev, NULL);
1216 return PTR_ERR(s->clk);
1218 ret = clk_prepare_enable(s->clk);
1222 freq = clk_get_rate(s->clk);
1229 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1235 s->devtype = devtype;
1236 dev_set_drvdata(dev, s);
1237 mutex_init(&s->efr_lock);
1239 kthread_init_worker(&s->kworker);
1240 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1242 if (IS_ERR(s->kworker_task)) {
1243 ret = PTR_ERR(s->kworker_task);
1246 sched_set_fifo(s->kworker_task);
1248 #ifdef CONFIG_GPIOLIB
1249 if (devtype->nr_gpio) {
1250 /* Setup GPIO cotroller */
1251 s->gpio.owner = THIS_MODULE;
1252 s->gpio.parent = dev;
1253 s->gpio.label = dev_name(dev);
1254 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1255 s->gpio.get = sc16is7xx_gpio_get;
1256 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1257 s->gpio.set = sc16is7xx_gpio_set;
1259 s->gpio.ngpio = devtype->nr_gpio;
1260 s->gpio.can_sleep = 1;
1261 ret = gpiochip_add_data(&s->gpio, s);
1267 /* reset device, purging any pending irq / data */
1268 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1269 SC16IS7XX_IOCONTROL_SRESET_BIT);
1271 for (i = 0; i < devtype->nr_uart; ++i) {
1273 /* Initialize port data */
1274 s->p[i].port.dev = dev;
1275 s->p[i].port.irq = irq;
1276 s->p[i].port.type = PORT_SC16IS7XX;
1277 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1278 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1279 s->p[i].port.iobase = i;
1280 s->p[i].port.iotype = UPIO_PORT;
1281 s->p[i].port.uartclk = freq;
1282 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1283 s->p[i].port.ops = &sc16is7xx_ops;
1284 s->p[i].port.line = sc16is7xx_alloc_line();
1285 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1290 /* Disable all interrupts */
1291 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1293 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1294 SC16IS7XX_EFCR_RXDISABLE_BIT |
1295 SC16IS7XX_EFCR_TXDISABLE_BIT);
1296 /* Initialize kthread work structs */
1297 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1298 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1300 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1303 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1304 SC16IS7XX_LCR_CONF_MODE_B);
1306 regcache_cache_bypass(s->regmap, true);
1308 /* Enable write access to enhanced features */
1309 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1310 SC16IS7XX_EFR_ENABLE_BIT);
1312 regcache_cache_bypass(s->regmap, false);
1314 /* Restore access to general registers */
1315 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1317 /* Go to suspend mode */
1318 sc16is7xx_power(&s->p[i].port, 0);
1322 struct property *prop;
1326 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1328 if (u < devtype->nr_uart)
1329 s->p[u].irda_mode = true;
1333 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1334 * If that succeeds, we can allow sharing the interrupt as well.
1335 * In case the interrupt controller doesn't support that, we fall
1336 * back to a non-shared falling-edge trigger.
1338 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1339 IRQF_TRIGGER_LOW | IRQF_SHARED |
1345 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1346 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1352 for (i--; i >= 0; i--) {
1353 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1354 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1357 #ifdef CONFIG_GPIOLIB
1358 if (devtype->nr_gpio)
1359 gpiochip_remove(&s->gpio);
1363 kthread_stop(s->kworker_task);
1366 clk_disable_unprepare(s->clk);
1371 static void sc16is7xx_remove(struct device *dev)
1373 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1376 #ifdef CONFIG_GPIOLIB
1377 if (s->devtype->nr_gpio)
1378 gpiochip_remove(&s->gpio);
1381 for (i = 0; i < s->devtype->nr_uart; i++) {
1382 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1383 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1384 sc16is7xx_power(&s->p[i].port, 0);
1387 kthread_flush_worker(&s->kworker);
1388 kthread_stop(s->kworker_task);
1390 clk_disable_unprepare(s->clk);
1393 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1394 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1395 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1396 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1397 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1398 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1399 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1402 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1404 static struct regmap_config regcfg = {
1408 .cache_type = REGCACHE_RBTREE,
1409 .volatile_reg = sc16is7xx_regmap_volatile,
1410 .precious_reg = sc16is7xx_regmap_precious,
1413 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1414 static int sc16is7xx_spi_probe(struct spi_device *spi)
1416 const struct sc16is7xx_devtype *devtype;
1417 struct regmap *regmap;
1421 spi->bits_per_word = 8;
1422 /* only supports mode 0 on SC16IS762 */
1423 spi->mode = spi->mode ? : SPI_MODE_0;
1424 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1425 ret = spi_setup(spi);
1429 if (spi->dev.of_node) {
1430 devtype = device_get_match_data(&spi->dev);
1434 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1436 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1439 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1440 (devtype->nr_uart - 1);
1441 regmap = devm_regmap_init_spi(spi, ®cfg);
1443 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1446 static void sc16is7xx_spi_remove(struct spi_device *spi)
1448 sc16is7xx_remove(&spi->dev);
1451 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1452 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1453 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1454 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1455 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1456 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1457 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1458 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1462 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1464 static struct spi_driver sc16is7xx_spi_uart_driver = {
1466 .name = SC16IS7XX_NAME,
1467 .of_match_table = sc16is7xx_dt_ids,
1469 .probe = sc16is7xx_spi_probe,
1470 .remove = sc16is7xx_spi_remove,
1471 .id_table = sc16is7xx_spi_id_table,
1474 MODULE_ALIAS("spi:sc16is7xx");
1477 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1478 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1479 const struct i2c_device_id *id)
1481 const struct sc16is7xx_devtype *devtype;
1482 struct regmap *regmap;
1484 if (i2c->dev.of_node) {
1485 devtype = device_get_match_data(&i2c->dev);
1489 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1492 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1493 (devtype->nr_uart - 1);
1494 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1496 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1499 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1501 sc16is7xx_remove(&client->dev);
1506 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1507 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1508 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1509 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1510 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1511 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1512 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1513 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1516 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1518 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1520 .name = SC16IS7XX_NAME,
1521 .of_match_table = sc16is7xx_dt_ids,
1523 .probe = sc16is7xx_i2c_probe,
1524 .remove = sc16is7xx_i2c_remove,
1525 .id_table = sc16is7xx_i2c_id_table,
1530 static int __init sc16is7xx_init(void)
1534 ret = uart_register_driver(&sc16is7xx_uart);
1536 pr_err("Registering UART driver failed\n");
1540 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1541 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1543 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1548 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1549 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1551 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1557 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1560 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1561 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1564 uart_unregister_driver(&sc16is7xx_uart);
1567 module_init(sc16is7xx_init);
1569 static void __exit sc16is7xx_exit(void)
1571 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1572 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1575 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1576 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1578 uart_unregister_driver(&sc16is7xx_uart);
1580 module_exit(sc16is7xx_exit);
1582 MODULE_LICENSE("GPL");
1583 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1584 MODULE_DESCRIPTION("SC16IS7XX serial driver");