1 // SPDX-License-Identifier: GPL-2.0
3 * Driver core for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
9 /* Note on 2410 error handling
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
30 #include <linux/platform_device.h>
31 #include <linux/init.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_s3c.h>
39 #include <linux/delay.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
45 /* UART name and device definitions */
47 #define S3C24XX_SERIAL_NAME "ttySAC"
48 #define S3C24XX_SERIAL_MAJOR 204
49 #define S3C24XX_SERIAL_MINOR 64
51 #define S3C24XX_TX_PIO 1
52 #define S3C24XX_TX_DMA 2
53 #define S3C24XX_RX_PIO 1
54 #define S3C24XX_RX_DMA 2
56 /* flag to ignore all characters coming in */
57 #define RXSTAT_DUMMY_READ (0x10000000)
59 enum s3c24xx_port_type {
65 struct s3c24xx_uart_info {
67 enum s3c24xx_port_type type;
68 unsigned int port_type;
69 unsigned int fifosize;
70 unsigned long rx_fifomask;
71 unsigned long rx_fifoshift;
72 unsigned long rx_fifofull;
73 unsigned long tx_fifomask;
74 unsigned long tx_fifoshift;
75 unsigned long tx_fifofull;
76 unsigned int def_clk_sel;
77 unsigned long num_clks;
78 unsigned long clksel_mask;
79 unsigned long clksel_shift;
80 unsigned long ucon_mask;
82 /* uart port features */
84 unsigned int has_divslot:1;
87 struct s3c24xx_serial_drv_data {
88 struct s3c24xx_uart_info *info;
89 struct s3c2410_uartcfg *def_cfg;
90 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
93 struct s3c24xx_uart_dma {
94 unsigned int rx_chan_id;
95 unsigned int tx_chan_id;
97 struct dma_slave_config rx_conf;
98 struct dma_slave_config tx_conf;
100 struct dma_chan *rx_chan;
101 struct dma_chan *tx_chan;
106 dma_cookie_t rx_cookie;
107 dma_cookie_t tx_cookie;
111 dma_addr_t tx_transfer_addr;
116 struct dma_async_tx_descriptor *tx_desc;
117 struct dma_async_tx_descriptor *rx_desc;
119 int tx_bytes_requested;
120 int rx_bytes_requested;
123 struct s3c24xx_uart_port {
124 unsigned char rx_claimed;
125 unsigned char tx_claimed;
126 unsigned char rx_enabled;
127 unsigned char tx_enabled;
128 unsigned int pm_level;
129 unsigned long baudclk_rate;
130 unsigned int min_dma_size;
135 unsigned int tx_in_progress;
136 unsigned int tx_mode;
137 unsigned int rx_mode;
139 struct s3c24xx_uart_info *info;
142 struct uart_port port;
143 struct s3c24xx_serial_drv_data *drv_data;
145 /* reference to platform data */
146 struct s3c2410_uartcfg *cfg;
148 struct s3c24xx_uart_dma *dma;
150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
151 struct notifier_block freq_transition;
155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
157 /* conversion functions */
159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
161 /* register access controls */
163 #define portaddr(port, reg) ((port)->membase + (reg))
164 #define portaddrl(port, reg) \
165 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
167 static u32 rd_reg(struct uart_port *port, u32 reg)
169 switch (port->iotype) {
171 return readb_relaxed(portaddr(port, reg));
173 return readl_relaxed(portaddr(port, reg));
180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
182 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
184 switch (port->iotype) {
186 writeb_relaxed(val, portaddr(port, reg));
189 writel_relaxed(val, portaddr(port, reg));
194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
196 /* Byte-order aware bit setting/clearing functions. */
198 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
204 local_irq_save(flags);
205 val = rd_regl(port, reg);
207 wr_regl(port, reg, val);
208 local_irq_restore(flags);
211 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
217 local_irq_save(flags);
218 val = rd_regl(port, reg);
220 wr_regl(port, reg, val);
221 local_irq_restore(flags);
224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
226 return container_of(port, struct s3c24xx_uart_port, port);
229 /* translate a port to the device name */
231 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
233 return to_platform_device(port->dev)->name;
236 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
243 struct s3c24xx_uart_port *ourport = to_ourport(port);
245 unsigned int ucon, ufcon;
248 spin_lock_irqsave(&port->lock, flags);
250 while (--count && !s3c24xx_serial_txempty_nofifo(port))
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufcon |= S3C2410_UFCON_RESETRX;
255 wr_regl(port, S3C2410_UFCON, ufcon);
257 ucon = rd_regl(port, S3C2410_UCON);
258 ucon |= S3C2410_UCON_RXIRQMODE;
259 wr_regl(port, S3C2410_UCON, ucon);
261 ourport->rx_enabled = 1;
262 spin_unlock_irqrestore(&port->lock, flags);
265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
267 struct s3c24xx_uart_port *ourport = to_ourport(port);
271 spin_lock_irqsave(&port->lock, flags);
273 ucon = rd_regl(port, S3C2410_UCON);
274 ucon &= ~S3C2410_UCON_RXIRQMODE;
275 wr_regl(port, S3C2410_UCON, ucon);
277 ourport->rx_enabled = 0;
278 spin_unlock_irqrestore(&port->lock, flags);
281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
283 struct s3c24xx_uart_port *ourport = to_ourport(port);
284 struct s3c24xx_uart_dma *dma = ourport->dma;
285 struct circ_buf *xmit = &port->state->xmit;
286 struct dma_tx_state state;
289 if (!ourport->tx_enabled)
292 switch (ourport->info->type) {
294 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
297 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
300 disable_irq_nosync(ourport->tx_irq);
304 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
305 dmaengine_pause(dma->tx_chan);
306 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
307 dmaengine_terminate_all(dma->tx_chan);
308 dma_sync_single_for_cpu(ourport->port.dev,
309 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
310 async_tx_ack(dma->tx_desc);
311 count = dma->tx_bytes_requested - state.residue;
312 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
313 port->icount.tx += count;
316 ourport->tx_enabled = 0;
317 ourport->tx_in_progress = 0;
319 if (port->flags & UPF_CONS_FLOW)
320 s3c24xx_serial_rx_enable(port);
322 ourport->tx_mode = 0;
325 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
327 static void s3c24xx_serial_tx_dma_complete(void *args)
329 struct s3c24xx_uart_port *ourport = args;
330 struct uart_port *port = &ourport->port;
331 struct circ_buf *xmit = &port->state->xmit;
332 struct s3c24xx_uart_dma *dma = ourport->dma;
333 struct dma_tx_state state;
337 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
338 count = dma->tx_bytes_requested - state.residue;
339 async_tx_ack(dma->tx_desc);
341 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
342 dma->tx_size, DMA_TO_DEVICE);
344 spin_lock_irqsave(&port->lock, flags);
346 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
347 port->icount.tx += count;
348 ourport->tx_in_progress = 0;
350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
351 uart_write_wakeup(port);
353 s3c24xx_serial_start_next_tx(ourport);
354 spin_unlock_irqrestore(&port->lock, flags);
357 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
359 struct uart_port *port = &ourport->port;
362 /* Mask Tx interrupt */
363 switch (ourport->info->type) {
365 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
368 WARN_ON(1); // No DMA
371 disable_irq_nosync(ourport->tx_irq);
375 /* Enable tx dma mode */
376 ucon = rd_regl(port, S3C2410_UCON);
377 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
378 ucon |= (dma_get_cache_alignment() >= 16) ?
379 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
380 ucon |= S3C64XX_UCON_TXMODE_DMA;
381 wr_regl(port, S3C2410_UCON, ucon);
383 ourport->tx_mode = S3C24XX_TX_DMA;
386 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
388 struct uart_port *port = &ourport->port;
391 /* Set ufcon txtrig */
392 ourport->tx_in_progress = S3C24XX_TX_PIO;
393 ufcon = rd_regl(port, S3C2410_UFCON);
394 wr_regl(port, S3C2410_UFCON, ufcon);
396 /* Enable tx pio mode */
397 ucon = rd_regl(port, S3C2410_UCON);
398 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
399 ucon |= S3C64XX_UCON_TXMODE_CPU;
400 wr_regl(port, S3C2410_UCON, ucon);
402 /* Unmask Tx interrupt */
403 switch (ourport->info->type) {
405 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
409 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
410 wr_regl(port, S3C2410_UCON, ucon);
413 enable_irq(ourport->tx_irq);
417 ourport->tx_mode = S3C24XX_TX_PIO;
420 * The Apple version only has edge triggered TX IRQs, so we need
421 * to kick off the process by sending some characters here.
423 if (ourport->info->type == TYPE_APPLE_S5L)
424 s3c24xx_serial_tx_chars(ourport);
427 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
429 if (ourport->tx_mode != S3C24XX_TX_PIO)
430 enable_tx_pio(ourport);
433 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
436 struct uart_port *port = &ourport->port;
437 struct circ_buf *xmit = &port->state->xmit;
438 struct s3c24xx_uart_dma *dma = ourport->dma;
440 if (ourport->tx_mode != S3C24XX_TX_DMA)
441 enable_tx_dma(ourport);
443 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
444 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
446 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
447 dma->tx_size, DMA_TO_DEVICE);
449 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
450 dma->tx_transfer_addr, dma->tx_size,
451 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
453 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
457 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
458 dma->tx_desc->callback_param = ourport;
459 dma->tx_bytes_requested = dma->tx_size;
461 ourport->tx_in_progress = S3C24XX_TX_DMA;
462 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
463 dma_async_issue_pending(dma->tx_chan);
467 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
469 struct uart_port *port = &ourport->port;
470 struct circ_buf *xmit = &port->state->xmit;
473 /* Get data size up to the end of buffer */
474 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
477 s3c24xx_serial_stop_tx(port);
481 if (!ourport->dma || !ourport->dma->tx_chan ||
482 count < ourport->min_dma_size ||
483 xmit->tail & (dma_get_cache_alignment() - 1))
484 s3c24xx_serial_start_tx_pio(ourport);
486 s3c24xx_serial_start_tx_dma(ourport, count);
489 static void s3c24xx_serial_start_tx(struct uart_port *port)
491 struct s3c24xx_uart_port *ourport = to_ourport(port);
492 struct circ_buf *xmit = &port->state->xmit;
494 if (!ourport->tx_enabled) {
495 if (port->flags & UPF_CONS_FLOW)
496 s3c24xx_serial_rx_disable(port);
498 ourport->tx_enabled = 1;
499 if (!ourport->dma || !ourport->dma->tx_chan)
500 s3c24xx_serial_start_tx_pio(ourport);
503 if (ourport->dma && ourport->dma->tx_chan) {
504 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
505 s3c24xx_serial_start_next_tx(ourport);
509 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
510 struct tty_port *tty, int count)
512 struct s3c24xx_uart_dma *dma = ourport->dma;
518 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
519 dma->rx_size, DMA_FROM_DEVICE);
521 ourport->port.icount.rx += count;
523 dev_err(ourport->port.dev, "No tty port\n");
526 copied = tty_insert_flip_string(tty,
527 ((unsigned char *)(ourport->dma->rx_buf)), count);
528 if (copied != count) {
530 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
534 static void s3c24xx_serial_stop_rx(struct uart_port *port)
536 struct s3c24xx_uart_port *ourport = to_ourport(port);
537 struct s3c24xx_uart_dma *dma = ourport->dma;
538 struct tty_port *t = &port->state->port;
539 struct dma_tx_state state;
540 enum dma_status dma_status;
541 unsigned int received;
543 if (ourport->rx_enabled) {
544 dev_dbg(port->dev, "stopping rx\n");
545 switch (ourport->info->type) {
547 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
551 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
552 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
555 disable_irq_nosync(ourport->rx_irq);
558 ourport->rx_enabled = 0;
560 if (dma && dma->rx_chan) {
561 dmaengine_pause(dma->tx_chan);
562 dma_status = dmaengine_tx_status(dma->rx_chan,
563 dma->rx_cookie, &state);
564 if (dma_status == DMA_IN_PROGRESS ||
565 dma_status == DMA_PAUSED) {
566 received = dma->rx_bytes_requested - state.residue;
567 dmaengine_terminate_all(dma->rx_chan);
568 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
573 static inline struct s3c24xx_uart_info
574 *s3c24xx_port_to_info(struct uart_port *port)
576 return to_ourport(port)->info;
579 static inline struct s3c2410_uartcfg
580 *s3c24xx_port_to_cfg(struct uart_port *port)
582 struct s3c24xx_uart_port *ourport;
584 if (port->dev == NULL)
587 ourport = container_of(port, struct s3c24xx_uart_port, port);
591 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
592 unsigned long ufstat)
594 struct s3c24xx_uart_info *info = ourport->info;
596 if (ufstat & info->rx_fifofull)
597 return ourport->port.fifosize;
599 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
602 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
603 static void s3c24xx_serial_rx_dma_complete(void *args)
605 struct s3c24xx_uart_port *ourport = args;
606 struct uart_port *port = &ourport->port;
608 struct s3c24xx_uart_dma *dma = ourport->dma;
609 struct tty_port *t = &port->state->port;
610 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
612 struct dma_tx_state state;
616 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
617 received = dma->rx_bytes_requested - state.residue;
618 async_tx_ack(dma->rx_desc);
620 spin_lock_irqsave(&port->lock, flags);
623 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
626 tty_flip_buffer_push(t);
630 s3c64xx_start_rx_dma(ourport);
632 spin_unlock_irqrestore(&port->lock, flags);
635 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
637 struct s3c24xx_uart_dma *dma = ourport->dma;
639 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
640 dma->rx_size, DMA_FROM_DEVICE);
642 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
643 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
646 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
650 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
651 dma->rx_desc->callback_param = ourport;
652 dma->rx_bytes_requested = dma->rx_size;
654 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
655 dma_async_issue_pending(dma->rx_chan);
658 /* ? - where has parity gone?? */
659 #define S3C2410_UERSTAT_PARITY (0x1000)
661 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
663 struct uart_port *port = &ourport->port;
666 /* set Rx mode to DMA mode */
667 ucon = rd_regl(port, S3C2410_UCON);
668 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
669 S3C64XX_UCON_TIMEOUT_MASK |
670 S3C64XX_UCON_EMPTYINT_EN |
671 S3C64XX_UCON_DMASUS_EN |
672 S3C64XX_UCON_TIMEOUT_EN |
673 S3C64XX_UCON_RXMODE_MASK);
674 ucon |= S3C64XX_UCON_RXBURST_16 |
675 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
676 S3C64XX_UCON_EMPTYINT_EN |
677 S3C64XX_UCON_TIMEOUT_EN |
678 S3C64XX_UCON_RXMODE_DMA;
679 wr_regl(port, S3C2410_UCON, ucon);
681 ourport->rx_mode = S3C24XX_RX_DMA;
684 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
686 struct uart_port *port = &ourport->port;
689 /* set Rx mode to DMA mode */
690 ucon = rd_regl(port, S3C2410_UCON);
691 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
692 ucon |= S3C64XX_UCON_RXMODE_CPU;
694 /* Apple types use these bits for IRQ masks */
695 if (ourport->info->type != TYPE_APPLE_S5L) {
696 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
697 S3C64XX_UCON_EMPTYINT_EN |
698 S3C64XX_UCON_DMASUS_EN |
699 S3C64XX_UCON_TIMEOUT_EN);
700 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
701 S3C64XX_UCON_TIMEOUT_EN;
703 wr_regl(port, S3C2410_UCON, ucon);
705 ourport->rx_mode = S3C24XX_RX_PIO;
708 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
710 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
712 unsigned int utrstat, received;
713 struct s3c24xx_uart_port *ourport = dev_id;
714 struct uart_port *port = &ourport->port;
715 struct s3c24xx_uart_dma *dma = ourport->dma;
716 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
717 struct tty_port *t = &port->state->port;
718 struct dma_tx_state state;
720 utrstat = rd_regl(port, S3C2410_UTRSTAT);
721 rd_regl(port, S3C2410_UFSTAT);
723 spin_lock(&port->lock);
725 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
726 s3c64xx_start_rx_dma(ourport);
727 if (ourport->rx_mode == S3C24XX_RX_PIO)
728 enable_rx_dma(ourport);
732 if (ourport->rx_mode == S3C24XX_RX_DMA) {
733 dmaengine_pause(dma->rx_chan);
734 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
735 dmaengine_terminate_all(dma->rx_chan);
736 received = dma->rx_bytes_requested - state.residue;
737 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
739 enable_rx_pio(ourport);
742 s3c24xx_serial_rx_drain_fifo(ourport);
745 tty_flip_buffer_push(t);
749 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
752 spin_unlock(&port->lock);
757 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
759 struct uart_port *port = &ourport->port;
760 unsigned int ufcon, ch, flag, ufstat, uerstat;
761 unsigned int fifocnt = 0;
762 int max_count = port->fifosize;
764 while (max_count-- > 0) {
766 * Receive all characters known to be in FIFO
767 * before reading FIFO level again
770 ufstat = rd_regl(port, S3C2410_UFSTAT);
771 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
777 uerstat = rd_regl(port, S3C2410_UERSTAT);
778 ch = rd_reg(port, S3C2410_URXH);
780 if (port->flags & UPF_CONS_FLOW) {
781 int txe = s3c24xx_serial_txempty_nofifo(port);
783 if (ourport->rx_enabled) {
785 ourport->rx_enabled = 0;
790 ufcon = rd_regl(port, S3C2410_UFCON);
791 ufcon |= S3C2410_UFCON_RESETRX;
792 wr_regl(port, S3C2410_UFCON, ufcon);
793 ourport->rx_enabled = 1;
800 /* insert the character into the buffer */
805 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
807 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
810 /* check for break */
811 if (uerstat & S3C2410_UERSTAT_BREAK) {
812 dev_dbg(port->dev, "break!\n");
814 if (uart_handle_break(port))
815 continue; /* Ignore character */
818 if (uerstat & S3C2410_UERSTAT_FRAME)
819 port->icount.frame++;
820 if (uerstat & S3C2410_UERSTAT_OVERRUN)
821 port->icount.overrun++;
823 uerstat &= port->read_status_mask;
825 if (uerstat & S3C2410_UERSTAT_BREAK)
827 else if (uerstat & S3C2410_UERSTAT_PARITY)
829 else if (uerstat & (S3C2410_UERSTAT_FRAME |
830 S3C2410_UERSTAT_OVERRUN))
834 if (uart_handle_sysrq_char(port, ch))
835 continue; /* Ignore character */
837 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
841 tty_flip_buffer_push(&port->state->port);
844 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
846 struct s3c24xx_uart_port *ourport = dev_id;
847 struct uart_port *port = &ourport->port;
849 spin_lock(&port->lock);
850 s3c24xx_serial_rx_drain_fifo(ourport);
851 spin_unlock(&port->lock);
856 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
858 struct s3c24xx_uart_port *ourport = dev_id;
860 if (ourport->dma && ourport->dma->rx_chan)
861 return s3c24xx_serial_rx_chars_dma(dev_id);
862 return s3c24xx_serial_rx_chars_pio(dev_id);
865 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
867 struct uart_port *port = &ourport->port;
868 struct circ_buf *xmit = &port->state->xmit;
869 int count, dma_count = 0;
871 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
873 if (ourport->dma && ourport->dma->tx_chan &&
874 count >= ourport->min_dma_size) {
875 int align = dma_get_cache_alignment() -
876 (xmit->tail & (dma_get_cache_alignment() - 1));
877 if (count - align >= ourport->min_dma_size) {
878 dma_count = count - align;
884 wr_reg(port, S3C2410_UTXH, port->x_char);
890 /* if there isn't anything more to transmit, or the uart is now
891 * stopped, disable the uart and exit
894 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
895 s3c24xx_serial_stop_tx(port);
899 /* try and drain the buffer... */
901 if (count > port->fifosize) {
902 count = port->fifosize;
906 while (!uart_circ_empty(xmit) && count > 0) {
907 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
910 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
911 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
916 if (!count && dma_count) {
917 s3c24xx_serial_start_tx_dma(ourport, dma_count);
921 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
922 spin_unlock(&port->lock);
923 uart_write_wakeup(port);
924 spin_lock(&port->lock);
927 if (uart_circ_empty(xmit))
928 s3c24xx_serial_stop_tx(port);
931 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
933 struct s3c24xx_uart_port *ourport = id;
934 struct uart_port *port = &ourport->port;
936 spin_lock(&port->lock);
938 s3c24xx_serial_tx_chars(ourport);
940 spin_unlock(&port->lock);
944 /* interrupt handler for s3c64xx and later SoC's.*/
945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
947 struct s3c24xx_uart_port *ourport = id;
948 struct uart_port *port = &ourport->port;
949 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
950 irqreturn_t ret = IRQ_HANDLED;
952 if (pend & S3C64XX_UINTM_RXD_MSK) {
953 ret = s3c24xx_serial_rx_irq(irq, id);
954 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
956 if (pend & S3C64XX_UINTM_TXD_MSK) {
957 ret = s3c24xx_serial_tx_irq(irq, id);
958 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
963 /* interrupt handler for Apple SoC's.*/
964 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
966 struct s3c24xx_uart_port *ourport = id;
967 struct uart_port *port = &ourport->port;
968 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
969 irqreturn_t ret = IRQ_NONE;
971 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
972 wr_regl(port, S3C2410_UTRSTAT,
973 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
974 ret = s3c24xx_serial_rx_irq(irq, id);
976 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
977 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
978 ret = s3c24xx_serial_tx_irq(irq, id);
984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
986 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
987 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
988 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
990 if (ufcon & S3C2410_UFCON_FIFOMODE) {
991 if ((ufstat & info->tx_fifomask) != 0 ||
992 (ufstat & info->tx_fifofull))
998 return s3c24xx_serial_txempty_nofifo(port);
1001 /* no modem control lines */
1002 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1004 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1006 if (umstat & S3C2410_UMSTAT_CTS)
1007 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1009 return TIOCM_CAR | TIOCM_DSR;
1012 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1014 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1016 if (mctrl & TIOCM_RTS)
1017 umcon |= S3C2410_UMCOM_RTS_LOW;
1019 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1021 wr_regl(port, S3C2410_UMCON, umcon);
1024 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1026 unsigned long flags;
1029 spin_lock_irqsave(&port->lock, flags);
1031 ucon = rd_regl(port, S3C2410_UCON);
1034 ucon |= S3C2410_UCON_SBREAK;
1036 ucon &= ~S3C2410_UCON_SBREAK;
1038 wr_regl(port, S3C2410_UCON, ucon);
1040 spin_unlock_irqrestore(&port->lock, flags);
1043 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1045 struct s3c24xx_uart_dma *dma = p->dma;
1046 struct dma_slave_caps dma_caps;
1047 const char *reason = NULL;
1050 /* Default slave configuration parameters */
1051 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1052 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1053 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1054 dma->rx_conf.src_maxburst = 1;
1056 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1057 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1058 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1059 dma->tx_conf.dst_maxburst = 1;
1061 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1063 if (IS_ERR(dma->rx_chan)) {
1064 reason = "DMA RX channel request failed";
1065 ret = PTR_ERR(dma->rx_chan);
1069 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1071 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1072 reason = "insufficient DMA RX engine capabilities";
1074 goto err_release_rx;
1077 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1079 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1080 if (IS_ERR(dma->tx_chan)) {
1081 reason = "DMA TX channel request failed";
1082 ret = PTR_ERR(dma->tx_chan);
1083 goto err_release_rx;
1086 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1088 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1089 reason = "insufficient DMA TX engine capabilities";
1091 goto err_release_tx;
1094 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1097 dma->rx_size = PAGE_SIZE;
1099 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1102 goto err_release_tx;
1105 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1106 dma->rx_size, DMA_FROM_DEVICE);
1107 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1108 reason = "DMA mapping error for RX buffer";
1114 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1115 UART_XMIT_SIZE, DMA_TO_DEVICE);
1116 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1117 reason = "DMA mapping error for TX buffer";
1125 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1130 dma_release_channel(dma->tx_chan);
1132 dma_release_channel(dma->rx_chan);
1135 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1139 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1141 struct s3c24xx_uart_dma *dma = p->dma;
1144 dmaengine_terminate_all(dma->rx_chan);
1145 dma_unmap_single(p->port.dev, dma->rx_addr,
1146 dma->rx_size, DMA_FROM_DEVICE);
1148 dma_release_channel(dma->rx_chan);
1149 dma->rx_chan = NULL;
1153 dmaengine_terminate_all(dma->tx_chan);
1154 dma_unmap_single(p->port.dev, dma->tx_addr,
1155 UART_XMIT_SIZE, DMA_TO_DEVICE);
1156 dma_release_channel(dma->tx_chan);
1157 dma->tx_chan = NULL;
1161 static void s3c24xx_serial_shutdown(struct uart_port *port)
1163 struct s3c24xx_uart_port *ourport = to_ourport(port);
1165 if (ourport->tx_claimed) {
1166 free_irq(ourport->tx_irq, ourport);
1167 ourport->tx_enabled = 0;
1168 ourport->tx_claimed = 0;
1169 ourport->tx_mode = 0;
1172 if (ourport->rx_claimed) {
1173 free_irq(ourport->rx_irq, ourport);
1174 ourport->rx_claimed = 0;
1175 ourport->rx_enabled = 0;
1179 s3c24xx_serial_release_dma(ourport);
1181 ourport->tx_in_progress = 0;
1184 static void s3c64xx_serial_shutdown(struct uart_port *port)
1186 struct s3c24xx_uart_port *ourport = to_ourport(port);
1188 ourport->tx_enabled = 0;
1189 ourport->tx_mode = 0;
1190 ourport->rx_enabled = 0;
1192 free_irq(port->irq, ourport);
1194 wr_regl(port, S3C64XX_UINTP, 0xf);
1195 wr_regl(port, S3C64XX_UINTM, 0xf);
1198 s3c24xx_serial_release_dma(ourport);
1200 ourport->tx_in_progress = 0;
1203 static void apple_s5l_serial_shutdown(struct uart_port *port)
1205 struct s3c24xx_uart_port *ourport = to_ourport(port);
1209 ucon = rd_regl(port, S3C2410_UCON);
1210 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1211 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1212 APPLE_S5L_UCON_RXTO_ENA_MSK);
1213 wr_regl(port, S3C2410_UCON, ucon);
1215 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1217 free_irq(port->irq, ourport);
1219 ourport->tx_enabled = 0;
1220 ourport->tx_mode = 0;
1221 ourport->rx_enabled = 0;
1224 s3c24xx_serial_release_dma(ourport);
1226 ourport->tx_in_progress = 0;
1229 static int s3c24xx_serial_startup(struct uart_port *port)
1231 struct s3c24xx_uart_port *ourport = to_ourport(port);
1234 ourport->rx_enabled = 1;
1236 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1237 s3c24xx_serial_portname(port), ourport);
1240 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1244 ourport->rx_claimed = 1;
1246 dev_dbg(port->dev, "requesting tx irq...\n");
1248 ourport->tx_enabled = 1;
1250 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1251 s3c24xx_serial_portname(port), ourport);
1254 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1258 ourport->tx_claimed = 1;
1260 /* the port reset code should have done the correct
1261 * register setup for the port controls
1267 s3c24xx_serial_shutdown(port);
1271 static int s3c64xx_serial_startup(struct uart_port *port)
1273 struct s3c24xx_uart_port *ourport = to_ourport(port);
1274 unsigned long flags;
1278 wr_regl(port, S3C64XX_UINTM, 0xf);
1280 ret = s3c24xx_serial_request_dma(ourport);
1282 devm_kfree(port->dev, ourport->dma);
1283 ourport->dma = NULL;
1287 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1288 s3c24xx_serial_portname(port), ourport);
1290 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1294 /* For compatibility with s3c24xx Soc's */
1295 ourport->rx_enabled = 1;
1296 ourport->tx_enabled = 0;
1298 spin_lock_irqsave(&port->lock, flags);
1300 ufcon = rd_regl(port, S3C2410_UFCON);
1301 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1302 if (!uart_console(port))
1303 ufcon |= S3C2410_UFCON_RESETTX;
1304 wr_regl(port, S3C2410_UFCON, ufcon);
1306 enable_rx_pio(ourport);
1308 spin_unlock_irqrestore(&port->lock, flags);
1310 /* Enable Rx Interrupt */
1311 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1316 static int apple_s5l_serial_startup(struct uart_port *port)
1318 struct s3c24xx_uart_port *ourport = to_ourport(port);
1319 unsigned long flags;
1323 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1325 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1326 s3c24xx_serial_portname(port), ourport);
1328 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1332 /* For compatibility with s3c24xx Soc's */
1333 ourport->rx_enabled = 1;
1334 ourport->tx_enabled = 0;
1336 spin_lock_irqsave(&port->lock, flags);
1338 ufcon = rd_regl(port, S3C2410_UFCON);
1339 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1340 if (!uart_console(port))
1341 ufcon |= S3C2410_UFCON_RESETTX;
1342 wr_regl(port, S3C2410_UFCON, ufcon);
1344 enable_rx_pio(ourport);
1346 spin_unlock_irqrestore(&port->lock, flags);
1348 /* Enable Rx Interrupt */
1349 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1350 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1355 /* power power management control */
1357 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1360 struct s3c24xx_uart_port *ourport = to_ourport(port);
1361 int timeout = 10000;
1363 ourport->pm_level = level;
1367 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1370 if (!IS_ERR(ourport->baudclk))
1371 clk_disable_unprepare(ourport->baudclk);
1373 clk_disable_unprepare(ourport->clk);
1377 clk_prepare_enable(ourport->clk);
1379 if (!IS_ERR(ourport->baudclk))
1380 clk_prepare_enable(ourport->baudclk);
1384 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1388 /* baud rate calculation
1390 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1391 * of different sources, including the peripheral clock ("pclk") and an
1392 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1393 * with a programmable extra divisor.
1395 * The following code goes through the clock sources, and calculates the
1396 * baud clocks (and the resultant actual baud rates) and then tries to
1397 * pick the closest one and select that.
1401 #define MAX_CLK_NAME_LENGTH 15
1403 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1405 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1408 if (info->num_clks == 1)
1411 ucon = rd_regl(port, S3C2410_UCON);
1412 ucon &= info->clksel_mask;
1413 return ucon >> info->clksel_shift;
1416 static void s3c24xx_serial_setsource(struct uart_port *port,
1417 unsigned int clk_sel)
1419 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1422 if (info->num_clks == 1)
1425 ucon = rd_regl(port, S3C2410_UCON);
1426 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1429 ucon &= ~info->clksel_mask;
1430 ucon |= clk_sel << info->clksel_shift;
1431 wr_regl(port, S3C2410_UCON, ucon);
1434 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1435 unsigned int req_baud, struct clk **best_clk,
1436 unsigned int *clk_num)
1438 struct s3c24xx_uart_info *info = ourport->info;
1441 unsigned int cnt, baud, quot, best_quot = 0;
1442 char clkname[MAX_CLK_NAME_LENGTH];
1443 int calc_deviation, deviation = (1 << 30) - 1;
1445 for (cnt = 0; cnt < info->num_clks; cnt++) {
1446 /* Keep selected clock if provided */
1447 if (ourport->cfg->clk_sel &&
1448 !(ourport->cfg->clk_sel & (1 << cnt)))
1451 sprintf(clkname, "clk_uart_baud%d", cnt);
1452 clk = clk_get(ourport->port.dev, clkname);
1456 rate = clk_get_rate(clk);
1460 if (ourport->info->has_divslot) {
1461 unsigned long div = rate / req_baud;
1463 /* The UDIVSLOT register on the newer UARTs allows us to
1464 * get a divisor adjustment of 1/16th on the baud clock.
1466 * We don't keep the UDIVSLOT value (the 16ths we
1467 * calculated by not multiplying the baud by 16) as it
1468 * is easy enough to recalculate.
1474 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1475 baud = rate / (quot * 16);
1479 calc_deviation = req_baud - baud;
1480 if (calc_deviation < 0)
1481 calc_deviation = -calc_deviation;
1483 if (calc_deviation < deviation) {
1487 deviation = calc_deviation;
1496 * This table takes the fractional value of the baud divisor and gives
1497 * the recommended setting for the UDIVSLOT register.
1499 static u16 udivslot_table[16] = {
1518 static void s3c24xx_serial_set_termios(struct uart_port *port,
1519 struct ktermios *termios,
1520 struct ktermios *old)
1522 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1523 struct s3c24xx_uart_port *ourport = to_ourport(port);
1524 struct clk *clk = ERR_PTR(-EINVAL);
1525 unsigned long flags;
1526 unsigned int baud, quot, clk_sel = 0;
1529 unsigned int udivslot = 0;
1532 * We don't support modem control lines.
1534 termios->c_cflag &= ~(HUPCL | CMSPAR);
1535 termios->c_cflag |= CLOCAL;
1538 * Ask the core to calculate the divisor for us.
1541 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1542 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1543 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1544 quot = port->custom_divisor;
1548 /* check to see if we need to change clock source */
1550 if (ourport->baudclk != clk) {
1551 clk_prepare_enable(clk);
1553 s3c24xx_serial_setsource(port, clk_sel);
1555 if (!IS_ERR(ourport->baudclk)) {
1556 clk_disable_unprepare(ourport->baudclk);
1557 ourport->baudclk = ERR_PTR(-EINVAL);
1560 ourport->baudclk = clk;
1561 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1564 if (ourport->info->has_divslot) {
1565 unsigned int div = ourport->baudclk_rate / baud;
1567 if (cfg->has_fracval) {
1568 udivslot = (div & 15);
1569 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1571 udivslot = udivslot_table[div & 15];
1572 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1573 udivslot, div & 15);
1577 switch (termios->c_cflag & CSIZE) {
1579 dev_dbg(port->dev, "config: 5bits/char\n");
1580 ulcon = S3C2410_LCON_CS5;
1583 dev_dbg(port->dev, "config: 6bits/char\n");
1584 ulcon = S3C2410_LCON_CS6;
1587 dev_dbg(port->dev, "config: 7bits/char\n");
1588 ulcon = S3C2410_LCON_CS7;
1592 dev_dbg(port->dev, "config: 8bits/char\n");
1593 ulcon = S3C2410_LCON_CS8;
1597 /* preserve original lcon IR settings */
1598 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1600 if (termios->c_cflag & CSTOPB)
1601 ulcon |= S3C2410_LCON_STOPB;
1603 if (termios->c_cflag & PARENB) {
1604 if (termios->c_cflag & PARODD)
1605 ulcon |= S3C2410_LCON_PODD;
1607 ulcon |= S3C2410_LCON_PEVEN;
1609 ulcon |= S3C2410_LCON_PNONE;
1612 spin_lock_irqsave(&port->lock, flags);
1615 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1616 ulcon, quot, udivslot);
1618 wr_regl(port, S3C2410_ULCON, ulcon);
1619 wr_regl(port, S3C2410_UBRDIV, quot);
1621 port->status &= ~UPSTAT_AUTOCTS;
1623 umcon = rd_regl(port, S3C2410_UMCON);
1624 if (termios->c_cflag & CRTSCTS) {
1625 umcon |= S3C2410_UMCOM_AFC;
1626 /* Disable RTS when RX FIFO contains 63 bytes */
1627 umcon &= ~S3C2412_UMCON_AFC_8;
1628 port->status = UPSTAT_AUTOCTS;
1630 umcon &= ~S3C2410_UMCOM_AFC;
1632 wr_regl(port, S3C2410_UMCON, umcon);
1634 if (ourport->info->has_divslot)
1635 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1638 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1639 rd_regl(port, S3C2410_ULCON),
1640 rd_regl(port, S3C2410_UCON),
1641 rd_regl(port, S3C2410_UFCON));
1644 * Update the per-port timeout.
1646 uart_update_timeout(port, termios->c_cflag, baud);
1649 * Which character status flags are we interested in?
1651 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1652 if (termios->c_iflag & INPCK)
1653 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1654 S3C2410_UERSTAT_PARITY;
1656 * Which character status flags should we ignore?
1658 port->ignore_status_mask = 0;
1659 if (termios->c_iflag & IGNPAR)
1660 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1661 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1662 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1665 * Ignore all characters if CREAD is not set.
1667 if ((termios->c_cflag & CREAD) == 0)
1668 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1670 spin_unlock_irqrestore(&port->lock, flags);
1673 static const char *s3c24xx_serial_type(struct uart_port *port)
1675 struct s3c24xx_uart_port *ourport = to_ourport(port);
1677 switch (ourport->info->type) {
1681 return "S3C6400/10";
1682 case TYPE_APPLE_S5L:
1689 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1691 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1693 if (flags & UART_CONFIG_TYPE)
1694 port->type = info->port_type;
1698 * verify the new serial_struct (for TIOCSSERIAL).
1701 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1703 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1705 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1711 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1713 static struct console s3c24xx_serial_console;
1715 static int __init s3c24xx_serial_console_init(void)
1717 register_console(&s3c24xx_serial_console);
1720 console_initcall(s3c24xx_serial_console_init);
1722 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1724 #define S3C24XX_SERIAL_CONSOLE NULL
1727 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1728 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1729 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1733 static const struct uart_ops s3c24xx_serial_ops = {
1734 .pm = s3c24xx_serial_pm,
1735 .tx_empty = s3c24xx_serial_tx_empty,
1736 .get_mctrl = s3c24xx_serial_get_mctrl,
1737 .set_mctrl = s3c24xx_serial_set_mctrl,
1738 .stop_tx = s3c24xx_serial_stop_tx,
1739 .start_tx = s3c24xx_serial_start_tx,
1740 .stop_rx = s3c24xx_serial_stop_rx,
1741 .break_ctl = s3c24xx_serial_break_ctl,
1742 .startup = s3c24xx_serial_startup,
1743 .shutdown = s3c24xx_serial_shutdown,
1744 .set_termios = s3c24xx_serial_set_termios,
1745 .type = s3c24xx_serial_type,
1746 .config_port = s3c24xx_serial_config_port,
1747 .verify_port = s3c24xx_serial_verify_port,
1748 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1749 .poll_get_char = s3c24xx_serial_get_poll_char,
1750 .poll_put_char = s3c24xx_serial_put_poll_char,
1754 static const struct uart_ops s3c64xx_serial_ops = {
1755 .pm = s3c24xx_serial_pm,
1756 .tx_empty = s3c24xx_serial_tx_empty,
1757 .get_mctrl = s3c24xx_serial_get_mctrl,
1758 .set_mctrl = s3c24xx_serial_set_mctrl,
1759 .stop_tx = s3c24xx_serial_stop_tx,
1760 .start_tx = s3c24xx_serial_start_tx,
1761 .stop_rx = s3c24xx_serial_stop_rx,
1762 .break_ctl = s3c24xx_serial_break_ctl,
1763 .startup = s3c64xx_serial_startup,
1764 .shutdown = s3c64xx_serial_shutdown,
1765 .set_termios = s3c24xx_serial_set_termios,
1766 .type = s3c24xx_serial_type,
1767 .config_port = s3c24xx_serial_config_port,
1768 .verify_port = s3c24xx_serial_verify_port,
1769 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1770 .poll_get_char = s3c24xx_serial_get_poll_char,
1771 .poll_put_char = s3c24xx_serial_put_poll_char,
1775 static const struct uart_ops apple_s5l_serial_ops = {
1776 .pm = s3c24xx_serial_pm,
1777 .tx_empty = s3c24xx_serial_tx_empty,
1778 .get_mctrl = s3c24xx_serial_get_mctrl,
1779 .set_mctrl = s3c24xx_serial_set_mctrl,
1780 .stop_tx = s3c24xx_serial_stop_tx,
1781 .start_tx = s3c24xx_serial_start_tx,
1782 .stop_rx = s3c24xx_serial_stop_rx,
1783 .break_ctl = s3c24xx_serial_break_ctl,
1784 .startup = apple_s5l_serial_startup,
1785 .shutdown = apple_s5l_serial_shutdown,
1786 .set_termios = s3c24xx_serial_set_termios,
1787 .type = s3c24xx_serial_type,
1788 .config_port = s3c24xx_serial_config_port,
1789 .verify_port = s3c24xx_serial_verify_port,
1790 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1791 .poll_get_char = s3c24xx_serial_get_poll_char,
1792 .poll_put_char = s3c24xx_serial_put_poll_char,
1796 static struct uart_driver s3c24xx_uart_drv = {
1797 .owner = THIS_MODULE,
1798 .driver_name = "s3c2410_serial",
1799 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1800 .cons = S3C24XX_SERIAL_CONSOLE,
1801 .dev_name = S3C24XX_SERIAL_NAME,
1802 .major = S3C24XX_SERIAL_MAJOR,
1803 .minor = S3C24XX_SERIAL_MINOR,
1806 #define __PORT_LOCK_UNLOCKED(i) \
1807 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1808 static struct s3c24xx_uart_port
1809 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1812 .lock = __PORT_LOCK_UNLOCKED(0),
1816 .ops = &s3c24xx_serial_ops,
1817 .flags = UPF_BOOT_AUTOCONF,
1823 .lock = __PORT_LOCK_UNLOCKED(1),
1827 .ops = &s3c24xx_serial_ops,
1828 .flags = UPF_BOOT_AUTOCONF,
1832 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1835 .lock = __PORT_LOCK_UNLOCKED(2),
1839 .ops = &s3c24xx_serial_ops,
1840 .flags = UPF_BOOT_AUTOCONF,
1845 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1848 .lock = __PORT_LOCK_UNLOCKED(3),
1852 .ops = &s3c24xx_serial_ops,
1853 .flags = UPF_BOOT_AUTOCONF,
1859 #undef __PORT_LOCK_UNLOCKED
1861 /* s3c24xx_serial_resetport
1863 * reset the fifos and other the settings.
1866 static void s3c24xx_serial_resetport(struct uart_port *port,
1867 struct s3c2410_uartcfg *cfg)
1869 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1870 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1872 ucon &= (info->clksel_mask | info->ucon_mask);
1873 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1875 /* reset both fifos */
1876 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1877 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1879 /* some delay is required after fifo reset */
1883 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1885 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1886 unsigned long val, void *data)
1888 struct s3c24xx_uart_port *port;
1889 struct uart_port *uport;
1891 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1892 uport = &port->port;
1894 /* check to see if port is enabled */
1896 if (port->pm_level != 0)
1899 /* try and work out if the baudrate is changing, we can detect
1900 * a change in rate, but we do not have support for detecting
1901 * a disturbance in the clock-rate over the change.
1904 if (IS_ERR(port->baudclk))
1907 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1910 if (val == CPUFREQ_PRECHANGE) {
1911 /* we should really shut the port down whilst the
1912 * frequency change is in progress.
1915 } else if (val == CPUFREQ_POSTCHANGE) {
1916 struct ktermios *termios;
1917 struct tty_struct *tty;
1919 if (uport->state == NULL)
1922 tty = uport->state->port.tty;
1927 termios = &tty->termios;
1929 if (termios == NULL) {
1930 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1934 s3c24xx_serial_set_termios(uport, termios, NULL);
1942 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1944 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1946 return cpufreq_register_notifier(&port->freq_transition,
1947 CPUFREQ_TRANSITION_NOTIFIER);
1951 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1953 cpufreq_unregister_notifier(&port->freq_transition,
1954 CPUFREQ_TRANSITION_NOTIFIER);
1959 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1965 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1970 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1972 struct device *dev = ourport->port.dev;
1973 struct s3c24xx_uart_info *info = ourport->info;
1974 char clk_name[MAX_CLK_NAME_LENGTH];
1975 unsigned int clk_sel;
1980 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1981 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1982 if (!(clk_sel & (1 << clk_num)))
1985 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1986 clk = clk_get(dev, clk_name);
1990 ret = clk_prepare_enable(clk);
1996 ourport->baudclk = clk;
1997 ourport->baudclk_rate = clk_get_rate(clk);
1998 s3c24xx_serial_setsource(&ourport->port, clk_num);
2006 /* s3c24xx_serial_init_port
2008 * initialise a single serial port from the platform device given
2011 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
2012 struct platform_device *platdev)
2014 struct uart_port *port = &ourport->port;
2015 struct s3c2410_uartcfg *cfg = ourport->cfg;
2016 struct resource *res;
2019 if (platdev == NULL)
2022 if (port->mapbase != 0)
2025 /* setup info for port */
2026 port->dev = &platdev->dev;
2030 if (cfg->uart_flags & UPF_CONS_FLOW) {
2031 dev_dbg(port->dev, "enabling flow control\n");
2032 port->flags |= UPF_CONS_FLOW;
2035 /* sort our the physical and virtual addresses for each UART */
2037 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2039 dev_err(port->dev, "failed to find memory resource for uart\n");
2043 dev_dbg(port->dev, "resource %pR)\n", res);
2045 port->membase = devm_ioremap_resource(port->dev, res);
2046 if (IS_ERR(port->membase)) {
2047 dev_err(port->dev, "failed to remap controller address\n");
2051 port->mapbase = res->start;
2052 ret = platform_get_irq(platdev, 0);
2057 ourport->rx_irq = ret;
2058 ourport->tx_irq = ret + 1;
2061 switch (ourport->info->type) {
2063 ret = platform_get_irq(platdev, 1);
2065 ourport->tx_irq = ret;
2072 * DMA is currently supported only on DT platforms, if DMA properties
2075 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2077 ourport->dma = devm_kzalloc(port->dev,
2078 sizeof(*ourport->dma),
2080 if (!ourport->dma) {
2086 ourport->clk = clk_get(&platdev->dev, "uart");
2087 if (IS_ERR(ourport->clk)) {
2088 pr_err("%s: Controller clock not found\n",
2089 dev_name(&platdev->dev));
2090 ret = PTR_ERR(ourport->clk);
2094 ret = clk_prepare_enable(ourport->clk);
2096 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2097 clk_put(ourport->clk);
2101 ret = s3c24xx_serial_enable_baudclk(ourport);
2103 pr_warn("uart: failed to enable baudclk\n");
2105 /* Keep all interrupts masked and cleared */
2106 switch (ourport->info->type) {
2108 wr_regl(port, S3C64XX_UINTM, 0xf);
2109 wr_regl(port, S3C64XX_UINTP, 0xf);
2110 wr_regl(port, S3C64XX_UINTSP, 0xf);
2112 case TYPE_APPLE_S5L: {
2115 ucon = rd_regl(port, S3C2410_UCON);
2116 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2117 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2118 APPLE_S5L_UCON_RXTO_ENA_MSK);
2119 wr_regl(port, S3C2410_UCON, ucon);
2121 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2128 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2129 &port->mapbase, port->membase, port->irq,
2130 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2132 /* reset the fifos (and setup the uart) */
2133 s3c24xx_serial_resetport(port, cfg);
2142 /* Device driver serial port probe */
2145 static const struct of_device_id s3c24xx_uart_dt_match[];
2148 static int probe_index;
2150 static inline struct s3c24xx_serial_drv_data *
2151 s3c24xx_get_driver_data(struct platform_device *pdev)
2154 if (pdev->dev.of_node) {
2155 const struct of_device_id *match;
2157 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
2158 return (struct s3c24xx_serial_drv_data *)match->data;
2161 return (struct s3c24xx_serial_drv_data *)
2162 platform_get_device_id(pdev)->driver_data;
2165 static int s3c24xx_serial_probe(struct platform_device *pdev)
2167 struct device_node *np = pdev->dev.of_node;
2168 struct s3c24xx_uart_port *ourport;
2169 int index = probe_index;
2173 ret = of_alias_get_id(np, "serial");
2178 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2179 dev_err(&pdev->dev, "serial%d out of range\n", index);
2182 ourport = &s3c24xx_serial_ports[index];
2184 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2185 if (!ourport->drv_data) {
2186 dev_err(&pdev->dev, "could not find driver data\n");
2190 ourport->baudclk = ERR_PTR(-EINVAL);
2191 ourport->info = ourport->drv_data->info;
2192 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2193 dev_get_platdata(&pdev->dev) :
2194 ourport->drv_data->def_cfg;
2196 switch (ourport->info->type) {
2198 ourport->port.ops = &s3c24xx_serial_ops;
2201 ourport->port.ops = &s3c64xx_serial_ops;
2203 case TYPE_APPLE_S5L:
2204 ourport->port.ops = &apple_s5l_serial_ops;
2209 of_property_read_u32(np,
2210 "samsung,uart-fifosize", &ourport->port.fifosize);
2212 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2215 ourport->port.iotype = UPIO_MEM;
2218 ourport->port.iotype = UPIO_MEM32;
2221 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2228 if (ourport->drv_data->fifosize[index])
2229 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2230 else if (ourport->info->fifosize)
2231 ourport->port.fifosize = ourport->info->fifosize;
2232 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2235 * DMA transfers must be aligned at least to cache line size,
2236 * so find minimal transfer size suitable for DMA mode
2238 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2239 dma_get_cache_alignment());
2241 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2243 ret = s3c24xx_serial_init_port(ourport, pdev);
2247 if (!s3c24xx_uart_drv.state) {
2248 ret = uart_register_driver(&s3c24xx_uart_drv);
2250 pr_err("Failed to register Samsung UART driver\n");
2255 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2256 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2257 platform_set_drvdata(pdev, &ourport->port);
2260 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2261 * so that a potential re-enablement through the pm-callback overlaps
2262 * and keeps the clock enabled in this case.
2264 clk_disable_unprepare(ourport->clk);
2265 if (!IS_ERR(ourport->baudclk))
2266 clk_disable_unprepare(ourport->baudclk);
2268 ret = s3c24xx_serial_cpufreq_register(ourport);
2270 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2277 static int s3c24xx_serial_remove(struct platform_device *dev)
2279 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2282 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2283 uart_remove_one_port(&s3c24xx_uart_drv, port);
2286 uart_unregister_driver(&s3c24xx_uart_drv);
2291 /* UART power management code */
2292 #ifdef CONFIG_PM_SLEEP
2293 static int s3c24xx_serial_suspend(struct device *dev)
2295 struct uart_port *port = s3c24xx_dev_to_port(dev);
2298 uart_suspend_port(&s3c24xx_uart_drv, port);
2303 static int s3c24xx_serial_resume(struct device *dev)
2305 struct uart_port *port = s3c24xx_dev_to_port(dev);
2306 struct s3c24xx_uart_port *ourport = to_ourport(port);
2309 clk_prepare_enable(ourport->clk);
2310 if (!IS_ERR(ourport->baudclk))
2311 clk_prepare_enable(ourport->baudclk);
2312 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2313 if (!IS_ERR(ourport->baudclk))
2314 clk_disable_unprepare(ourport->baudclk);
2315 clk_disable_unprepare(ourport->clk);
2317 uart_resume_port(&s3c24xx_uart_drv, port);
2323 static int s3c24xx_serial_resume_noirq(struct device *dev)
2325 struct uart_port *port = s3c24xx_dev_to_port(dev);
2326 struct s3c24xx_uart_port *ourport = to_ourport(port);
2329 /* restore IRQ mask */
2330 switch (ourport->info->type) {
2331 case TYPE_S3C6400: {
2332 unsigned int uintm = 0xf;
2334 if (ourport->tx_enabled)
2335 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2336 if (ourport->rx_enabled)
2337 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2338 clk_prepare_enable(ourport->clk);
2339 if (!IS_ERR(ourport->baudclk))
2340 clk_prepare_enable(ourport->baudclk);
2341 wr_regl(port, S3C64XX_UINTM, uintm);
2342 if (!IS_ERR(ourport->baudclk))
2343 clk_disable_unprepare(ourport->baudclk);
2344 clk_disable_unprepare(ourport->clk);
2347 case TYPE_APPLE_S5L: {
2351 ret = clk_prepare_enable(ourport->clk);
2353 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2356 if (!IS_ERR(ourport->baudclk)) {
2357 ret = clk_prepare_enable(ourport->baudclk);
2359 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2360 clk_disable_unprepare(ourport->clk);
2365 ucon = rd_regl(port, S3C2410_UCON);
2367 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2368 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2369 APPLE_S5L_UCON_RXTO_ENA_MSK);
2371 if (ourport->tx_enabled)
2372 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2373 if (ourport->rx_enabled)
2374 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2375 APPLE_S5L_UCON_RXTO_ENA_MSK;
2377 wr_regl(port, S3C2410_UCON, ucon);
2379 if (!IS_ERR(ourport->baudclk))
2380 clk_disable_unprepare(ourport->baudclk);
2381 clk_disable_unprepare(ourport->clk);
2392 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2393 .suspend = s3c24xx_serial_suspend,
2394 .resume = s3c24xx_serial_resume,
2395 .resume_noirq = s3c24xx_serial_resume_noirq,
2397 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2399 #else /* !CONFIG_PM_SLEEP */
2401 #define SERIAL_SAMSUNG_PM_OPS NULL
2402 #endif /* CONFIG_PM_SLEEP */
2406 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2408 static struct uart_port *cons_uart;
2411 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2413 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2414 unsigned long ufstat, utrstat;
2416 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2417 /* fifo mode - check amount of data in fifo registers... */
2419 ufstat = rd_regl(port, S3C2410_UFSTAT);
2420 return (ufstat & info->tx_fifofull) ? 0 : 1;
2423 /* in non-fifo mode, we go and use the tx buffer empty */
2425 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2426 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2430 s3c24xx_port_configured(unsigned int ucon)
2432 /* consider the serial port configured if the tx/rx mode set */
2433 return (ucon & 0xf) != 0;
2436 #ifdef CONFIG_CONSOLE_POLL
2438 * Console polling routines for writing and reading from the uart while
2439 * in an interrupt or debug context.
2442 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2444 struct s3c24xx_uart_port *ourport = to_ourport(port);
2445 unsigned int ufstat;
2447 ufstat = rd_regl(port, S3C2410_UFSTAT);
2448 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2449 return NO_POLL_CHAR;
2451 return rd_reg(port, S3C2410_URXH);
2454 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2457 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2458 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2460 /* not possible to xmit on unconfigured port */
2461 if (!s3c24xx_port_configured(ucon))
2464 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2466 wr_reg(port, S3C2410_UTXH, c);
2469 #endif /* CONFIG_CONSOLE_POLL */
2472 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2474 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2476 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2478 wr_reg(port, S3C2410_UTXH, ch);
2482 s3c24xx_serial_console_write(struct console *co, const char *s,
2485 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2487 /* not possible to xmit on unconfigured port */
2488 if (!s3c24xx_port_configured(ucon))
2491 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2495 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2496 int *parity, int *bits)
2501 unsigned int ubrdiv;
2503 unsigned int clk_sel;
2504 char clk_name[MAX_CLK_NAME_LENGTH];
2506 ulcon = rd_regl(port, S3C2410_ULCON);
2507 ucon = rd_regl(port, S3C2410_UCON);
2508 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2510 if (s3c24xx_port_configured(ucon)) {
2511 switch (ulcon & S3C2410_LCON_CSMASK) {
2512 case S3C2410_LCON_CS5:
2515 case S3C2410_LCON_CS6:
2518 case S3C2410_LCON_CS7:
2521 case S3C2410_LCON_CS8:
2527 switch (ulcon & S3C2410_LCON_PMASK) {
2528 case S3C2410_LCON_PEVEN:
2532 case S3C2410_LCON_PODD:
2536 case S3C2410_LCON_PNONE:
2541 /* now calculate the baud rate */
2543 clk_sel = s3c24xx_serial_getsource(port);
2544 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2546 clk = clk_get(port->dev, clk_name);
2548 rate = clk_get_rate(clk);
2552 *baud = rate / (16 * (ubrdiv + 1));
2553 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2558 s3c24xx_serial_console_setup(struct console *co, char *options)
2560 struct uart_port *port;
2566 /* is this a valid port */
2568 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2571 port = &s3c24xx_serial_ports[co->index].port;
2573 /* is the port configured? */
2575 if (port->mapbase == 0x0)
2581 * Check whether an invalid uart number has been specified, and
2582 * if so, search for the first available port that does have
2586 uart_parse_options(options, &baud, &parity, &bits, &flow);
2588 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2590 dev_dbg(port->dev, "baud %d\n", baud);
2592 return uart_set_options(port, co, baud, parity, bits, flow);
2595 static struct console s3c24xx_serial_console = {
2596 .name = S3C24XX_SERIAL_NAME,
2597 .device = uart_console_device,
2598 .flags = CON_PRINTBUFFER,
2600 .write = s3c24xx_serial_console_write,
2601 .setup = s3c24xx_serial_console_setup,
2602 .data = &s3c24xx_uart_drv,
2604 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2606 #ifdef CONFIG_CPU_S3C2410
2607 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2608 .info = &(struct s3c24xx_uart_info) {
2609 .name = "Samsung S3C2410 UART",
2610 .type = TYPE_S3C24XX,
2611 .port_type = PORT_S3C2410,
2613 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2614 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2615 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2616 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2617 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2618 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2619 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2621 .clksel_mask = S3C2410_UCON_CLKMASK,
2622 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2624 .def_cfg = &(struct s3c2410_uartcfg) {
2625 .ucon = S3C2410_UCON_DEFAULT,
2626 .ufcon = S3C2410_UFCON_DEFAULT,
2629 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2631 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2634 #ifdef CONFIG_CPU_S3C2412
2635 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2636 .info = &(struct s3c24xx_uart_info) {
2637 .name = "Samsung S3C2412 UART",
2638 .type = TYPE_S3C24XX,
2639 .port_type = PORT_S3C2412,
2642 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2643 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2644 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2645 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2646 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2647 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2648 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2650 .clksel_mask = S3C2412_UCON_CLKMASK,
2651 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2653 .def_cfg = &(struct s3c2410_uartcfg) {
2654 .ucon = S3C2410_UCON_DEFAULT,
2655 .ufcon = S3C2410_UFCON_DEFAULT,
2658 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2660 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2663 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2664 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2665 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2666 .info = &(struct s3c24xx_uart_info) {
2667 .name = "Samsung S3C2440 UART",
2668 .type = TYPE_S3C24XX,
2669 .port_type = PORT_S3C2440,
2672 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2673 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2674 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2675 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2676 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2677 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2678 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2680 .clksel_mask = S3C2412_UCON_CLKMASK,
2681 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2682 .ucon_mask = S3C2440_UCON0_DIVMASK,
2684 .def_cfg = &(struct s3c2410_uartcfg) {
2685 .ucon = S3C2410_UCON_DEFAULT,
2686 .ufcon = S3C2410_UFCON_DEFAULT,
2689 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2691 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2694 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2695 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2696 .info = &(struct s3c24xx_uart_info) {
2697 .name = "Samsung S3C6400 UART",
2698 .type = TYPE_S3C6400,
2699 .port_type = PORT_S3C6400,
2702 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2703 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2704 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2705 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2706 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2707 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2708 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2710 .clksel_mask = S3C6400_UCON_CLKMASK,
2711 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2713 .def_cfg = &(struct s3c2410_uartcfg) {
2714 .ucon = S3C2410_UCON_DEFAULT,
2715 .ufcon = S3C2410_UFCON_DEFAULT,
2718 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2720 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2723 #ifdef CONFIG_CPU_S5PV210
2724 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2725 .info = &(struct s3c24xx_uart_info) {
2726 .name = "Samsung S5PV210 UART",
2727 .type = TYPE_S3C6400,
2728 .port_type = PORT_S3C6400,
2730 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2731 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2732 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2733 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2734 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2735 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2736 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2738 .clksel_mask = S5PV210_UCON_CLKMASK,
2739 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2741 .def_cfg = &(struct s3c2410_uartcfg) {
2742 .ucon = S5PV210_UCON_DEFAULT,
2743 .ufcon = S5PV210_UFCON_DEFAULT,
2745 .fifosize = { 256, 64, 16, 16 },
2747 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2749 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2752 #if defined(CONFIG_ARCH_EXYNOS)
2753 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2754 .info = &(struct s3c24xx_uart_info) { \
2755 .name = "Samsung Exynos UART", \
2756 .type = TYPE_S3C6400, \
2757 .port_type = PORT_S3C6400, \
2759 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2760 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2761 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2762 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2763 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2764 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2765 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2768 .clksel_shift = 0, \
2770 .def_cfg = &(struct s3c2410_uartcfg) { \
2771 .ucon = S5PV210_UCON_DEFAULT, \
2772 .ufcon = S5PV210_UFCON_DEFAULT, \
2776 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2777 EXYNOS_COMMON_SERIAL_DRV_DATA,
2778 .fifosize = { 256, 64, 16, 16 },
2781 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2782 EXYNOS_COMMON_SERIAL_DRV_DATA,
2783 .fifosize = { 64, 256, 16, 256 },
2786 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2787 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2789 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2790 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2793 #ifdef CONFIG_ARCH_APPLE
2794 static struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2795 .info = &(struct s3c24xx_uart_info) {
2796 .name = "Apple S5L UART",
2797 .type = TYPE_APPLE_S5L,
2798 .port_type = PORT_8250,
2800 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2801 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2802 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2803 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2804 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2805 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2806 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2811 .def_cfg = &(struct s3c2410_uartcfg) {
2812 .ucon = APPLE_S5L_UCON_DEFAULT,
2813 .ufcon = S3C2410_UFCON_DEFAULT,
2816 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)&s5l_serial_drv_data)
2818 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2821 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2823 .name = "s3c2410-uart",
2824 .driver_data = S3C2410_SERIAL_DRV_DATA,
2826 .name = "s3c2412-uart",
2827 .driver_data = S3C2412_SERIAL_DRV_DATA,
2829 .name = "s3c2440-uart",
2830 .driver_data = S3C2440_SERIAL_DRV_DATA,
2832 .name = "s3c6400-uart",
2833 .driver_data = S3C6400_SERIAL_DRV_DATA,
2835 .name = "s5pv210-uart",
2836 .driver_data = S5PV210_SERIAL_DRV_DATA,
2838 .name = "exynos4210-uart",
2839 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2841 .name = "exynos5433-uart",
2842 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2845 .driver_data = S5L_SERIAL_DRV_DATA,
2849 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2852 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2853 { .compatible = "samsung,s3c2410-uart",
2854 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2855 { .compatible = "samsung,s3c2412-uart",
2856 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2857 { .compatible = "samsung,s3c2440-uart",
2858 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2859 { .compatible = "samsung,s3c6400-uart",
2860 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2861 { .compatible = "samsung,s5pv210-uart",
2862 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2863 { .compatible = "samsung,exynos4210-uart",
2864 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2865 { .compatible = "samsung,exynos5433-uart",
2866 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2867 { .compatible = "apple,s5l-uart",
2868 .data = (void *)S5L_SERIAL_DRV_DATA },
2871 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2874 static struct platform_driver samsung_serial_driver = {
2875 .probe = s3c24xx_serial_probe,
2876 .remove = s3c24xx_serial_remove,
2877 .id_table = s3c24xx_serial_driver_ids,
2879 .name = "samsung-uart",
2880 .pm = SERIAL_SAMSUNG_PM_OPS,
2881 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2885 module_platform_driver(samsung_serial_driver);
2887 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2892 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2894 switch (port->iotype) {
2896 writeb(val, portaddr(port, reg));
2899 writel(val, portaddr(port, reg));
2904 struct samsung_early_console_data {
2908 static void samsung_early_busyuart(struct uart_port *port)
2910 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2914 static void samsung_early_busyuart_fifo(struct uart_port *port)
2916 struct samsung_early_console_data *data = port->private_data;
2918 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2922 static void samsung_early_putc(struct uart_port *port, int c)
2924 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2925 samsung_early_busyuart_fifo(port);
2927 samsung_early_busyuart(port);
2929 wr_reg_barrier(port, S3C2410_UTXH, c);
2932 static void samsung_early_write(struct console *con, const char *s,
2935 struct earlycon_device *dev = con->data;
2937 uart_console_write(&dev->port, s, n, samsung_early_putc);
2940 static int __init samsung_early_console_setup(struct earlycon_device *device,
2943 if (!device->port.membase)
2946 device->con->write = samsung_early_write;
2951 static struct samsung_early_console_data s3c2410_early_console_data = {
2952 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2955 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2958 device->port.private_data = &s3c2410_early_console_data;
2959 return samsung_early_console_setup(device, opt);
2962 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2963 s3c2410_early_console_setup);
2965 /* S3C2412, S3C2440, S3C64xx */
2966 static struct samsung_early_console_data s3c2440_early_console_data = {
2967 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2970 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2973 device->port.private_data = &s3c2440_early_console_data;
2974 return samsung_early_console_setup(device, opt);
2977 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2978 s3c2440_early_console_setup);
2979 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2980 s3c2440_early_console_setup);
2981 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2982 s3c2440_early_console_setup);
2984 /* S5PV210, Exynos */
2985 static struct samsung_early_console_data s5pv210_early_console_data = {
2986 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2989 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2992 device->port.private_data = &s5pv210_early_console_data;
2993 return samsung_early_console_setup(device, opt);
2996 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2997 s5pv210_early_console_setup);
2998 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2999 s5pv210_early_console_setup);
3002 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3005 /* Close enough to S3C2410 for earlycon... */
3006 device->port.private_data = &s3c2410_early_console_data;
3009 /* ... but we need to override the existing fixmap entry as nGnRnE */
3010 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3011 __pgprot(PROT_DEVICE_nGnRnE));
3013 return samsung_early_console_setup(device, opt);
3016 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3019 MODULE_ALIAS("platform:samsung-uart");
3020 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3021 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3022 MODULE_LICENSE("GPL v2");