1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for SA11x0 serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14 #include <linux/module.h>
15 #include <linux/ioport.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/platform_data/sa11x0-serial.h>
20 #include <linux/platform_device.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
28 #include <mach/hardware.h>
29 #include <mach/irqs.h>
31 #include "serial_mctrl_gpio.h"
33 /* We've been assigned a range on the "Low-density serial ports" major */
34 #define SERIAL_SA1100_MAJOR 204
39 #define SA1100_ISR_PASS_LIMIT 256
42 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
44 #define SM_TO_UTSR0(x) ((x) & 0xff)
45 #define SM_TO_UTSR1(x) ((x) >> 8)
46 #define UTSR0_TO_SM(x) ((x))
47 #define UTSR1_TO_SM(x) ((x) << 8)
49 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
50 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
51 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
52 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
53 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
54 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
55 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
57 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
58 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
59 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
60 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
61 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
62 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
63 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
66 * This is the size of our serial port register set.
68 #define UART_PORT_SIZE 0x24
71 * This determines how often we check the modem status signals
72 * for any change. They generally aren't connected to an IRQ
73 * so we have to poll them. We also check immediately before
74 * filling the TX fifo incase CTS has been dropped.
76 #define MCTRL_TIMEOUT (250*HZ/1000)
79 struct uart_port port;
80 struct timer_list timer;
81 unsigned int old_status;
82 struct mctrl_gpios *gpios;
86 * Handle any change of modem status signal since we were last called.
88 static void sa1100_mctrl_check(struct sa1100_port *sport)
90 unsigned int status, changed;
92 status = sport->port.ops->get_mctrl(&sport->port);
93 changed = status ^ sport->old_status;
98 sport->old_status = status;
100 if (changed & TIOCM_RI)
101 sport->port.icount.rng++;
102 if (changed & TIOCM_DSR)
103 sport->port.icount.dsr++;
104 if (changed & TIOCM_CAR)
105 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
106 if (changed & TIOCM_CTS)
107 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
109 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
113 * This is our per-port timeout handler, for checking the
114 * modem status signals.
116 static void sa1100_timeout(struct timer_list *t)
118 struct sa1100_port *sport = from_timer(sport, t, timer);
121 if (sport->port.state) {
122 spin_lock_irqsave(&sport->port.lock, flags);
123 sa1100_mctrl_check(sport);
124 spin_unlock_irqrestore(&sport->port.lock, flags);
126 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
131 * interrupts disabled on entry
133 static void sa1100_stop_tx(struct uart_port *port)
135 struct sa1100_port *sport =
136 container_of(port, struct sa1100_port, port);
139 utcr3 = UART_GET_UTCR3(sport);
140 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
141 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
145 * port locked and interrupts disabled
147 static void sa1100_start_tx(struct uart_port *port)
149 struct sa1100_port *sport =
150 container_of(port, struct sa1100_port, port);
153 utcr3 = UART_GET_UTCR3(sport);
154 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
155 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
161 static void sa1100_stop_rx(struct uart_port *port)
163 struct sa1100_port *sport =
164 container_of(port, struct sa1100_port, port);
167 utcr3 = UART_GET_UTCR3(sport);
168 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
172 * Set the modem control timer to fire immediately.
174 static void sa1100_enable_ms(struct uart_port *port)
176 struct sa1100_port *sport =
177 container_of(port, struct sa1100_port, port);
179 mod_timer(&sport->timer, jiffies);
181 mctrl_gpio_enable_ms(sport->gpios);
185 sa1100_rx_chars(struct sa1100_port *sport)
187 unsigned int status, ch, flg;
189 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
190 UTSR0_TO_SM(UART_GET_UTSR0(sport));
191 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
192 ch = UART_GET_CHAR(sport);
194 sport->port.icount.rx++;
199 * note that the error handling code is
200 * out of the main execution path
202 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
203 if (status & UTSR1_TO_SM(UTSR1_PRE))
204 sport->port.icount.parity++;
205 else if (status & UTSR1_TO_SM(UTSR1_FRE))
206 sport->port.icount.frame++;
207 if (status & UTSR1_TO_SM(UTSR1_ROR))
208 sport->port.icount.overrun++;
210 status &= sport->port.read_status_mask;
212 if (status & UTSR1_TO_SM(UTSR1_PRE))
214 else if (status & UTSR1_TO_SM(UTSR1_FRE))
218 sport->port.sysrq = 0;
222 if (uart_handle_sysrq_char(&sport->port, ch))
225 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
228 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
229 UTSR0_TO_SM(UART_GET_UTSR0(sport));
232 spin_unlock(&sport->port.lock);
233 tty_flip_buffer_push(&sport->port.state->port);
234 spin_lock(&sport->port.lock);
237 static void sa1100_tx_chars(struct sa1100_port *sport)
239 struct circ_buf *xmit = &sport->port.state->xmit;
241 if (sport->port.x_char) {
242 UART_PUT_CHAR(sport, sport->port.x_char);
243 sport->port.icount.tx++;
244 sport->port.x_char = 0;
249 * Check the modem control lines before
250 * transmitting anything.
252 sa1100_mctrl_check(sport);
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
255 sa1100_stop_tx(&sport->port);
260 * Tried using FIFO (not checking TNF) for fifo fill:
261 * still had the '4 bytes repeated' problem.
263 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
264 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
265 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
266 sport->port.icount.tx++;
267 if (uart_circ_empty(xmit))
271 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
272 uart_write_wakeup(&sport->port);
274 if (uart_circ_empty(xmit))
275 sa1100_stop_tx(&sport->port);
278 static irqreturn_t sa1100_int(int irq, void *dev_id)
280 struct sa1100_port *sport = dev_id;
281 unsigned int status, pass_counter = 0;
283 spin_lock(&sport->port.lock);
284 status = UART_GET_UTSR0(sport);
285 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
287 if (status & (UTSR0_RFS | UTSR0_RID)) {
288 /* Clear the receiver idle bit, if set */
289 if (status & UTSR0_RID)
290 UART_PUT_UTSR0(sport, UTSR0_RID);
291 sa1100_rx_chars(sport);
294 /* Clear the relevant break bits */
295 if (status & (UTSR0_RBB | UTSR0_REB))
296 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
298 if (status & UTSR0_RBB)
299 sport->port.icount.brk++;
301 if (status & UTSR0_REB)
302 uart_handle_break(&sport->port);
304 if (status & UTSR0_TFS)
305 sa1100_tx_chars(sport);
306 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
308 status = UART_GET_UTSR0(sport);
309 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
311 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
312 spin_unlock(&sport->port.lock);
318 * Return TIOCSER_TEMT when transmitter is not busy.
320 static unsigned int sa1100_tx_empty(struct uart_port *port)
322 struct sa1100_port *sport =
323 container_of(port, struct sa1100_port, port);
325 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
328 static unsigned int sa1100_get_mctrl(struct uart_port *port)
330 struct sa1100_port *sport =
331 container_of(port, struct sa1100_port, port);
332 int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
334 mctrl_gpio_get(sport->gpios, &ret);
339 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
341 struct sa1100_port *sport =
342 container_of(port, struct sa1100_port, port);
344 mctrl_gpio_set(sport->gpios, mctrl);
348 * Interrupts always disabled.
350 static void sa1100_break_ctl(struct uart_port *port, int break_state)
352 struct sa1100_port *sport =
353 container_of(port, struct sa1100_port, port);
357 spin_lock_irqsave(&sport->port.lock, flags);
358 utcr3 = UART_GET_UTCR3(sport);
359 if (break_state == -1)
363 UART_PUT_UTCR3(sport, utcr3);
364 spin_unlock_irqrestore(&sport->port.lock, flags);
367 static int sa1100_startup(struct uart_port *port)
369 struct sa1100_port *sport =
370 container_of(port, struct sa1100_port, port);
376 retval = request_irq(sport->port.irq, sa1100_int, 0,
377 "sa11x0-uart", sport);
382 * Finally, clear and enable interrupts
384 UART_PUT_UTSR0(sport, -1);
385 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
388 * Enable modem status interrupts
390 spin_lock_irq(&sport->port.lock);
391 sa1100_enable_ms(&sport->port);
392 spin_unlock_irq(&sport->port.lock);
397 static void sa1100_shutdown(struct uart_port *port)
399 struct sa1100_port *sport =
400 container_of(port, struct sa1100_port, port);
405 del_timer_sync(&sport->timer);
410 free_irq(sport->port.irq, sport);
413 * Disable all interrupts, port and break condition.
415 UART_PUT_UTCR3(sport, 0);
419 sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
420 struct ktermios *old)
422 struct sa1100_port *sport =
423 container_of(port, struct sa1100_port, port);
425 unsigned int utcr0, old_utcr3, baud, quot;
426 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
429 * We only support CS7 and CS8.
431 while ((termios->c_cflag & CSIZE) != CS7 &&
432 (termios->c_cflag & CSIZE) != CS8) {
433 termios->c_cflag &= ~CSIZE;
434 termios->c_cflag |= old_csize;
438 if ((termios->c_cflag & CSIZE) == CS8)
443 if (termios->c_cflag & CSTOPB)
445 if (termios->c_cflag & PARENB) {
447 if (!(termios->c_cflag & PARODD))
452 * Ask the core to calculate the divisor for us.
454 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
455 quot = uart_get_divisor(port, baud);
457 spin_lock_irqsave(&sport->port.lock, flags);
459 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
460 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
461 if (termios->c_iflag & INPCK)
462 sport->port.read_status_mask |=
463 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
464 if (termios->c_iflag & (BRKINT | PARMRK))
465 sport->port.read_status_mask |=
466 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
469 * Characters to ignore
471 sport->port.ignore_status_mask = 0;
472 if (termios->c_iflag & IGNPAR)
473 sport->port.ignore_status_mask |=
474 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
475 if (termios->c_iflag & IGNBRK) {
476 sport->port.ignore_status_mask |=
477 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
479 * If we're ignoring parity and break indicators,
480 * ignore overruns too (for real raw support).
482 if (termios->c_iflag & IGNPAR)
483 sport->port.ignore_status_mask |=
484 UTSR1_TO_SM(UTSR1_ROR);
487 del_timer_sync(&sport->timer);
490 * Update the per-port timeout.
492 uart_update_timeout(port, termios->c_cflag, baud);
495 * disable interrupts and drain transmitter
497 old_utcr3 = UART_GET_UTCR3(sport);
498 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
500 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
503 /* then, disable everything */
504 UART_PUT_UTCR3(sport, 0);
506 /* set the parity, stop bits and data size */
507 UART_PUT_UTCR0(sport, utcr0);
509 /* set the baud rate */
511 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
512 UART_PUT_UTCR2(sport, (quot & 0xff));
514 UART_PUT_UTSR0(sport, -1);
516 UART_PUT_UTCR3(sport, old_utcr3);
518 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
519 sa1100_enable_ms(&sport->port);
521 spin_unlock_irqrestore(&sport->port.lock, flags);
524 static const char *sa1100_type(struct uart_port *port)
526 struct sa1100_port *sport =
527 container_of(port, struct sa1100_port, port);
529 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
533 * Release the memory region(s) being used by 'port'.
535 static void sa1100_release_port(struct uart_port *port)
537 struct sa1100_port *sport =
538 container_of(port, struct sa1100_port, port);
540 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
544 * Request the memory region(s) being used by 'port'.
546 static int sa1100_request_port(struct uart_port *port)
548 struct sa1100_port *sport =
549 container_of(port, struct sa1100_port, port);
551 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
552 "sa11x0-uart") != NULL ? 0 : -EBUSY;
556 * Configure/autoconfigure the port.
558 static void sa1100_config_port(struct uart_port *port, int flags)
560 struct sa1100_port *sport =
561 container_of(port, struct sa1100_port, port);
563 if (flags & UART_CONFIG_TYPE &&
564 sa1100_request_port(&sport->port) == 0)
565 sport->port.type = PORT_SA1100;
569 * Verify the new serial_struct (for TIOCSSERIAL).
570 * The only change we allow are to the flags and type, and
571 * even then only between PORT_SA1100 and PORT_UNKNOWN
574 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
576 struct sa1100_port *sport =
577 container_of(port, struct sa1100_port, port);
580 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
582 if (sport->port.irq != ser->irq)
584 if (ser->io_type != SERIAL_IO_MEM)
586 if (sport->port.uartclk / 16 != ser->baud_base)
588 if ((void *)sport->port.mapbase != ser->iomem_base)
590 if (sport->port.iobase != ser->port)
597 static struct uart_ops sa1100_pops = {
598 .tx_empty = sa1100_tx_empty,
599 .set_mctrl = sa1100_set_mctrl,
600 .get_mctrl = sa1100_get_mctrl,
601 .stop_tx = sa1100_stop_tx,
602 .start_tx = sa1100_start_tx,
603 .stop_rx = sa1100_stop_rx,
604 .enable_ms = sa1100_enable_ms,
605 .break_ctl = sa1100_break_ctl,
606 .startup = sa1100_startup,
607 .shutdown = sa1100_shutdown,
608 .set_termios = sa1100_set_termios,
610 .release_port = sa1100_release_port,
611 .request_port = sa1100_request_port,
612 .config_port = sa1100_config_port,
613 .verify_port = sa1100_verify_port,
616 static struct sa1100_port sa1100_ports[NR_PORTS];
619 * Setup the SA1100 serial ports. Note that we don't include the IrDA
620 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
622 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
623 * Which serial port this ends up being depends on the machine you're
624 * running this kernel on. I'm not convinced that this is a good idea,
625 * but that's the way it traditionally works.
627 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
630 static void __init sa1100_init_ports(void)
632 static int first = 1;
639 for (i = 0; i < NR_PORTS; i++) {
640 sa1100_ports[i].port.uartclk = 3686400;
641 sa1100_ports[i].port.ops = &sa1100_pops;
642 sa1100_ports[i].port.fifosize = 8;
643 sa1100_ports[i].port.line = i;
644 sa1100_ports[i].port.iotype = UPIO_MEM;
645 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
649 * make transmit lines outputs, so that when the port
650 * is closed, the output is in the MARK state.
652 PPDR |= PPC_TXD1 | PPC_TXD3;
653 PPSR |= PPC_TXD1 | PPC_TXD3;
656 void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
659 sa1100_pops.get_mctrl = fns->get_mctrl;
661 sa1100_pops.set_mctrl = fns->set_mctrl;
663 sa1100_pops.pm = fns->pm;
665 * FIXME: fns->set_wake is unused - this should be called from
666 * the suspend() callback if device_may_wakeup(dev)) is set.
670 void __init sa1100_register_uart(int idx, int port)
672 if (idx >= NR_PORTS) {
673 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
679 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
680 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
681 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
682 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
686 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
687 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
688 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
689 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
693 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
694 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
695 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
696 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
700 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
705 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
706 static void sa1100_console_putchar(struct uart_port *port, int ch)
708 struct sa1100_port *sport =
709 container_of(port, struct sa1100_port, port);
711 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
713 UART_PUT_CHAR(sport, ch);
717 * Interrupts are disabled on entering
720 sa1100_console_write(struct console *co, const char *s, unsigned int count)
722 struct sa1100_port *sport = &sa1100_ports[co->index];
723 unsigned int old_utcr3, status;
726 * First, save UTCR3 and then disable interrupts
728 old_utcr3 = UART_GET_UTCR3(sport);
729 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
732 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
735 * Finally, wait for transmitter to become empty
739 status = UART_GET_UTSR1(sport);
740 } while (status & UTSR1_TBY);
741 UART_PUT_UTCR3(sport, old_utcr3);
745 * If the port was already initialised (eg, by a boot loader),
746 * try to determine the current setup.
749 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
750 int *parity, int *bits)
754 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
755 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
756 /* ok, the port was enabled */
757 unsigned int utcr0, quot;
759 utcr0 = UART_GET_UTCR0(sport);
762 if (utcr0 & UTCR0_PE) {
763 if (utcr0 & UTCR0_OES)
769 if (utcr0 & UTCR0_DSS)
774 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
776 *baud = sport->port.uartclk / (16 * (quot + 1));
781 sa1100_console_setup(struct console *co, char *options)
783 struct sa1100_port *sport;
790 * Check whether an invalid uart number has been specified, and
791 * if so, search for the first available port that does have
794 if (co->index == -1 || co->index >= NR_PORTS)
796 sport = &sa1100_ports[co->index];
799 uart_parse_options(options, &baud, &parity, &bits, &flow);
801 sa1100_console_get_options(sport, &baud, &parity, &bits);
803 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
806 static struct uart_driver sa1100_reg;
807 static struct console sa1100_console = {
809 .write = sa1100_console_write,
810 .device = uart_console_device,
811 .setup = sa1100_console_setup,
812 .flags = CON_PRINTBUFFER,
817 static int __init sa1100_rs_console_init(void)
820 register_console(&sa1100_console);
823 console_initcall(sa1100_rs_console_init);
825 #define SA1100_CONSOLE &sa1100_console
827 #define SA1100_CONSOLE NULL
830 static struct uart_driver sa1100_reg = {
831 .owner = THIS_MODULE,
832 .driver_name = "ttySA",
834 .major = SERIAL_SA1100_MAJOR,
835 .minor = MINOR_START,
837 .cons = SA1100_CONSOLE,
840 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
842 struct sa1100_port *sport = platform_get_drvdata(dev);
845 uart_suspend_port(&sa1100_reg, &sport->port);
850 static int sa1100_serial_resume(struct platform_device *dev)
852 struct sa1100_port *sport = platform_get_drvdata(dev);
855 uart_resume_port(&sa1100_reg, &sport->port);
860 static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
862 sport->port.dev = &dev->dev;
864 // mctrl_gpio_init() requires that the GPIO driver supports interrupts,
865 // but we need to support GPIO drivers for hardware that has no such
866 // interrupts. Use mctrl_gpio_init_noauto() instead.
867 sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
868 if (IS_ERR(sport->gpios)) {
869 int err = PTR_ERR(sport->gpios);
871 dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
874 if (err == -EPROBE_DEFER)
880 platform_set_drvdata(dev, sport);
882 return uart_add_one_port(&sa1100_reg, &sport->port);
885 static int sa1100_serial_probe(struct platform_device *dev)
887 struct resource *res = dev->resource;
890 for (i = 0; i < dev->num_resources; i++, res++)
891 if (res->flags & IORESOURCE_MEM)
894 if (i < dev->num_resources) {
895 for (i = 0; i < NR_PORTS; i++) {
896 if (sa1100_ports[i].port.mapbase != res->start)
899 sa1100_serial_add_one_port(&sa1100_ports[i], dev);
907 static int sa1100_serial_remove(struct platform_device *pdev)
909 struct sa1100_port *sport = platform_get_drvdata(pdev);
912 uart_remove_one_port(&sa1100_reg, &sport->port);
917 static struct platform_driver sa11x0_serial_driver = {
918 .probe = sa1100_serial_probe,
919 .remove = sa1100_serial_remove,
920 .suspend = sa1100_serial_suspend,
921 .resume = sa1100_serial_resume,
923 .name = "sa11x0-uart",
927 static int __init sa1100_serial_init(void)
931 printk(KERN_INFO "Serial: SA11x0 driver\n");
935 ret = uart_register_driver(&sa1100_reg);
937 ret = platform_driver_register(&sa11x0_serial_driver);
939 uart_unregister_driver(&sa1100_reg);
944 static void __exit sa1100_serial_exit(void)
946 platform_driver_unregister(&sa11x0_serial_driver);
947 uart_unregister_driver(&sa1100_reg);
950 module_init(sa1100_serial_init);
951 module_exit(sa1100_serial_exit);
953 MODULE_AUTHOR("Deep Blue Solutions Ltd");
954 MODULE_DESCRIPTION("SA1100 generic serial port driver");
955 MODULE_LICENSE("GPL");
956 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
957 MODULE_ALIAS("platform:sa11x0-uart");