1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
9 #include <linux/console.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/qcom-geni-se.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 #include <linux/slab.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
23 /* UART specific GENI registers */
24 #define SE_UART_LOOPBACK_CFG 0x22c
25 #define SE_UART_TX_TRANS_CFG 0x25c
26 #define SE_UART_TX_WORD_LEN 0x268
27 #define SE_UART_TX_STOP_BIT_LEN 0x26c
28 #define SE_UART_TX_TRANS_LEN 0x270
29 #define SE_UART_RX_TRANS_CFG 0x280
30 #define SE_UART_RX_WORD_LEN 0x28c
31 #define SE_UART_RX_STALE_CNT 0x294
32 #define SE_UART_TX_PARITY_CFG 0x2a4
33 #define SE_UART_RX_PARITY_CFG 0x2a8
34 #define SE_UART_MANUAL_RFR 0x2ac
36 /* SE_UART_TRANS_CFG */
37 #define UART_TX_PAR_EN BIT(0)
38 #define UART_CTS_MASK BIT(1)
40 /* SE_UART_TX_WORD_LEN */
41 #define TX_WORD_LEN_MSK GENMASK(9, 0)
43 /* SE_UART_TX_STOP_BIT_LEN */
44 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
45 #define TX_STOP_BIT_LEN_1 0
46 #define TX_STOP_BIT_LEN_1_5 1
47 #define TX_STOP_BIT_LEN_2 2
49 /* SE_UART_TX_TRANS_LEN */
50 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
52 /* SE_UART_RX_TRANS_CFG */
53 #define UART_RX_INS_STATUS_BIT BIT(2)
54 #define UART_RX_PAR_EN BIT(3)
56 /* SE_UART_RX_WORD_LEN */
57 #define RX_WORD_LEN_MASK GENMASK(9, 0)
59 /* SE_UART_RX_STALE_CNT */
60 #define RX_STALE_CNT GENMASK(23, 0)
62 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63 #define PAR_CALC_EN BIT(0)
64 #define PAR_MODE_MSK GENMASK(2, 1)
65 #define PAR_MODE_SHFT 1
68 #define PAR_SPACE 0x10
71 /* SE_UART_MANUAL_RFR register fields */
72 #define UART_MANUAL_RFR_EN BIT(31)
73 #define UART_RFR_NOT_READY BIT(1)
74 #define UART_RFR_READY BIT(0)
76 /* UART M_CMD OP codes */
77 #define UART_START_TX 0x1
78 #define UART_START_BREAK 0x4
79 #define UART_STOP_BREAK 0x5
80 /* UART S_CMD OP codes */
81 #define UART_START_READ 0x1
82 #define UART_PARAM 0x1
84 #define UART_OVERSAMPLING 32
85 #define STALE_TIMEOUT 16
86 #define DEFAULT_BITS_PER_CHAR 10
87 #define GENI_UART_CONS_PORTS 1
88 #define GENI_UART_PORTS 3
89 #define DEF_FIFO_DEPTH_WORDS 16
91 #define DEF_FIFO_WIDTH_BITS 32
92 #define UART_CONSOLE_RX_WM 2
93 #define MAX_LOOPBACK_CFG 3
95 #ifdef CONFIG_CONSOLE_POLL
96 #define CONSOLE_RX_BYTES_PW 1
98 #define CONSOLE_RX_BYTES_PW 4
101 struct qcom_geni_serial_port {
102 struct uart_port uport;
111 enum geni_se_xfer_mode xfer_mode;
113 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
115 unsigned int tx_bytes_pw;
116 unsigned int rx_bytes_pw;
121 unsigned int tx_remaining;
124 static const struct uart_ops qcom_geni_console_pops;
125 static const struct uart_ops qcom_geni_uart_pops;
126 static struct uart_driver qcom_geni_console_driver;
127 static struct uart_driver qcom_geni_uart_driver;
128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
133 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
134 32000000, 48000000, 64000000, 80000000,
135 96000000, 100000000, 102400000,
136 112000000, 120000000, 128000000};
138 #define to_dev_port(ptr, member) \
139 container_of(ptr, struct qcom_geni_serial_port, member)
141 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
145 .ops = &qcom_geni_uart_pops,
146 .flags = UPF_BOOT_AUTOCONF,
153 .ops = &qcom_geni_uart_pops,
154 .flags = UPF_BOOT_AUTOCONF,
161 .ops = &qcom_geni_uart_pops,
162 .flags = UPF_BOOT_AUTOCONF,
168 static ssize_t loopback_show(struct device *dev,
169 struct device_attribute *attr, char *buf)
171 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
173 return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
176 static ssize_t loopback_store(struct device *dev,
177 struct device_attribute *attr, const char *buf,
180 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
183 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
184 dev_err(dev, "Invalid input\n");
187 port->loopback = loopback;
190 static DEVICE_ATTR_RW(loopback);
192 static struct qcom_geni_serial_port qcom_geni_console_port = {
195 .ops = &qcom_geni_console_pops,
196 .flags = UPF_BOOT_AUTOCONF,
201 static int qcom_geni_serial_request_port(struct uart_port *uport)
203 struct platform_device *pdev = to_platform_device(uport->dev);
204 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
205 struct resource *res;
207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 uport->membase = devm_ioremap_resource(&pdev->dev, res);
209 if (IS_ERR(uport->membase))
210 return PTR_ERR(uport->membase);
211 port->se.base = uport->membase;
215 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
217 if (cfg_flags & UART_CONFIG_TYPE) {
218 uport->type = PORT_MSM;
219 qcom_geni_serial_request_port(uport);
223 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
225 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
228 if (uart_console(uport)) {
231 geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);
232 if (!(geni_ios & IO2_DATA_IN))
239 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
242 u32 uart_manual_rfr = 0;
244 if (uart_console(uport))
247 if (!(mctrl & TIOCM_RTS))
248 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
249 writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
252 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
257 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
259 struct qcom_geni_serial_port *port;
260 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
262 if (line < 0 || line >= nr_ports)
263 return ERR_PTR(-ENXIO);
265 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
269 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
270 int offset, int field, bool set)
273 struct qcom_geni_serial_port *port;
275 unsigned int fifo_bits;
276 unsigned long timeout_us = 20000;
278 /* Ensure polling is not re-ordered before the prior writes/reads */
281 if (uport->private_data) {
282 port = to_dev_port(uport, uport);
286 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
288 * Total polling iterations based on FIFO worth of bytes to be
289 * sent at current baud. Add a little fluff to the wait.
291 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
295 * Use custom implementation instead of readl_poll_atomic since ktimer
296 * is not ready at the time of early console.
298 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
300 reg = readl_relaxed(uport->membase + offset);
301 if ((bool)(reg & field) == set)
309 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
313 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
314 m_cmd = UART_START_TX << M_OPCODE_SHFT;
315 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
318 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
321 u32 irq_clear = M_CMD_DONE_EN;
323 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
324 M_CMD_DONE_EN, true);
326 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
327 SE_GENI_M_CMD_CTRL_REG);
328 irq_clear |= M_CMD_ABORT_EN;
329 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
330 M_CMD_ABORT_EN, true);
332 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
335 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
337 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
339 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
340 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
341 S_GENI_CMD_ABORT, false);
342 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
343 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
346 #ifdef CONFIG_CONSOLE_POLL
347 static int qcom_geni_serial_get_char(struct uart_port *uport)
352 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
355 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
359 * Ensure the writes to clear interrupts is not re-ordered after
364 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
365 if (!(status & RX_FIFO_WC_MSK))
368 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
369 return rx_fifo & 0xff;
372 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
375 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
377 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
378 qcom_geni_serial_setup_tx(uport, 1);
379 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
380 M_TX_FIFO_WATERMARK_EN, true));
381 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
382 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
383 SE_GENI_M_IRQ_CLEAR);
384 qcom_geni_serial_poll_tx_done(uport);
388 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
389 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
391 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
395 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
399 u32 bytes_to_send = count;
401 for (i = 0; i < count; i++) {
403 * uart_console_write() adds a carriage return for each newline.
404 * Account for additional bytes to be written.
410 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
411 qcom_geni_serial_setup_tx(uport, bytes_to_send);
412 for (i = 0; i < count; ) {
413 size_t chars_to_write = 0;
414 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
417 * If the WM bit never set, then the Tx state machine is not
418 * in a valid state, so break, cancel/abort any existing
419 * command. Unfortunately the current data being written is
422 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
423 M_TX_FIFO_WATERMARK_EN, true))
425 chars_to_write = min_t(size_t, count - i, avail / 2);
426 uart_console_write(uport, s + i, chars_to_write,
427 qcom_geni_serial_wr_char);
428 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
429 SE_GENI_M_IRQ_CLEAR);
432 qcom_geni_serial_poll_tx_done(uport);
435 static void qcom_geni_serial_console_write(struct console *co, const char *s,
438 struct uart_port *uport;
439 struct qcom_geni_serial_port *port;
445 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
447 port = get_port_from_line(co->index, true);
451 uport = &port->uport;
452 if (oops_in_progress)
453 locked = spin_trylock_irqsave(&uport->lock, flags);
455 spin_lock_irqsave(&uport->lock, flags);
457 geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
459 /* Cancel the current write to log the fault */
461 geni_se_cancel_m_cmd(&port->se);
462 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
463 M_CMD_CANCEL_EN, true)) {
464 geni_se_abort_m_cmd(&port->se);
465 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
466 M_CMD_ABORT_EN, true);
467 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
468 SE_GENI_M_IRQ_CLEAR);
470 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
471 SE_GENI_M_IRQ_CLEAR);
472 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
474 * It seems we can't interrupt existing transfers if all data
475 * has been sent, in which case we need to look for done first.
477 qcom_geni_serial_poll_tx_done(uport);
479 if (uart_circ_chars_pending(&uport->state->xmit)) {
480 irq_en = readl_relaxed(uport->membase +
482 writel_relaxed(irq_en | M_TX_FIFO_WATERMARK_EN,
483 uport->membase + SE_GENI_M_IRQ_EN);
487 __qcom_geni_serial_console_write(uport, s, count);
489 if (port->tx_remaining)
490 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
493 spin_unlock_irqrestore(&uport->lock, flags);
496 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
499 unsigned char buf[sizeof(u32)];
500 struct tty_port *tport;
501 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
503 tport = &uport->state->port;
504 for (i = 0; i < bytes; ) {
506 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
508 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
513 for (c = 0; c < chunk; c++) {
517 if (port->brk && buf[c] == 0) {
519 if (uart_handle_break(uport))
523 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
526 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
530 tty_flip_buffer_push(tport);
534 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
539 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
541 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
544 struct tty_port *tport;
545 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
546 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
547 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
550 tport = &uport->state->port;
551 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
555 buf = (unsigned char *)port->rx_fifo;
556 ret = tty_insert_flip_string(tport, buf, bytes);
558 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
559 __func__, ret, bytes);
562 uport->icount.rx += ret;
563 tty_flip_buffer_push(tport);
567 static void qcom_geni_serial_start_tx(struct uart_port *uport)
570 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
573 if (port->xfer_mode == GENI_SE_FIFO) {
575 * readl ensures reading & writing of IRQ_EN register
576 * is not re-ordered before checking the status of the
579 status = readl(uport->membase + SE_GENI_STATUS);
580 if (status & M_GENI_CMD_ACTIVE)
583 if (!qcom_geni_serial_tx_empty(uport))
586 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
587 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
589 writel_relaxed(port->tx_wm, uport->membase +
590 SE_GENI_TX_WATERMARK_REG);
591 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
595 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
599 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
601 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
602 irq_en &= ~M_CMD_DONE_EN;
603 if (port->xfer_mode == GENI_SE_FIFO) {
604 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
605 writel_relaxed(0, uport->membase +
606 SE_GENI_TX_WATERMARK_REG);
608 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
609 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
610 /* Possible stop tx is called multiple times. */
611 if (!(status & M_GENI_CMD_ACTIVE))
615 * Ensure cancel command write is not re-ordered before checking
616 * the status of the Primary Sequencer.
620 geni_se_cancel_m_cmd(&port->se);
621 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
622 M_CMD_CANCEL_EN, true)) {
623 geni_se_abort_m_cmd(&port->se);
624 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
625 M_CMD_ABORT_EN, true);
626 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
627 SE_GENI_M_IRQ_CLEAR);
629 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
632 static void qcom_geni_serial_start_rx(struct uart_port *uport)
636 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
638 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
639 if (status & S_GENI_CMD_ACTIVE)
640 qcom_geni_serial_stop_rx(uport);
643 * Ensure setup command write is not re-ordered before checking
644 * the status of the Secondary Sequencer.
648 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
650 if (port->xfer_mode == GENI_SE_FIFO) {
651 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
652 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
653 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
655 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
656 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
657 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
661 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
665 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
666 u32 irq_clear = S_CMD_DONE_EN;
668 if (port->xfer_mode == GENI_SE_FIFO) {
669 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
670 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
671 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
673 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
674 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
675 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
678 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
679 /* Possible stop rx is called multiple times. */
680 if (!(status & S_GENI_CMD_ACTIVE))
684 * Ensure cancel command write is not re-ordered before checking
685 * the status of the Secondary Sequencer.
689 geni_se_cancel_s_cmd(&port->se);
690 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
691 S_GENI_CMD_CANCEL, false);
692 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
693 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
694 if (status & S_GENI_CMD_ACTIVE)
695 qcom_geni_serial_abort_rx(uport);
698 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
702 u32 last_word_byte_cnt;
703 u32 last_word_partial;
705 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
707 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
708 word_cnt = status & RX_FIFO_WC_MSK;
709 last_word_partial = status & RX_LAST;
710 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
711 RX_LAST_BYTE_VALID_SHFT;
715 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
716 if (last_word_partial && last_word_byte_cnt)
717 total_bytes += last_word_byte_cnt;
719 total_bytes += port->rx_bytes_pw;
720 port->handle_rx(uport, total_bytes, drop);
723 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
726 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
727 struct circ_buf *xmit = &uport->state->xmit;
737 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
739 /* Complete the current tx command before taking newly added data */
741 pending = port->tx_remaining;
743 pending = uart_circ_chars_pending(xmit);
745 /* All data has been transmitted and acknowledged as received */
746 if (!pending && !status && done) {
747 qcom_geni_serial_stop_tx(uport);
748 goto out_write_wakeup;
751 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
752 avail *= port->tx_bytes_pw;
755 chunk = min(avail, pending);
757 goto out_write_wakeup;
759 if (!port->tx_remaining) {
760 qcom_geni_serial_setup_tx(uport, pending);
761 port->tx_remaining = pending;
763 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
764 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
765 writel_relaxed(irq_en | M_TX_FIFO_WATERMARK_EN,
766 uport->membase + SE_GENI_M_IRQ_EN);
770 for (i = 0; i < chunk; ) {
771 unsigned int tx_bytes;
775 memset(buf, 0, ARRAY_SIZE(buf));
776 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
778 for (c = 0; c < tx_bytes ; c++) {
779 buf[c] = xmit->buf[tail++];
780 tail &= UART_XMIT_SIZE - 1;
783 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
786 uport->icount.tx += tx_bytes;
787 remaining -= tx_bytes;
788 port->tx_remaining -= tx_bytes;
794 * The tx fifo watermark is level triggered and latched. Though we had
795 * cleared it in qcom_geni_serial_isr it will have already reasserted
796 * so we must clear it again here after our writes.
798 writel_relaxed(M_TX_FIFO_WATERMARK_EN,
799 uport->membase + SE_GENI_M_IRQ_CLEAR);
802 if (!port->tx_remaining) {
803 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
804 if (irq_en & M_TX_FIFO_WATERMARK_EN)
805 writel_relaxed(irq_en & ~M_TX_FIFO_WATERMARK_EN,
806 uport->membase + SE_GENI_M_IRQ_EN);
809 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
810 uart_write_wakeup(uport);
813 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
815 unsigned int m_irq_status;
816 unsigned int s_irq_status;
817 unsigned int geni_status;
818 struct uart_port *uport = dev;
820 unsigned int m_irq_en;
821 bool drop_rx = false;
822 struct tty_port *tport = &uport->state->port;
823 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
825 if (uport->suspended)
828 spin_lock_irqsave(&uport->lock, flags);
829 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
830 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
831 geni_status = readl_relaxed(uport->membase + SE_GENI_STATUS);
832 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
833 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
834 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
836 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
839 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
840 uport->icount.overrun++;
841 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
844 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
845 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
846 geni_status & M_GENI_CMD_ACTIVE);
848 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
849 if (s_irq_status & S_GP_IRQ_0_EN)
850 uport->icount.parity++;
852 } else if (s_irq_status & S_GP_IRQ_2_EN ||
853 s_irq_status & S_GP_IRQ_3_EN) {
858 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
859 s_irq_status & S_RX_FIFO_LAST_EN)
860 qcom_geni_serial_handle_rx(uport, drop_rx);
863 uart_unlock_and_check_sysrq(uport, flags);
868 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
870 struct uart_port *uport;
872 uport = &port->uport;
873 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
874 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
875 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
877 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
880 static void set_rfr_wm(struct qcom_geni_serial_port *port)
883 * Set RFR (Flow off) to FIFO_DEPTH - 2.
884 * RX WM level at 10% RX_FIFO_DEPTH.
885 * TX WM level at 10% TX_FIFO_DEPTH.
887 port->rx_rfr = port->rx_fifo_depth - 2;
888 port->rx_wm = UART_CONSOLE_RX_WM;
889 port->tx_wm = DEF_TX_WM;
892 static void qcom_geni_serial_shutdown(struct uart_port *uport)
896 /* Stop the console before stopping the current tx */
897 if (uart_console(uport))
898 console_stop(uport->cons);
900 free_irq(uport->irq, uport);
901 spin_lock_irqsave(&uport->lock, flags);
902 qcom_geni_serial_stop_tx(uport);
903 qcom_geni_serial_stop_rx(uport);
904 spin_unlock_irqrestore(&uport->lock, flags);
907 static int qcom_geni_serial_port_setup(struct uart_port *uport)
909 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
910 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
913 if (uart_console(uport)) {
914 port->tx_bytes_pw = 1;
915 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
917 port->tx_bytes_pw = 4;
918 port->rx_bytes_pw = 4;
921 proto = geni_se_read_proto(&port->se);
922 if (proto != GENI_SE_UART) {
923 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
927 qcom_geni_serial_stop_rx(uport);
929 get_tx_fifo_size(port);
932 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
934 * Make an unconditional cancel on the main sequencer to reset
935 * it else we could end up in data loss scenarios.
937 port->xfer_mode = GENI_SE_FIFO;
938 if (uart_console(uport))
939 qcom_geni_serial_poll_tx_done(uport);
940 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
942 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
944 geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
945 geni_se_select_mode(&port->se, port->xfer_mode);
946 if (!uart_console(uport)) {
947 port->rx_fifo = devm_kcalloc(uport->dev,
948 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
957 static int qcom_geni_serial_startup(struct uart_port *uport)
960 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
962 scnprintf(port->name, sizeof(port->name),
964 (uart_console(uport) ? "console" : "uart"), uport->line);
967 ret = qcom_geni_serial_port_setup(uport);
972 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
975 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
979 static unsigned long get_clk_cfg(unsigned long clk_freq)
983 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
984 if (!(root_freq[i] % clk_freq))
990 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
992 unsigned long ser_clk;
993 unsigned long desired_clk;
995 desired_clk = baud * UART_OVERSAMPLING;
996 ser_clk = get_clk_cfg(desired_clk);
998 pr_err("%s: Can't find matching DFS entry for baud %d\n",
1003 *clk_div = ser_clk / desired_clk;
1007 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1008 struct ktermios *termios, struct ktermios *old)
1011 unsigned int bits_per_char;
1012 unsigned int tx_trans_cfg;
1013 unsigned int tx_parity_cfg;
1014 unsigned int rx_trans_cfg;
1015 unsigned int rx_parity_cfg;
1016 unsigned int stop_bit_len;
1017 unsigned int clk_div;
1018 unsigned long ser_clk_cfg;
1019 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1020 unsigned long clk_rate;
1022 qcom_geni_serial_stop_rx(uport);
1024 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1026 clk_rate = get_clk_div_rate(baud, &clk_div);
1028 goto out_restart_rx;
1030 uport->uartclk = clk_rate;
1031 clk_set_rate(port->se.clk, clk_rate);
1032 ser_clk_cfg = SER_CLK_EN;
1033 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1036 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
1037 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
1038 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
1039 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
1040 if (termios->c_cflag & PARENB) {
1041 tx_trans_cfg |= UART_TX_PAR_EN;
1042 rx_trans_cfg |= UART_RX_PAR_EN;
1043 tx_parity_cfg |= PAR_CALC_EN;
1044 rx_parity_cfg |= PAR_CALC_EN;
1045 if (termios->c_cflag & PARODD) {
1046 tx_parity_cfg |= PAR_ODD;
1047 rx_parity_cfg |= PAR_ODD;
1048 } else if (termios->c_cflag & CMSPAR) {
1049 tx_parity_cfg |= PAR_SPACE;
1050 rx_parity_cfg |= PAR_SPACE;
1052 tx_parity_cfg |= PAR_EVEN;
1053 rx_parity_cfg |= PAR_EVEN;
1056 tx_trans_cfg &= ~UART_TX_PAR_EN;
1057 rx_trans_cfg &= ~UART_RX_PAR_EN;
1058 tx_parity_cfg &= ~PAR_CALC_EN;
1059 rx_parity_cfg &= ~PAR_CALC_EN;
1063 switch (termios->c_cflag & CSIZE) {
1080 if (termios->c_cflag & CSTOPB)
1081 stop_bit_len = TX_STOP_BIT_LEN_2;
1083 stop_bit_len = TX_STOP_BIT_LEN_1;
1085 /* flow control, clear the CTS_MASK bit if using flow control. */
1086 if (termios->c_cflag & CRTSCTS)
1087 tx_trans_cfg &= ~UART_CTS_MASK;
1089 tx_trans_cfg |= UART_CTS_MASK;
1092 uart_update_timeout(uport, termios->c_cflag, baud);
1094 if (!uart_console(uport))
1095 writel_relaxed(port->loopback,
1096 uport->membase + SE_UART_LOOPBACK_CFG);
1097 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1098 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1099 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1100 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1101 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1102 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1103 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1104 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1105 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1107 qcom_geni_serial_start_rx(uport);
1110 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1112 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1115 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1116 static int __init qcom_geni_console_setup(struct console *co, char *options)
1118 struct uart_port *uport;
1119 struct qcom_geni_serial_port *port;
1126 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1129 port = get_port_from_line(co->index, true);
1131 pr_err("Invalid line %d\n", co->index);
1132 return PTR_ERR(port);
1135 uport = &port->uport;
1137 if (unlikely(!uport->membase))
1141 ret = qcom_geni_serial_port_setup(uport);
1147 uart_parse_options(options, &baud, &parity, &bits, &flow);
1149 return uart_set_options(uport, co, baud, parity, bits, flow);
1152 static void qcom_geni_serial_earlycon_write(struct console *con,
1153 const char *s, unsigned int n)
1155 struct earlycon_device *dev = con->data;
1157 __qcom_geni_serial_console_write(&dev->port, s, n);
1160 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1163 struct uart_port *uport = &dev->port;
1165 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1166 u32 rx_trans_cfg = 0;
1167 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1168 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1172 if (!uport->membase)
1175 memset(&se, 0, sizeof(se));
1176 se.base = uport->membase;
1177 if (geni_se_read_proto(&se) != GENI_SE_UART)
1180 * Ignore Flow control.
1183 tx_trans_cfg = UART_CTS_MASK;
1184 bits_per_char = BITS_PER_BYTE;
1187 * Make an unconditional cancel on the main sequencer to reset
1188 * it else we could end up in data loss scenarios.
1190 qcom_geni_serial_poll_tx_done(uport);
1191 qcom_geni_serial_abort_rx(uport);
1192 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1193 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1194 geni_se_select_mode(&se, GENI_SE_FIFO);
1196 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1197 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1198 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1199 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1200 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1201 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1202 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1204 dev->con->write = qcom_geni_serial_earlycon_write;
1205 dev->con->setup = NULL;
1208 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1209 qcom_geni_serial_earlycon_setup);
1211 static int __init console_register(struct uart_driver *drv)
1213 return uart_register_driver(drv);
1216 static void console_unregister(struct uart_driver *drv)
1218 uart_unregister_driver(drv);
1221 static struct console cons_ops = {
1223 .write = qcom_geni_serial_console_write,
1224 .device = uart_console_device,
1225 .setup = qcom_geni_console_setup,
1226 .flags = CON_PRINTBUFFER,
1228 .data = &qcom_geni_console_driver,
1231 static struct uart_driver qcom_geni_console_driver = {
1232 .owner = THIS_MODULE,
1233 .driver_name = "qcom_geni_console",
1234 .dev_name = "ttyMSM",
1235 .nr = GENI_UART_CONS_PORTS,
1239 static int console_register(struct uart_driver *drv)
1244 static void console_unregister(struct uart_driver *drv)
1247 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1249 static struct uart_driver qcom_geni_uart_driver = {
1250 .owner = THIS_MODULE,
1251 .driver_name = "qcom_geni_uart",
1252 .dev_name = "ttyHS",
1253 .nr = GENI_UART_PORTS,
1256 static void qcom_geni_serial_pm(struct uart_port *uport,
1257 unsigned int new_state, unsigned int old_state)
1259 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1261 /* If we've never been called, treat it as off */
1262 if (old_state == UART_PM_STATE_UNDEFINED)
1263 old_state = UART_PM_STATE_OFF;
1265 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1266 geni_se_resources_on(&port->se);
1267 else if (new_state == UART_PM_STATE_OFF &&
1268 old_state == UART_PM_STATE_ON)
1269 geni_se_resources_off(&port->se);
1272 static const struct uart_ops qcom_geni_console_pops = {
1273 .tx_empty = qcom_geni_serial_tx_empty,
1274 .stop_tx = qcom_geni_serial_stop_tx,
1275 .start_tx = qcom_geni_serial_start_tx,
1276 .stop_rx = qcom_geni_serial_stop_rx,
1277 .set_termios = qcom_geni_serial_set_termios,
1278 .startup = qcom_geni_serial_startup,
1279 .request_port = qcom_geni_serial_request_port,
1280 .config_port = qcom_geni_serial_config_port,
1281 .shutdown = qcom_geni_serial_shutdown,
1282 .type = qcom_geni_serial_get_type,
1283 .set_mctrl = qcom_geni_serial_set_mctrl,
1284 .get_mctrl = qcom_geni_serial_get_mctrl,
1285 #ifdef CONFIG_CONSOLE_POLL
1286 .poll_get_char = qcom_geni_serial_get_char,
1287 .poll_put_char = qcom_geni_serial_poll_put_char,
1289 .pm = qcom_geni_serial_pm,
1292 static const struct uart_ops qcom_geni_uart_pops = {
1293 .tx_empty = qcom_geni_serial_tx_empty,
1294 .stop_tx = qcom_geni_serial_stop_tx,
1295 .start_tx = qcom_geni_serial_start_tx,
1296 .stop_rx = qcom_geni_serial_stop_rx,
1297 .set_termios = qcom_geni_serial_set_termios,
1298 .startup = qcom_geni_serial_startup,
1299 .request_port = qcom_geni_serial_request_port,
1300 .config_port = qcom_geni_serial_config_port,
1301 .shutdown = qcom_geni_serial_shutdown,
1302 .type = qcom_geni_serial_get_type,
1303 .set_mctrl = qcom_geni_serial_set_mctrl,
1304 .get_mctrl = qcom_geni_serial_get_mctrl,
1305 .pm = qcom_geni_serial_pm,
1308 static int qcom_geni_serial_probe(struct platform_device *pdev)
1312 struct qcom_geni_serial_port *port;
1313 struct uart_port *uport;
1314 struct resource *res;
1316 bool console = false;
1317 struct uart_driver *drv;
1319 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1323 drv = &qcom_geni_console_driver;
1324 line = of_alias_get_id(pdev->dev.of_node, "serial");
1326 drv = &qcom_geni_uart_driver;
1327 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1330 port = get_port_from_line(line, console);
1332 dev_err(&pdev->dev, "Invalid line %d\n", line);
1333 return PTR_ERR(port);
1336 uport = &port->uport;
1337 /* Don't allow 2 drivers to access the same port */
1338 if (uport->private_data)
1341 uport->dev = &pdev->dev;
1342 port->se.dev = &pdev->dev;
1343 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1344 port->se.clk = devm_clk_get(&pdev->dev, "se");
1345 if (IS_ERR(port->se.clk)) {
1346 ret = PTR_ERR(port->se.clk);
1347 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1351 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354 uport->mapbase = res->start;
1356 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1357 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1358 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1360 irq = platform_get_irq(pdev, 0);
1362 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1367 uport->private_data = drv;
1368 platform_set_drvdata(pdev, port);
1369 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1371 device_create_file(uport->dev, &dev_attr_loopback);
1372 return uart_add_one_port(drv, uport);
1375 static int qcom_geni_serial_remove(struct platform_device *pdev)
1377 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1378 struct uart_driver *drv = port->uport.private_data;
1380 uart_remove_one_port(drv, &port->uport);
1384 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1386 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1387 struct uart_port *uport = &port->uport;
1389 return uart_suspend_port(uport->private_data, uport);
1392 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1394 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1395 struct uart_port *uport = &port->uport;
1397 return uart_resume_port(uport->private_data, uport);
1400 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1401 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1402 qcom_geni_serial_sys_resume)
1405 static const struct of_device_id qcom_geni_serial_match_table[] = {
1406 { .compatible = "qcom,geni-debug-uart", },
1407 { .compatible = "qcom,geni-uart", },
1410 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1412 static struct platform_driver qcom_geni_serial_platform_driver = {
1413 .remove = qcom_geni_serial_remove,
1414 .probe = qcom_geni_serial_probe,
1416 .name = "qcom_geni_serial",
1417 .of_match_table = qcom_geni_serial_match_table,
1418 .pm = &qcom_geni_serial_pm_ops,
1422 static int __init qcom_geni_serial_init(void)
1426 ret = console_register(&qcom_geni_console_driver);
1430 ret = uart_register_driver(&qcom_geni_uart_driver);
1432 console_unregister(&qcom_geni_console_driver);
1436 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1438 console_unregister(&qcom_geni_console_driver);
1439 uart_unregister_driver(&qcom_geni_uart_driver);
1443 module_init(qcom_geni_serial_init);
1445 static void __exit qcom_geni_serial_exit(void)
1447 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1448 console_unregister(&qcom_geni_console_driver);
1449 uart_unregister_driver(&qcom_geni_uart_driver);
1451 module_exit(qcom_geni_serial_exit);
1453 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1454 MODULE_LICENSE("GPL v2");