drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/console.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/irq.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/pm_wakeirq.h>
  15 #include <linux/qcom-geni-se.h>
  16 #include <linux/serial.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/slab.h>
  19 #include <linux/tty.h>
  20 #include <linux/tty_flip.h>
  21
  22 /* UART specific GENI registers */
  23 #define SE_UART_LOOPBACK_CFG            0x22c
  24 #define SE_UART_TX_TRANS_CFG            0x25c
  25 #define SE_UART_TX_WORD_LEN             0x268
  26 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  27 #define SE_UART_TX_TRANS_LEN            0x270
  28 #define SE_UART_RX_TRANS_CFG            0x280
  29 #define SE_UART_RX_WORD_LEN             0x28c
  30 #define SE_UART_RX_STALE_CNT            0x294
  31 #define SE_UART_TX_PARITY_CFG           0x2a4
  32 #define SE_UART_RX_PARITY_CFG           0x2a8
  33 #define SE_UART_MANUAL_RFR              0x2ac
  34
  35 /* SE_UART_TRANS_CFG */
  36 #define UART_TX_PAR_EN          BIT(0)
  37 #define UART_CTS_MASK           BIT(1)
  38
  39 /* SE_UART_TX_WORD_LEN */
  40 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  41
  42 /* SE_UART_TX_STOP_BIT_LEN */
  43 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  44 #define TX_STOP_BIT_LEN_1       0
  45 #define TX_STOP_BIT_LEN_1_5     1
  46 #define TX_STOP_BIT_LEN_2       2
  47
  48 /* SE_UART_TX_TRANS_LEN */
  49 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  50
  51 /* SE_UART_RX_TRANS_CFG */
  52 #define UART_RX_INS_STATUS_BIT  BIT(2)
  53 #define UART_RX_PAR_EN          BIT(3)
  54
  55 /* SE_UART_RX_WORD_LEN */
  56 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  57
  58 /* SE_UART_RX_STALE_CNT */
  59 #define RX_STALE_CNT            GENMASK(23, 0)
  60
  61 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  62 #define PAR_CALC_EN             BIT(0)
  63 #define PAR_MODE_MSK            GENMASK(2, 1)
  64 #define PAR_MODE_SHFT           1
  65 #define PAR_EVEN                0x00
  66 #define PAR_ODD                 0x01
  67 #define PAR_SPACE               0x10
  68 #define PAR_MARK                0x11
  69
  70 /* SE_UART_MANUAL_RFR register fields */
  71 #define UART_MANUAL_RFR_EN      BIT(31)
  72 #define UART_RFR_NOT_READY      BIT(1)
  73 #define UART_RFR_READY          BIT(0)
  74
  75 /* UART M_CMD OP codes */
  76 #define UART_START_TX           0x1
  77 #define UART_START_BREAK        0x4
  78 #define UART_STOP_BREAK         0x5
  79 /* UART S_CMD OP codes */
  80 #define UART_START_READ         0x1
  81 #define UART_PARAM              0x1
  82
  83 #define UART_OVERSAMPLING       32
  84 #define STALE_TIMEOUT           16
  85 #define DEFAULT_BITS_PER_CHAR   10
  86 #define GENI_UART_CONS_PORTS    1
  87 #define GENI_UART_PORTS         3
  88 #define DEF_FIFO_DEPTH_WORDS    16
  89 #define DEF_TX_WM               2
  90 #define DEF_FIFO_WIDTH_BITS     32
  91 #define UART_RX_WM              2
  92
  93 /* SE_UART_LOOPBACK_CFG */
  94 #define RX_TX_SORTED    BIT(0)
  95 #define CTS_RTS_SORTED  BIT(1)
  96 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
  97
  98 #ifdef CONFIG_CONSOLE_POLL
  99 #define CONSOLE_RX_BYTES_PW 1
 100 #else
 101 #define CONSOLE_RX_BYTES_PW 4
 102 #endif
 103
 104 struct qcom_geni_serial_port {
 105         struct uart_port uport;
 106         struct geni_se se;
 107         const char *name;
 108         u32 tx_fifo_depth;
 109         u32 tx_fifo_width;
 110         u32 rx_fifo_depth;
 111         bool setup;
 112         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 113         unsigned int baud;
 114         unsigned int tx_bytes_pw;
 115         unsigned int rx_bytes_pw;
 116         u32 *rx_fifo;
 117         u32 loopback;
 118         bool brk;
 119
 120         unsigned int tx_remaining;
 121         int wakeup_irq;
 122 };
 123
 124 static const struct uart_ops qcom_geni_console_pops;
 125 static const struct uart_ops qcom_geni_uart_pops;
 126 static struct uart_driver qcom_geni_console_driver;
 127 static struct uart_driver qcom_geni_uart_driver;
 128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 132
 133 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 134                                         32000000, 48000000, 64000000, 80000000,
 135                                         96000000, 100000000, 102400000,
 136                                         112000000, 120000000, 128000000};
 137
 138 #define to_dev_port(ptr, member) \
 139                 container_of(ptr, struct qcom_geni_serial_port, member)
 140
 141 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 142         [0] = {
 143                 .uport = {
 144                                 .iotype = UPIO_MEM,
 145                                 .ops = &qcom_geni_uart_pops,
 146                                 .flags = UPF_BOOT_AUTOCONF,
 147                                 .line = 0,
 148                 },
 149         },
 150         [1] = {
 151                 .uport = {
 152                                 .iotype = UPIO_MEM,
 153                                 .ops = &qcom_geni_uart_pops,
 154                                 .flags = UPF_BOOT_AUTOCONF,
 155                                 .line = 1,
 156                 },
 157         },
 158         [2] = {
 159                 .uport = {
 160                                 .iotype = UPIO_MEM,
 161                                 .ops = &qcom_geni_uart_pops,
 162                                 .flags = UPF_BOOT_AUTOCONF,
 163                                 .line = 2,
 164                 },
 165         },
 166 };
 167
 168 static struct qcom_geni_serial_port qcom_geni_console_port = {
 169         .uport = {
 170                 .iotype = UPIO_MEM,
 171                 .ops = &qcom_geni_console_pops,
 172                 .flags = UPF_BOOT_AUTOCONF,
 173                 .line = 0,
 174         },
 175 };
 176
 177 static int qcom_geni_serial_request_port(struct uart_port *uport)
 178 {
 179         struct platform_device *pdev = to_platform_device(uport->dev);
 180         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 181
 182         uport->membase = devm_platform_ioremap_resource(pdev, 0);
 183         if (IS_ERR(uport->membase))
 184                 return PTR_ERR(uport->membase);
 185         port->se.base = uport->membase;
 186         return 0;
 187 }
 188
 189 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 190 {
 191         if (cfg_flags & UART_CONFIG_TYPE) {
 192                 uport->type = PORT_MSM;
 193                 qcom_geni_serial_request_port(uport);
 194         }
 195 }
 196
 197 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 198 {
 199         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 200         u32 geni_ios;
 201
 202         if (uart_console(uport)) {
 203                 mctrl |= TIOCM_CTS;
 204         } else {
 205                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 206                 if (!(geni_ios & IO2_DATA_IN))
 207                         mctrl |= TIOCM_CTS;
 208         }
 209
 210         return mctrl;
 211 }
 212
 213 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 214                                                         unsigned int mctrl)
 215 {
 216         u32 uart_manual_rfr = 0;
 217         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 218
 219         if (uart_console(uport))
 220                 return;
 221
 222         if (mctrl & TIOCM_LOOP)
 223                 port->loopback = RX_TX_CTS_RTS_SORTED;
 224
 225         if (!(mctrl & TIOCM_RTS))
 226                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 227         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 228 }
 229
 230 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 231 {
 232         return "MSM";
 233 }
 234
 235 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 236 {
 237         struct qcom_geni_serial_port *port;
 238         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 239
 240         if (line < 0 || line >= nr_ports)
 241                 return ERR_PTR(-ENXIO);
 242
 243         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 244         return port;
 245 }
 246
 247 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 248                                 int offset, int field, bool set)
 249 {
 250         u32 reg;
 251         struct qcom_geni_serial_port *port;
 252         unsigned int baud;
 253         unsigned int fifo_bits;
 254         unsigned long timeout_us = 20000;
 255
 256         if (uport->private_data) {
 257                 port = to_dev_port(uport, uport);
 258                 baud = port->baud;
 259                 if (!baud)
 260                         baud = 115200;
 261                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 262                 /*
 263                  * Total polling iterations based on FIFO worth of bytes to be
 264                  * sent at current baud. Add a little fluff to the wait.
 265                  */
 266                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 267         }
 268
 269         /*
 270          * Use custom implementation instead of readl_poll_atomic since ktimer
 271          * is not ready at the time of early console.
 272          */
 273         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 274         while (timeout_us) {
 275                 reg = readl(uport->membase + offset);
 276                 if ((bool)(reg & field) == set)
 277                         return true;
 278                 udelay(10);
 279                 timeout_us -= 10;
 280         }
 281         return false;
 282 }
 283
 284 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 285 {
 286         u32 m_cmd;
 287
 288         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 289         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 290         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 291 }
 292
 293 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 294 {
 295         int done;
 296         u32 irq_clear = M_CMD_DONE_EN;
 297
 298         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 299                                                 M_CMD_DONE_EN, true);
 300         if (!done) {
 301                 writel(M_GENI_CMD_ABORT, uport->membase +
 302                                                 SE_GENI_M_CMD_CTRL_REG);
 303                 irq_clear |= M_CMD_ABORT_EN;
 304                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 305                                                         M_CMD_ABORT_EN, true);
 306         }
 307         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 308 }
 309
 310 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 311 {
 312         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 313
 314         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 315         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 316                                         S_GENI_CMD_ABORT, false);
 317         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 318         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 319 }
 320
 321 #ifdef CONFIG_CONSOLE_POLL
 322 static int qcom_geni_serial_get_char(struct uart_port *uport)
 323 {
 324         u32 rx_fifo;
 325         u32 status;
 326
 327         status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 328         writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 329
 330         status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 331         writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 332
 333         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 334         if (!(status & RX_FIFO_WC_MSK))
 335                 return NO_POLL_CHAR;
 336
 337         rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
 338         return rx_fifo & 0xff;
 339 }
 340
 341 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 342                                                         unsigned char c)
 343 {
 344         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 345         qcom_geni_serial_setup_tx(uport, 1);
 346         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 347                                                 M_TX_FIFO_WATERMARK_EN, true));
 348         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 349         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 350         qcom_geni_serial_poll_tx_done(uport);
 351 }
 352 #endif
 353
 354 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 355 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 356 {
 357         writel(ch, uport->membase + SE_GENI_TX_FIFOn);
 358 }
 359
 360 static void
 361 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 362                                  unsigned int count)
 363 {
 364         int i;
 365         u32 bytes_to_send = count;
 366
 367         for (i = 0; i < count; i++) {
 368                 /*
 369                  * uart_console_write() adds a carriage return for each newline.
 370                  * Account for additional bytes to be written.
 371                  */
 372                 if (s[i] == '\n')
 373                         bytes_to_send++;
 374         }
 375
 376         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 377         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 378         for (i = 0; i < count; ) {
 379                 size_t chars_to_write = 0;
 380                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 381
 382                 /*
 383                  * If the WM bit never set, then the Tx state machine is not
 384                  * in a valid state, so break, cancel/abort any existing
 385                  * command. Unfortunately the current data being written is
 386                  * lost.
 387                  */
 388                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 389                                                 M_TX_FIFO_WATERMARK_EN, true))
 390                         break;
 391                 chars_to_write = min_t(size_t, count - i, avail / 2);
 392                 uart_console_write(uport, s + i, chars_to_write,
 393                                                 qcom_geni_serial_wr_char);
 394                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 395                                                         SE_GENI_M_IRQ_CLEAR);
 396                 i += chars_to_write;
 397         }
 398         qcom_geni_serial_poll_tx_done(uport);
 399 }
 400
 401 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 402                               unsigned int count)
 403 {
 404         struct uart_port *uport;
 405         struct qcom_geni_serial_port *port;
 406         bool locked = true;
 407         unsigned long flags;
 408         u32 geni_status;
 409         u32 irq_en;
 410
 411         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 412
 413         port = get_port_from_line(co->index, true);
 414         if (IS_ERR(port))
 415                 return;
 416
 417         uport = &port->uport;
 418         if (oops_in_progress)
 419                 locked = spin_trylock_irqsave(&uport->lock, flags);
 420         else
 421                 spin_lock_irqsave(&uport->lock, flags);
 422
 423         geni_status = readl(uport->membase + SE_GENI_STATUS);
 424
 425         /* Cancel the current write to log the fault */
 426         if (!locked) {
 427                 geni_se_cancel_m_cmd(&port->se);
 428                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 429                                                 M_CMD_CANCEL_EN, true)) {
 430                         geni_se_abort_m_cmd(&port->se);
 431                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 432                                                         M_CMD_ABORT_EN, true);
 433                         writel(M_CMD_ABORT_EN, uport->membase +
 434                                                         SE_GENI_M_IRQ_CLEAR);
 435                 }
 436                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 437         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 438                 /*
 439                  * It seems we can't interrupt existing transfers if all data
 440                  * has been sent, in which case we need to look for done first.
 441                  */
 442                 qcom_geni_serial_poll_tx_done(uport);
 443
 444                 if (uart_circ_chars_pending(&uport->state->xmit)) {
 445                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 446                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 447                                         uport->membase + SE_GENI_M_IRQ_EN);
 448                 }
 449         }
 450
 451         __qcom_geni_serial_console_write(uport, s, count);
 452
 453         if (port->tx_remaining)
 454                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 455
 456         if (locked)
 457                 spin_unlock_irqrestore(&uport->lock, flags);
 458 }
 459
 460 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 461 {
 462         u32 i;
 463         unsigned char buf[sizeof(u32)];
 464         struct tty_port *tport;
 465         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 466
 467         tport = &uport->state->port;
 468         for (i = 0; i < bytes; ) {
 469                 int c;
 470                 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
 471
 472                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 473                 i += chunk;
 474                 if (drop)
 475                         continue;
 476
 477                 for (c = 0; c < chunk; c++) {
 478                         int sysrq;
 479
 480                         uport->icount.rx++;
 481                         if (port->brk && buf[c] == 0) {
 482                                 port->brk = false;
 483                                 if (uart_handle_break(uport))
 484                                         continue;
 485                         }
 486
 487                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 488
 489                         if (!sysrq)
 490                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 491                 }
 492         }
 493         if (!drop)
 494                 tty_flip_buffer_push(tport);
 495         return 0;
 496 }
 497 #else
 498 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 499 {
 500         return -EPERM;
 501 }
 502
 503 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 504
 505 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 506 {
 507         unsigned char *buf;
 508         struct tty_port *tport;
 509         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 510         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 511         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 512         int ret;
 513
 514         tport = &uport->state->port;
 515         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 516         if (drop)
 517                 return 0;
 518
 519         buf = (unsigned char *)port->rx_fifo;
 520         ret = tty_insert_flip_string(tport, buf, bytes);
 521         if (ret != bytes) {
 522                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 523                                 __func__, ret, bytes);
 524                 WARN_ON_ONCE(1);
 525         }
 526         uport->icount.rx += ret;
 527         tty_flip_buffer_push(tport);
 528         return ret;
 529 }
 530
 531 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 532 {
 533         u32 irq_en;
 534         u32 status;
 535
 536         status = readl(uport->membase + SE_GENI_STATUS);
 537         if (status & M_GENI_CMD_ACTIVE)
 538                 return;
 539
 540         if (!qcom_geni_serial_tx_empty(uport))
 541                 return;
 542
 543         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 544         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 545
 546         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 547         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 548 }
 549
 550 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 551 {
 552         u32 irq_en;
 553         u32 status;
 554         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 555
 556         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 557         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 558         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 559         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 560         status = readl(uport->membase + SE_GENI_STATUS);
 561         /* Possible stop tx is called multiple times. */
 562         if (!(status & M_GENI_CMD_ACTIVE))
 563                 return;
 564
 565         geni_se_cancel_m_cmd(&port->se);
 566         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 567                                                 M_CMD_CANCEL_EN, true)) {
 568                 geni_se_abort_m_cmd(&port->se);
 569                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 570                                                 M_CMD_ABORT_EN, true);
 571                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 572         }
 573         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 574 }
 575
 576 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 577 {
 578         u32 irq_en;
 579         u32 status;
 580         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 581
 582         status = readl(uport->membase + SE_GENI_STATUS);
 583         if (status & S_GENI_CMD_ACTIVE)
 584                 qcom_geni_serial_stop_rx(uport);
 585
 586         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 587
 588         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 589         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 590         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 591
 592         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 593         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 594         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 595 }
 596
 597 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 598 {
 599         u32 irq_en;
 600         u32 status;
 601         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 602         u32 irq_clear = S_CMD_DONE_EN;
 603
 604         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 605         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 606         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 607
 608         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 609         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 610         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 611
 612         status = readl(uport->membase + SE_GENI_STATUS);
 613         /* Possible stop rx is called multiple times. */
 614         if (!(status & S_GENI_CMD_ACTIVE))
 615                 return;
 616
 617         geni_se_cancel_s_cmd(&port->se);
 618         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 619                                         S_GENI_CMD_CANCEL, false);
 620         status = readl(uport->membase + SE_GENI_STATUS);
 621         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 622         if (status & S_GENI_CMD_ACTIVE)
 623                 qcom_geni_serial_abort_rx(uport);
 624 }
 625
 626 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 627 {
 628         u32 status;
 629         u32 word_cnt;
 630         u32 last_word_byte_cnt;
 631         u32 last_word_partial;
 632         u32 total_bytes;
 633         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 634
 635         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 636         word_cnt = status & RX_FIFO_WC_MSK;
 637         last_word_partial = status & RX_LAST;
 638         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 639                                                 RX_LAST_BYTE_VALID_SHFT;
 640
 641         if (!word_cnt)
 642                 return;
 643         total_bytes = port->rx_bytes_pw * (word_cnt - 1);
 644         if (last_word_partial && last_word_byte_cnt)
 645                 total_bytes += last_word_byte_cnt;
 646         else
 647                 total_bytes += port->rx_bytes_pw;
 648         port->handle_rx(uport, total_bytes, drop);
 649 }
 650
 651 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 652                 bool active)
 653 {
 654         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 655         struct circ_buf *xmit = &uport->state->xmit;
 656         size_t avail;
 657         size_t remaining;
 658         size_t pending;
 659         int i;
 660         u32 status;
 661         u32 irq_en;
 662         unsigned int chunk;
 663         int tail;
 664
 665         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 666
 667         /* Complete the current tx command before taking newly added data */
 668         if (active)
 669                 pending = port->tx_remaining;
 670         else
 671                 pending = uart_circ_chars_pending(xmit);
 672
 673         /* All data has been transmitted and acknowledged as received */
 674         if (!pending && !status && done) {
 675                 qcom_geni_serial_stop_tx(uport);
 676                 goto out_write_wakeup;
 677         }
 678
 679         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 680         avail *= port->tx_bytes_pw;
 681
 682         tail = xmit->tail;
 683         chunk = min(avail, pending);
 684         if (!chunk)
 685                 goto out_write_wakeup;
 686
 687         if (!port->tx_remaining) {
 688                 qcom_geni_serial_setup_tx(uport, pending);
 689                 port->tx_remaining = pending;
 690
 691                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 692                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 693                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 694                                         uport->membase + SE_GENI_M_IRQ_EN);
 695         }
 696
 697         remaining = chunk;
 698         for (i = 0; i < chunk; ) {
 699                 unsigned int tx_bytes;
 700                 u8 buf[sizeof(u32)];
 701                 int c;
 702
 703                 memset(buf, 0, ARRAY_SIZE(buf));
 704                 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
 705
 706                 for (c = 0; c < tx_bytes ; c++) {
 707                         buf[c] = xmit->buf[tail++];
 708                         tail &= UART_XMIT_SIZE - 1;
 709                 }
 710
 711                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 712
 713                 i += tx_bytes;
 714                 uport->icount.tx += tx_bytes;
 715                 remaining -= tx_bytes;
 716                 port->tx_remaining -= tx_bytes;
 717         }
 718
 719         xmit->tail = tail;
 720
 721         /*
 722          * The tx fifo watermark is level triggered and latched. Though we had
 723          * cleared it in qcom_geni_serial_isr it will have already reasserted
 724          * so we must clear it again here after our writes.
 725          */
 726         writel(M_TX_FIFO_WATERMARK_EN,
 727                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 728
 729 out_write_wakeup:
 730         if (!port->tx_remaining) {
 731                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 732                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 733                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 734                                         uport->membase + SE_GENI_M_IRQ_EN);
 735         }
 736
 737         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 738                 uart_write_wakeup(uport);
 739 }
 740
 741 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 742 {
 743         u32 m_irq_en;
 744         u32 m_irq_status;
 745         u32 s_irq_status;
 746         u32 geni_status;
 747         struct uart_port *uport = dev;
 748         unsigned long flags;
 749         bool drop_rx = false;
 750         struct tty_port *tport = &uport->state->port;
 751         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 752
 753         if (uport->suspended)
 754                 return IRQ_NONE;
 755
 756         spin_lock_irqsave(&uport->lock, flags);
 757         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 758         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 759         geni_status = readl(uport->membase + SE_GENI_STATUS);
 760         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 761         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 762         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 763
 764         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 765                 goto out_unlock;
 766
 767         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 768                 uport->icount.overrun++;
 769                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 770         }
 771
 772         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 773                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 774                                         geni_status & M_GENI_CMD_ACTIVE);
 775
 776         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 777                 if (s_irq_status & S_GP_IRQ_0_EN)
 778                         uport->icount.parity++;
 779                 drop_rx = true;
 780         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 781                                         s_irq_status & S_GP_IRQ_3_EN) {
 782                 uport->icount.brk++;
 783                 port->brk = true;
 784         }
 785
 786         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 787                                         s_irq_status & S_RX_FIFO_LAST_EN)
 788                 qcom_geni_serial_handle_rx(uport, drop_rx);
 789
 790 out_unlock:
 791         uart_unlock_and_check_sysrq(uport, flags);
 792
 793         return IRQ_HANDLED;
 794 }
 795
 796 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 797 {
 798         struct uart_port *uport;
 799
 800         uport = &port->uport;
 801         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 802         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 803         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 804         uport->fifosize =
 805                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 806 }
 807
 808
 809 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 810 {
 811         unsigned long flags;
 812
 813         /* Stop the console before stopping the current tx */
 814         if (uart_console(uport))
 815                 console_stop(uport->cons);
 816
 817         disable_irq(uport->irq);
 818         spin_lock_irqsave(&uport->lock, flags);
 819         qcom_geni_serial_stop_tx(uport);
 820         qcom_geni_serial_stop_rx(uport);
 821         spin_unlock_irqrestore(&uport->lock, flags);
 822 }
 823
 824 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 825 {
 826         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 827         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 828         u32 proto;
 829
 830         if (uart_console(uport)) {
 831                 port->tx_bytes_pw = 1;
 832                 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
 833         } else {
 834                 port->tx_bytes_pw = 4;
 835                 port->rx_bytes_pw = 4;
 836         }
 837
 838         proto = geni_se_read_proto(&port->se);
 839         if (proto != GENI_SE_UART) {
 840                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 841                 return -ENXIO;
 842         }
 843
 844         qcom_geni_serial_stop_rx(uport);
 845
 846         get_tx_fifo_size(port);
 847
 848         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 849         /*
 850          * Make an unconditional cancel on the main sequencer to reset
 851          * it else we could end up in data loss scenarios.
 852          */
 853         if (uart_console(uport))
 854                 qcom_geni_serial_poll_tx_done(uport);
 855         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
 856                                                 false, true, false);
 857         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
 858                                                 false, false, true);
 859         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 860         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 861         if (!uart_console(uport)) {
 862                 port->rx_fifo = devm_kcalloc(uport->dev,
 863                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
 864                 if (!port->rx_fifo)
 865                         return -ENOMEM;
 866         }
 867         port->setup = true;
 868
 869         return 0;
 870 }
 871
 872 static int qcom_geni_serial_startup(struct uart_port *uport)
 873 {
 874         int ret;
 875         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 876
 877         if (!port->setup) {
 878                 ret = qcom_geni_serial_port_setup(uport);
 879                 if (ret)
 880                         return ret;
 881         }
 882         enable_irq(uport->irq);
 883
 884         return 0;
 885 }
 886
 887 static unsigned long get_clk_cfg(unsigned long clk_freq)
 888 {
 889         int i;
 890
 891         for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 892                 if (!(root_freq[i] % clk_freq))
 893                         return root_freq[i];
 894         }
 895         return 0;
 896 }
 897
 898 static unsigned long get_clk_div_rate(unsigned int baud,
 899                         unsigned int sampling_rate, unsigned int *clk_div)
 900 {
 901         unsigned long ser_clk;
 902         unsigned long desired_clk;
 903
 904         desired_clk = baud * sampling_rate;
 905         ser_clk = get_clk_cfg(desired_clk);
 906         if (!ser_clk) {
 907                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 908                                                                 __func__, baud);
 909                 return ser_clk;
 910         }
 911
 912         *clk_div = ser_clk / desired_clk;
 913         return ser_clk;
 914 }
 915
 916 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 917                                 struct ktermios *termios, struct ktermios *old)
 918 {
 919         unsigned int baud;
 920         u32 bits_per_char;
 921         u32 tx_trans_cfg;
 922         u32 tx_parity_cfg;
 923         u32 rx_trans_cfg;
 924         u32 rx_parity_cfg;
 925         u32 stop_bit_len;
 926         unsigned int clk_div;
 927         u32 ser_clk_cfg;
 928         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 929         unsigned long clk_rate;
 930         u32 ver, sampling_rate;
 931
 932         qcom_geni_serial_stop_rx(uport);
 933         /* baud rate */
 934         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 935         port->baud = baud;
 936
 937         sampling_rate = UART_OVERSAMPLING;
 938         /* Sampling rate is halved for IP versions >= 2.5 */
 939         ver = geni_se_get_qup_hw_version(&port->se);
 940         if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
 941                 sampling_rate /= 2;
 942
 943         clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
 944         if (!clk_rate)
 945                 goto out_restart_rx;
 946
 947         uport->uartclk = clk_rate;
 948         clk_set_rate(port->se.clk, clk_rate);
 949         ser_clk_cfg = SER_CLK_EN;
 950         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 951
 952         /* parity */
 953         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
 954         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
 955         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
 956         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
 957         if (termios->c_cflag & PARENB) {
 958                 tx_trans_cfg |= UART_TX_PAR_EN;
 959                 rx_trans_cfg |= UART_RX_PAR_EN;
 960                 tx_parity_cfg |= PAR_CALC_EN;
 961                 rx_parity_cfg |= PAR_CALC_EN;
 962                 if (termios->c_cflag & PARODD) {
 963                         tx_parity_cfg |= PAR_ODD;
 964                         rx_parity_cfg |= PAR_ODD;
 965                 } else if (termios->c_cflag & CMSPAR) {
 966                         tx_parity_cfg |= PAR_SPACE;
 967                         rx_parity_cfg |= PAR_SPACE;
 968                 } else {
 969                         tx_parity_cfg |= PAR_EVEN;
 970                         rx_parity_cfg |= PAR_EVEN;
 971                 }
 972         } else {
 973                 tx_trans_cfg &= ~UART_TX_PAR_EN;
 974                 rx_trans_cfg &= ~UART_RX_PAR_EN;
 975                 tx_parity_cfg &= ~PAR_CALC_EN;
 976                 rx_parity_cfg &= ~PAR_CALC_EN;
 977         }
 978
 979         /* bits per char */
 980         switch (termios->c_cflag & CSIZE) {
 981         case CS5:
 982                 bits_per_char = 5;
 983                 break;
 984         case CS6:
 985                 bits_per_char = 6;
 986                 break;
 987         case CS7:
 988                 bits_per_char = 7;
 989                 break;
 990         case CS8:
 991         default:
 992                 bits_per_char = 8;
 993                 break;
 994         }
 995
 996         /* stop bits */
 997         if (termios->c_cflag & CSTOPB)
 998                 stop_bit_len = TX_STOP_BIT_LEN_2;
 999         else
1000                 stop_bit_len = TX_STOP_BIT_LEN_1;
1001
1002         /* flow control, clear the CTS_MASK bit if using flow control. */
1003         if (termios->c_cflag & CRTSCTS)
1004                 tx_trans_cfg &= ~UART_CTS_MASK;
1005         else
1006                 tx_trans_cfg |= UART_CTS_MASK;
1007
1008         if (baud)
1009                 uart_update_timeout(uport, termios->c_cflag, baud);
1010
1011         if (!uart_console(uport))
1012                 writel(port->loopback,
1013                                 uport->membase + SE_UART_LOOPBACK_CFG);
1014         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1015         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1016         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1017         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1018         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1019         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1020         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1021         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1022         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1023 out_restart_rx:
1024         qcom_geni_serial_start_rx(uport);
1025 }
1026
1027 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1028 {
1029         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1030 }
1031
1032 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1033 static int __init qcom_geni_console_setup(struct console *co, char *options)
1034 {
1035         struct uart_port *uport;
1036         struct qcom_geni_serial_port *port;
1037         int baud = 9600;
1038         int bits = 8;
1039         int parity = 'n';
1040         int flow = 'n';
1041         int ret;
1042
1043         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1044                 return -ENXIO;
1045
1046         port = get_port_from_line(co->index, true);
1047         if (IS_ERR(port)) {
1048                 pr_err("Invalid line %d\n", co->index);
1049                 return PTR_ERR(port);
1050         }
1051
1052         uport = &port->uport;
1053
1054         if (unlikely(!uport->membase))
1055                 return -ENXIO;
1056
1057         if (!port->setup) {
1058                 ret = qcom_geni_serial_port_setup(uport);
1059                 if (ret)
1060                         return ret;
1061         }
1062
1063         if (options)
1064                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1065
1066         return uart_set_options(uport, co, baud, parity, bits, flow);
1067 }
1068
1069 static void qcom_geni_serial_earlycon_write(struct console *con,
1070                                         const char *s, unsigned int n)
1071 {
1072         struct earlycon_device *dev = con->data;
1073
1074         __qcom_geni_serial_console_write(&dev->port, s, n);
1075 }
1076
1077 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1078                                                                 const char *opt)
1079 {
1080         struct uart_port *uport = &dev->port;
1081         u32 tx_trans_cfg;
1082         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1083         u32 rx_trans_cfg = 0;
1084         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1085         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1086         u32 bits_per_char;
1087         struct geni_se se;
1088
1089         if (!uport->membase)
1090                 return -EINVAL;
1091
1092         memset(&se, 0, sizeof(se));
1093         se.base = uport->membase;
1094         if (geni_se_read_proto(&se) != GENI_SE_UART)
1095                 return -ENXIO;
1096         /*
1097          * Ignore Flow control.
1098          * n = 8.
1099          */
1100         tx_trans_cfg = UART_CTS_MASK;
1101         bits_per_char = BITS_PER_BYTE;
1102
1103         /*
1104          * Make an unconditional cancel on the main sequencer to reset
1105          * it else we could end up in data loss scenarios.
1106          */
1107         qcom_geni_serial_poll_tx_done(uport);
1108         qcom_geni_serial_abort_rx(uport);
1109         geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1110         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1111         geni_se_select_mode(&se, GENI_SE_FIFO);
1112
1113         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1114         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1115         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1116         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1117         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1118         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1119         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1120
1121         dev->con->write = qcom_geni_serial_earlycon_write;
1122         dev->con->setup = NULL;
1123         return 0;
1124 }
1125 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1126                                 qcom_geni_serial_earlycon_setup);
1127
1128 static int __init console_register(struct uart_driver *drv)
1129 {
1130         return uart_register_driver(drv);
1131 }
1132
1133 static void console_unregister(struct uart_driver *drv)
1134 {
1135         uart_unregister_driver(drv);
1136 }
1137
1138 static struct console cons_ops = {
1139         .name = "ttyMSM",
1140         .write = qcom_geni_serial_console_write,
1141         .device = uart_console_device,
1142         .setup = qcom_geni_console_setup,
1143         .flags = CON_PRINTBUFFER,
1144         .index = -1,
1145         .data = &qcom_geni_console_driver,
1146 };
1147
1148 static struct uart_driver qcom_geni_console_driver = {
1149         .owner = THIS_MODULE,
1150         .driver_name = "qcom_geni_console",
1151         .dev_name = "ttyMSM",
1152         .nr =  GENI_UART_CONS_PORTS,
1153         .cons = &cons_ops,
1154 };
1155 #else
1156 static int console_register(struct uart_driver *drv)
1157 {
1158         return 0;
1159 }
1160
1161 static void console_unregister(struct uart_driver *drv)
1162 {
1163 }
1164 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1165
1166 static struct uart_driver qcom_geni_uart_driver = {
1167         .owner = THIS_MODULE,
1168         .driver_name = "qcom_geni_uart",
1169         .dev_name = "ttyHS",
1170         .nr =  GENI_UART_PORTS,
1171 };
1172
1173 static void qcom_geni_serial_pm(struct uart_port *uport,
1174                 unsigned int new_state, unsigned int old_state)
1175 {
1176         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1177
1178         /* If we've never been called, treat it as off */
1179         if (old_state == UART_PM_STATE_UNDEFINED)
1180                 old_state = UART_PM_STATE_OFF;
1181
1182         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1183                 geni_se_resources_on(&port->se);
1184         else if (new_state == UART_PM_STATE_OFF &&
1185                         old_state == UART_PM_STATE_ON)
1186                 geni_se_resources_off(&port->se);
1187 }
1188
1189 static const struct uart_ops qcom_geni_console_pops = {
1190         .tx_empty = qcom_geni_serial_tx_empty,
1191         .stop_tx = qcom_geni_serial_stop_tx,
1192         .start_tx = qcom_geni_serial_start_tx,
1193         .stop_rx = qcom_geni_serial_stop_rx,
1194         .set_termios = qcom_geni_serial_set_termios,
1195         .startup = qcom_geni_serial_startup,
1196         .request_port = qcom_geni_serial_request_port,
1197         .config_port = qcom_geni_serial_config_port,
1198         .shutdown = qcom_geni_serial_shutdown,
1199         .type = qcom_geni_serial_get_type,
1200         .set_mctrl = qcom_geni_serial_set_mctrl,
1201         .get_mctrl = qcom_geni_serial_get_mctrl,
1202 #ifdef CONFIG_CONSOLE_POLL
1203         .poll_get_char  = qcom_geni_serial_get_char,
1204         .poll_put_char  = qcom_geni_serial_poll_put_char,
1205 #endif
1206         .pm = qcom_geni_serial_pm,
1207 };
1208
1209 static const struct uart_ops qcom_geni_uart_pops = {
1210         .tx_empty = qcom_geni_serial_tx_empty,
1211         .stop_tx = qcom_geni_serial_stop_tx,
1212         .start_tx = qcom_geni_serial_start_tx,
1213         .stop_rx = qcom_geni_serial_stop_rx,
1214         .set_termios = qcom_geni_serial_set_termios,
1215         .startup = qcom_geni_serial_startup,
1216         .request_port = qcom_geni_serial_request_port,
1217         .config_port = qcom_geni_serial_config_port,
1218         .shutdown = qcom_geni_serial_shutdown,
1219         .type = qcom_geni_serial_get_type,
1220         .set_mctrl = qcom_geni_serial_set_mctrl,
1221         .get_mctrl = qcom_geni_serial_get_mctrl,
1222         .pm = qcom_geni_serial_pm,
1223 };
1224
1225 static int qcom_geni_serial_probe(struct platform_device *pdev)
1226 {
1227         int ret = 0;
1228         int line = -1;
1229         struct qcom_geni_serial_port *port;
1230         struct uart_port *uport;
1231         struct resource *res;
1232         int irq;
1233         bool console = false;
1234         struct uart_driver *drv;
1235
1236         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1237                 console = true;
1238
1239         if (console) {
1240                 drv = &qcom_geni_console_driver;
1241                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1242         } else {
1243                 drv = &qcom_geni_uart_driver;
1244                 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1245         }
1246
1247         port = get_port_from_line(line, console);
1248         if (IS_ERR(port)) {
1249                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1250                 return PTR_ERR(port);
1251         }
1252
1253         uport = &port->uport;
1254         /* Don't allow 2 drivers to access the same port */
1255         if (uport->private_data)
1256                 return -ENODEV;
1257
1258         uport->dev = &pdev->dev;
1259         port->se.dev = &pdev->dev;
1260         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1261         port->se.clk = devm_clk_get(&pdev->dev, "se");
1262         if (IS_ERR(port->se.clk)) {
1263                 ret = PTR_ERR(port->se.clk);
1264                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1265                 return ret;
1266         }
1267
1268         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269         if (!res)
1270                 return -EINVAL;
1271         uport->mapbase = res->start;
1272
1273         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1274         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1275         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1276
1277         port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1278                         "qcom_geni_serial_%s%d",
1279                         uart_console(uport) ? "console" : "uart", uport->line);
1280         if (!port->name)
1281                 return -ENOMEM;
1282
1283         irq = platform_get_irq(pdev, 0);
1284         if (irq < 0)
1285                 return irq;
1286         uport->irq = irq;
1287         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1288
1289         if (!console)
1290                 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1291
1292         uport->private_data = drv;
1293         platform_set_drvdata(pdev, port);
1294         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1295
1296         ret = uart_add_one_port(drv, uport);
1297         if (ret)
1298                 return ret;
1299
1300         irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1301         ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1302                         IRQF_TRIGGER_HIGH, port->name, uport);
1303         if (ret) {
1304                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1305                 uart_remove_one_port(drv, uport);
1306                 return ret;
1307         }
1308
1309         /*
1310          * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1311          * enabled/disabled from dev_pm_arm_wake_irq during system
1312          * suspend/resume respectively.
1313          */
1314         pm_runtime_set_active(&pdev->dev);
1315
1316         if (port->wakeup_irq > 0) {
1317                 device_init_wakeup(&pdev->dev, true);
1318                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1319                                                 port->wakeup_irq);
1320                 if (ret) {
1321                         device_init_wakeup(&pdev->dev, false);
1322                         uart_remove_one_port(drv, uport);
1323                         return ret;
1324                 }
1325         }
1326
1327         return 0;
1328 }
1329
1330 static int qcom_geni_serial_remove(struct platform_device *pdev)
1331 {
1332         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1333         struct uart_driver *drv = port->uport.private_data;
1334
1335         dev_pm_clear_wake_irq(&pdev->dev);
1336         device_init_wakeup(&pdev->dev, false);
1337         uart_remove_one_port(drv, &port->uport);
1338
1339         return 0;
1340 }
1341
1342 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1343 {
1344         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1345         struct uart_port *uport = &port->uport;
1346
1347         return uart_suspend_port(uport->private_data, uport);
1348 }
1349
1350 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1351 {
1352         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1353         struct uart_port *uport = &port->uport;
1354
1355         return uart_resume_port(uport->private_data, uport);
1356 }
1357
1358 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1359         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1360                                         qcom_geni_serial_sys_resume)
1361 };
1362
1363 static const struct of_device_id qcom_geni_serial_match_table[] = {
1364         { .compatible = "qcom,geni-debug-uart", },
1365         { .compatible = "qcom,geni-uart", },
1366         {}
1367 };
1368 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1369
1370 static struct platform_driver qcom_geni_serial_platform_driver = {
1371         .remove = qcom_geni_serial_remove,
1372         .probe = qcom_geni_serial_probe,
1373         .driver = {
1374                 .name = "qcom_geni_serial",
1375                 .of_match_table = qcom_geni_serial_match_table,
1376                 .pm = &qcom_geni_serial_pm_ops,
1377         },
1378 };
1379
1380 static int __init qcom_geni_serial_init(void)
1381 {
1382         int ret;
1383
1384         ret = console_register(&qcom_geni_console_driver);
1385         if (ret)
1386                 return ret;
1387
1388         ret = uart_register_driver(&qcom_geni_uart_driver);
1389         if (ret) {
1390                 console_unregister(&qcom_geni_console_driver);
1391                 return ret;
1392         }
1393
1394         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1395         if (ret) {
1396                 console_unregister(&qcom_geni_console_driver);
1397                 uart_unregister_driver(&qcom_geni_uart_driver);
1398         }
1399         return ret;
1400 }
1401 module_init(qcom_geni_serial_init);
1402
1403 static void __exit qcom_geni_serial_exit(void)
1404 {
1405         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1406         console_unregister(&qcom_geni_console_driver);
1407         uart_unregister_driver(&qcom_geni_uart_driver);
1408 }
1409 module_exit(qcom_geni_serial_exit);
1410
1411 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1412 MODULE_LICENSE("GPL v2");