drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/console.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/irq.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/pm_wakeirq.h>
  15 #include <linux/qcom-geni-se.h>
  16 #include <linux/serial.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/slab.h>
  19 #include <linux/tty.h>
  20 #include <linux/tty_flip.h>
  21
  22 /* UART specific GENI registers */
  23 #define SE_UART_LOOPBACK_CFG            0x22c
  24 #define SE_UART_TX_TRANS_CFG            0x25c
  25 #define SE_UART_TX_WORD_LEN             0x268
  26 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  27 #define SE_UART_TX_TRANS_LEN            0x270
  28 #define SE_UART_RX_TRANS_CFG            0x280
  29 #define SE_UART_RX_WORD_LEN             0x28c
  30 #define SE_UART_RX_STALE_CNT            0x294
  31 #define SE_UART_TX_PARITY_CFG           0x2a4
  32 #define SE_UART_RX_PARITY_CFG           0x2a8
  33 #define SE_UART_MANUAL_RFR              0x2ac
  34
  35 /* SE_UART_TRANS_CFG */
  36 #define UART_TX_PAR_EN          BIT(0)
  37 #define UART_CTS_MASK           BIT(1)
  38
  39 /* SE_UART_TX_WORD_LEN */
  40 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  41
  42 /* SE_UART_TX_STOP_BIT_LEN */
  43 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  44 #define TX_STOP_BIT_LEN_1       0
  45 #define TX_STOP_BIT_LEN_1_5     1
  46 #define TX_STOP_BIT_LEN_2       2
  47
  48 /* SE_UART_TX_TRANS_LEN */
  49 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  50
  51 /* SE_UART_RX_TRANS_CFG */
  52 #define UART_RX_INS_STATUS_BIT  BIT(2)
  53 #define UART_RX_PAR_EN          BIT(3)
  54
  55 /* SE_UART_RX_WORD_LEN */
  56 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  57
  58 /* SE_UART_RX_STALE_CNT */
  59 #define RX_STALE_CNT            GENMASK(23, 0)
  60
  61 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  62 #define PAR_CALC_EN             BIT(0)
  63 #define PAR_MODE_MSK            GENMASK(2, 1)
  64 #define PAR_MODE_SHFT           1
  65 #define PAR_EVEN                0x00
  66 #define PAR_ODD                 0x01
  67 #define PAR_SPACE               0x10
  68 #define PAR_MARK                0x11
  69
  70 /* SE_UART_MANUAL_RFR register fields */
  71 #define UART_MANUAL_RFR_EN      BIT(31)
  72 #define UART_RFR_NOT_READY      BIT(1)
  73 #define UART_RFR_READY          BIT(0)
  74
  75 /* UART M_CMD OP codes */
  76 #define UART_START_TX           0x1
  77 #define UART_START_BREAK        0x4
  78 #define UART_STOP_BREAK         0x5
  79 /* UART S_CMD OP codes */
  80 #define UART_START_READ         0x1
  81 #define UART_PARAM              0x1
  82
  83 #define UART_OVERSAMPLING       32
  84 #define STALE_TIMEOUT           16
  85 #define DEFAULT_BITS_PER_CHAR   10
  86 #define GENI_UART_CONS_PORTS    1
  87 #define GENI_UART_PORTS         3
  88 #define DEF_FIFO_DEPTH_WORDS    16
  89 #define DEF_TX_WM               2
  90 #define DEF_FIFO_WIDTH_BITS     32
  91 #define UART_RX_WM              2
  92
  93 /* SE_UART_LOOPBACK_CFG */
  94 #define RX_TX_SORTED    BIT(0)
  95 #define CTS_RTS_SORTED  BIT(1)
  96 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
  97
  98 #ifdef CONFIG_CONSOLE_POLL
  99 #define CONSOLE_RX_BYTES_PW 1
 100 #else
 101 #define CONSOLE_RX_BYTES_PW 4
 102 #endif
 103
 104 struct qcom_geni_serial_port {
 105         struct uart_port uport;
 106         struct geni_se se;
 107         const char *name;
 108         u32 tx_fifo_depth;
 109         u32 tx_fifo_width;
 110         u32 rx_fifo_depth;
 111         bool setup;
 112         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 113         unsigned int baud;
 114         unsigned int tx_bytes_pw;
 115         unsigned int rx_bytes_pw;
 116         u32 *rx_fifo;
 117         u32 loopback;
 118         bool brk;
 119
 120         unsigned int tx_remaining;
 121         int wakeup_irq;
 122 };
 123
 124 static const struct uart_ops qcom_geni_console_pops;
 125 static const struct uart_ops qcom_geni_uart_pops;
 126 static struct uart_driver qcom_geni_console_driver;
 127 static struct uart_driver qcom_geni_uart_driver;
 128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 132 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 133
 134 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 135                                         32000000, 48000000, 64000000, 80000000,
 136                                         96000000, 100000000, 102400000,
 137                                         112000000, 120000000, 128000000};
 138
 139 #define to_dev_port(ptr, member) \
 140                 container_of(ptr, struct qcom_geni_serial_port, member)
 141
 142 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 143         [0] = {
 144                 .uport = {
 145                                 .iotype = UPIO_MEM,
 146                                 .ops = &qcom_geni_uart_pops,
 147                                 .flags = UPF_BOOT_AUTOCONF,
 148                                 .line = 0,
 149                 },
 150         },
 151         [1] = {
 152                 .uport = {
 153                                 .iotype = UPIO_MEM,
 154                                 .ops = &qcom_geni_uart_pops,
 155                                 .flags = UPF_BOOT_AUTOCONF,
 156                                 .line = 1,
 157                 },
 158         },
 159         [2] = {
 160                 .uport = {
 161                                 .iotype = UPIO_MEM,
 162                                 .ops = &qcom_geni_uart_pops,
 163                                 .flags = UPF_BOOT_AUTOCONF,
 164                                 .line = 2,
 165                 },
 166         },
 167 };
 168
 169 static struct qcom_geni_serial_port qcom_geni_console_port = {
 170         .uport = {
 171                 .iotype = UPIO_MEM,
 172                 .ops = &qcom_geni_console_pops,
 173                 .flags = UPF_BOOT_AUTOCONF,
 174                 .line = 0,
 175         },
 176 };
 177
 178 static int qcom_geni_serial_request_port(struct uart_port *uport)
 179 {
 180         struct platform_device *pdev = to_platform_device(uport->dev);
 181         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 182
 183         uport->membase = devm_platform_ioremap_resource(pdev, 0);
 184         if (IS_ERR(uport->membase))
 185                 return PTR_ERR(uport->membase);
 186         port->se.base = uport->membase;
 187         return 0;
 188 }
 189
 190 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 191 {
 192         if (cfg_flags & UART_CONFIG_TYPE) {
 193                 uport->type = PORT_MSM;
 194                 qcom_geni_serial_request_port(uport);
 195         }
 196 }
 197
 198 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 199 {
 200         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 201         u32 geni_ios;
 202
 203         if (uart_console(uport)) {
 204                 mctrl |= TIOCM_CTS;
 205         } else {
 206                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 207                 if (!(geni_ios & IO2_DATA_IN))
 208                         mctrl |= TIOCM_CTS;
 209         }
 210
 211         return mctrl;
 212 }
 213
 214 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 215                                                         unsigned int mctrl)
 216 {
 217         u32 uart_manual_rfr = 0;
 218         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 219
 220         if (uart_console(uport))
 221                 return;
 222
 223         if (mctrl & TIOCM_LOOP)
 224                 port->loopback = RX_TX_CTS_RTS_SORTED;
 225
 226         if (!(mctrl & TIOCM_RTS))
 227                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 228         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 229 }
 230
 231 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 232 {
 233         return "MSM";
 234 }
 235
 236 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 237 {
 238         struct qcom_geni_serial_port *port;
 239         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 240
 241         if (line < 0 || line >= nr_ports)
 242                 return ERR_PTR(-ENXIO);
 243
 244         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 245         return port;
 246 }
 247
 248 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 249                                 int offset, int field, bool set)
 250 {
 251         u32 reg;
 252         struct qcom_geni_serial_port *port;
 253         unsigned int baud;
 254         unsigned int fifo_bits;
 255         unsigned long timeout_us = 20000;
 256
 257         if (uport->private_data) {
 258                 port = to_dev_port(uport, uport);
 259                 baud = port->baud;
 260                 if (!baud)
 261                         baud = 115200;
 262                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 263                 /*
 264                  * Total polling iterations based on FIFO worth of bytes to be
 265                  * sent at current baud. Add a little fluff to the wait.
 266                  */
 267                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 268         }
 269
 270         /*
 271          * Use custom implementation instead of readl_poll_atomic since ktimer
 272          * is not ready at the time of early console.
 273          */
 274         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 275         while (timeout_us) {
 276                 reg = readl(uport->membase + offset);
 277                 if ((bool)(reg & field) == set)
 278                         return true;
 279                 udelay(10);
 280                 timeout_us -= 10;
 281         }
 282         return false;
 283 }
 284
 285 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 286 {
 287         u32 m_cmd;
 288
 289         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 290         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 291         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 292 }
 293
 294 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 295 {
 296         int done;
 297         u32 irq_clear = M_CMD_DONE_EN;
 298
 299         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 300                                                 M_CMD_DONE_EN, true);
 301         if (!done) {
 302                 writel(M_GENI_CMD_ABORT, uport->membase +
 303                                                 SE_GENI_M_CMD_CTRL_REG);
 304                 irq_clear |= M_CMD_ABORT_EN;
 305                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 306                                                         M_CMD_ABORT_EN, true);
 307         }
 308         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 309 }
 310
 311 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 312 {
 313         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 314
 315         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 316         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 317                                         S_GENI_CMD_ABORT, false);
 318         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 319         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 320 }
 321
 322 #ifdef CONFIG_CONSOLE_POLL
 323 static int qcom_geni_serial_get_char(struct uart_port *uport)
 324 {
 325         u32 rx_fifo;
 326         u32 status;
 327
 328         status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 329         writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 330
 331         status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 332         writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 333
 334         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 335         if (!(status & RX_FIFO_WC_MSK))
 336                 return NO_POLL_CHAR;
 337
 338         rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
 339         return rx_fifo & 0xff;
 340 }
 341
 342 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 343                                                         unsigned char c)
 344 {
 345         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 346         qcom_geni_serial_setup_tx(uport, 1);
 347         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 348                                                 M_TX_FIFO_WATERMARK_EN, true));
 349         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 350         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 351         qcom_geni_serial_poll_tx_done(uport);
 352 }
 353 #endif
 354
 355 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 356 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 357 {
 358         writel(ch, uport->membase + SE_GENI_TX_FIFOn);
 359 }
 360
 361 static void
 362 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 363                                  unsigned int count)
 364 {
 365         int i;
 366         u32 bytes_to_send = count;
 367
 368         for (i = 0; i < count; i++) {
 369                 /*
 370                  * uart_console_write() adds a carriage return for each newline.
 371                  * Account for additional bytes to be written.
 372                  */
 373                 if (s[i] == '\n')
 374                         bytes_to_send++;
 375         }
 376
 377         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 378         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 379         for (i = 0; i < count; ) {
 380                 size_t chars_to_write = 0;
 381                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 382
 383                 /*
 384                  * If the WM bit never set, then the Tx state machine is not
 385                  * in a valid state, so break, cancel/abort any existing
 386                  * command. Unfortunately the current data being written is
 387                  * lost.
 388                  */
 389                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 390                                                 M_TX_FIFO_WATERMARK_EN, true))
 391                         break;
 392                 chars_to_write = min_t(size_t, count - i, avail / 2);
 393                 uart_console_write(uport, s + i, chars_to_write,
 394                                                 qcom_geni_serial_wr_char);
 395                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 396                                                         SE_GENI_M_IRQ_CLEAR);
 397                 i += chars_to_write;
 398         }
 399         qcom_geni_serial_poll_tx_done(uport);
 400 }
 401
 402 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 403                               unsigned int count)
 404 {
 405         struct uart_port *uport;
 406         struct qcom_geni_serial_port *port;
 407         bool locked = true;
 408         unsigned long flags;
 409         u32 geni_status;
 410         u32 irq_en;
 411
 412         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 413
 414         port = get_port_from_line(co->index, true);
 415         if (IS_ERR(port))
 416                 return;
 417
 418         uport = &port->uport;
 419         if (oops_in_progress)
 420                 locked = spin_trylock_irqsave(&uport->lock, flags);
 421         else
 422                 spin_lock_irqsave(&uport->lock, flags);
 423
 424         geni_status = readl(uport->membase + SE_GENI_STATUS);
 425
 426         /* Cancel the current write to log the fault */
 427         if (!locked) {
 428                 geni_se_cancel_m_cmd(&port->se);
 429                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 430                                                 M_CMD_CANCEL_EN, true)) {
 431                         geni_se_abort_m_cmd(&port->se);
 432                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 433                                                         M_CMD_ABORT_EN, true);
 434                         writel(M_CMD_ABORT_EN, uport->membase +
 435                                                         SE_GENI_M_IRQ_CLEAR);
 436                 }
 437                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 438         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 439                 /*
 440                  * It seems we can't interrupt existing transfers if all data
 441                  * has been sent, in which case we need to look for done first.
 442                  */
 443                 qcom_geni_serial_poll_tx_done(uport);
 444
 445                 if (uart_circ_chars_pending(&uport->state->xmit)) {
 446                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 447                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 448                                         uport->membase + SE_GENI_M_IRQ_EN);
 449                 }
 450         }
 451
 452         __qcom_geni_serial_console_write(uport, s, count);
 453
 454         if (port->tx_remaining)
 455                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 456
 457         if (locked)
 458                 spin_unlock_irqrestore(&uport->lock, flags);
 459 }
 460
 461 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 462 {
 463         u32 i;
 464         unsigned char buf[sizeof(u32)];
 465         struct tty_port *tport;
 466         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 467
 468         tport = &uport->state->port;
 469         for (i = 0; i < bytes; ) {
 470                 int c;
 471                 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
 472
 473                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 474                 i += chunk;
 475                 if (drop)
 476                         continue;
 477
 478                 for (c = 0; c < chunk; c++) {
 479                         int sysrq;
 480
 481                         uport->icount.rx++;
 482                         if (port->brk && buf[c] == 0) {
 483                                 port->brk = false;
 484                                 if (uart_handle_break(uport))
 485                                         continue;
 486                         }
 487
 488                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 489
 490                         if (!sysrq)
 491                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 492                 }
 493         }
 494         if (!drop)
 495                 tty_flip_buffer_push(tport);
 496         return 0;
 497 }
 498 #else
 499 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 500 {
 501         return -EPERM;
 502 }
 503
 504 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 505
 506 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 507 {
 508         unsigned char *buf;
 509         struct tty_port *tport;
 510         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 511         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 512         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 513         int ret;
 514
 515         tport = &uport->state->port;
 516         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 517         if (drop)
 518                 return 0;
 519
 520         buf = (unsigned char *)port->rx_fifo;
 521         ret = tty_insert_flip_string(tport, buf, bytes);
 522         if (ret != bytes) {
 523                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 524                                 __func__, ret, bytes);
 525                 WARN_ON_ONCE(1);
 526         }
 527         uport->icount.rx += ret;
 528         tty_flip_buffer_push(tport);
 529         return ret;
 530 }
 531
 532 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 533 {
 534         u32 irq_en;
 535         u32 status;
 536
 537         status = readl(uport->membase + SE_GENI_STATUS);
 538         if (status & M_GENI_CMD_ACTIVE)
 539                 return;
 540
 541         if (!qcom_geni_serial_tx_empty(uport))
 542                 return;
 543
 544         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 545         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 546
 547         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 548         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 549 }
 550
 551 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 552 {
 553         u32 irq_en;
 554         u32 status;
 555         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 556
 557         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 558         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 559         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 560         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 561         status = readl(uport->membase + SE_GENI_STATUS);
 562         /* Possible stop tx is called multiple times. */
 563         if (!(status & M_GENI_CMD_ACTIVE))
 564                 return;
 565
 566         geni_se_cancel_m_cmd(&port->se);
 567         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 568                                                 M_CMD_CANCEL_EN, true)) {
 569                 geni_se_abort_m_cmd(&port->se);
 570                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 571                                                 M_CMD_ABORT_EN, true);
 572                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 573         }
 574         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 575 }
 576
 577 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 578 {
 579         u32 irq_en;
 580         u32 status;
 581         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 582
 583         status = readl(uport->membase + SE_GENI_STATUS);
 584         if (status & S_GENI_CMD_ACTIVE)
 585                 qcom_geni_serial_stop_rx(uport);
 586
 587         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 588
 589         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 590         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 591         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 592
 593         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 594         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 595         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 596 }
 597
 598 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 599 {
 600         u32 irq_en;
 601         u32 status;
 602         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 603         u32 s_irq_status;
 604
 605         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 606         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 607         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 608
 609         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 610         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 611         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 612
 613         status = readl(uport->membase + SE_GENI_STATUS);
 614         /* Possible stop rx is called multiple times. */
 615         if (!(status & S_GENI_CMD_ACTIVE))
 616                 return;
 617
 618         geni_se_cancel_s_cmd(&port->se);
 619         qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 620                                         S_CMD_CANCEL_EN, true);
 621         /*
 622          * If timeout occurs secondary engine remains active
 623          * and Abort sequence is executed.
 624          */
 625         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 626         /* Flush the Rx buffer */
 627         if (s_irq_status & S_RX_FIFO_LAST_EN)
 628                 qcom_geni_serial_handle_rx(uport, true);
 629         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 630
 631         status = readl(uport->membase + SE_GENI_STATUS);
 632         if (status & S_GENI_CMD_ACTIVE)
 633                 qcom_geni_serial_abort_rx(uport);
 634 }
 635
 636 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 637 {
 638         u32 status;
 639         u32 word_cnt;
 640         u32 last_word_byte_cnt;
 641         u32 last_word_partial;
 642         u32 total_bytes;
 643         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 644
 645         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 646         word_cnt = status & RX_FIFO_WC_MSK;
 647         last_word_partial = status & RX_LAST;
 648         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 649                                                 RX_LAST_BYTE_VALID_SHFT;
 650
 651         if (!word_cnt)
 652                 return;
 653         total_bytes = port->rx_bytes_pw * (word_cnt - 1);
 654         if (last_word_partial && last_word_byte_cnt)
 655                 total_bytes += last_word_byte_cnt;
 656         else
 657                 total_bytes += port->rx_bytes_pw;
 658         port->handle_rx(uport, total_bytes, drop);
 659 }
 660
 661 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 662                 bool active)
 663 {
 664         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 665         struct circ_buf *xmit = &uport->state->xmit;
 666         size_t avail;
 667         size_t remaining;
 668         size_t pending;
 669         int i;
 670         u32 status;
 671         u32 irq_en;
 672         unsigned int chunk;
 673         int tail;
 674
 675         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 676
 677         /* Complete the current tx command before taking newly added data */
 678         if (active)
 679                 pending = port->tx_remaining;
 680         else
 681                 pending = uart_circ_chars_pending(xmit);
 682
 683         /* All data has been transmitted and acknowledged as received */
 684         if (!pending && !status && done) {
 685                 qcom_geni_serial_stop_tx(uport);
 686                 goto out_write_wakeup;
 687         }
 688
 689         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 690         avail *= port->tx_bytes_pw;
 691
 692         tail = xmit->tail;
 693         chunk = min(avail, pending);
 694         if (!chunk)
 695                 goto out_write_wakeup;
 696
 697         if (!port->tx_remaining) {
 698                 qcom_geni_serial_setup_tx(uport, pending);
 699                 port->tx_remaining = pending;
 700
 701                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 702                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 703                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 704                                         uport->membase + SE_GENI_M_IRQ_EN);
 705         }
 706
 707         remaining = chunk;
 708         for (i = 0; i < chunk; ) {
 709                 unsigned int tx_bytes;
 710                 u8 buf[sizeof(u32)];
 711                 int c;
 712
 713                 memset(buf, 0, ARRAY_SIZE(buf));
 714                 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
 715
 716                 for (c = 0; c < tx_bytes ; c++) {
 717                         buf[c] = xmit->buf[tail++];
 718                         tail &= UART_XMIT_SIZE - 1;
 719                 }
 720
 721                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 722
 723                 i += tx_bytes;
 724                 uport->icount.tx += tx_bytes;
 725                 remaining -= tx_bytes;
 726                 port->tx_remaining -= tx_bytes;
 727         }
 728
 729         xmit->tail = tail;
 730
 731         /*
 732          * The tx fifo watermark is level triggered and latched. Though we had
 733          * cleared it in qcom_geni_serial_isr it will have already reasserted
 734          * so we must clear it again here after our writes.
 735          */
 736         writel(M_TX_FIFO_WATERMARK_EN,
 737                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 738
 739 out_write_wakeup:
 740         if (!port->tx_remaining) {
 741                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 742                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 743                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 744                                         uport->membase + SE_GENI_M_IRQ_EN);
 745         }
 746
 747         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 748                 uart_write_wakeup(uport);
 749 }
 750
 751 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 752 {
 753         u32 m_irq_en;
 754         u32 m_irq_status;
 755         u32 s_irq_status;
 756         u32 geni_status;
 757         struct uart_port *uport = dev;
 758         unsigned long flags;
 759         bool drop_rx = false;
 760         struct tty_port *tport = &uport->state->port;
 761         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 762
 763         if (uport->suspended)
 764                 return IRQ_NONE;
 765
 766         spin_lock_irqsave(&uport->lock, flags);
 767         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 768         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 769         geni_status = readl(uport->membase + SE_GENI_STATUS);
 770         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 771         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 772         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 773
 774         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 775                 goto out_unlock;
 776
 777         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 778                 uport->icount.overrun++;
 779                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 780         }
 781
 782         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 783                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 784                                         geni_status & M_GENI_CMD_ACTIVE);
 785
 786         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 787                 if (s_irq_status & S_GP_IRQ_0_EN)
 788                         uport->icount.parity++;
 789                 drop_rx = true;
 790         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 791                                         s_irq_status & S_GP_IRQ_3_EN) {
 792                 uport->icount.brk++;
 793                 port->brk = true;
 794         }
 795
 796         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 797                                         s_irq_status & S_RX_FIFO_LAST_EN)
 798                 qcom_geni_serial_handle_rx(uport, drop_rx);
 799
 800 out_unlock:
 801         uart_unlock_and_check_sysrq(uport, flags);
 802
 803         return IRQ_HANDLED;
 804 }
 805
 806 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 807 {
 808         struct uart_port *uport;
 809
 810         uport = &port->uport;
 811         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 812         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 813         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 814         uport->fifosize =
 815                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 816 }
 817
 818
 819 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 820 {
 821         unsigned long flags;
 822
 823         /* Stop the console before stopping the current tx */
 824         if (uart_console(uport))
 825                 console_stop(uport->cons);
 826
 827         disable_irq(uport->irq);
 828         spin_lock_irqsave(&uport->lock, flags);
 829         qcom_geni_serial_stop_tx(uport);
 830         qcom_geni_serial_stop_rx(uport);
 831         spin_unlock_irqrestore(&uport->lock, flags);
 832 }
 833
 834 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 835 {
 836         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 837         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 838         u32 proto;
 839
 840         if (uart_console(uport)) {
 841                 port->tx_bytes_pw = 1;
 842                 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
 843         } else {
 844                 port->tx_bytes_pw = 4;
 845                 port->rx_bytes_pw = 4;
 846         }
 847
 848         proto = geni_se_read_proto(&port->se);
 849         if (proto != GENI_SE_UART) {
 850                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 851                 return -ENXIO;
 852         }
 853
 854         qcom_geni_serial_stop_rx(uport);
 855
 856         get_tx_fifo_size(port);
 857
 858         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 859         /*
 860          * Make an unconditional cancel on the main sequencer to reset
 861          * it else we could end up in data loss scenarios.
 862          */
 863         if (uart_console(uport))
 864                 qcom_geni_serial_poll_tx_done(uport);
 865         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
 866                                                 false, true, false);
 867         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
 868                                                 false, false, true);
 869         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 870         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 871         if (!uart_console(uport)) {
 872                 port->rx_fifo = devm_kcalloc(uport->dev,
 873                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
 874                 if (!port->rx_fifo)
 875                         return -ENOMEM;
 876         }
 877         port->setup = true;
 878
 879         return 0;
 880 }
 881
 882 static int qcom_geni_serial_startup(struct uart_port *uport)
 883 {
 884         int ret;
 885         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 886
 887         if (!port->setup) {
 888                 ret = qcom_geni_serial_port_setup(uport);
 889                 if (ret)
 890                         return ret;
 891         }
 892         enable_irq(uport->irq);
 893
 894         return 0;
 895 }
 896
 897 static unsigned long get_clk_cfg(unsigned long clk_freq)
 898 {
 899         int i;
 900
 901         for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 902                 if (!(root_freq[i] % clk_freq))
 903                         return root_freq[i];
 904         }
 905         return 0;
 906 }
 907
 908 static unsigned long get_clk_div_rate(unsigned int baud,
 909                         unsigned int sampling_rate, unsigned int *clk_div)
 910 {
 911         unsigned long ser_clk;
 912         unsigned long desired_clk;
 913
 914         desired_clk = baud * sampling_rate;
 915         ser_clk = get_clk_cfg(desired_clk);
 916         if (!ser_clk) {
 917                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 918                                                                 __func__, baud);
 919                 return ser_clk;
 920         }
 921
 922         *clk_div = ser_clk / desired_clk;
 923         return ser_clk;
 924 }
 925
 926 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 927                                 struct ktermios *termios, struct ktermios *old)
 928 {
 929         unsigned int baud;
 930         u32 bits_per_char;
 931         u32 tx_trans_cfg;
 932         u32 tx_parity_cfg;
 933         u32 rx_trans_cfg;
 934         u32 rx_parity_cfg;
 935         u32 stop_bit_len;
 936         unsigned int clk_div;
 937         u32 ser_clk_cfg;
 938         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 939         unsigned long clk_rate;
 940         u32 ver, sampling_rate;
 941
 942         qcom_geni_serial_stop_rx(uport);
 943         /* baud rate */
 944         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 945         port->baud = baud;
 946
 947         sampling_rate = UART_OVERSAMPLING;
 948         /* Sampling rate is halved for IP versions >= 2.5 */
 949         ver = geni_se_get_qup_hw_version(&port->se);
 950         if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
 951                 sampling_rate /= 2;
 952
 953         clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
 954         if (!clk_rate)
 955                 goto out_restart_rx;
 956
 957         uport->uartclk = clk_rate;
 958         clk_set_rate(port->se.clk, clk_rate);
 959         ser_clk_cfg = SER_CLK_EN;
 960         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 961
 962         /* parity */
 963         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
 964         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
 965         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
 966         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
 967         if (termios->c_cflag & PARENB) {
 968                 tx_trans_cfg |= UART_TX_PAR_EN;
 969                 rx_trans_cfg |= UART_RX_PAR_EN;
 970                 tx_parity_cfg |= PAR_CALC_EN;
 971                 rx_parity_cfg |= PAR_CALC_EN;
 972                 if (termios->c_cflag & PARODD) {
 973                         tx_parity_cfg |= PAR_ODD;
 974                         rx_parity_cfg |= PAR_ODD;
 975                 } else if (termios->c_cflag & CMSPAR) {
 976                         tx_parity_cfg |= PAR_SPACE;
 977                         rx_parity_cfg |= PAR_SPACE;
 978                 } else {
 979                         tx_parity_cfg |= PAR_EVEN;
 980                         rx_parity_cfg |= PAR_EVEN;
 981                 }
 982         } else {
 983                 tx_trans_cfg &= ~UART_TX_PAR_EN;
 984                 rx_trans_cfg &= ~UART_RX_PAR_EN;
 985                 tx_parity_cfg &= ~PAR_CALC_EN;
 986                 rx_parity_cfg &= ~PAR_CALC_EN;
 987         }
 988
 989         /* bits per char */
 990         switch (termios->c_cflag & CSIZE) {
 991         case CS5:
 992                 bits_per_char = 5;
 993                 break;
 994         case CS6:
 995                 bits_per_char = 6;
 996                 break;
 997         case CS7:
 998                 bits_per_char = 7;
 999                 break;
1000         case CS8:
1001         default:
1002                 bits_per_char = 8;
1003                 break;
1004         }
1005
1006         /* stop bits */
1007         if (termios->c_cflag & CSTOPB)
1008                 stop_bit_len = TX_STOP_BIT_LEN_2;
1009         else
1010                 stop_bit_len = TX_STOP_BIT_LEN_1;
1011
1012         /* flow control, clear the CTS_MASK bit if using flow control. */
1013         if (termios->c_cflag & CRTSCTS)
1014                 tx_trans_cfg &= ~UART_CTS_MASK;
1015         else
1016                 tx_trans_cfg |= UART_CTS_MASK;
1017
1018         if (baud)
1019                 uart_update_timeout(uport, termios->c_cflag, baud);
1020
1021         if (!uart_console(uport))
1022                 writel(port->loopback,
1023                                 uport->membase + SE_UART_LOOPBACK_CFG);
1024         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1025         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1026         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1027         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1028         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1029         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1030         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1031         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1032         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1033 out_restart_rx:
1034         qcom_geni_serial_start_rx(uport);
1035 }
1036
1037 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1038 {
1039         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1040 }
1041
1042 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1043 static int __init qcom_geni_console_setup(struct console *co, char *options)
1044 {
1045         struct uart_port *uport;
1046         struct qcom_geni_serial_port *port;
1047         int baud = 9600;
1048         int bits = 8;
1049         int parity = 'n';
1050         int flow = 'n';
1051         int ret;
1052
1053         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1054                 return -ENXIO;
1055
1056         port = get_port_from_line(co->index, true);
1057         if (IS_ERR(port)) {
1058                 pr_err("Invalid line %d\n", co->index);
1059                 return PTR_ERR(port);
1060         }
1061
1062         uport = &port->uport;
1063
1064         if (unlikely(!uport->membase))
1065                 return -ENXIO;
1066
1067         if (!port->setup) {
1068                 ret = qcom_geni_serial_port_setup(uport);
1069                 if (ret)
1070                         return ret;
1071         }
1072
1073         if (options)
1074                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1075
1076         return uart_set_options(uport, co, baud, parity, bits, flow);
1077 }
1078
1079 static void qcom_geni_serial_earlycon_write(struct console *con,
1080                                         const char *s, unsigned int n)
1081 {
1082         struct earlycon_device *dev = con->data;
1083
1084         __qcom_geni_serial_console_write(&dev->port, s, n);
1085 }
1086
1087 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1088                                                                 const char *opt)
1089 {
1090         struct uart_port *uport = &dev->port;
1091         u32 tx_trans_cfg;
1092         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1093         u32 rx_trans_cfg = 0;
1094         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1095         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1096         u32 bits_per_char;
1097         struct geni_se se;
1098
1099         if (!uport->membase)
1100                 return -EINVAL;
1101
1102         memset(&se, 0, sizeof(se));
1103         se.base = uport->membase;
1104         if (geni_se_read_proto(&se) != GENI_SE_UART)
1105                 return -ENXIO;
1106         /*
1107          * Ignore Flow control.
1108          * n = 8.
1109          */
1110         tx_trans_cfg = UART_CTS_MASK;
1111         bits_per_char = BITS_PER_BYTE;
1112
1113         /*
1114          * Make an unconditional cancel on the main sequencer to reset
1115          * it else we could end up in data loss scenarios.
1116          */
1117         qcom_geni_serial_poll_tx_done(uport);
1118         qcom_geni_serial_abort_rx(uport);
1119         geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1120         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1121         geni_se_select_mode(&se, GENI_SE_FIFO);
1122
1123         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1124         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1125         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1126         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1127         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1128         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1129         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1130
1131         dev->con->write = qcom_geni_serial_earlycon_write;
1132         dev->con->setup = NULL;
1133         return 0;
1134 }
1135 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1136                                 qcom_geni_serial_earlycon_setup);
1137
1138 static int __init console_register(struct uart_driver *drv)
1139 {
1140         return uart_register_driver(drv);
1141 }
1142
1143 static void console_unregister(struct uart_driver *drv)
1144 {
1145         uart_unregister_driver(drv);
1146 }
1147
1148 static struct console cons_ops = {
1149         .name = "ttyMSM",
1150         .write = qcom_geni_serial_console_write,
1151         .device = uart_console_device,
1152         .setup = qcom_geni_console_setup,
1153         .flags = CON_PRINTBUFFER,
1154         .index = -1,
1155         .data = &qcom_geni_console_driver,
1156 };
1157
1158 static struct uart_driver qcom_geni_console_driver = {
1159         .owner = THIS_MODULE,
1160         .driver_name = "qcom_geni_console",
1161         .dev_name = "ttyMSM",
1162         .nr =  GENI_UART_CONS_PORTS,
1163         .cons = &cons_ops,
1164 };
1165 #else
1166 static int console_register(struct uart_driver *drv)
1167 {
1168         return 0;
1169 }
1170
1171 static void console_unregister(struct uart_driver *drv)
1172 {
1173 }
1174 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1175
1176 static struct uart_driver qcom_geni_uart_driver = {
1177         .owner = THIS_MODULE,
1178         .driver_name = "qcom_geni_uart",
1179         .dev_name = "ttyHS",
1180         .nr =  GENI_UART_PORTS,
1181 };
1182
1183 static void qcom_geni_serial_pm(struct uart_port *uport,
1184                 unsigned int new_state, unsigned int old_state)
1185 {
1186         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1187
1188         /* If we've never been called, treat it as off */
1189         if (old_state == UART_PM_STATE_UNDEFINED)
1190                 old_state = UART_PM_STATE_OFF;
1191
1192         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1193                 geni_se_resources_on(&port->se);
1194         else if (new_state == UART_PM_STATE_OFF &&
1195                         old_state == UART_PM_STATE_ON)
1196                 geni_se_resources_off(&port->se);
1197 }
1198
1199 static const struct uart_ops qcom_geni_console_pops = {
1200         .tx_empty = qcom_geni_serial_tx_empty,
1201         .stop_tx = qcom_geni_serial_stop_tx,
1202         .start_tx = qcom_geni_serial_start_tx,
1203         .stop_rx = qcom_geni_serial_stop_rx,
1204         .set_termios = qcom_geni_serial_set_termios,
1205         .startup = qcom_geni_serial_startup,
1206         .request_port = qcom_geni_serial_request_port,
1207         .config_port = qcom_geni_serial_config_port,
1208         .shutdown = qcom_geni_serial_shutdown,
1209         .type = qcom_geni_serial_get_type,
1210         .set_mctrl = qcom_geni_serial_set_mctrl,
1211         .get_mctrl = qcom_geni_serial_get_mctrl,
1212 #ifdef CONFIG_CONSOLE_POLL
1213         .poll_get_char  = qcom_geni_serial_get_char,
1214         .poll_put_char  = qcom_geni_serial_poll_put_char,
1215 #endif
1216         .pm = qcom_geni_serial_pm,
1217 };
1218
1219 static const struct uart_ops qcom_geni_uart_pops = {
1220         .tx_empty = qcom_geni_serial_tx_empty,
1221         .stop_tx = qcom_geni_serial_stop_tx,
1222         .start_tx = qcom_geni_serial_start_tx,
1223         .stop_rx = qcom_geni_serial_stop_rx,
1224         .set_termios = qcom_geni_serial_set_termios,
1225         .startup = qcom_geni_serial_startup,
1226         .request_port = qcom_geni_serial_request_port,
1227         .config_port = qcom_geni_serial_config_port,
1228         .shutdown = qcom_geni_serial_shutdown,
1229         .type = qcom_geni_serial_get_type,
1230         .set_mctrl = qcom_geni_serial_set_mctrl,
1231         .get_mctrl = qcom_geni_serial_get_mctrl,
1232         .pm = qcom_geni_serial_pm,
1233 };
1234
1235 static int qcom_geni_serial_probe(struct platform_device *pdev)
1236 {
1237         int ret = 0;
1238         int line = -1;
1239         struct qcom_geni_serial_port *port;
1240         struct uart_port *uport;
1241         struct resource *res;
1242         int irq;
1243         bool console = false;
1244         struct uart_driver *drv;
1245
1246         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1247                 console = true;
1248
1249         if (console) {
1250                 drv = &qcom_geni_console_driver;
1251                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1252         } else {
1253                 drv = &qcom_geni_uart_driver;
1254                 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1255         }
1256
1257         port = get_port_from_line(line, console);
1258         if (IS_ERR(port)) {
1259                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1260                 return PTR_ERR(port);
1261         }
1262
1263         uport = &port->uport;
1264         /* Don't allow 2 drivers to access the same port */
1265         if (uport->private_data)
1266                 return -ENODEV;
1267
1268         uport->dev = &pdev->dev;
1269         port->se.dev = &pdev->dev;
1270         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1271         port->se.clk = devm_clk_get(&pdev->dev, "se");
1272         if (IS_ERR(port->se.clk)) {
1273                 ret = PTR_ERR(port->se.clk);
1274                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1275                 return ret;
1276         }
1277
1278         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1279         if (!res)
1280                 return -EINVAL;
1281         uport->mapbase = res->start;
1282
1283         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1284         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1285         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1286
1287         port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1288                         "qcom_geni_serial_%s%d",
1289                         uart_console(uport) ? "console" : "uart", uport->line);
1290         if (!port->name)
1291                 return -ENOMEM;
1292
1293         irq = platform_get_irq(pdev, 0);
1294         if (irq < 0)
1295                 return irq;
1296         uport->irq = irq;
1297         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1298
1299         if (!console)
1300                 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1301
1302         uport->private_data = drv;
1303         platform_set_drvdata(pdev, port);
1304         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1305
1306         ret = uart_add_one_port(drv, uport);
1307         if (ret)
1308                 return ret;
1309
1310         irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1311         ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1312                         IRQF_TRIGGER_HIGH, port->name, uport);
1313         if (ret) {
1314                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1315                 uart_remove_one_port(drv, uport);
1316                 return ret;
1317         }
1318
1319         /*
1320          * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1321          * enabled/disabled from dev_pm_arm_wake_irq during system
1322          * suspend/resume respectively.
1323          */
1324         pm_runtime_set_active(&pdev->dev);
1325
1326         if (port->wakeup_irq > 0) {
1327                 device_init_wakeup(&pdev->dev, true);
1328                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1329                                                 port->wakeup_irq);
1330                 if (ret) {
1331                         device_init_wakeup(&pdev->dev, false);
1332                         uart_remove_one_port(drv, uport);
1333                         return ret;
1334                 }
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int qcom_geni_serial_remove(struct platform_device *pdev)
1341 {
1342         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1343         struct uart_driver *drv = port->uport.private_data;
1344
1345         dev_pm_clear_wake_irq(&pdev->dev);
1346         device_init_wakeup(&pdev->dev, false);
1347         uart_remove_one_port(drv, &port->uport);
1348
1349         return 0;
1350 }
1351
1352 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1353 {
1354         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1355         struct uart_port *uport = &port->uport;
1356
1357         return uart_suspend_port(uport->private_data, uport);
1358 }
1359
1360 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1361 {
1362         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1363         struct uart_port *uport = &port->uport;
1364
1365         return uart_resume_port(uport->private_data, uport);
1366 }
1367
1368 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1369         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1370                                         qcom_geni_serial_sys_resume)
1371 };
1372
1373 static const struct of_device_id qcom_geni_serial_match_table[] = {
1374         { .compatible = "qcom,geni-debug-uart", },
1375         { .compatible = "qcom,geni-uart", },
1376         {}
1377 };
1378 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1379
1380 static struct platform_driver qcom_geni_serial_platform_driver = {
1381         .remove = qcom_geni_serial_remove,
1382         .probe = qcom_geni_serial_probe,
1383         .driver = {
1384                 .name = "qcom_geni_serial",
1385                 .of_match_table = qcom_geni_serial_match_table,
1386                 .pm = &qcom_geni_serial_pm_ops,
1387         },
1388 };
1389
1390 static int __init qcom_geni_serial_init(void)
1391 {
1392         int ret;
1393
1394         ret = console_register(&qcom_geni_console_driver);
1395         if (ret)
1396                 return ret;
1397
1398         ret = uart_register_driver(&qcom_geni_uart_driver);
1399         if (ret) {
1400                 console_unregister(&qcom_geni_console_driver);
1401                 return ret;
1402         }
1403
1404         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1405         if (ret) {
1406                 console_unregister(&qcom_geni_console_driver);
1407                 uart_unregister_driver(&qcom_geni_uart_driver);
1408         }
1409         return ret;
1410 }
1411 module_init(qcom_geni_serial_init);
1412
1413 static void __exit qcom_geni_serial_exit(void)
1414 {
1415         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1416         console_unregister(&qcom_geni_console_driver);
1417         uart_unregister_driver(&qcom_geni_uart_driver);
1418 }
1419 module_exit(qcom_geni_serial_exit);
1420
1421 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1422 MODULE_LICENSE("GPL v2");