1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi Owl family serial console
5 * Copyright 2013 Actions Semi Inc.
6 * Author: Actions Semi, Inc.
8 * Copyright (c) 2016-2017 Andreas Färber
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/delay.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial.h>
19 #include <linux/serial_core.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
23 #define OWL_UART_PORT_NUM 7
24 #define OWL_UART_DEV_NAME "ttyOWL"
26 #define OWL_UART_CTL 0x000
27 #define OWL_UART_RXDAT 0x004
28 #define OWL_UART_TXDAT 0x008
29 #define OWL_UART_STAT 0x00c
31 #define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
32 #define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
33 #define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
34 #define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
35 #define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
36 #define OWL_UART_CTL_STPS_2BITS BIT(2)
37 #define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
38 #define OWL_UART_CTL_PRS_NONE (0x0 << 4)
39 #define OWL_UART_CTL_PRS_ODD (0x4 << 4)
40 #define OWL_UART_CTL_PRS_MARK (0x5 << 4)
41 #define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
42 #define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
43 #define OWL_UART_CTL_AFE BIT(12)
44 #define OWL_UART_CTL_TRFS_TX BIT(14)
45 #define OWL_UART_CTL_EN BIT(15)
46 #define OWL_UART_CTL_RXDE BIT(16)
47 #define OWL_UART_CTL_TXDE BIT(17)
48 #define OWL_UART_CTL_RXIE BIT(18)
49 #define OWL_UART_CTL_TXIE BIT(19)
50 #define OWL_UART_CTL_LBEN BIT(20)
52 #define OWL_UART_STAT_RIP BIT(0)
53 #define OWL_UART_STAT_TIP BIT(1)
54 #define OWL_UART_STAT_RXER BIT(2)
55 #define OWL_UART_STAT_TFER BIT(3)
56 #define OWL_UART_STAT_RXST BIT(4)
57 #define OWL_UART_STAT_RFEM BIT(5)
58 #define OWL_UART_STAT_TFFU BIT(6)
59 #define OWL_UART_STAT_CTSS BIT(7)
60 #define OWL_UART_STAT_RTSS BIT(8)
61 #define OWL_UART_STAT_TFES BIT(10)
62 #define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
63 #define OWL_UART_STAT_UTBB BIT(17)
65 static struct uart_driver owl_uart_driver;
67 struct owl_uart_info {
68 unsigned int tx_fifosize;
71 struct owl_uart_port {
72 struct uart_port port;
76 #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
78 static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
80 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
82 writel(val, port->membase + off);
85 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
87 return readl(port->membase + off);
90 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
94 ctl = owl_uart_read(port, OWL_UART_CTL);
96 if (mctrl & TIOCM_LOOP)
97 ctl |= OWL_UART_CTL_LBEN;
99 ctl &= ~OWL_UART_CTL_LBEN;
101 owl_uart_write(port, ctl, OWL_UART_CTL);
104 static unsigned int owl_uart_get_mctrl(struct uart_port *port)
106 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
109 ctl = owl_uart_read(port, OWL_UART_CTL);
110 stat = owl_uart_read(port, OWL_UART_STAT);
111 if (stat & OWL_UART_STAT_RTSS)
113 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
118 static unsigned int owl_uart_tx_empty(struct uart_port *port)
124 spin_lock_irqsave(&port->lock, flags);
126 val = owl_uart_read(port, OWL_UART_STAT);
127 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
129 spin_unlock_irqrestore(&port->lock, flags);
134 static void owl_uart_stop_rx(struct uart_port *port)
138 val = owl_uart_read(port, OWL_UART_CTL);
139 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
140 owl_uart_write(port, val, OWL_UART_CTL);
142 val = owl_uart_read(port, OWL_UART_STAT);
143 val |= OWL_UART_STAT_RIP;
144 owl_uart_write(port, val, OWL_UART_STAT);
147 static void owl_uart_stop_tx(struct uart_port *port)
151 val = owl_uart_read(port, OWL_UART_CTL);
152 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
153 owl_uart_write(port, val, OWL_UART_CTL);
155 val = owl_uart_read(port, OWL_UART_STAT);
156 val |= OWL_UART_STAT_TIP;
157 owl_uart_write(port, val, OWL_UART_STAT);
160 static void owl_uart_start_tx(struct uart_port *port)
164 if (uart_tx_stopped(port)) {
165 owl_uart_stop_tx(port);
169 val = owl_uart_read(port, OWL_UART_STAT);
170 val |= OWL_UART_STAT_TIP;
171 owl_uart_write(port, val, OWL_UART_STAT);
173 val = owl_uart_read(port, OWL_UART_CTL);
174 val |= OWL_UART_CTL_TXIE;
175 owl_uart_write(port, val, OWL_UART_CTL);
178 static void owl_uart_send_chars(struct uart_port *port)
180 struct circ_buf *xmit = &port->state->xmit;
183 if (uart_tx_stopped(port))
187 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
189 owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
194 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
195 if (uart_circ_empty(xmit))
198 ch = xmit->buf[xmit->tail];
199 owl_uart_write(port, ch, OWL_UART_TXDAT);
200 xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
204 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
205 uart_write_wakeup(port);
207 if (uart_circ_empty(xmit))
208 owl_uart_stop_tx(port);
211 static void owl_uart_receive_chars(struct uart_port *port)
215 val = owl_uart_read(port, OWL_UART_CTL);
216 val &= ~OWL_UART_CTL_TRFS_TX;
217 owl_uart_write(port, val, OWL_UART_CTL);
219 stat = owl_uart_read(port, OWL_UART_STAT);
220 while (!(stat & OWL_UART_STAT_RFEM)) {
221 char flag = TTY_NORMAL;
223 if (stat & OWL_UART_STAT_RXER)
224 port->icount.overrun++;
226 if (stat & OWL_UART_STAT_RXST) {
227 /* We are not able to distinguish the error type. */
229 port->icount.frame++;
231 stat &= port->read_status_mask;
232 if (stat & OWL_UART_STAT_RXST)
237 val = owl_uart_read(port, OWL_UART_RXDAT);
240 if ((stat & port->ignore_status_mask) == 0)
241 tty_insert_flip_char(&port->state->port, val, flag);
243 stat = owl_uart_read(port, OWL_UART_STAT);
246 spin_unlock(&port->lock);
247 tty_flip_buffer_push(&port->state->port);
248 spin_lock(&port->lock);
251 static irqreturn_t owl_uart_irq(int irq, void *dev_id)
253 struct uart_port *port = dev_id;
257 spin_lock_irqsave(&port->lock, flags);
259 stat = owl_uart_read(port, OWL_UART_STAT);
261 if (stat & OWL_UART_STAT_RIP)
262 owl_uart_receive_chars(port);
264 if (stat & OWL_UART_STAT_TIP)
265 owl_uart_send_chars(port);
267 stat = owl_uart_read(port, OWL_UART_STAT);
268 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
269 owl_uart_write(port, stat, OWL_UART_STAT);
271 spin_unlock_irqrestore(&port->lock, flags);
276 static void owl_uart_shutdown(struct uart_port *port)
281 spin_lock_irqsave(&port->lock, flags);
283 val = owl_uart_read(port, OWL_UART_CTL);
284 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
285 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
286 owl_uart_write(port, val, OWL_UART_CTL);
288 spin_unlock_irqrestore(&port->lock, flags);
290 free_irq(port->irq, port);
293 static int owl_uart_startup(struct uart_port *port)
299 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
304 spin_lock_irqsave(&port->lock, flags);
306 val = owl_uart_read(port, OWL_UART_STAT);
307 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
308 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
309 owl_uart_write(port, val, OWL_UART_STAT);
311 val = owl_uart_read(port, OWL_UART_CTL);
312 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
313 val |= OWL_UART_CTL_EN;
314 owl_uart_write(port, val, OWL_UART_CTL);
316 spin_unlock_irqrestore(&port->lock, flags);
321 static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
324 clk_set_rate(owl_port->clk, baud * 8);
327 static void owl_uart_set_termios(struct uart_port *port,
328 struct ktermios *termios,
329 struct ktermios *old)
331 struct owl_uart_port *owl_port = to_owl_uart_port(port);
336 spin_lock_irqsave(&port->lock, flags);
338 ctl = owl_uart_read(port, OWL_UART_CTL);
340 ctl &= ~OWL_UART_CTL_DWLS_MASK;
341 switch (termios->c_cflag & CSIZE) {
343 ctl |= OWL_UART_CTL_DWLS_5BITS;
346 ctl |= OWL_UART_CTL_DWLS_6BITS;
349 ctl |= OWL_UART_CTL_DWLS_7BITS;
353 ctl |= OWL_UART_CTL_DWLS_8BITS;
357 if (termios->c_cflag & CSTOPB)
358 ctl |= OWL_UART_CTL_STPS_2BITS;
360 ctl &= ~OWL_UART_CTL_STPS_2BITS;
362 ctl &= ~OWL_UART_CTL_PRS_MASK;
363 if (termios->c_cflag & PARENB) {
364 if (termios->c_cflag & CMSPAR) {
365 if (termios->c_cflag & PARODD)
366 ctl |= OWL_UART_CTL_PRS_MARK;
368 ctl |= OWL_UART_CTL_PRS_SPACE;
369 } else if (termios->c_cflag & PARODD)
370 ctl |= OWL_UART_CTL_PRS_ODD;
372 ctl |= OWL_UART_CTL_PRS_EVEN;
374 ctl |= OWL_UART_CTL_PRS_NONE;
376 if (termios->c_cflag & CRTSCTS)
377 ctl |= OWL_UART_CTL_AFE;
379 ctl &= ~OWL_UART_CTL_AFE;
381 owl_uart_write(port, ctl, OWL_UART_CTL);
383 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
384 owl_uart_change_baudrate(owl_port, baud);
386 /* Don't rewrite B0 */
387 if (tty_termios_baud_rate(termios))
388 tty_termios_encode_baud_rate(termios, baud, baud);
390 port->read_status_mask |= OWL_UART_STAT_RXER;
391 if (termios->c_iflag & INPCK)
392 port->read_status_mask |= OWL_UART_STAT_RXST;
394 uart_update_timeout(port, termios->c_cflag, baud);
396 spin_unlock_irqrestore(&port->lock, flags);
399 static void owl_uart_release_port(struct uart_port *port)
401 struct platform_device *pdev = to_platform_device(port->dev);
402 struct resource *res;
404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408 if (port->flags & UPF_IOREMAP) {
409 devm_release_mem_region(port->dev, port->mapbase,
411 devm_iounmap(port->dev, port->membase);
412 port->membase = NULL;
416 static int owl_uart_request_port(struct uart_port *port)
418 struct platform_device *pdev = to_platform_device(port->dev);
419 struct resource *res;
421 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425 if (!devm_request_mem_region(port->dev, port->mapbase,
426 resource_size(res), dev_name(port->dev)))
429 if (port->flags & UPF_IOREMAP) {
430 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
439 static const char *owl_uart_type(struct uart_port *port)
441 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
444 static int owl_uart_verify_port(struct uart_port *port,
445 struct serial_struct *ser)
447 if (port->type != PORT_OWL)
450 if (port->irq != ser->irq)
456 static void owl_uart_config_port(struct uart_port *port, int flags)
458 if (flags & UART_CONFIG_TYPE) {
459 port->type = PORT_OWL;
460 owl_uart_request_port(port);
464 static const struct uart_ops owl_uart_ops = {
465 .set_mctrl = owl_uart_set_mctrl,
466 .get_mctrl = owl_uart_get_mctrl,
467 .tx_empty = owl_uart_tx_empty,
468 .start_tx = owl_uart_start_tx,
469 .stop_rx = owl_uart_stop_rx,
470 .stop_tx = owl_uart_stop_tx,
471 .startup = owl_uart_startup,
472 .shutdown = owl_uart_shutdown,
473 .set_termios = owl_uart_set_termios,
474 .type = owl_uart_type,
475 .config_port = owl_uart_config_port,
476 .request_port = owl_uart_request_port,
477 .release_port = owl_uart_release_port,
478 .verify_port = owl_uart_verify_port,
481 #ifdef CONFIG_SERIAL_OWL_CONSOLE
483 static void owl_console_putchar(struct uart_port *port, int ch)
488 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
491 owl_uart_write(port, ch, OWL_UART_TXDAT);
494 static void owl_uart_port_write(struct uart_port *port, const char *s,
501 local_irq_save(flags);
505 else if (oops_in_progress)
506 locked = spin_trylock(&port->lock);
508 spin_lock(&port->lock);
512 old_ctl = owl_uart_read(port, OWL_UART_CTL);
513 val = old_ctl | OWL_UART_CTL_TRFS_TX;
515 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
516 owl_uart_write(port, val, OWL_UART_CTL);
518 uart_console_write(port, s, count, owl_console_putchar);
520 /* wait until all contents have been sent out */
521 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
524 /* clear IRQ pending */
525 val = owl_uart_read(port, OWL_UART_STAT);
526 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
527 owl_uart_write(port, val, OWL_UART_STAT);
529 owl_uart_write(port, old_ctl, OWL_UART_CTL);
532 spin_unlock(&port->lock);
534 local_irq_restore(flags);
537 static void owl_uart_console_write(struct console *co, const char *s,
540 struct owl_uart_port *owl_port;
542 owl_port = owl_uart_ports[co->index];
546 owl_uart_port_write(&owl_port->port, s, count);
549 static int owl_uart_console_setup(struct console *co, char *options)
551 struct owl_uart_port *owl_port;
557 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
560 owl_port = owl_uart_ports[co->index];
561 if (!owl_port || !owl_port->port.membase)
565 uart_parse_options(options, &baud, &parity, &bits, &flow);
567 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
570 static struct console owl_uart_console = {
571 .name = OWL_UART_DEV_NAME,
572 .write = owl_uart_console_write,
573 .device = uart_console_device,
574 .setup = owl_uart_console_setup,
575 .flags = CON_PRINTBUFFER,
577 .data = &owl_uart_driver,
580 static int __init owl_uart_console_init(void)
582 register_console(&owl_uart_console);
586 console_initcall(owl_uart_console_init);
588 static void owl_uart_early_console_write(struct console *co,
592 struct earlycon_device *dev = co->data;
594 owl_uart_port_write(&dev->port, s, count);
598 owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
600 if (!device->port.membase)
603 device->con->write = owl_uart_early_console_write;
607 OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
608 owl_uart_early_console_setup);
610 #define OWL_UART_CONSOLE (&owl_uart_console)
612 #define OWL_UART_CONSOLE NULL
615 static struct uart_driver owl_uart_driver = {
616 .owner = THIS_MODULE,
617 .driver_name = "owl-uart",
618 .dev_name = OWL_UART_DEV_NAME,
619 .nr = OWL_UART_PORT_NUM,
620 .cons = OWL_UART_CONSOLE,
623 static const struct owl_uart_info owl_s500_info = {
627 static const struct owl_uart_info owl_s900_info = {
631 static const struct of_device_id owl_uart_dt_matches[] = {
632 { .compatible = "actions,s500-uart", .data = &owl_s500_info },
633 { .compatible = "actions,s900-uart", .data = &owl_s900_info },
636 MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
638 static int owl_uart_probe(struct platform_device *pdev)
640 const struct of_device_id *match;
641 const struct owl_uart_info *info = NULL;
642 struct resource *res_mem;
643 struct owl_uart_port *owl_port;
646 if (pdev->dev.of_node) {
647 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
648 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
653 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
654 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
658 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
660 dev_err(&pdev->dev, "could not get mem\n");
664 irq = platform_get_irq(pdev, 0);
666 dev_err(&pdev->dev, "could not get irq\n");
670 if (owl_uart_ports[pdev->id]) {
671 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
675 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
679 owl_port->clk = devm_clk_get(&pdev->dev, NULL);
680 if (IS_ERR(owl_port->clk)) {
681 dev_err(&pdev->dev, "could not get clk\n");
682 return PTR_ERR(owl_port->clk);
685 owl_port->port.dev = &pdev->dev;
686 owl_port->port.line = pdev->id;
687 owl_port->port.type = PORT_OWL;
688 owl_port->port.iotype = UPIO_MEM;
689 owl_port->port.mapbase = res_mem->start;
690 owl_port->port.irq = irq;
691 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
692 if (owl_port->port.uartclk == 0) {
693 dev_err(&pdev->dev, "clock rate is zero\n");
696 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
697 owl_port->port.x_char = 0;
698 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
699 owl_port->port.ops = &owl_uart_ops;
701 owl_uart_ports[pdev->id] = owl_port;
702 platform_set_drvdata(pdev, owl_port);
704 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
706 owl_uart_ports[pdev->id] = NULL;
711 static int owl_uart_remove(struct platform_device *pdev)
713 struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
715 uart_remove_one_port(&owl_uart_driver, &owl_port->port);
716 owl_uart_ports[pdev->id] = NULL;
721 static struct platform_driver owl_uart_platform_driver = {
722 .probe = owl_uart_probe,
723 .remove = owl_uart_remove,
726 .of_match_table = owl_uart_dt_matches,
730 static int __init owl_uart_init(void)
734 ret = uart_register_driver(&owl_uart_driver);
738 ret = platform_driver_register(&owl_uart_platform_driver);
740 uart_unregister_driver(&owl_uart_driver);
745 static void __init owl_uart_exit(void)
747 platform_driver_unregister(&owl_uart_platform_driver);
748 uart_unregister_driver(&owl_uart_driver);
751 module_init(owl_uart_init);
752 module_exit(owl_uart_exit);
754 MODULE_LICENSE("GPL");