drivers/tty/serial/omap-serial.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for OMAP-UART controller.
   4  * Based on drivers/serial/8250.c
   5  *
   6  * Copyright (C) 2010 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Govindraj R     <govindraj.raja@ti.com>
  10  *      Thara Gopinath  <thara@ti.com>
  11  *
  12  * Note: This driver is made separate from 8250 driver as we cannot
  13  * over load 8250 driver with omap platform specific configuration for
  14  * features like DMA, it makes easier to implement features like DMA and
  15  * hardware flow control and software flow control configuration with
  16  * this driver as required for the omap-platform.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/console.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/tty.h>
  26 #include <linux/tty_flip.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/clk.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/irq.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/pm_wakeirq.h>
  34 #include <linux/of.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/gpio/consumer.h>
  37 #include <linux/platform_data/serial-omap.h>
  38
  39 #define OMAP_MAX_HSUART_PORTS   10
  40
  41 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  42
  43 #define OMAP_UART_REV_42 0x0402
  44 #define OMAP_UART_REV_46 0x0406
  45 #define OMAP_UART_REV_52 0x0502
  46 #define OMAP_UART_REV_63 0x0603
  47
  48 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  49
  50 /* Feature flags */
  51 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  52
  53 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  54 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  55
  56 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
  57
  58 /* SCR register bitmasks */
  59 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  60 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  61 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  62
  63 /* FCR register bitmasks */
  64 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  65 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  66
  67 /* MVR register bitmasks */
  68 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  69
  70 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  71 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  72 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  73
  74 #define OMAP_UART_MVR_MAJ_MASK          0x700
  75 #define OMAP_UART_MVR_MAJ_SHIFT         8
  76 #define OMAP_UART_MVR_MIN_MASK          0x3f
  77
  78 #define OMAP_UART_DMA_CH_FREE   -1
  79
  80 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  81 #define OMAP_MODE13X_SPEED      230400
  82
  83 /* WER = 0x7F
  84  * Enable module level wakeup in WER reg
  85  */
  86 #define OMAP_UART_WER_MOD_WKUP  0x7F
  87
  88 /* Enable XON/XOFF flow control on output */
  89 #define OMAP_UART_SW_TX         0x08
  90
  91 /* Enable XON/XOFF flow control on input */
  92 #define OMAP_UART_SW_RX         0x02
  93
  94 #define OMAP_UART_SW_CLR        0xF0
  95
  96 #define OMAP_UART_TCR_TRIG      0x0F
  97
  98 struct uart_omap_dma {
  99         u8                      uart_dma_tx;
 100         u8                      uart_dma_rx;
 101         int                     rx_dma_channel;
 102         int                     tx_dma_channel;
 103         dma_addr_t              rx_buf_dma_phys;
 104         dma_addr_t              tx_buf_dma_phys;
 105         unsigned int            uart_base;
 106         /*
 107          * Buffer for rx dma. It is not required for tx because the buffer
 108          * comes from port structure.
 109          */
 110         unsigned char           *rx_buf;
 111         unsigned int            prev_rx_dma_pos;
 112         int                     tx_buf_size;
 113         int                     tx_dma_used;
 114         int                     rx_dma_used;
 115         spinlock_t              tx_lock;
 116         spinlock_t              rx_lock;
 117         /* timer to poll activity on rx dma */
 118         struct timer_list       rx_timer;
 119         unsigned int            rx_buf_size;
 120         unsigned int            rx_poll_rate;
 121         unsigned int            rx_timeout;
 122 };
 123
 124 struct uart_omap_port {
 125         struct uart_port        port;
 126         struct uart_omap_dma    uart_dma;
 127         struct device           *dev;
 128         int                     wakeirq;
 129
 130         unsigned char           ier;
 131         unsigned char           lcr;
 132         unsigned char           mcr;
 133         unsigned char           fcr;
 134         unsigned char           efr;
 135         unsigned char           dll;
 136         unsigned char           dlh;
 137         unsigned char           mdr1;
 138         unsigned char           scr;
 139         unsigned char           wer;
 140
 141         int                     use_dma;
 142         /*
 143          * Some bits in registers are cleared on a read, so they must
 144          * be saved whenever the register is read, but the bits will not
 145          * be immediately processed.
 146          */
 147         unsigned int            lsr_break_flag;
 148         unsigned char           msr_saved_flags;
 149         char                    name[20];
 150         unsigned long           port_activity;
 151         int                     context_loss_cnt;
 152         u32                     errata;
 153         u32                     features;
 154
 155         struct gpio_desc        *rts_gpiod;
 156
 157         struct pm_qos_request   pm_qos_request;
 158         u32                     latency;
 159         u32                     calc_latency;
 160         struct work_struct      qos_work;
 161         bool                    is_suspending;
 162 };
 163
 164 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 165
 166 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 167
 168 /* Forward declaration of functions */
 169 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 170
 171 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 172 {
 173         offset <<= up->port.regshift;
 174         return readw(up->port.membase + offset);
 175 }
 176
 177 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 178 {
 179         offset <<= up->port.regshift;
 180         writew(value, up->port.membase + offset);
 181 }
 182
 183 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 184 {
 185         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 186         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 187                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 188         serial_out(up, UART_FCR, 0);
 189 }
 190
 191 #ifdef CONFIG_PM
 192 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 193 {
 194         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 195
 196         if (!pdata || !pdata->get_context_loss_count)
 197                 return -EINVAL;
 198
 199         return pdata->get_context_loss_count(up->dev);
 200 }
 201
 202 /* REVISIT: Remove this when omap3 boots in device tree only mode */
 203 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 204 {
 205         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 206
 207         if (!pdata || !pdata->enable_wakeup)
 208                 return;
 209
 210         pdata->enable_wakeup(up->dev, enable);
 211 }
 212 #endif /* CONFIG_PM */
 213
 214 /*
 215  * Calculate the absolute difference between the desired and actual baud
 216  * rate for the given mode.
 217  */
 218 static inline int calculate_baud_abs_diff(struct uart_port *port,
 219                                 unsigned int baud, unsigned int mode)
 220 {
 221         unsigned int n = port->uartclk / (mode * baud);
 222         int abs_diff;
 223
 224         if (n == 0)
 225                 n = 1;
 226
 227         abs_diff = baud - (port->uartclk / (mode * n));
 228         if (abs_diff < 0)
 229                 abs_diff = -abs_diff;
 230
 231         return abs_diff;
 232 }
 233
 234 /*
 235  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 236  * @port: uart port info
 237  * @baud: baudrate for which mode needs to be determined
 238  *
 239  * Returns true if baud rate is MODE16X and false if MODE13X
 240  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 241  * and Error Rates" determines modes not for all common baud rates.
 242  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 243  * table it's determined as 13x.
 244  */
 245 static bool
 246 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 247 {
 248         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
 249         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
 250
 251         return (abs_diff_13 >= abs_diff_16);
 252 }
 253
 254 /*
 255  * serial_omap_get_divisor - calculate divisor value
 256  * @port: uart port info
 257  * @baud: baudrate for which divisor needs to be calculated.
 258  */
 259 static unsigned int
 260 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 261 {
 262         unsigned int mode;
 263
 264         if (!serial_omap_baud_is_mode16(port, baud))
 265                 mode = 13;
 266         else
 267                 mode = 16;
 268         return port->uartclk/(mode * baud);
 269 }
 270
 271 static void serial_omap_enable_ms(struct uart_port *port)
 272 {
 273         struct uart_omap_port *up = to_uart_omap_port(port);
 274
 275         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 276
 277         pm_runtime_get_sync(up->dev);
 278         up->ier |= UART_IER_MSI;
 279         serial_out(up, UART_IER, up->ier);
 280         pm_runtime_mark_last_busy(up->dev);
 281         pm_runtime_put_autosuspend(up->dev);
 282 }
 283
 284 static void serial_omap_stop_tx(struct uart_port *port)
 285 {
 286         struct uart_omap_port *up = to_uart_omap_port(port);
 287         int res;
 288
 289         pm_runtime_get_sync(up->dev);
 290
 291         /* Handle RS-485 */
 292         if (port->rs485.flags & SER_RS485_ENABLED) {
 293                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 294                         /* THR interrupt is fired when both TX FIFO and TX
 295                          * shift register are empty. This means there's nothing
 296                          * left to transmit now, so make sure the THR interrupt
 297                          * is fired when TX FIFO is below the trigger level,
 298                          * disable THR interrupts and toggle the RS-485 GPIO
 299                          * data direction pin if needed.
 300                          */
 301                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 302                         serial_out(up, UART_OMAP_SCR, up->scr);
 303                         res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
 304                                 1 : 0;
 305                         if (gpiod_get_value(up->rts_gpiod) != res) {
 306                                 if (port->rs485.delay_rts_after_send > 0)
 307                                         mdelay(
 308                                         port->rs485.delay_rts_after_send);
 309                                 gpiod_set_value(up->rts_gpiod, res);
 310                         }
 311                 } else {
 312                         /* We're asked to stop, but there's still stuff in the
 313                          * UART FIFO, so make sure the THR interrupt is fired
 314                          * when both TX FIFO and TX shift register are empty.
 315                          * The next THR interrupt (if no transmission is started
 316                          * in the meantime) will indicate the end of a
 317                          * transmission. Therefore we _don't_ disable THR
 318                          * interrupts in this situation.
 319                          */
 320                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 321                         serial_out(up, UART_OMAP_SCR, up->scr);
 322                         return;
 323                 }
 324         }
 325
 326         if (up->ier & UART_IER_THRI) {
 327                 up->ier &= ~UART_IER_THRI;
 328                 serial_out(up, UART_IER, up->ier);
 329         }
 330
 331         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 332             !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
 333                 /*
 334                  * Empty the RX FIFO, we are not interested in anything
 335                  * received during the half-duplex transmission.
 336                  */
 337                 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
 338                 /* Re-enable RX interrupts */
 339                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
 340                 up->port.read_status_mask |= UART_LSR_DR;
 341                 serial_out(up, UART_IER, up->ier);
 342         }
 343
 344         pm_runtime_mark_last_busy(up->dev);
 345         pm_runtime_put_autosuspend(up->dev);
 346 }
 347
 348 static void serial_omap_stop_rx(struct uart_port *port)
 349 {
 350         struct uart_omap_port *up = to_uart_omap_port(port);
 351
 352         pm_runtime_get_sync(up->dev);
 353         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 354         up->port.read_status_mask &= ~UART_LSR_DR;
 355         serial_out(up, UART_IER, up->ier);
 356         pm_runtime_mark_last_busy(up->dev);
 357         pm_runtime_put_autosuspend(up->dev);
 358 }
 359
 360 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 361 {
 362         struct circ_buf *xmit = &up->port.state->xmit;
 363         int count;
 364
 365         if (up->port.x_char) {
 366                 serial_out(up, UART_TX, up->port.x_char);
 367                 up->port.icount.tx++;
 368                 up->port.x_char = 0;
 369                 return;
 370         }
 371         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 372                 serial_omap_stop_tx(&up->port);
 373                 return;
 374         }
 375         count = up->port.fifosize / 4;
 376         do {
 377                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 378                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 379                 up->port.icount.tx++;
 380                 if (uart_circ_empty(xmit))
 381                         break;
 382         } while (--count > 0);
 383
 384         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 385                 uart_write_wakeup(&up->port);
 386
 387         if (uart_circ_empty(xmit))
 388                 serial_omap_stop_tx(&up->port);
 389 }
 390
 391 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 392 {
 393         if (!(up->ier & UART_IER_THRI)) {
 394                 up->ier |= UART_IER_THRI;
 395                 serial_out(up, UART_IER, up->ier);
 396         }
 397 }
 398
 399 static void serial_omap_start_tx(struct uart_port *port)
 400 {
 401         struct uart_omap_port *up = to_uart_omap_port(port);
 402         int res;
 403
 404         pm_runtime_get_sync(up->dev);
 405
 406         /* Handle RS-485 */
 407         if (port->rs485.flags & SER_RS485_ENABLED) {
 408                 /* Fire THR interrupts when FIFO is below trigger level */
 409                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 410                 serial_out(up, UART_OMAP_SCR, up->scr);
 411
 412                 /* if rts not already enabled */
 413                 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 414                 if (gpiod_get_value(up->rts_gpiod) != res) {
 415                         gpiod_set_value(up->rts_gpiod, res);
 416                         if (port->rs485.delay_rts_before_send > 0)
 417                                 mdelay(port->rs485.delay_rts_before_send);
 418                 }
 419         }
 420
 421         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 422             !(port->rs485.flags & SER_RS485_RX_DURING_TX))
 423                 serial_omap_stop_rx(port);
 424
 425         serial_omap_enable_ier_thri(up);
 426         pm_runtime_mark_last_busy(up->dev);
 427         pm_runtime_put_autosuspend(up->dev);
 428 }
 429
 430 static void serial_omap_throttle(struct uart_port *port)
 431 {
 432         struct uart_omap_port *up = to_uart_omap_port(port);
 433         unsigned long flags;
 434
 435         pm_runtime_get_sync(up->dev);
 436         spin_lock_irqsave(&up->port.lock, flags);
 437         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 438         serial_out(up, UART_IER, up->ier);
 439         spin_unlock_irqrestore(&up->port.lock, flags);
 440         pm_runtime_mark_last_busy(up->dev);
 441         pm_runtime_put_autosuspend(up->dev);
 442 }
 443
 444 static void serial_omap_unthrottle(struct uart_port *port)
 445 {
 446         struct uart_omap_port *up = to_uart_omap_port(port);
 447         unsigned long flags;
 448
 449         pm_runtime_get_sync(up->dev);
 450         spin_lock_irqsave(&up->port.lock, flags);
 451         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 452         serial_out(up, UART_IER, up->ier);
 453         spin_unlock_irqrestore(&up->port.lock, flags);
 454         pm_runtime_mark_last_busy(up->dev);
 455         pm_runtime_put_autosuspend(up->dev);
 456 }
 457
 458 static unsigned int check_modem_status(struct uart_omap_port *up)
 459 {
 460         unsigned int status;
 461
 462         status = serial_in(up, UART_MSR);
 463         status |= up->msr_saved_flags;
 464         up->msr_saved_flags = 0;
 465         if ((status & UART_MSR_ANY_DELTA) == 0)
 466                 return status;
 467
 468         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 469             up->port.state != NULL) {
 470                 if (status & UART_MSR_TERI)
 471                         up->port.icount.rng++;
 472                 if (status & UART_MSR_DDSR)
 473                         up->port.icount.dsr++;
 474                 if (status & UART_MSR_DDCD)
 475                         uart_handle_dcd_change
 476                                 (&up->port, status & UART_MSR_DCD);
 477                 if (status & UART_MSR_DCTS)
 478                         uart_handle_cts_change
 479                                 (&up->port, status & UART_MSR_CTS);
 480                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 481         }
 482
 483         return status;
 484 }
 485
 486 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 487 {
 488         unsigned int flag;
 489
 490         /*
 491          * Read one data character out to avoid stalling the receiver according
 492          * to the table 23-246 of the omap4 TRM.
 493          */
 494         if (likely(lsr & UART_LSR_DR))
 495                 serial_in(up, UART_RX);
 496
 497         up->port.icount.rx++;
 498         flag = TTY_NORMAL;
 499
 500         if (lsr & UART_LSR_BI) {
 501                 flag = TTY_BREAK;
 502                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 503                 up->port.icount.brk++;
 504                 /*
 505                  * We do the SysRQ and SAK checking
 506                  * here because otherwise the break
 507                  * may get masked by ignore_status_mask
 508                  * or read_status_mask.
 509                  */
 510                 if (uart_handle_break(&up->port))
 511                         return;
 512
 513         }
 514
 515         if (lsr & UART_LSR_PE) {
 516                 flag = TTY_PARITY;
 517                 up->port.icount.parity++;
 518         }
 519
 520         if (lsr & UART_LSR_FE) {
 521                 flag = TTY_FRAME;
 522                 up->port.icount.frame++;
 523         }
 524
 525         if (lsr & UART_LSR_OE)
 526                 up->port.icount.overrun++;
 527
 528 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 529         if (up->port.line == up->port.cons->index) {
 530                 /* Recover the break flag from console xmit */
 531                 lsr |= up->lsr_break_flag;
 532         }
 533 #endif
 534         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 535 }
 536
 537 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 538 {
 539         unsigned char ch = 0;
 540         unsigned int flag;
 541
 542         if (!(lsr & UART_LSR_DR))
 543                 return;
 544
 545         ch = serial_in(up, UART_RX);
 546         flag = TTY_NORMAL;
 547         up->port.icount.rx++;
 548
 549         if (uart_handle_sysrq_char(&up->port, ch))
 550                 return;
 551
 552         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 553 }
 554
 555 /**
 556  * serial_omap_irq() - This handles the interrupt from one port
 557  * @irq: uart port irq number
 558  * @dev_id: uart port info
 559  */
 560 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 561 {
 562         struct uart_omap_port *up = dev_id;
 563         unsigned int iir, lsr;
 564         unsigned int type;
 565         irqreturn_t ret = IRQ_NONE;
 566         int max_count = 256;
 567
 568         spin_lock(&up->port.lock);
 569         pm_runtime_get_sync(up->dev);
 570
 571         do {
 572                 iir = serial_in(up, UART_IIR);
 573                 if (iir & UART_IIR_NO_INT)
 574                         break;
 575
 576                 ret = IRQ_HANDLED;
 577                 lsr = serial_in(up, UART_LSR);
 578
 579                 /* extract IRQ type from IIR register */
 580                 type = iir & 0x3e;
 581
 582                 switch (type) {
 583                 case UART_IIR_MSI:
 584                         check_modem_status(up);
 585                         break;
 586                 case UART_IIR_THRI:
 587                         transmit_chars(up, lsr);
 588                         break;
 589                 case UART_IIR_RX_TIMEOUT:
 590                         /* FALLTHROUGH */
 591                 case UART_IIR_RDI:
 592                         serial_omap_rdi(up, lsr);
 593                         break;
 594                 case UART_IIR_RLSI:
 595                         serial_omap_rlsi(up, lsr);
 596                         break;
 597                 case UART_IIR_CTS_RTS_DSR:
 598                         /* simply try again */
 599                         break;
 600                 case UART_IIR_XOFF:
 601                         /* FALLTHROUGH */
 602                 default:
 603                         break;
 604                 }
 605         } while (max_count--);
 606
 607         spin_unlock(&up->port.lock);
 608
 609         tty_flip_buffer_push(&up->port.state->port);
 610
 611         pm_runtime_mark_last_busy(up->dev);
 612         pm_runtime_put_autosuspend(up->dev);
 613         up->port_activity = jiffies;
 614
 615         return ret;
 616 }
 617
 618 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 619 {
 620         struct uart_omap_port *up = to_uart_omap_port(port);
 621         unsigned long flags = 0;
 622         unsigned int ret = 0;
 623
 624         pm_runtime_get_sync(up->dev);
 625         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 626         spin_lock_irqsave(&up->port.lock, flags);
 627         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 628         spin_unlock_irqrestore(&up->port.lock, flags);
 629         pm_runtime_mark_last_busy(up->dev);
 630         pm_runtime_put_autosuspend(up->dev);
 631         return ret;
 632 }
 633
 634 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 635 {
 636         struct uart_omap_port *up = to_uart_omap_port(port);
 637         unsigned int status;
 638         unsigned int ret = 0;
 639
 640         pm_runtime_get_sync(up->dev);
 641         status = check_modem_status(up);
 642         pm_runtime_mark_last_busy(up->dev);
 643         pm_runtime_put_autosuspend(up->dev);
 644
 645         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 646
 647         if (status & UART_MSR_DCD)
 648                 ret |= TIOCM_CAR;
 649         if (status & UART_MSR_RI)
 650                 ret |= TIOCM_RNG;
 651         if (status & UART_MSR_DSR)
 652                 ret |= TIOCM_DSR;
 653         if (status & UART_MSR_CTS)
 654                 ret |= TIOCM_CTS;
 655         return ret;
 656 }
 657
 658 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 659 {
 660         struct uart_omap_port *up = to_uart_omap_port(port);
 661         unsigned char mcr = 0, old_mcr, lcr;
 662
 663         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 664         if (mctrl & TIOCM_RTS)
 665                 mcr |= UART_MCR_RTS;
 666         if (mctrl & TIOCM_DTR)
 667                 mcr |= UART_MCR_DTR;
 668         if (mctrl & TIOCM_OUT1)
 669                 mcr |= UART_MCR_OUT1;
 670         if (mctrl & TIOCM_OUT2)
 671                 mcr |= UART_MCR_OUT2;
 672         if (mctrl & TIOCM_LOOP)
 673                 mcr |= UART_MCR_LOOP;
 674
 675         pm_runtime_get_sync(up->dev);
 676         old_mcr = serial_in(up, UART_MCR);
 677         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 678                      UART_MCR_DTR | UART_MCR_RTS);
 679         up->mcr = old_mcr | mcr;
 680         serial_out(up, UART_MCR, up->mcr);
 681
 682         /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
 683         lcr = serial_in(up, UART_LCR);
 684         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 685         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 686                 up->efr |= UART_EFR_RTS;
 687         else
 688                 up->efr &= ~UART_EFR_RTS;
 689         serial_out(up, UART_EFR, up->efr);
 690         serial_out(up, UART_LCR, lcr);
 691
 692         pm_runtime_mark_last_busy(up->dev);
 693         pm_runtime_put_autosuspend(up->dev);
 694 }
 695
 696 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 697 {
 698         struct uart_omap_port *up = to_uart_omap_port(port);
 699         unsigned long flags = 0;
 700
 701         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 702         pm_runtime_get_sync(up->dev);
 703         spin_lock_irqsave(&up->port.lock, flags);
 704         if (break_state == -1)
 705                 up->lcr |= UART_LCR_SBC;
 706         else
 707                 up->lcr &= ~UART_LCR_SBC;
 708         serial_out(up, UART_LCR, up->lcr);
 709         spin_unlock_irqrestore(&up->port.lock, flags);
 710         pm_runtime_mark_last_busy(up->dev);
 711         pm_runtime_put_autosuspend(up->dev);
 712 }
 713
 714 static int serial_omap_startup(struct uart_port *port)
 715 {
 716         struct uart_omap_port *up = to_uart_omap_port(port);
 717         unsigned long flags = 0;
 718         int retval;
 719
 720         /*
 721          * Allocate the IRQ
 722          */
 723         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 724                                 up->name, up);
 725         if (retval)
 726                 return retval;
 727
 728         /* Optional wake-up IRQ */
 729         if (up->wakeirq) {
 730                 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
 731                 if (retval) {
 732                         free_irq(up->port.irq, up);
 733                         return retval;
 734                 }
 735         }
 736
 737         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 738
 739         pm_runtime_get_sync(up->dev);
 740         /*
 741          * Clear the FIFO buffers and disable them.
 742          * (they will be reenabled in set_termios())
 743          */
 744         serial_omap_clear_fifos(up);
 745
 746         /*
 747          * Clear the interrupt registers.
 748          */
 749         (void) serial_in(up, UART_LSR);
 750         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 751                 (void) serial_in(up, UART_RX);
 752         (void) serial_in(up, UART_IIR);
 753         (void) serial_in(up, UART_MSR);
 754
 755         /*
 756          * Now, initialize the UART
 757          */
 758         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 759         spin_lock_irqsave(&up->port.lock, flags);
 760         /*
 761          * Most PC uarts need OUT2 raised to enable interrupts.
 762          */
 763         up->port.mctrl |= TIOCM_OUT2;
 764         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 765         spin_unlock_irqrestore(&up->port.lock, flags);
 766
 767         up->msr_saved_flags = 0;
 768         /*
 769          * Finally, enable interrupts. Note: Modem status interrupts
 770          * are set via set_termios(), which will be occurring imminently
 771          * anyway, so we don't enable them here.
 772          */
 773         up->ier = UART_IER_RLSI | UART_IER_RDI;
 774         serial_out(up, UART_IER, up->ier);
 775
 776         /* Enable module level wake up */
 777         up->wer = OMAP_UART_WER_MOD_WKUP;
 778         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 779                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 780
 781         serial_out(up, UART_OMAP_WER, up->wer);
 782
 783         pm_runtime_mark_last_busy(up->dev);
 784         pm_runtime_put_autosuspend(up->dev);
 785         up->port_activity = jiffies;
 786         return 0;
 787 }
 788
 789 static void serial_omap_shutdown(struct uart_port *port)
 790 {
 791         struct uart_omap_port *up = to_uart_omap_port(port);
 792         unsigned long flags = 0;
 793
 794         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 795
 796         pm_runtime_get_sync(up->dev);
 797         /*
 798          * Disable interrupts from this port
 799          */
 800         up->ier = 0;
 801         serial_out(up, UART_IER, 0);
 802
 803         spin_lock_irqsave(&up->port.lock, flags);
 804         up->port.mctrl &= ~TIOCM_OUT2;
 805         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 806         spin_unlock_irqrestore(&up->port.lock, flags);
 807
 808         /*
 809          * Disable break condition and FIFOs
 810          */
 811         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 812         serial_omap_clear_fifos(up);
 813
 814         /*
 815          * Read data port to reset things, and then free the irq
 816          */
 817         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 818                 (void) serial_in(up, UART_RX);
 819
 820         pm_runtime_mark_last_busy(up->dev);
 821         pm_runtime_put_autosuspend(up->dev);
 822         free_irq(up->port.irq, up);
 823         dev_pm_clear_wake_irq(up->dev);
 824 }
 825
 826 static void serial_omap_uart_qos_work(struct work_struct *work)
 827 {
 828         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 829                                                 qos_work);
 830
 831         cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
 832 }
 833
 834 static void
 835 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 836                         struct ktermios *old)
 837 {
 838         struct uart_omap_port *up = to_uart_omap_port(port);
 839         unsigned char cval = 0;
 840         unsigned long flags = 0;
 841         unsigned int baud, quot;
 842
 843         switch (termios->c_cflag & CSIZE) {
 844         case CS5:
 845                 cval = UART_LCR_WLEN5;
 846                 break;
 847         case CS6:
 848                 cval = UART_LCR_WLEN6;
 849                 break;
 850         case CS7:
 851                 cval = UART_LCR_WLEN7;
 852                 break;
 853         default:
 854         case CS8:
 855                 cval = UART_LCR_WLEN8;
 856                 break;
 857         }
 858
 859         if (termios->c_cflag & CSTOPB)
 860                 cval |= UART_LCR_STOP;
 861         if (termios->c_cflag & PARENB)
 862                 cval |= UART_LCR_PARITY;
 863         if (!(termios->c_cflag & PARODD))
 864                 cval |= UART_LCR_EPAR;
 865         if (termios->c_cflag & CMSPAR)
 866                 cval |= UART_LCR_SPAR;
 867
 868         /*
 869          * Ask the core to calculate the divisor for us.
 870          */
 871
 872         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 873         quot = serial_omap_get_divisor(port, baud);
 874
 875         /* calculate wakeup latency constraint */
 876         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 877         up->latency = up->calc_latency;
 878         schedule_work(&up->qos_work);
 879
 880         up->dll = quot & 0xff;
 881         up->dlh = quot >> 8;
 882         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 883
 884         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 885                         UART_FCR_ENABLE_FIFO;
 886
 887         /*
 888          * Ok, we're now changing the port state. Do it with
 889          * interrupts disabled.
 890          */
 891         pm_runtime_get_sync(up->dev);
 892         spin_lock_irqsave(&up->port.lock, flags);
 893
 894         /*
 895          * Update the per-port timeout.
 896          */
 897         uart_update_timeout(port, termios->c_cflag, baud);
 898
 899         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 900         if (termios->c_iflag & INPCK)
 901                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 902         if (termios->c_iflag & (BRKINT | PARMRK))
 903                 up->port.read_status_mask |= UART_LSR_BI;
 904
 905         /*
 906          * Characters to ignore
 907          */
 908         up->port.ignore_status_mask = 0;
 909         if (termios->c_iflag & IGNPAR)
 910                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 911         if (termios->c_iflag & IGNBRK) {
 912                 up->port.ignore_status_mask |= UART_LSR_BI;
 913                 /*
 914                  * If we're ignoring parity and break indicators,
 915                  * ignore overruns too (for real raw support).
 916                  */
 917                 if (termios->c_iflag & IGNPAR)
 918                         up->port.ignore_status_mask |= UART_LSR_OE;
 919         }
 920
 921         /*
 922          * ignore all characters if CREAD is not set
 923          */
 924         if ((termios->c_cflag & CREAD) == 0)
 925                 up->port.ignore_status_mask |= UART_LSR_DR;
 926
 927         /*
 928          * Modem status interrupts
 929          */
 930         up->ier &= ~UART_IER_MSI;
 931         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 932                 up->ier |= UART_IER_MSI;
 933         serial_out(up, UART_IER, up->ier);
 934         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 935         up->lcr = cval;
 936         up->scr = 0;
 937
 938         /* FIFOs and DMA Settings */
 939
 940         /* FCR can be changed only when the
 941          * baud clock is not running
 942          * DLL_REG and DLH_REG set to 0.
 943          */
 944         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 945         serial_out(up, UART_DLL, 0);
 946         serial_out(up, UART_DLM, 0);
 947         serial_out(up, UART_LCR, 0);
 948
 949         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 950
 951         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 952         up->efr &= ~UART_EFR_SCD;
 953         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 954
 955         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 956         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 957         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 958         /* FIFO ENABLE, DMA MODE */
 959
 960         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 961         /*
 962          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 963          * sets Enables the granularity of 1 for TRIGGER RX
 964          * level. Along with setting RX FIFO trigger level
 965          * to 1 (as noted below, 16 characters) and TLR[3:0]
 966          * to zero this will result RX FIFO threshold level
 967          * to 1 character, instead of 16 as noted in comment
 968          * below.
 969          */
 970
 971         /* Set receive FIFO threshold to 16 characters and
 972          * transmit FIFO threshold to 32 spaces
 973          */
 974         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 975         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 976         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 977                 UART_FCR_ENABLE_FIFO;
 978
 979         serial_out(up, UART_FCR, up->fcr);
 980         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 981
 982         serial_out(up, UART_OMAP_SCR, up->scr);
 983
 984         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 985         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 986         serial_out(up, UART_MCR, up->mcr);
 987         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 988         serial_out(up, UART_EFR, up->efr);
 989         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 990
 991         /* Protocol, Baud Rate, and Interrupt Settings */
 992
 993         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 994                 serial_omap_mdr1_errataset(up, up->mdr1);
 995         else
 996                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 997
 998         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 999         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1000
1001         serial_out(up, UART_LCR, 0);
1002         serial_out(up, UART_IER, 0);
1003         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1004
1005         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1006         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1007
1008         serial_out(up, UART_LCR, 0);
1009         serial_out(up, UART_IER, up->ier);
1010         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1011
1012         serial_out(up, UART_EFR, up->efr);
1013         serial_out(up, UART_LCR, cval);
1014
1015         if (!serial_omap_baud_is_mode16(port, baud))
1016                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1017         else
1018                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1019
1020         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1021                 serial_omap_mdr1_errataset(up, up->mdr1);
1022         else
1023                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1024
1025         /* Configure flow control */
1026         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1027
1028         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1029         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1030         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1031
1032         /* Enable access to TCR/TLR */
1033         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1034         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1035         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1036
1037         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1038
1039         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1040
1041         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1042                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1043                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1044                 up->efr |= UART_EFR_CTS;
1045         } else {
1046                 /* Disable AUTORTS and AUTOCTS */
1047                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1048         }
1049
1050         if (up->port.flags & UPF_SOFT_FLOW) {
1051                 /* clear SW control mode bits */
1052                 up->efr &= OMAP_UART_SW_CLR;
1053
1054                 /*
1055                  * IXON Flag:
1056                  * Enable XON/XOFF flow control on input.
1057                  * Receiver compares XON1, XOFF1.
1058                  */
1059                 if (termios->c_iflag & IXON)
1060                         up->efr |= OMAP_UART_SW_RX;
1061
1062                 /*
1063                  * IXOFF Flag:
1064                  * Enable XON/XOFF flow control on output.
1065                  * Transmit XON1, XOFF1
1066                  */
1067                 if (termios->c_iflag & IXOFF) {
1068                         up->port.status |= UPSTAT_AUTOXOFF;
1069                         up->efr |= OMAP_UART_SW_TX;
1070                 }
1071
1072                 /*
1073                  * IXANY Flag:
1074                  * Enable any character to restart output.
1075                  * Operation resumes after receiving any
1076                  * character after recognition of the XOFF character
1077                  */
1078                 if (termios->c_iflag & IXANY)
1079                         up->mcr |= UART_MCR_XONANY;
1080                 else
1081                         up->mcr &= ~UART_MCR_XONANY;
1082         }
1083         serial_out(up, UART_MCR, up->mcr);
1084         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1085         serial_out(up, UART_EFR, up->efr);
1086         serial_out(up, UART_LCR, up->lcr);
1087
1088         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1089
1090         spin_unlock_irqrestore(&up->port.lock, flags);
1091         pm_runtime_mark_last_busy(up->dev);
1092         pm_runtime_put_autosuspend(up->dev);
1093         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1094 }
1095
1096 static void
1097 serial_omap_pm(struct uart_port *port, unsigned int state,
1098                unsigned int oldstate)
1099 {
1100         struct uart_omap_port *up = to_uart_omap_port(port);
1101         unsigned char efr;
1102
1103         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1104
1105         pm_runtime_get_sync(up->dev);
1106         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1107         efr = serial_in(up, UART_EFR);
1108         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1109         serial_out(up, UART_LCR, 0);
1110
1111         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1112         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1113         serial_out(up, UART_EFR, efr);
1114         serial_out(up, UART_LCR, 0);
1115
1116         pm_runtime_mark_last_busy(up->dev);
1117         pm_runtime_put_autosuspend(up->dev);
1118 }
1119
1120 static void serial_omap_release_port(struct uart_port *port)
1121 {
1122         dev_dbg(port->dev, "serial_omap_release_port+\n");
1123 }
1124
1125 static int serial_omap_request_port(struct uart_port *port)
1126 {
1127         dev_dbg(port->dev, "serial_omap_request_port+\n");
1128         return 0;
1129 }
1130
1131 static void serial_omap_config_port(struct uart_port *port, int flags)
1132 {
1133         struct uart_omap_port *up = to_uart_omap_port(port);
1134
1135         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1136                                                         up->port.line);
1137         up->port.type = PORT_OMAP;
1138         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1139 }
1140
1141 static int
1142 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1143 {
1144         /* we don't want the core code to modify any port params */
1145         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1146         return -EINVAL;
1147 }
1148
1149 static const char *
1150 serial_omap_type(struct uart_port *port)
1151 {
1152         struct uart_omap_port *up = to_uart_omap_port(port);
1153
1154         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1155         return up->name;
1156 }
1157
1158 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1159
1160 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1161 {
1162         unsigned int status, tmout = 10000;
1163
1164         /* Wait up to 10ms for the character(s) to be sent. */
1165         do {
1166                 status = serial_in(up, UART_LSR);
1167
1168                 if (status & UART_LSR_BI)
1169                         up->lsr_break_flag = UART_LSR_BI;
1170
1171                 if (--tmout == 0)
1172                         break;
1173                 udelay(1);
1174         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1175
1176         /* Wait up to 1s for flow control if necessary */
1177         if (up->port.flags & UPF_CONS_FLOW) {
1178                 tmout = 1000000;
1179                 for (tmout = 1000000; tmout; tmout--) {
1180                         unsigned int msr = serial_in(up, UART_MSR);
1181
1182                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1183                         if (msr & UART_MSR_CTS)
1184                                 break;
1185
1186                         udelay(1);
1187                 }
1188         }
1189 }
1190
1191 #ifdef CONFIG_CONSOLE_POLL
1192
1193 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1194 {
1195         struct uart_omap_port *up = to_uart_omap_port(port);
1196
1197         pm_runtime_get_sync(up->dev);
1198         wait_for_xmitr(up);
1199         serial_out(up, UART_TX, ch);
1200         pm_runtime_mark_last_busy(up->dev);
1201         pm_runtime_put_autosuspend(up->dev);
1202 }
1203
1204 static int serial_omap_poll_get_char(struct uart_port *port)
1205 {
1206         struct uart_omap_port *up = to_uart_omap_port(port);
1207         unsigned int status;
1208
1209         pm_runtime_get_sync(up->dev);
1210         status = serial_in(up, UART_LSR);
1211         if (!(status & UART_LSR_DR)) {
1212                 status = NO_POLL_CHAR;
1213                 goto out;
1214         }
1215
1216         status = serial_in(up, UART_RX);
1217
1218 out:
1219         pm_runtime_mark_last_busy(up->dev);
1220         pm_runtime_put_autosuspend(up->dev);
1221
1222         return status;
1223 }
1224
1225 #endif /* CONFIG_CONSOLE_POLL */
1226
1227 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1228
1229 #ifdef CONFIG_SERIAL_EARLYCON
1230 static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1231 {
1232         offset <<= port->regshift;
1233         return readw(port->membase + offset);
1234 }
1235
1236 static void omap_serial_early_out(struct uart_port *port, int offset,
1237                                   int value)
1238 {
1239         offset <<= port->regshift;
1240         writew(value, port->membase + offset);
1241 }
1242
1243 static void omap_serial_early_putc(struct uart_port *port, int c)
1244 {
1245         unsigned int status;
1246
1247         for (;;) {
1248                 status = omap_serial_early_in(port, UART_LSR);
1249                 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1250                         break;
1251                 cpu_relax();
1252         }
1253         omap_serial_early_out(port, UART_TX, c);
1254 }
1255
1256 static void early_omap_serial_write(struct console *console, const char *s,
1257                                     unsigned int count)
1258 {
1259         struct earlycon_device *device = console->data;
1260         struct uart_port *port = &device->port;
1261
1262         uart_console_write(port, s, count, omap_serial_early_putc);
1263 }
1264
1265 static int __init early_omap_serial_setup(struct earlycon_device *device,
1266                                           const char *options)
1267 {
1268         struct uart_port *port = &device->port;
1269
1270         if (!(device->port.membase || device->port.iobase))
1271                 return -ENODEV;
1272
1273         port->regshift = 2;
1274         device->con->write = early_omap_serial_write;
1275         return 0;
1276 }
1277
1278 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1279 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1280 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1281 #endif /* CONFIG_SERIAL_EARLYCON */
1282
1283 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1284
1285 static struct uart_driver serial_omap_reg;
1286
1287 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1288 {
1289         struct uart_omap_port *up = to_uart_omap_port(port);
1290
1291         wait_for_xmitr(up);
1292         serial_out(up, UART_TX, ch);
1293 }
1294
1295 static void
1296 serial_omap_console_write(struct console *co, const char *s,
1297                 unsigned int count)
1298 {
1299         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1300         unsigned long flags;
1301         unsigned int ier;
1302         int locked = 1;
1303
1304         pm_runtime_get_sync(up->dev);
1305
1306         local_irq_save(flags);
1307         if (up->port.sysrq)
1308                 locked = 0;
1309         else if (oops_in_progress)
1310                 locked = spin_trylock(&up->port.lock);
1311         else
1312                 spin_lock(&up->port.lock);
1313
1314         /*
1315          * First save the IER then disable the interrupts
1316          */
1317         ier = serial_in(up, UART_IER);
1318         serial_out(up, UART_IER, 0);
1319
1320         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1321
1322         /*
1323          * Finally, wait for transmitter to become empty
1324          * and restore the IER
1325          */
1326         wait_for_xmitr(up);
1327         serial_out(up, UART_IER, ier);
1328         /*
1329          * The receive handling will happen properly because the
1330          * receive ready bit will still be set; it is not cleared
1331          * on read.  However, modem control will not, we must
1332          * call it if we have saved something in the saved flags
1333          * while processing with interrupts off.
1334          */
1335         if (up->msr_saved_flags)
1336                 check_modem_status(up);
1337
1338         pm_runtime_mark_last_busy(up->dev);
1339         pm_runtime_put_autosuspend(up->dev);
1340         if (locked)
1341                 spin_unlock(&up->port.lock);
1342         local_irq_restore(flags);
1343 }
1344
1345 static int __init
1346 serial_omap_console_setup(struct console *co, char *options)
1347 {
1348         struct uart_omap_port *up;
1349         int baud = 115200;
1350         int bits = 8;
1351         int parity = 'n';
1352         int flow = 'n';
1353
1354         if (serial_omap_console_ports[co->index] == NULL)
1355                 return -ENODEV;
1356         up = serial_omap_console_ports[co->index];
1357
1358         if (options)
1359                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1360
1361         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1362 }
1363
1364 static struct console serial_omap_console = {
1365         .name           = OMAP_SERIAL_NAME,
1366         .write          = serial_omap_console_write,
1367         .device         = uart_console_device,
1368         .setup          = serial_omap_console_setup,
1369         .flags          = CON_PRINTBUFFER,
1370         .index          = -1,
1371         .data           = &serial_omap_reg,
1372 };
1373
1374 static void serial_omap_add_console_port(struct uart_omap_port *up)
1375 {
1376         serial_omap_console_ports[up->port.line] = up;
1377 }
1378
1379 #define OMAP_CONSOLE    (&serial_omap_console)
1380
1381 #else
1382
1383 #define OMAP_CONSOLE    NULL
1384
1385 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1386 {}
1387
1388 #endif
1389
1390 /* Enable or disable the rs485 support */
1391 static int
1392 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1393 {
1394         struct uart_omap_port *up = to_uart_omap_port(port);
1395         unsigned int mode;
1396         int val;
1397
1398         pm_runtime_get_sync(up->dev);
1399
1400         /* Disable interrupts from this port */
1401         mode = up->ier;
1402         up->ier = 0;
1403         serial_out(up, UART_IER, 0);
1404
1405         /* Clamp the delays to [0, 100ms] */
1406         rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1407         rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
1408
1409         /* store new config */
1410         port->rs485 = *rs485;
1411
1412         /*
1413          * Just as a precaution, only allow rs485
1414          * to be enabled if the gpio pin is valid
1415          */
1416         if (up->rts_gpiod) {
1417                 /* enable / disable rts */
1418                 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1419                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1420                 val = (port->rs485.flags & val) ? 1 : 0;
1421                 gpiod_set_value(up->rts_gpiod, val);
1422         } else
1423                 port->rs485.flags &= ~SER_RS485_ENABLED;
1424
1425         /* Enable interrupts */
1426         up->ier = mode;
1427         serial_out(up, UART_IER, up->ier);
1428
1429         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1430          * TX FIFO is below the trigger level.
1431          */
1432         if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1433             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1434                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1435                 serial_out(up, UART_OMAP_SCR, up->scr);
1436         }
1437
1438         pm_runtime_mark_last_busy(up->dev);
1439         pm_runtime_put_autosuspend(up->dev);
1440
1441         return 0;
1442 }
1443
1444 static const struct uart_ops serial_omap_pops = {
1445         .tx_empty       = serial_omap_tx_empty,
1446         .set_mctrl      = serial_omap_set_mctrl,
1447         .get_mctrl      = serial_omap_get_mctrl,
1448         .stop_tx        = serial_omap_stop_tx,
1449         .start_tx       = serial_omap_start_tx,
1450         .throttle       = serial_omap_throttle,
1451         .unthrottle     = serial_omap_unthrottle,
1452         .stop_rx        = serial_omap_stop_rx,
1453         .enable_ms      = serial_omap_enable_ms,
1454         .break_ctl      = serial_omap_break_ctl,
1455         .startup        = serial_omap_startup,
1456         .shutdown       = serial_omap_shutdown,
1457         .set_termios    = serial_omap_set_termios,
1458         .pm             = serial_omap_pm,
1459         .type           = serial_omap_type,
1460         .release_port   = serial_omap_release_port,
1461         .request_port   = serial_omap_request_port,
1462         .config_port    = serial_omap_config_port,
1463         .verify_port    = serial_omap_verify_port,
1464 #ifdef CONFIG_CONSOLE_POLL
1465         .poll_put_char  = serial_omap_poll_put_char,
1466         .poll_get_char  = serial_omap_poll_get_char,
1467 #endif
1468 };
1469
1470 static struct uart_driver serial_omap_reg = {
1471         .owner          = THIS_MODULE,
1472         .driver_name    = "OMAP-SERIAL",
1473         .dev_name       = OMAP_SERIAL_NAME,
1474         .nr             = OMAP_MAX_HSUART_PORTS,
1475         .cons           = OMAP_CONSOLE,
1476 };
1477
1478 #ifdef CONFIG_PM_SLEEP
1479 static int serial_omap_prepare(struct device *dev)
1480 {
1481         struct uart_omap_port *up = dev_get_drvdata(dev);
1482
1483         up->is_suspending = true;
1484
1485         return 0;
1486 }
1487
1488 static void serial_omap_complete(struct device *dev)
1489 {
1490         struct uart_omap_port *up = dev_get_drvdata(dev);
1491
1492         up->is_suspending = false;
1493 }
1494
1495 static int serial_omap_suspend(struct device *dev)
1496 {
1497         struct uart_omap_port *up = dev_get_drvdata(dev);
1498
1499         uart_suspend_port(&serial_omap_reg, &up->port);
1500         flush_work(&up->qos_work);
1501
1502         if (device_may_wakeup(dev))
1503                 serial_omap_enable_wakeup(up, true);
1504         else
1505                 serial_omap_enable_wakeup(up, false);
1506
1507         return 0;
1508 }
1509
1510 static int serial_omap_resume(struct device *dev)
1511 {
1512         struct uart_omap_port *up = dev_get_drvdata(dev);
1513
1514         if (device_may_wakeup(dev))
1515                 serial_omap_enable_wakeup(up, false);
1516
1517         uart_resume_port(&serial_omap_reg, &up->port);
1518
1519         return 0;
1520 }
1521 #else
1522 #define serial_omap_prepare NULL
1523 #define serial_omap_complete NULL
1524 #endif /* CONFIG_PM_SLEEP */
1525
1526 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1527 {
1528         u32 mvr, scheme;
1529         u16 revision, major, minor;
1530
1531         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1532
1533         /* Check revision register scheme */
1534         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1535
1536         switch (scheme) {
1537         case 0: /* Legacy Scheme: OMAP2/3 */
1538                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1539                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1540                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1541                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1542                 break;
1543         case 1:
1544                 /* New Scheme: OMAP4+ */
1545                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1546                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1547                                         OMAP_UART_MVR_MAJ_SHIFT;
1548                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1549                 break;
1550         default:
1551                 dev_warn(up->dev,
1552                         "Unknown %s revision, defaulting to highest\n",
1553                         up->name);
1554                 /* highest possible revision */
1555                 major = 0xff;
1556                 minor = 0xff;
1557         }
1558
1559         /* normalize revision for the driver */
1560         revision = UART_BUILD_REVISION(major, minor);
1561
1562         switch (revision) {
1563         case OMAP_UART_REV_46:
1564                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1565                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1566                 break;
1567         case OMAP_UART_REV_52:
1568                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1569                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1570                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1571                 break;
1572         case OMAP_UART_REV_63:
1573                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1574                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1575                 break;
1576         default:
1577                 break;
1578         }
1579 }
1580
1581 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1582 {
1583         struct omap_uart_port_info *omap_up_info;
1584
1585         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1586         if (!omap_up_info)
1587                 return NULL; /* out of memory */
1588
1589         of_property_read_u32(dev->of_node, "clock-frequency",
1590                                          &omap_up_info->uartclk);
1591
1592         omap_up_info->flags = UPF_BOOT_AUTOCONF;
1593
1594         return omap_up_info;
1595 }
1596
1597 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1598                                    struct device *dev)
1599 {
1600         struct serial_rs485 *rs485conf = &up->port.rs485;
1601         struct device_node *np = dev->of_node;
1602         enum gpiod_flags gflags;
1603         int ret;
1604
1605         rs485conf->flags = 0;
1606         up->rts_gpiod = NULL;
1607
1608         if (!np)
1609                 return 0;
1610
1611         ret = uart_get_rs485_mode(&up->port);
1612         if (ret)
1613                 return ret;
1614
1615         if (of_property_read_bool(np, "rs485-rts-active-high")) {
1616                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1617                 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1618         } else {
1619                 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1620                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1621         }
1622
1623         /* check for tx enable gpio */
1624         gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1625                 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1626         up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1627         if (IS_ERR(up->rts_gpiod)) {
1628                 ret = PTR_ERR(up->rts_gpiod);
1629                 if (ret == -EPROBE_DEFER)
1630                         return ret;
1631                 /*
1632                  * FIXME: the code historically ignored any other error than
1633                  * -EPROBE_DEFER and just went on without GPIO.
1634                  */
1635                 up->rts_gpiod = NULL;
1636         } else {
1637                 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int serial_omap_probe(struct platform_device *pdev)
1644 {
1645         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1646         struct uart_omap_port *up;
1647         struct resource *mem;
1648         void __iomem *base;
1649         int uartirq = 0;
1650         int wakeirq = 0;
1651         int ret;
1652
1653         /* The optional wakeirq may be specified in the board dts file */
1654         if (pdev->dev.of_node) {
1655                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1656                 if (!uartirq)
1657                         return -EPROBE_DEFER;
1658                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1659                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1660                 pdev->dev.platform_data = omap_up_info;
1661         } else {
1662                 uartirq = platform_get_irq(pdev, 0);
1663                 if (uartirq < 0)
1664                         return -EPROBE_DEFER;
1665         }
1666
1667         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1668         if (!up)
1669                 return -ENOMEM;
1670
1671         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672         base = devm_ioremap_resource(&pdev->dev, mem);
1673         if (IS_ERR(base))
1674                 return PTR_ERR(base);
1675
1676         up->dev = &pdev->dev;
1677         up->port.dev = &pdev->dev;
1678         up->port.type = PORT_OMAP;
1679         up->port.iotype = UPIO_MEM;
1680         up->port.irq = uartirq;
1681         up->port.regshift = 2;
1682         up->port.fifosize = 64;
1683         up->port.ops = &serial_omap_pops;
1684         up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1685
1686         if (pdev->dev.of_node)
1687                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1688         else
1689                 ret = pdev->id;
1690
1691         if (ret < 0) {
1692                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1693                         ret);
1694                 goto err_port_line;
1695         }
1696         up->port.line = ret;
1697
1698         if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1699                 dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1700                         OMAP_MAX_HSUART_PORTS);
1701                 ret = -ENXIO;
1702                 goto err_port_line;
1703         }
1704
1705         up->wakeirq = wakeirq;
1706         if (!up->wakeirq)
1707                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1708                          up->port.line);
1709
1710         ret = serial_omap_probe_rs485(up, &pdev->dev);
1711         if (ret < 0)
1712                 goto err_rs485;
1713
1714         sprintf(up->name, "OMAP UART%d", up->port.line);
1715         up->port.mapbase = mem->start;
1716         up->port.membase = base;
1717         up->port.flags = omap_up_info->flags;
1718         up->port.uartclk = omap_up_info->uartclk;
1719         up->port.rs485_config = serial_omap_config_rs485;
1720         if (!up->port.uartclk) {
1721                 up->port.uartclk = DEFAULT_CLK_SPEED;
1722                 dev_warn(&pdev->dev,
1723                          "No clock speed specified: using default: %d\n",
1724                          DEFAULT_CLK_SPEED);
1725         }
1726
1727         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1728         up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1729         cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1730         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1731
1732         platform_set_drvdata(pdev, up);
1733         if (omap_up_info->autosuspend_timeout == 0)
1734                 omap_up_info->autosuspend_timeout = -1;
1735
1736         device_init_wakeup(up->dev, true);
1737         pm_runtime_use_autosuspend(&pdev->dev);
1738         pm_runtime_set_autosuspend_delay(&pdev->dev,
1739                         omap_up_info->autosuspend_timeout);
1740
1741         pm_runtime_irq_safe(&pdev->dev);
1742         pm_runtime_enable(&pdev->dev);
1743
1744         pm_runtime_get_sync(&pdev->dev);
1745
1746         omap_serial_fill_features_erratas(up);
1747
1748         ui[up->port.line] = up;
1749         serial_omap_add_console_port(up);
1750
1751         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1752         if (ret != 0)
1753                 goto err_add_port;
1754
1755         pm_runtime_mark_last_busy(up->dev);
1756         pm_runtime_put_autosuspend(up->dev);
1757         return 0;
1758
1759 err_add_port:
1760         pm_runtime_dont_use_autosuspend(&pdev->dev);
1761         pm_runtime_put_sync(&pdev->dev);
1762         pm_runtime_disable(&pdev->dev);
1763         cpu_latency_qos_remove_request(&up->pm_qos_request);
1764         device_init_wakeup(up->dev, false);
1765 err_rs485:
1766 err_port_line:
1767         return ret;
1768 }
1769
1770 static int serial_omap_remove(struct platform_device *dev)
1771 {
1772         struct uart_omap_port *up = platform_get_drvdata(dev);
1773
1774         pm_runtime_get_sync(up->dev);
1775
1776         uart_remove_one_port(&serial_omap_reg, &up->port);
1777
1778         pm_runtime_dont_use_autosuspend(up->dev);
1779         pm_runtime_put_sync(up->dev);
1780         pm_runtime_disable(up->dev);
1781         cpu_latency_qos_remove_request(&up->pm_qos_request);
1782         device_init_wakeup(&dev->dev, false);
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1789  * The access to uart register after MDR1 Access
1790  * causes UART to corrupt data.
1791  *
1792  * Need a delay =
1793  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1794  * give 10 times as much
1795  */
1796 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1797 {
1798         u8 timeout = 255;
1799
1800         serial_out(up, UART_OMAP_MDR1, mdr1);
1801         udelay(2);
1802         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1803                         UART_FCR_CLEAR_RCVR);
1804         /*
1805          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1806          * TX_FIFO_E bit is 1.
1807          */
1808         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1809                                 (UART_LSR_THRE | UART_LSR_DR))) {
1810                 timeout--;
1811                 if (!timeout) {
1812                         /* Should *never* happen. we warn and carry on */
1813                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1814                                                 serial_in(up, UART_LSR));
1815                         break;
1816                 }
1817                 udelay(1);
1818         }
1819 }
1820
1821 #ifdef CONFIG_PM
1822 static void serial_omap_restore_context(struct uart_omap_port *up)
1823 {
1824         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1825                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1826         else
1827                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1828
1829         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1830         serial_out(up, UART_EFR, UART_EFR_ECB);
1831         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1832         serial_out(up, UART_IER, 0x0);
1833         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1834         serial_out(up, UART_DLL, up->dll);
1835         serial_out(up, UART_DLM, up->dlh);
1836         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1837         serial_out(up, UART_IER, up->ier);
1838         serial_out(up, UART_FCR, up->fcr);
1839         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1840         serial_out(up, UART_MCR, up->mcr);
1841         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1842         serial_out(up, UART_OMAP_SCR, up->scr);
1843         serial_out(up, UART_EFR, up->efr);
1844         serial_out(up, UART_LCR, up->lcr);
1845         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1846                 serial_omap_mdr1_errataset(up, up->mdr1);
1847         else
1848                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1849         serial_out(up, UART_OMAP_WER, up->wer);
1850 }
1851
1852 static int serial_omap_runtime_suspend(struct device *dev)
1853 {
1854         struct uart_omap_port *up = dev_get_drvdata(dev);
1855
1856         if (!up)
1857                 return -EINVAL;
1858
1859         /*
1860         * When using 'no_console_suspend', the console UART must not be
1861         * suspended. Since driver suspend is managed by runtime suspend,
1862         * preventing runtime suspend (by returning error) will keep device
1863         * active during suspend.
1864         */
1865         if (up->is_suspending && !console_suspend_enabled &&
1866             uart_console(&up->port))
1867                 return -EBUSY;
1868
1869         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1870
1871         serial_omap_enable_wakeup(up, true);
1872
1873         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1874         schedule_work(&up->qos_work);
1875
1876         return 0;
1877 }
1878
1879 static int serial_omap_runtime_resume(struct device *dev)
1880 {
1881         struct uart_omap_port *up = dev_get_drvdata(dev);
1882
1883         int loss_cnt = serial_omap_get_context_loss_count(up);
1884
1885         serial_omap_enable_wakeup(up, false);
1886
1887         if (loss_cnt < 0) {
1888                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1889                         loss_cnt);
1890                 serial_omap_restore_context(up);
1891         } else if (up->context_loss_cnt != loss_cnt) {
1892                 serial_omap_restore_context(up);
1893         }
1894         up->latency = up->calc_latency;
1895         schedule_work(&up->qos_work);
1896
1897         return 0;
1898 }
1899 #endif
1900
1901 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1902         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1903         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1904                                 serial_omap_runtime_resume, NULL)
1905         .prepare        = serial_omap_prepare,
1906         .complete       = serial_omap_complete,
1907 };
1908
1909 #if defined(CONFIG_OF)
1910 static const struct of_device_id omap_serial_of_match[] = {
1911         { .compatible = "ti,omap2-uart" },
1912         { .compatible = "ti,omap3-uart" },
1913         { .compatible = "ti,omap4-uart" },
1914         {},
1915 };
1916 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1917 #endif
1918
1919 static struct platform_driver serial_omap_driver = {
1920         .probe          = serial_omap_probe,
1921         .remove         = serial_omap_remove,
1922         .driver         = {
1923                 .name   = OMAP_SERIAL_DRIVER_NAME,
1924                 .pm     = &serial_omap_dev_pm_ops,
1925                 .of_match_table = of_match_ptr(omap_serial_of_match),
1926         },
1927 };
1928
1929 static int __init serial_omap_init(void)
1930 {
1931         int ret;
1932
1933         ret = uart_register_driver(&serial_omap_reg);
1934         if (ret != 0)
1935                 return ret;
1936         ret = platform_driver_register(&serial_omap_driver);
1937         if (ret != 0)
1938                 uart_unregister_driver(&serial_omap_reg);
1939         return ret;
1940 }
1941
1942 static void __exit serial_omap_exit(void)
1943 {
1944         platform_driver_unregister(&serial_omap_driver);
1945         uart_unregister_driver(&serial_omap_reg);
1946 }
1947
1948 module_init(serial_omap_init);
1949 module_exit(serial_omap_exit);
1950
1951 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1952 MODULE_LICENSE("GPL");
1953 MODULE_AUTHOR("Texas Instruments Inc");