2 * ***************************************************************************
3 * Marvell Armada-3700 Serial Driver
4 * Author: Wilson Ding <dingwei@marvell.com>
5 * Copyright (C) 2015 Marvell International Ltd.
6 * ***************************************************************************
7 * This program is free software: you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation, either version 2 of the License, or any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * ***************************************************************************
21 #include <linux/clk.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/slab.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
41 #define UART_STD_RBR 0x00
42 #define UART_EXT_RBR 0x18
44 #define UART_STD_TSH 0x04
45 #define UART_EXT_TSH 0x1C
47 #define UART_STD_CTRL1 0x08
48 #define UART_EXT_CTRL1 0x04
49 #define CTRL_SOFT_RST BIT(31)
50 #define CTRL_TXFIFO_RST BIT(15)
51 #define CTRL_RXFIFO_RST BIT(14)
52 #define CTRL_SND_BRK_SEQ BIT(11)
53 #define CTRL_BRK_DET_INT BIT(3)
54 #define CTRL_FRM_ERR_INT BIT(2)
55 #define CTRL_PAR_ERR_INT BIT(1)
56 #define CTRL_OVR_ERR_INT BIT(0)
57 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
58 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
60 #define UART_STD_CTRL2 UART_STD_CTRL1
61 #define UART_EXT_CTRL2 0x20
62 #define CTRL_STD_TX_RDY_INT BIT(5)
63 #define CTRL_EXT_TX_RDY_INT BIT(6)
64 #define CTRL_STD_RX_RDY_INT BIT(4)
65 #define CTRL_EXT_RX_RDY_INT BIT(5)
67 #define UART_STAT 0x0C
68 #define STAT_TX_FIFO_EMP BIT(13)
69 #define STAT_TX_FIFO_FUL BIT(11)
70 #define STAT_TX_EMP BIT(6)
71 #define STAT_STD_TX_RDY BIT(5)
72 #define STAT_EXT_TX_RDY BIT(15)
73 #define STAT_STD_RX_RDY BIT(4)
74 #define STAT_EXT_RX_RDY BIT(14)
75 #define STAT_BRK_DET BIT(3)
76 #define STAT_FRM_ERR BIT(2)
77 #define STAT_PAR_ERR BIT(1)
78 #define STAT_OVR_ERR BIT(0)
79 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
80 | STAT_PAR_ERR | STAT_OVR_ERR)
82 #define UART_BRDV 0x10
83 #define BRDV_BAUD_MASK 0x3FF
85 #define MVEBU_NR_UARTS 2
87 #define MVEBU_UART_TYPE "mvebu-uart"
88 #define DRIVER_NAME "mvebu_serial"
91 /* Either there is only one summed IRQ... */
93 /* ...or there are two separate IRQ for RX and TX */
99 /* Diverging register offsets */
100 struct uart_regs_layout {
107 /* Diverging flags */
109 unsigned int ctrl_tx_rdy_int;
110 unsigned int ctrl_rx_rdy_int;
111 unsigned int stat_tx_rdy;
112 unsigned int stat_rx_rdy;
115 /* Driver data, a structure for each UART port */
116 struct mvebu_uart_driver_data {
118 struct uart_regs_layout regs;
119 struct uart_flags flags;
122 /* MVEBU UART driver structure */
124 struct uart_port *port;
126 int irq[UART_IRQ_COUNT];
127 unsigned char __iomem *nb;
128 struct mvebu_uart_driver_data *data;
131 static struct mvebu_uart *to_mvuart(struct uart_port *port)
133 return (struct mvebu_uart *)port->private_data;
136 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
138 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
139 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
140 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
141 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
143 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
144 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
145 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
146 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
148 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
150 /* Core UART Driver Operations */
151 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
156 spin_lock_irqsave(&port->lock, flags);
157 st = readl(port->membase + UART_STAT);
158 spin_unlock_irqrestore(&port->lock, flags);
160 return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
163 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
165 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
168 static void mvebu_uart_set_mctrl(struct uart_port *port,
172 * Even if we do not support configuring the modem control lines, this
173 * function must be proided to the serial core
177 static void mvebu_uart_stop_tx(struct uart_port *port)
179 unsigned int ctl = readl(port->membase + UART_INTR(port));
181 ctl &= ~CTRL_TX_RDY_INT(port);
182 writel(ctl, port->membase + UART_INTR(port));
185 static void mvebu_uart_start_tx(struct uart_port *port)
188 struct circ_buf *xmit = &port->state->xmit;
190 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
191 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
192 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
196 ctl = readl(port->membase + UART_INTR(port));
197 ctl |= CTRL_TX_RDY_INT(port);
198 writel(ctl, port->membase + UART_INTR(port));
201 static void mvebu_uart_stop_rx(struct uart_port *port)
205 ctl = readl(port->membase + UART_CTRL(port));
206 ctl &= ~CTRL_BRK_INT;
207 writel(ctl, port->membase + UART_CTRL(port));
209 ctl = readl(port->membase + UART_INTR(port));
210 ctl &= ~CTRL_RX_RDY_INT(port);
211 writel(ctl, port->membase + UART_INTR(port));
214 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
219 spin_lock_irqsave(&port->lock, flags);
220 ctl = readl(port->membase + UART_CTRL(port));
222 ctl |= CTRL_SND_BRK_SEQ;
224 ctl &= ~CTRL_SND_BRK_SEQ;
225 writel(ctl, port->membase + UART_CTRL(port));
226 spin_unlock_irqrestore(&port->lock, flags);
229 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
231 struct tty_port *tport = &port->state->port;
232 unsigned char ch = 0;
236 if (status & STAT_RX_RDY(port)) {
237 ch = readl(port->membase + UART_RBR(port));
242 if (status & STAT_PAR_ERR)
243 port->icount.parity++;
246 if (status & STAT_BRK_DET) {
248 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
249 if (uart_handle_break(port))
253 if (status & STAT_OVR_ERR)
254 port->icount.overrun++;
256 if (status & STAT_FRM_ERR)
257 port->icount.frame++;
259 if (uart_handle_sysrq_char(port, ch))
262 if (status & port->ignore_status_mask & STAT_PAR_ERR)
263 status &= ~STAT_RX_RDY(port);
265 status &= port->read_status_mask;
267 if (status & STAT_PAR_ERR)
270 status &= ~port->ignore_status_mask;
272 if (status & STAT_RX_RDY(port))
273 tty_insert_flip_char(tport, ch, flag);
275 if (status & STAT_BRK_DET)
276 tty_insert_flip_char(tport, 0, TTY_BREAK);
278 if (status & STAT_FRM_ERR)
279 tty_insert_flip_char(tport, 0, TTY_FRAME);
281 if (status & STAT_OVR_ERR)
282 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
285 status = readl(port->membase + UART_STAT);
286 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
288 tty_flip_buffer_push(tport);
291 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
293 struct circ_buf *xmit = &port->state->xmit;
298 writel(port->x_char, port->membase + UART_TSH(port));
304 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
305 mvebu_uart_stop_tx(port);
309 for (count = 0; count < port->fifosize; count++) {
310 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
311 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
314 if (uart_circ_empty(xmit))
317 st = readl(port->membase + UART_STAT);
318 if (st & STAT_TX_FIFO_FUL)
322 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
323 uart_write_wakeup(port);
325 if (uart_circ_empty(xmit))
326 mvebu_uart_stop_tx(port);
329 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
331 struct uart_port *port = (struct uart_port *)dev_id;
332 unsigned int st = readl(port->membase + UART_STAT);
334 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
336 mvebu_uart_rx_chars(port, st);
338 if (st & STAT_TX_RDY(port))
339 mvebu_uart_tx_chars(port, st);
344 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
346 struct uart_port *port = (struct uart_port *)dev_id;
347 unsigned int st = readl(port->membase + UART_STAT);
349 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
351 mvebu_uart_rx_chars(port, st);
356 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
358 struct uart_port *port = (struct uart_port *)dev_id;
359 unsigned int st = readl(port->membase + UART_STAT);
361 if (st & STAT_TX_RDY(port))
362 mvebu_uart_tx_chars(port, st);
367 static int mvebu_uart_startup(struct uart_port *port)
369 struct mvebu_uart *mvuart = to_mvuart(port);
373 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
374 port->membase + UART_CTRL(port));
377 /* Clear the error bits of state register before IRQ request */
378 ret = readl(port->membase + UART_STAT);
380 writel(ret, port->membase + UART_STAT);
382 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
384 ctl = readl(port->membase + UART_INTR(port));
385 ctl |= CTRL_RX_RDY_INT(port);
386 writel(ctl, port->membase + UART_INTR(port));
388 if (!mvuart->irq[UART_TX_IRQ]) {
389 /* Old bindings with just one interrupt (UART0 only) */
390 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
391 mvebu_uart_isr, port->irqflags,
392 dev_name(port->dev), port);
394 dev_err(port->dev, "unable to request IRQ %d\n",
395 mvuart->irq[UART_IRQ_SUM]);
399 /* New bindings with an IRQ for RX and TX (both UART) */
400 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
401 mvebu_uart_rx_isr, port->irqflags,
402 dev_name(port->dev), port);
404 dev_err(port->dev, "unable to request IRQ %d\n",
405 mvuart->irq[UART_RX_IRQ]);
409 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
410 mvebu_uart_tx_isr, port->irqflags,
414 dev_err(port->dev, "unable to request IRQ %d\n",
415 mvuart->irq[UART_TX_IRQ]);
416 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
425 static void mvebu_uart_shutdown(struct uart_port *port)
427 struct mvebu_uart *mvuart = to_mvuart(port);
429 writel(0, port->membase + UART_INTR(port));
431 if (!mvuart->irq[UART_TX_IRQ]) {
432 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
434 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
435 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
439 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
441 struct mvebu_uart *mvuart = to_mvuart(port);
442 unsigned int baud_rate_div;
445 if (IS_ERR(mvuart->clk))
446 return -PTR_ERR(mvuart->clk);
449 * The UART clock is divided by the value of the divisor to generate
450 * UCLK_OUT clock, which is 16 times faster than the baudrate.
451 * This prescaler can achieve all standard baudrates until 230400.
452 * Higher baudrates could be achieved for the extended UART by using the
453 * programmable oversampling stack (also called fractional divisor).
455 baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
456 brdv = readl(port->membase + UART_BRDV);
457 brdv &= ~BRDV_BAUD_MASK;
458 brdv |= baud_rate_div;
459 writel(brdv, port->membase + UART_BRDV);
464 static void mvebu_uart_set_termios(struct uart_port *port,
465 struct ktermios *termios,
466 struct ktermios *old)
471 spin_lock_irqsave(&port->lock, flags);
473 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
474 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
476 if (termios->c_iflag & INPCK)
477 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
479 port->ignore_status_mask = 0;
480 if (termios->c_iflag & IGNPAR)
481 port->ignore_status_mask |=
482 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
484 if ((termios->c_cflag & CREAD) == 0)
485 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
488 * Maximum achievable frequency with simple baudrate divisor is 230400.
489 * Since the error per bit frame would be of more than 15%, achieving
490 * higher frequencies would require to implement the fractional divisor
493 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
494 if (mvebu_uart_baud_rate_set(port, baud)) {
495 /* No clock available, baudrate cannot be changed */
497 baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
499 tty_termios_encode_baud_rate(termios, baud, baud);
500 uart_update_timeout(port, termios->c_cflag, baud);
503 /* Only the following flag changes are supported */
505 termios->c_iflag &= INPCK | IGNPAR;
506 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
507 termios->c_cflag &= CREAD | CBAUD;
508 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
509 termios->c_lflag = old->c_lflag;
512 spin_unlock_irqrestore(&port->lock, flags);
515 static const char *mvebu_uart_type(struct uart_port *port)
517 return MVEBU_UART_TYPE;
520 static void mvebu_uart_release_port(struct uart_port *port)
522 /* Nothing to do here */
525 static int mvebu_uart_request_port(struct uart_port *port)
530 #ifdef CONFIG_CONSOLE_POLL
531 static int mvebu_uart_get_poll_char(struct uart_port *port)
533 unsigned int st = readl(port->membase + UART_STAT);
535 if (!(st & STAT_RX_RDY(port)))
538 return readl(port->membase + UART_RBR(port));
541 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
546 st = readl(port->membase + UART_STAT);
548 if (!(st & STAT_TX_FIFO_FUL))
554 writel(c, port->membase + UART_TSH(port));
558 static const struct uart_ops mvebu_uart_ops = {
559 .tx_empty = mvebu_uart_tx_empty,
560 .set_mctrl = mvebu_uart_set_mctrl,
561 .get_mctrl = mvebu_uart_get_mctrl,
562 .stop_tx = mvebu_uart_stop_tx,
563 .start_tx = mvebu_uart_start_tx,
564 .stop_rx = mvebu_uart_stop_rx,
565 .break_ctl = mvebu_uart_break_ctl,
566 .startup = mvebu_uart_startup,
567 .shutdown = mvebu_uart_shutdown,
568 .set_termios = mvebu_uart_set_termios,
569 .type = mvebu_uart_type,
570 .release_port = mvebu_uart_release_port,
571 .request_port = mvebu_uart_request_port,
572 #ifdef CONFIG_CONSOLE_POLL
573 .poll_get_char = mvebu_uart_get_poll_char,
574 .poll_put_char = mvebu_uart_put_poll_char,
578 /* Console Driver Operations */
580 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
582 static void mvebu_uart_putc(struct uart_port *port, int c)
587 st = readl(port->membase + UART_STAT);
588 if (!(st & STAT_TX_FIFO_FUL))
592 /* At early stage, DT is not parsed yet, only use UART0 */
593 writel(c, port->membase + UART_STD_TSH);
596 st = readl(port->membase + UART_STAT);
597 if (st & STAT_TX_FIFO_EMP)
602 static void mvebu_uart_putc_early_write(struct console *con,
606 struct earlycon_device *dev = con->data;
608 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
612 mvebu_uart_early_console_setup(struct earlycon_device *device,
615 if (!device->port.membase)
618 device->con->write = mvebu_uart_putc_early_write;
623 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
624 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
625 mvebu_uart_early_console_setup);
627 static void wait_for_xmitr(struct uart_port *port)
631 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
632 (val & STAT_TX_EMP), 1, 10000);
635 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
637 wait_for_xmitr(port);
638 writel(ch, port->membase + UART_TSH(port));
641 static void mvebu_uart_console_write(struct console *co, const char *s,
644 struct uart_port *port = &mvebu_uart_ports[co->index];
646 unsigned int ier, intr, ctl;
649 if (oops_in_progress)
650 locked = spin_trylock_irqsave(&port->lock, flags);
652 spin_lock_irqsave(&port->lock, flags);
654 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
655 intr = readl(port->membase + UART_INTR(port)) &
656 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
657 writel(0, port->membase + UART_CTRL(port));
658 writel(0, port->membase + UART_INTR(port));
660 uart_console_write(port, s, count, mvebu_uart_console_putchar);
662 wait_for_xmitr(port);
665 writel(ier, port->membase + UART_CTRL(port));
668 ctl = intr | readl(port->membase + UART_INTR(port));
669 writel(ctl, port->membase + UART_INTR(port));
673 spin_unlock_irqrestore(&port->lock, flags);
676 static int mvebu_uart_console_setup(struct console *co, char *options)
678 struct uart_port *port;
684 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
687 port = &mvebu_uart_ports[co->index];
689 if (!port->mapbase || !port->membase) {
690 pr_debug("console on ttyMV%i not present\n", co->index);
695 uart_parse_options(options, &baud, &parity, &bits, &flow);
697 return uart_set_options(port, co, baud, parity, bits, flow);
700 static struct uart_driver mvebu_uart_driver;
702 static struct console mvebu_uart_console = {
704 .write = mvebu_uart_console_write,
705 .device = uart_console_device,
706 .setup = mvebu_uart_console_setup,
707 .flags = CON_PRINTBUFFER,
709 .data = &mvebu_uart_driver,
712 static int __init mvebu_uart_console_init(void)
714 register_console(&mvebu_uart_console);
718 console_initcall(mvebu_uart_console_init);
721 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
723 static struct uart_driver mvebu_uart_driver = {
724 .owner = THIS_MODULE,
725 .driver_name = DRIVER_NAME,
727 .nr = MVEBU_NR_UARTS,
728 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
729 .cons = &mvebu_uart_console,
733 static const struct of_device_id mvebu_uart_of_match[];
735 /* Counter to keep track of each UART port id when not using CONFIG_OF */
736 static int uart_num_counter;
738 static int mvebu_uart_probe(struct platform_device *pdev)
740 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
743 struct uart_port *port;
744 struct mvebu_uart *mvuart;
748 dev_err(&pdev->dev, "no registers defined\n");
752 /* Assume that all UART ports have a DT alias or none has */
753 id = of_alias_get_id(pdev->dev.of_node, "serial");
754 if (!pdev->dev.of_node || id < 0)
755 pdev->id = uart_num_counter++;
759 if (pdev->id >= MVEBU_NR_UARTS) {
760 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
765 port = &mvebu_uart_ports[pdev->id];
767 spin_lock_init(&port->lock);
769 port->dev = &pdev->dev;
770 port->type = PORT_MVEBU;
771 port->ops = &mvebu_uart_ops;
775 port->iotype = UPIO_MEM32;
776 port->flags = UPF_FIXED_PORT;
777 port->line = pdev->id;
780 * IRQ number is not stored in this structure because we may have two of
781 * them per port (RX and TX). Instead, use the driver UART structure
782 * array so called ->irq[].
786 port->mapbase = reg->start;
788 port->membase = devm_ioremap_resource(&pdev->dev, reg);
789 if (IS_ERR(port->membase))
790 return -PTR_ERR(port->membase);
792 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
797 /* Get controller data depending on the compatible string */
798 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
801 port->private_data = mvuart;
802 platform_set_drvdata(pdev, mvuart);
804 /* Get fixed clock frequency */
805 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
806 if (IS_ERR(mvuart->clk)) {
807 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
808 return PTR_ERR(mvuart->clk);
810 if (IS_EXTENDED(port)) {
811 dev_err(&pdev->dev, "unable to get UART clock\n");
812 return PTR_ERR(mvuart->clk);
815 if (!clk_prepare_enable(mvuart->clk))
816 port->uartclk = clk_get_rate(mvuart->clk);
819 /* Manage interrupts */
820 if (platform_irq_count(pdev) == 1) {
821 /* Old bindings: no name on the single unamed UART0 IRQ */
822 irq = platform_get_irq(pdev, 0);
824 dev_err(&pdev->dev, "unable to get UART IRQ\n");
828 mvuart->irq[UART_IRQ_SUM] = irq;
831 * New bindings: named interrupts (RX, TX) for both UARTS,
832 * only make use of uart-rx and uart-tx interrupts, do not use
833 * uart-sum of UART0 port.
835 irq = platform_get_irq_byname(pdev, "uart-rx");
837 dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n");
841 mvuart->irq[UART_RX_IRQ] = irq;
843 irq = platform_get_irq_byname(pdev, "uart-tx");
845 dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n");
849 mvuart->irq[UART_TX_IRQ] = irq;
853 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
855 writel(0, port->membase + UART_CTRL(port));
857 ret = uart_add_one_port(&mvebu_uart_driver, port);
863 static struct mvebu_uart_driver_data uart_std_driver_data = {
865 .regs.rbr = UART_STD_RBR,
866 .regs.tsh = UART_STD_TSH,
867 .regs.ctrl = UART_STD_CTRL1,
868 .regs.intr = UART_STD_CTRL2,
869 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
870 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
871 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
872 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
875 static struct mvebu_uart_driver_data uart_ext_driver_data = {
877 .regs.rbr = UART_EXT_RBR,
878 .regs.tsh = UART_EXT_TSH,
879 .regs.ctrl = UART_EXT_CTRL1,
880 .regs.intr = UART_EXT_CTRL2,
881 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
882 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
883 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
884 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
887 /* Match table for of_platform binding */
888 static const struct of_device_id mvebu_uart_of_match[] = {
890 .compatible = "marvell,armada-3700-uart",
891 .data = (void *)&uart_std_driver_data,
894 .compatible = "marvell,armada-3700-uart-ext",
895 .data = (void *)&uart_ext_driver_data,
900 static struct platform_driver mvebu_uart_platform_driver = {
901 .probe = mvebu_uart_probe,
903 .name = "mvebu-uart",
904 .of_match_table = of_match_ptr(mvebu_uart_of_match),
905 .suppress_bind_attrs = true,
909 static int __init mvebu_uart_init(void)
913 ret = uart_register_driver(&mvebu_uart_driver);
917 ret = platform_driver_register(&mvebu_uart_platform_driver);
919 uart_unregister_driver(&mvebu_uart_driver);
923 arch_initcall(mvebu_uart_init);