2 * Based on meson_uart.c, by AMLOGIC, INC.
4 * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/console.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial.h>
27 #include <linux/serial_core.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
31 /* Register offsets */
32 #define AML_UART_WFIFO 0x00
33 #define AML_UART_RFIFO 0x04
34 #define AML_UART_CONTROL 0x08
35 #define AML_UART_STATUS 0x0c
36 #define AML_UART_MISC 0x10
37 #define AML_UART_REG5 0x14
39 /* AML_UART_CONTROL bits */
40 #define AML_UART_TX_EN BIT(12)
41 #define AML_UART_RX_EN BIT(13)
42 #define AML_UART_TX_RST BIT(22)
43 #define AML_UART_RX_RST BIT(23)
44 #define AML_UART_CLR_ERR BIT(24)
45 #define AML_UART_RX_INT_EN BIT(27)
46 #define AML_UART_TX_INT_EN BIT(28)
47 #define AML_UART_DATA_LEN_MASK (0x03 << 20)
48 #define AML_UART_DATA_LEN_8BIT (0x00 << 20)
49 #define AML_UART_DATA_LEN_7BIT (0x01 << 20)
50 #define AML_UART_DATA_LEN_6BIT (0x02 << 20)
51 #define AML_UART_DATA_LEN_5BIT (0x03 << 20)
53 /* AML_UART_STATUS bits */
54 #define AML_UART_PARITY_ERR BIT(16)
55 #define AML_UART_FRAME_ERR BIT(17)
56 #define AML_UART_TX_FIFO_WERR BIT(18)
57 #define AML_UART_RX_EMPTY BIT(20)
58 #define AML_UART_TX_FULL BIT(21)
59 #define AML_UART_TX_EMPTY BIT(22)
60 #define AML_UART_XMIT_BUSY BIT(25)
61 #define AML_UART_ERR (AML_UART_PARITY_ERR | \
62 AML_UART_FRAME_ERR | \
63 AML_UART_TX_FIFO_WERR)
65 /* AML_UART_CONTROL bits */
66 #define AML_UART_TWO_WIRE_EN BIT(15)
67 #define AML_UART_PARITY_TYPE BIT(18)
68 #define AML_UART_PARITY_EN BIT(19)
69 #define AML_UART_CLEAR_ERR BIT(24)
70 #define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16)
71 #define AML_UART_STOP_BIN_1SB (0x00 << 16)
72 #define AML_UART_STOP_BIN_2SB (0x01 << 16)
74 /* AML_UART_MISC bits */
75 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
76 #define AML_UART_RECV_IRQ(c) ((c) & 0xff)
78 /* AML_UART_REG5 bits */
79 #define AML_UART_BAUD_MASK 0x7fffff
80 #define AML_UART_BAUD_USE BIT(23)
81 #define AML_UART_BAUD_XTAL BIT(24)
83 #define AML_UART_PORT_NUM 6
84 #define AML_UART_DEV_NAME "ttyAML"
87 static struct uart_driver meson_uart_driver;
89 static struct uart_port *meson_ports[AML_UART_PORT_NUM];
91 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
95 static unsigned int meson_uart_get_mctrl(struct uart_port *port)
100 static unsigned int meson_uart_tx_empty(struct uart_port *port)
104 val = readl(port->membase + AML_UART_STATUS);
105 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
106 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
109 static void meson_uart_stop_tx(struct uart_port *port)
113 val = readl(port->membase + AML_UART_CONTROL);
114 val &= ~AML_UART_TX_INT_EN;
115 writel(val, port->membase + AML_UART_CONTROL);
118 static void meson_uart_stop_rx(struct uart_port *port)
122 val = readl(port->membase + AML_UART_CONTROL);
123 val &= ~AML_UART_RX_EN;
124 writel(val, port->membase + AML_UART_CONTROL);
127 static void meson_uart_shutdown(struct uart_port *port)
132 free_irq(port->irq, port);
134 spin_lock_irqsave(&port->lock, flags);
136 val = readl(port->membase + AML_UART_CONTROL);
137 val &= ~AML_UART_RX_EN;
138 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
139 writel(val, port->membase + AML_UART_CONTROL);
141 spin_unlock_irqrestore(&port->lock, flags);
144 static void meson_uart_start_tx(struct uart_port *port)
146 struct circ_buf *xmit = &port->state->xmit;
150 if (uart_tx_stopped(port)) {
151 meson_uart_stop_tx(port);
155 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
157 writel(port->x_char, port->membase + AML_UART_WFIFO);
163 if (uart_circ_empty(xmit))
166 ch = xmit->buf[xmit->tail];
167 writel(ch, port->membase + AML_UART_WFIFO);
168 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
172 if (!uart_circ_empty(xmit)) {
173 val = readl(port->membase + AML_UART_CONTROL);
174 val |= AML_UART_TX_INT_EN;
175 writel(val, port->membase + AML_UART_CONTROL);
178 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
179 uart_write_wakeup(port);
182 static void meson_receive_chars(struct uart_port *port)
184 struct tty_port *tport = &port->state->port;
186 u32 status, ch, mode;
191 status = readl(port->membase + AML_UART_STATUS);
193 if (status & AML_UART_ERR) {
194 if (status & AML_UART_TX_FIFO_WERR)
195 port->icount.overrun++;
196 else if (status & AML_UART_FRAME_ERR)
197 port->icount.frame++;
198 else if (status & AML_UART_PARITY_ERR)
199 port->icount.frame++;
201 mode = readl(port->membase + AML_UART_CONTROL);
202 mode |= AML_UART_CLEAR_ERR;
203 writel(mode, port->membase + AML_UART_CONTROL);
205 /* It doesn't clear to 0 automatically */
206 mode &= ~AML_UART_CLEAR_ERR;
207 writel(mode, port->membase + AML_UART_CONTROL);
209 status &= port->read_status_mask;
210 if (status & AML_UART_FRAME_ERR)
212 else if (status & AML_UART_PARITY_ERR)
216 ch = readl(port->membase + AML_UART_RFIFO);
219 if ((status & port->ignore_status_mask) == 0)
220 tty_insert_flip_char(tport, ch, flag);
222 if (status & AML_UART_TX_FIFO_WERR)
223 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
225 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
227 spin_unlock(&port->lock);
228 tty_flip_buffer_push(tport);
229 spin_lock(&port->lock);
232 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
234 struct uart_port *port = (struct uart_port *)dev_id;
236 spin_lock(&port->lock);
238 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
239 meson_receive_chars(port);
241 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
242 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
243 meson_uart_start_tx(port);
246 spin_unlock(&port->lock);
251 static const char *meson_uart_type(struct uart_port *port)
253 return (port->type == PORT_MESON) ? "meson_uart" : NULL;
256 static void meson_uart_reset(struct uart_port *port)
260 val = readl(port->membase + AML_UART_CONTROL);
261 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
262 writel(val, port->membase + AML_UART_CONTROL);
264 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
265 writel(val, port->membase + AML_UART_CONTROL);
268 static int meson_uart_startup(struct uart_port *port)
273 val = readl(port->membase + AML_UART_CONTROL);
274 val |= AML_UART_CLR_ERR;
275 writel(val, port->membase + AML_UART_CONTROL);
276 val &= ~AML_UART_CLR_ERR;
277 writel(val, port->membase + AML_UART_CONTROL);
279 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
280 writel(val, port->membase + AML_UART_CONTROL);
282 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
283 writel(val, port->membase + AML_UART_CONTROL);
285 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
286 writel(val, port->membase + AML_UART_MISC);
288 ret = request_irq(port->irq, meson_uart_interrupt, 0,
294 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
298 while (!meson_uart_tx_empty(port))
301 if (port->uartclk == 24000000) {
302 val = ((port->uartclk / 3) / baud) - 1;
303 val |= AML_UART_BAUD_XTAL;
305 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
307 val |= AML_UART_BAUD_USE;
308 writel(val, port->membase + AML_UART_REG5);
311 static void meson_uart_set_termios(struct uart_port *port,
312 struct ktermios *termios,
313 struct ktermios *old)
315 unsigned int cflags, iflags, baud;
319 spin_lock_irqsave(&port->lock, flags);
321 cflags = termios->c_cflag;
322 iflags = termios->c_iflag;
324 val = readl(port->membase + AML_UART_CONTROL);
326 val &= ~AML_UART_DATA_LEN_MASK;
327 switch (cflags & CSIZE) {
329 val |= AML_UART_DATA_LEN_8BIT;
332 val |= AML_UART_DATA_LEN_7BIT;
335 val |= AML_UART_DATA_LEN_6BIT;
338 val |= AML_UART_DATA_LEN_5BIT;
343 val |= AML_UART_PARITY_EN;
345 val &= ~AML_UART_PARITY_EN;
348 val |= AML_UART_PARITY_TYPE;
350 val &= ~AML_UART_PARITY_TYPE;
352 val &= ~AML_UART_STOP_BIN_LEN_MASK;
354 val |= AML_UART_STOP_BIN_2SB;
356 val |= AML_UART_STOP_BIN_1SB;
358 if (cflags & CRTSCTS)
359 val &= ~AML_UART_TWO_WIRE_EN;
361 val |= AML_UART_TWO_WIRE_EN;
363 writel(val, port->membase + AML_UART_CONTROL);
365 baud = uart_get_baud_rate(port, termios, old, 9600, 4000000);
366 meson_uart_change_speed(port, baud);
368 port->read_status_mask = AML_UART_TX_FIFO_WERR;
370 port->read_status_mask |= AML_UART_PARITY_ERR |
373 port->ignore_status_mask = 0;
375 port->ignore_status_mask |= AML_UART_PARITY_ERR |
378 uart_update_timeout(port, termios->c_cflag, baud);
379 spin_unlock_irqrestore(&port->lock, flags);
382 static int meson_uart_verify_port(struct uart_port *port,
383 struct serial_struct *ser)
387 if (port->type != PORT_MESON)
389 if (port->irq != ser->irq)
391 if (ser->baud_base < 9600)
396 static void meson_uart_release_port(struct uart_port *port)
398 devm_iounmap(port->dev, port->membase);
399 port->membase = NULL;
400 devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
403 static int meson_uart_request_port(struct uart_port *port)
405 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
406 dev_name(port->dev))) {
407 dev_err(port->dev, "Memory region busy\n");
411 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
419 static void meson_uart_config_port(struct uart_port *port, int flags)
421 if (flags & UART_CONFIG_TYPE) {
422 port->type = PORT_MESON;
423 meson_uart_request_port(port);
427 static const struct uart_ops meson_uart_ops = {
428 .set_mctrl = meson_uart_set_mctrl,
429 .get_mctrl = meson_uart_get_mctrl,
430 .tx_empty = meson_uart_tx_empty,
431 .start_tx = meson_uart_start_tx,
432 .stop_tx = meson_uart_stop_tx,
433 .stop_rx = meson_uart_stop_rx,
434 .startup = meson_uart_startup,
435 .shutdown = meson_uart_shutdown,
436 .set_termios = meson_uart_set_termios,
437 .type = meson_uart_type,
438 .config_port = meson_uart_config_port,
439 .request_port = meson_uart_request_port,
440 .release_port = meson_uart_release_port,
441 .verify_port = meson_uart_verify_port,
444 #ifdef CONFIG_SERIAL_MESON_CONSOLE
445 static void meson_uart_enable_tx_engine(struct uart_port *port)
449 val = readl(port->membase + AML_UART_CONTROL);
450 val |= AML_UART_TX_EN;
451 writel(val, port->membase + AML_UART_CONTROL);
454 static void meson_console_putchar(struct uart_port *port, int ch)
459 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
461 writel(ch, port->membase + AML_UART_WFIFO);
464 static void meson_serial_port_write(struct uart_port *port, const char *s,
471 local_irq_save(flags);
474 } else if (oops_in_progress) {
475 locked = spin_trylock(&port->lock);
477 spin_lock(&port->lock);
481 val = readl(port->membase + AML_UART_CONTROL);
482 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
483 writel(tmp, port->membase + AML_UART_CONTROL);
485 uart_console_write(port, s, count, meson_console_putchar);
486 writel(val, port->membase + AML_UART_CONTROL);
489 spin_unlock(&port->lock);
490 local_irq_restore(flags);
493 static void meson_serial_console_write(struct console *co, const char *s,
496 struct uart_port *port;
498 port = meson_ports[co->index];
502 meson_serial_port_write(port, s, count);
505 static int meson_serial_console_setup(struct console *co, char *options)
507 struct uart_port *port;
513 if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
516 port = meson_ports[co->index];
517 if (!port || !port->membase)
520 meson_uart_enable_tx_engine(port);
523 uart_parse_options(options, &baud, &parity, &bits, &flow);
525 return uart_set_options(port, co, baud, parity, bits, flow);
528 static struct console meson_serial_console = {
529 .name = AML_UART_DEV_NAME,
530 .write = meson_serial_console_write,
531 .device = uart_console_device,
532 .setup = meson_serial_console_setup,
533 .flags = CON_PRINTBUFFER,
535 .data = &meson_uart_driver,
538 static int __init meson_serial_console_init(void)
540 register_console(&meson_serial_console);
543 console_initcall(meson_serial_console_init);
545 static void meson_serial_early_console_write(struct console *co,
549 struct earlycon_device *dev = co->data;
551 meson_serial_port_write(&dev->port, s, count);
555 meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
557 if (!device->port.membase)
560 meson_uart_enable_tx_engine(&device->port);
561 device->con->write = meson_serial_early_console_write;
564 /* Legacy bindings, should be removed when no more used */
565 OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart",
566 meson_serial_early_console_setup);
567 /* Stable bindings */
568 OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart",
569 meson_serial_early_console_setup);
571 #define MESON_SERIAL_CONSOLE (&meson_serial_console)
573 #define MESON_SERIAL_CONSOLE NULL
576 static struct uart_driver meson_uart_driver = {
577 .owner = THIS_MODULE,
578 .driver_name = "meson_uart",
579 .dev_name = AML_UART_DEV_NAME,
580 .nr = AML_UART_PORT_NUM,
581 .cons = MESON_SERIAL_CONSOLE,
584 static inline struct clk *meson_uart_probe_clock(struct device *dev,
587 struct clk *clk = NULL;
590 clk = devm_clk_get(dev, id);
594 ret = clk_prepare_enable(clk);
596 dev_err(dev, "couldn't enable clk\n");
600 devm_add_action_or_reset(dev,
601 (void(*)(void *))clk_disable_unprepare,
608 * This function gets clocks in the legacy non-stable DT bindings.
609 * This code will be remove once all the platforms switch to the
612 static int meson_uart_probe_clocks_legacy(struct platform_device *pdev,
613 struct uart_port *port)
615 struct clk *clk = NULL;
617 clk = meson_uart_probe_clock(&pdev->dev, NULL);
621 port->uartclk = clk_get_rate(clk);
626 static int meson_uart_probe_clocks(struct platform_device *pdev,
627 struct uart_port *port)
629 struct clk *clk_xtal = NULL;
630 struct clk *clk_pclk = NULL;
631 struct clk *clk_baud = NULL;
633 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk");
634 if (IS_ERR(clk_pclk))
635 return PTR_ERR(clk_pclk);
637 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal");
638 if (IS_ERR(clk_xtal))
639 return PTR_ERR(clk_xtal);
641 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud");
642 if (IS_ERR(clk_baud))
643 return PTR_ERR(clk_baud);
645 port->uartclk = clk_get_rate(clk_baud);
650 static int meson_uart_probe(struct platform_device *pdev)
652 struct resource *res_mem, *res_irq;
653 struct uart_port *port;
656 if (pdev->dev.of_node)
657 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
659 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
662 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
670 if (meson_ports[pdev->id]) {
671 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
675 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
679 /* Use legacy way until all platforms switch to new bindings */
680 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
681 ret = meson_uart_probe_clocks_legacy(pdev, port);
683 ret = meson_uart_probe_clocks(pdev, port);
688 port->iotype = UPIO_MEM;
689 port->mapbase = res_mem->start;
690 port->mapsize = resource_size(res_mem);
691 port->irq = res_irq->start;
692 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
693 port->dev = &pdev->dev;
694 port->line = pdev->id;
695 port->type = PORT_MESON;
697 port->ops = &meson_uart_ops;
700 meson_ports[pdev->id] = port;
701 platform_set_drvdata(pdev, port);
703 /* reset port before registering (and possibly registering console) */
704 if (meson_uart_request_port(port) >= 0) {
705 meson_uart_reset(port);
706 meson_uart_release_port(port);
709 ret = uart_add_one_port(&meson_uart_driver, port);
711 meson_ports[pdev->id] = NULL;
716 static int meson_uart_remove(struct platform_device *pdev)
718 struct uart_port *port;
720 port = platform_get_drvdata(pdev);
721 uart_remove_one_port(&meson_uart_driver, port);
722 meson_ports[pdev->id] = NULL;
727 static const struct of_device_id meson_uart_dt_match[] = {
728 /* Legacy bindings, should be removed when no more used */
729 { .compatible = "amlogic,meson-uart" },
730 /* Stable bindings */
731 { .compatible = "amlogic,meson6-uart" },
732 { .compatible = "amlogic,meson8-uart" },
733 { .compatible = "amlogic,meson8b-uart" },
734 { .compatible = "amlogic,meson-gx-uart" },
737 MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
739 static struct platform_driver meson_uart_platform_driver = {
740 .probe = meson_uart_probe,
741 .remove = meson_uart_remove,
743 .name = "meson_uart",
744 .of_match_table = meson_uart_dt_match,
748 static int __init meson_uart_init(void)
752 ret = uart_register_driver(&meson_uart_driver);
756 ret = platform_driver_register(&meson_uart_platform_driver);
758 uart_unregister_driver(&meson_uart_driver);
763 static void __exit meson_uart_exit(void)
765 platform_driver_unregister(&meson_uart_platform_driver);
766 uart_unregister_driver(&meson_uart_driver);
769 module_init(meson_uart_init);
770 module_exit(meson_uart_exit);
772 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
773 MODULE_DESCRIPTION("Amlogic Meson serial port driver");
774 MODULE_LICENSE("GPL v2");