drivers/tty/serial/imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Motorola/Freescale IMX serial ports
   4  *
   5  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6  *
   7  * Author: Sascha Hauer <sascha@saschahauer.de>
   8  * Copyright (C) 2004 Pengutronix
   9  */
  10
  11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/module.h>
  16 #include <linux/ioport.h>
  17 #include <linux/init.h>
  18 #include <linux/console.h>
  19 #include <linux/sysrq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/serial.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/rational.h>
  28 #include <linux/slab.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/io.h>
  32 #include <linux/dma-mapping.h>
  33
  34 #include <asm/irq.h>
  35 #include <linux/platform_data/serial-imx.h>
  36 #include <linux/platform_data/dma-imx.h>
  37
  38 #include "serial_mctrl_gpio.h"
  39
  40 /* Register definitions */
  41 #define URXD0 0x0  /* Receiver Register */
  42 #define URTX0 0x40 /* Transmitter Register */
  43 #define UCR1  0x80 /* Control Register 1 */
  44 #define UCR2  0x84 /* Control Register 2 */
  45 #define UCR3  0x88 /* Control Register 3 */
  46 #define UCR4  0x8c /* Control Register 4 */
  47 #define UFCR  0x90 /* FIFO Control Register */
  48 #define USR1  0x94 /* Status Register 1 */
  49 #define USR2  0x98 /* Status Register 2 */
  50 #define UESC  0x9c /* Escape Character Register */
  51 #define UTIM  0xa0 /* Escape Timer Register */
  52 #define UBIR  0xa4 /* BRM Incremental Register */
  53 #define UBMR  0xa8 /* BRM Modulator Register */
  54 #define UBRC  0xac /* Baud Rate Count Register */
  55 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  56 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  57 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  58
  59 /* UART Control Register Bit Fields.*/
  60 #define URXD_DUMMY_READ (1<<16)
  61 #define URXD_CHARRDY    (1<<15)
  62 #define URXD_ERR        (1<<14)
  63 #define URXD_OVRRUN     (1<<13)
  64 #define URXD_FRMERR     (1<<12)
  65 #define URXD_BRK        (1<<11)
  66 #define URXD_PRERR      (1<<10)
  67 #define URXD_RX_DATA    (0xFF<<0)
  68 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  69 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  70 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  71 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  72 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  73 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  74 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  75 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  76 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  77 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  78 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  79 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  80 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  81 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  82 #define UCR1_DOZE       (1<<1)  /* Doze */
  83 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  84 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  85 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  86 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  87 #define UCR2_CTS        (1<<12) /* Clear to send */
  88 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  89 #define UCR2_PREN       (1<<8)  /* Parity enable */
  90 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
  91 #define UCR2_STPB       (1<<6)  /* Stop */
  92 #define UCR2_WS         (1<<5)  /* Word size */
  93 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  94 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
  95 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  96 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
  97 #define UCR2_SRST       (1<<0)  /* SW reset */
  98 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
  99 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 100 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 101 #define UCR3_DSR        (1<<10) /* Data set ready */
 102 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 103 #define UCR3_RI         (1<<8)  /* Ring indicator */
 104 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 105 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 106 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 107 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 108 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 109 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 110 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 111 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 112 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 113 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 114 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 115 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 116 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 117 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 118 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 119 #define UCR4_IRSC       (1<<5)  /* IR special case */
 120 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 121 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 122 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 123 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 124 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 125 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 126 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 127 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 128 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 129 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 130 #define USR1_RTSS       (1<<14) /* RTS pin status */
 131 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 132 #define USR1_RTSD       (1<<12) /* RTS delta */
 133 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 134 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 135 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 136 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 137 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 138 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 139 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 140 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 141 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 142 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 143 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 144 #define USR2_IDLE        (1<<12) /* Idle condition */
 145 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 146 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 147 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 148 #define USR2_WAKE        (1<<7)  /* Wake */
 149 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 150 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 151 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 152 #define USR2_BRCD        (1<<2)  /* Break condition */
 153 #define USR2_ORE        (1<<1)   /* Overrun error */
 154 #define USR2_RDR        (1<<0)   /* Recv data ready */
 155 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 156 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 157 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 158 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 159 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 160 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 161 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 162
 163 /* We've been assigned a range on the "Low-density serial ports" major */
 164 #define SERIAL_IMX_MAJOR        207
 165 #define MINOR_START             16
 166 #define DEV_NAME                "ttymxc"
 167
 168 /*
 169  * This determines how often we check the modem status signals
 170  * for any change.  They generally aren't connected to an IRQ
 171  * so we have to poll them.  We also check immediately before
 172  * filling the TX fifo incase CTS has been dropped.
 173  */
 174 #define MCTRL_TIMEOUT   (250*HZ/1000)
 175
 176 #define DRIVER_NAME "IMX-uart"
 177
 178 #define UART_NR 8
 179
 180 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 181 enum imx_uart_type {
 182         IMX1_UART,
 183         IMX21_UART,
 184         IMX53_UART,
 185         IMX6Q_UART,
 186 };
 187
 188 /* device type dependent stuff */
 189 struct imx_uart_data {
 190         unsigned uts_reg;
 191         enum imx_uart_type devtype;
 192 };
 193
 194 struct imx_port {
 195         struct uart_port        port;
 196         struct timer_list       timer;
 197         unsigned int            old_status;
 198         unsigned int            have_rtscts:1;
 199         unsigned int            have_rtsgpio:1;
 200         unsigned int            dte_mode:1;
 201         struct clk              *clk_ipg;
 202         struct clk              *clk_per;
 203         const struct imx_uart_data *devdata;
 204
 205         struct mctrl_gpios *gpios;
 206
 207         /* DMA fields */
 208         unsigned int            dma_is_inited:1;
 209         unsigned int            dma_is_enabled:1;
 210         unsigned int            dma_is_rxing:1;
 211         unsigned int            dma_is_txing:1;
 212         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 213         struct scatterlist      rx_sgl, tx_sgl[2];
 214         void                    *rx_buf;
 215         struct circ_buf         rx_ring;
 216         unsigned int            rx_periods;
 217         dma_cookie_t            rx_cookie;
 218         unsigned int            tx_bytes;
 219         unsigned int            dma_tx_nents;
 220         unsigned int            saved_reg[10];
 221         bool                    context_saved;
 222 };
 223
 224 struct imx_port_ucrs {
 225         unsigned int    ucr1;
 226         unsigned int    ucr2;
 227         unsigned int    ucr3;
 228 };
 229
 230 static struct imx_uart_data imx_uart_devdata[] = {
 231         [IMX1_UART] = {
 232                 .uts_reg = IMX1_UTS,
 233                 .devtype = IMX1_UART,
 234         },
 235         [IMX21_UART] = {
 236                 .uts_reg = IMX21_UTS,
 237                 .devtype = IMX21_UART,
 238         },
 239         [IMX53_UART] = {
 240                 .uts_reg = IMX21_UTS,
 241                 .devtype = IMX53_UART,
 242         },
 243         [IMX6Q_UART] = {
 244                 .uts_reg = IMX21_UTS,
 245                 .devtype = IMX6Q_UART,
 246         },
 247 };
 248
 249 static const struct platform_device_id imx_uart_devtype[] = {
 250         {
 251                 .name = "imx1-uart",
 252                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 253         }, {
 254                 .name = "imx21-uart",
 255                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 256         }, {
 257                 .name = "imx53-uart",
 258                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 259         }, {
 260                 .name = "imx6q-uart",
 261                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 262         }, {
 263                 /* sentinel */
 264         }
 265 };
 266 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 267
 268 static const struct of_device_id imx_uart_dt_ids[] = {
 269         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 270         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 271         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 272         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 273         { /* sentinel */ }
 274 };
 275 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 276
 277 static inline unsigned uts_reg(struct imx_port *sport)
 278 {
 279         return sport->devdata->uts_reg;
 280 }
 281
 282 static inline int is_imx1_uart(struct imx_port *sport)
 283 {
 284         return sport->devdata->devtype == IMX1_UART;
 285 }
 286
 287 static inline int is_imx21_uart(struct imx_port *sport)
 288 {
 289         return sport->devdata->devtype == IMX21_UART;
 290 }
 291
 292 static inline int is_imx53_uart(struct imx_port *sport)
 293 {
 294         return sport->devdata->devtype == IMX53_UART;
 295 }
 296
 297 static inline int is_imx6q_uart(struct imx_port *sport)
 298 {
 299         return sport->devdata->devtype == IMX6Q_UART;
 300 }
 301 /*
 302  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 303  */
 304 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 305 static void imx_port_ucrs_save(struct uart_port *port,
 306                                struct imx_port_ucrs *ucr)
 307 {
 308         /* save control registers */
 309         ucr->ucr1 = readl(port->membase + UCR1);
 310         ucr->ucr2 = readl(port->membase + UCR2);
 311         ucr->ucr3 = readl(port->membase + UCR3);
 312 }
 313
 314 static void imx_port_ucrs_restore(struct uart_port *port,
 315                                   struct imx_port_ucrs *ucr)
 316 {
 317         /* restore control registers */
 318         writel(ucr->ucr1, port->membase + UCR1);
 319         writel(ucr->ucr2, port->membase + UCR2);
 320         writel(ucr->ucr3, port->membase + UCR3);
 321 }
 322 #endif
 323
 324 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 325 {
 326         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 327
 328         sport->port.mctrl |= TIOCM_RTS;
 329         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 330 }
 331
 332 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 333 {
 334         *ucr2 &= ~UCR2_CTSC;
 335         *ucr2 |= UCR2_CTS;
 336
 337         sport->port.mctrl &= ~TIOCM_RTS;
 338         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 339 }
 340
 341 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 342 {
 343         *ucr2 |= UCR2_CTSC;
 344 }
 345
 346 /*
 347  * interrupts disabled on entry
 348  */
 349 static void imx_stop_tx(struct uart_port *port)
 350 {
 351         struct imx_port *sport = (struct imx_port *)port;
 352         unsigned long temp;
 353
 354         /*
 355          * We are maybe in the SMP context, so if the DMA TX thread is running
 356          * on other cpu, we have to wait for it to finish.
 357          */
 358         if (sport->dma_is_enabled && sport->dma_is_txing)
 359                 return;
 360
 361         temp = readl(port->membase + UCR1);
 362         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 363
 364         /* in rs485 mode disable transmitter if shifter is empty */
 365         if (port->rs485.flags & SER_RS485_ENABLED &&
 366             readl(port->membase + USR2) & USR2_TXDC) {
 367                 temp = readl(port->membase + UCR2);
 368                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 369                         imx_port_rts_active(sport, &temp);
 370                 else
 371                         imx_port_rts_inactive(sport, &temp);
 372                 temp |= UCR2_RXEN;
 373                 writel(temp, port->membase + UCR2);
 374
 375                 temp = readl(port->membase + UCR4);
 376                 temp &= ~UCR4_TCEN;
 377                 writel(temp, port->membase + UCR4);
 378         }
 379 }
 380
 381 /*
 382  * interrupts disabled on entry
 383  */
 384 static void imx_stop_rx(struct uart_port *port)
 385 {
 386         struct imx_port *sport = (struct imx_port *)port;
 387         unsigned long temp;
 388
 389         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 390                 if (sport->port.suspended) {
 391                         dmaengine_terminate_all(sport->dma_chan_rx);
 392                         sport->dma_is_rxing = 0;
 393                 } else {
 394                         return;
 395                 }
 396         }
 397
 398         temp = readl(sport->port.membase + UCR2);
 399         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 400
 401         /* disable the `Receiver Ready Interrrupt` */
 402         temp = readl(sport->port.membase + UCR1);
 403         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 404 }
 405
 406 /*
 407  * Set the modem control timer to fire immediately.
 408  */
 409 static void imx_enable_ms(struct uart_port *port)
 410 {
 411         struct imx_port *sport = (struct imx_port *)port;
 412
 413         mod_timer(&sport->timer, jiffies);
 414
 415         mctrl_gpio_enable_ms(sport->gpios);
 416 }
 417
 418 static void imx_dma_tx(struct imx_port *sport);
 419 static inline void imx_transmit_buffer(struct imx_port *sport)
 420 {
 421         struct circ_buf *xmit = &sport->port.state->xmit;
 422         unsigned long temp;
 423
 424         if (sport->port.x_char) {
 425                 /* Send next char */
 426                 writel(sport->port.x_char, sport->port.membase + URTX0);
 427                 sport->port.icount.tx++;
 428                 sport->port.x_char = 0;
 429                 return;
 430         }
 431
 432         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 433                 imx_stop_tx(&sport->port);
 434                 return;
 435         }
 436
 437         if (sport->dma_is_enabled) {
 438                 /*
 439                  * We've just sent a X-char Ensure the TX DMA is enabled
 440                  * and the TX IRQ is disabled.
 441                  **/
 442                 temp = readl(sport->port.membase + UCR1);
 443                 temp &= ~UCR1_TXMPTYEN;
 444                 if (sport->dma_is_txing) {
 445                         temp |= UCR1_TDMAEN;
 446                         writel(temp, sport->port.membase + UCR1);
 447                 } else {
 448                         writel(temp, sport->port.membase + UCR1);
 449                         imx_dma_tx(sport);
 450                 }
 451         }
 452
 453         if (sport->dma_is_txing)
 454                 return;
 455
 456         while (!uart_circ_empty(xmit) &&
 457                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 458                 /* send xmit->buf[xmit->tail]
 459                  * out the port here */
 460                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 461                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 462                 sport->port.icount.tx++;
 463         }
 464
 465         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 466                 uart_write_wakeup(&sport->port);
 467
 468         if (uart_circ_empty(xmit))
 469                 imx_stop_tx(&sport->port);
 470 }
 471
 472 static void dma_tx_callback(void *data)
 473 {
 474         struct imx_port *sport = data;
 475         struct scatterlist *sgl = &sport->tx_sgl[0];
 476         struct circ_buf *xmit = &sport->port.state->xmit;
 477         unsigned long flags;
 478         unsigned long temp;
 479
 480         spin_lock_irqsave(&sport->port.lock, flags);
 481
 482         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 483
 484         temp = readl(sport->port.membase + UCR1);
 485         temp &= ~UCR1_TDMAEN;
 486         writel(temp, sport->port.membase + UCR1);
 487
 488         /* update the stat */
 489         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 490         sport->port.icount.tx += sport->tx_bytes;
 491
 492         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 493
 494         sport->dma_is_txing = 0;
 495
 496         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 497                 uart_write_wakeup(&sport->port);
 498
 499         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 500                 imx_dma_tx(sport);
 501
 502         spin_unlock_irqrestore(&sport->port.lock, flags);
 503 }
 504
 505 static void imx_dma_tx(struct imx_port *sport)
 506 {
 507         struct circ_buf *xmit = &sport->port.state->xmit;
 508         struct scatterlist *sgl = sport->tx_sgl;
 509         struct dma_async_tx_descriptor *desc;
 510         struct dma_chan *chan = sport->dma_chan_tx;
 511         struct device *dev = sport->port.dev;
 512         unsigned long temp;
 513         int ret;
 514
 515         if (sport->dma_is_txing)
 516                 return;
 517
 518         sport->tx_bytes = uart_circ_chars_pending(xmit);
 519
 520         if (xmit->tail < xmit->head) {
 521                 sport->dma_tx_nents = 1;
 522                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 523         } else {
 524                 sport->dma_tx_nents = 2;
 525                 sg_init_table(sgl, 2);
 526                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 527                                 UART_XMIT_SIZE - xmit->tail);
 528                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 529         }
 530
 531         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 532         if (ret == 0) {
 533                 dev_err(dev, "DMA mapping error for TX.\n");
 534                 return;
 535         }
 536         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 537                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 538         if (!desc) {
 539                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 540                              DMA_TO_DEVICE);
 541                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 542                 return;
 543         }
 544         desc->callback = dma_tx_callback;
 545         desc->callback_param = sport;
 546
 547         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 548                         uart_circ_chars_pending(xmit));
 549
 550         temp = readl(sport->port.membase + UCR1);
 551         temp |= UCR1_TDMAEN;
 552         writel(temp, sport->port.membase + UCR1);
 553
 554         /* fire it */
 555         sport->dma_is_txing = 1;
 556         dmaengine_submit(desc);
 557         dma_async_issue_pending(chan);
 558         return;
 559 }
 560
 561 /*
 562  * interrupts disabled on entry
 563  */
 564 static void imx_start_tx(struct uart_port *port)
 565 {
 566         struct imx_port *sport = (struct imx_port *)port;
 567         unsigned long temp;
 568
 569         if (port->rs485.flags & SER_RS485_ENABLED) {
 570                 temp = readl(port->membase + UCR2);
 571                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 572                         imx_port_rts_active(sport, &temp);
 573                 else
 574                         imx_port_rts_inactive(sport, &temp);
 575                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 576                         temp &= ~UCR2_RXEN;
 577                 writel(temp, port->membase + UCR2);
 578
 579                 /* enable transmitter and shifter empty irq */
 580                 temp = readl(port->membase + UCR4);
 581                 temp |= UCR4_TCEN;
 582                 writel(temp, port->membase + UCR4);
 583         }
 584
 585         if (!sport->dma_is_enabled) {
 586                 temp = readl(sport->port.membase + UCR1);
 587                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 588         }
 589
 590         if (sport->dma_is_enabled) {
 591                 if (sport->port.x_char) {
 592                         /* We have X-char to send, so enable TX IRQ and
 593                          * disable TX DMA to let TX interrupt to send X-char */
 594                         temp = readl(sport->port.membase + UCR1);
 595                         temp &= ~UCR1_TDMAEN;
 596                         temp |= UCR1_TXMPTYEN;
 597                         writel(temp, sport->port.membase + UCR1);
 598                         return;
 599                 }
 600
 601                 if (!uart_circ_empty(&port->state->xmit) &&
 602                     !uart_tx_stopped(port))
 603                         imx_dma_tx(sport);
 604                 return;
 605         }
 606 }
 607
 608 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 609 {
 610         struct imx_port *sport = dev_id;
 611         unsigned int val;
 612         unsigned long flags;
 613
 614         spin_lock_irqsave(&sport->port.lock, flags);
 615
 616         writel(USR1_RTSD, sport->port.membase + USR1);
 617         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 618         uart_handle_cts_change(&sport->port, !!val);
 619         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 620
 621         spin_unlock_irqrestore(&sport->port.lock, flags);
 622         return IRQ_HANDLED;
 623 }
 624
 625 static irqreturn_t imx_txint(int irq, void *dev_id)
 626 {
 627         struct imx_port *sport = dev_id;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&sport->port.lock, flags);
 631         imx_transmit_buffer(sport);
 632         spin_unlock_irqrestore(&sport->port.lock, flags);
 633         return IRQ_HANDLED;
 634 }
 635
 636 static irqreturn_t imx_rxint(int irq, void *dev_id)
 637 {
 638         struct imx_port *sport = dev_id;
 639         unsigned int rx, flg, ignored = 0;
 640         struct tty_port *port = &sport->port.state->port;
 641         unsigned long flags, temp;
 642
 643         spin_lock_irqsave(&sport->port.lock, flags);
 644
 645         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 646                 flg = TTY_NORMAL;
 647                 sport->port.icount.rx++;
 648
 649                 rx = readl(sport->port.membase + URXD0);
 650
 651                 temp = readl(sport->port.membase + USR2);
 652                 if (temp & USR2_BRCD) {
 653                         writel(USR2_BRCD, sport->port.membase + USR2);
 654                         if (uart_handle_break(&sport->port))
 655                                 continue;
 656                 }
 657
 658                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 659                         continue;
 660
 661                 if (unlikely(rx & URXD_ERR)) {
 662                         if (rx & URXD_BRK)
 663                                 sport->port.icount.brk++;
 664                         else if (rx & URXD_PRERR)
 665                                 sport->port.icount.parity++;
 666                         else if (rx & URXD_FRMERR)
 667                                 sport->port.icount.frame++;
 668                         if (rx & URXD_OVRRUN)
 669                                 sport->port.icount.overrun++;
 670
 671                         if (rx & sport->port.ignore_status_mask) {
 672                                 if (++ignored > 100)
 673                                         goto out;
 674                                 continue;
 675                         }
 676
 677                         rx &= (sport->port.read_status_mask | 0xFF);
 678
 679                         if (rx & URXD_BRK)
 680                                 flg = TTY_BREAK;
 681                         else if (rx & URXD_PRERR)
 682                                 flg = TTY_PARITY;
 683                         else if (rx & URXD_FRMERR)
 684                                 flg = TTY_FRAME;
 685                         if (rx & URXD_OVRRUN)
 686                                 flg = TTY_OVERRUN;
 687
 688 #ifdef SUPPORT_SYSRQ
 689                         sport->port.sysrq = 0;
 690 #endif
 691                 }
 692
 693                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 694                         goto out;
 695
 696                 if (tty_insert_flip_char(port, rx, flg) == 0)
 697                         sport->port.icount.buf_overrun++;
 698         }
 699
 700 out:
 701         spin_unlock_irqrestore(&sport->port.lock, flags);
 702         tty_flip_buffer_push(port);
 703         return IRQ_HANDLED;
 704 }
 705
 706 static void imx_disable_rx_int(struct imx_port *sport)
 707 {
 708         unsigned long temp;
 709
 710         /* disable the receiver ready and aging timer interrupts */
 711         temp = readl(sport->port.membase + UCR1);
 712         temp &= ~(UCR1_RRDYEN);
 713         writel(temp, sport->port.membase + UCR1);
 714
 715         temp = readl(sport->port.membase + UCR2);
 716         temp &= ~(UCR2_ATEN);
 717         writel(temp, sport->port.membase + UCR2);
 718
 719         /* disable the rx errors interrupts */
 720         temp = readl(sport->port.membase + UCR4);
 721         temp &= ~UCR4_OREN;
 722         writel(temp, sport->port.membase + UCR4);
 723 }
 724
 725 static void clear_rx_errors(struct imx_port *sport);
 726
 727 /*
 728  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 729  */
 730 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 731 {
 732         unsigned int tmp = TIOCM_DSR;
 733         unsigned usr1 = readl(sport->port.membase + USR1);
 734         unsigned usr2 = readl(sport->port.membase + USR2);
 735
 736         if (usr1 & USR1_RTSS)
 737                 tmp |= TIOCM_CTS;
 738
 739         /* in DCE mode DCDIN is always 0 */
 740         if (!(usr2 & USR2_DCDIN))
 741                 tmp |= TIOCM_CAR;
 742
 743         if (sport->dte_mode)
 744                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 745                         tmp |= TIOCM_RI;
 746
 747         return tmp;
 748 }
 749
 750 /*
 751  * Handle any change of modem status signal since we were last called.
 752  */
 753 static void imx_mctrl_check(struct imx_port *sport)
 754 {
 755         unsigned int status, changed;
 756
 757         status = imx_get_hwmctrl(sport);
 758         changed = status ^ sport->old_status;
 759
 760         if (changed == 0)
 761                 return;
 762
 763         sport->old_status = status;
 764
 765         if (changed & TIOCM_RI && status & TIOCM_RI)
 766                 sport->port.icount.rng++;
 767         if (changed & TIOCM_DSR)
 768                 sport->port.icount.dsr++;
 769         if (changed & TIOCM_CAR)
 770                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 771         if (changed & TIOCM_CTS)
 772                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 773
 774         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 775 }
 776
 777 static irqreturn_t imx_int(int irq, void *dev_id)
 778 {
 779         struct imx_port *sport = dev_id;
 780         unsigned int sts;
 781         unsigned int sts2;
 782         irqreturn_t ret = IRQ_NONE;
 783
 784         sts = readl(sport->port.membase + USR1);
 785         sts2 = readl(sport->port.membase + USR2);
 786
 787         if (!sport->dma_is_enabled && (sts & (USR1_RRDY | USR1_AGTIM))) {
 788                 imx_rxint(irq, dev_id);
 789                 ret = IRQ_HANDLED;
 790         }
 791
 792         if ((sts & USR1_TRDY &&
 793              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 794             (sts2 & USR2_TXDC &&
 795              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
 796                 imx_txint(irq, dev_id);
 797                 ret = IRQ_HANDLED;
 798         }
 799
 800         if (sts & USR1_DTRD) {
 801                 unsigned long flags;
 802
 803                 if (sts & USR1_DTRD)
 804                         writel(USR1_DTRD, sport->port.membase + USR1);
 805
 806                 spin_lock_irqsave(&sport->port.lock, flags);
 807                 imx_mctrl_check(sport);
 808                 spin_unlock_irqrestore(&sport->port.lock, flags);
 809
 810                 ret = IRQ_HANDLED;
 811         }
 812
 813         if (sts & USR1_RTSD) {
 814                 imx_rtsint(irq, dev_id);
 815                 ret = IRQ_HANDLED;
 816         }
 817
 818         if (sts & USR1_AWAKE) {
 819                 writel(USR1_AWAKE, sport->port.membase + USR1);
 820                 ret = IRQ_HANDLED;
 821         }
 822
 823         if (sts2 & USR2_ORE) {
 824                 sport->port.icount.overrun++;
 825                 writel(USR2_ORE, sport->port.membase + USR2);
 826                 ret = IRQ_HANDLED;
 827         }
 828
 829         return ret;
 830 }
 831
 832 /*
 833  * Return TIOCSER_TEMT when transmitter is not busy.
 834  */
 835 static unsigned int imx_tx_empty(struct uart_port *port)
 836 {
 837         struct imx_port *sport = (struct imx_port *)port;
 838         unsigned int ret;
 839
 840         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 841
 842         /* If the TX DMA is working, return 0. */
 843         if (sport->dma_is_enabled && sport->dma_is_txing)
 844                 ret = 0;
 845
 846         return ret;
 847 }
 848
 849 static unsigned int imx_get_mctrl(struct uart_port *port)
 850 {
 851         struct imx_port *sport = (struct imx_port *)port;
 852         unsigned int ret = imx_get_hwmctrl(sport);
 853
 854         mctrl_gpio_get(sport->gpios, &ret);
 855
 856         return ret;
 857 }
 858
 859 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 860 {
 861         struct imx_port *sport = (struct imx_port *)port;
 862         unsigned long temp;
 863
 864         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 865                 temp = readl(sport->port.membase + UCR2);
 866                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 867                 if (mctrl & TIOCM_RTS)
 868                         temp |= UCR2_CTS | UCR2_CTSC;
 869                 writel(temp, sport->port.membase + UCR2);
 870         }
 871
 872         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 873         if (!(mctrl & TIOCM_DTR))
 874                 temp |= UCR3_DSR;
 875         writel(temp, sport->port.membase + UCR3);
 876
 877         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 878         if (mctrl & TIOCM_LOOP)
 879                 temp |= UTS_LOOP;
 880         writel(temp, sport->port.membase + uts_reg(sport));
 881
 882         mctrl_gpio_set(sport->gpios, mctrl);
 883 }
 884
 885 /*
 886  * Interrupts always disabled.
 887  */
 888 static void imx_break_ctl(struct uart_port *port, int break_state)
 889 {
 890         struct imx_port *sport = (struct imx_port *)port;
 891         unsigned long flags, temp;
 892
 893         spin_lock_irqsave(&sport->port.lock, flags);
 894
 895         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 896
 897         if (break_state != 0)
 898                 temp |= UCR1_SNDBRK;
 899
 900         writel(temp, sport->port.membase + UCR1);
 901
 902         spin_unlock_irqrestore(&sport->port.lock, flags);
 903 }
 904
 905 /*
 906  * This is our per-port timeout handler, for checking the
 907  * modem status signals.
 908  */
 909 static void imx_timeout(struct timer_list *t)
 910 {
 911         struct imx_port *sport = from_timer(sport, t, timer);
 912         unsigned long flags;
 913
 914         if (sport->port.state) {
 915                 spin_lock_irqsave(&sport->port.lock, flags);
 916                 imx_mctrl_check(sport);
 917                 spin_unlock_irqrestore(&sport->port.lock, flags);
 918
 919                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 920         }
 921 }
 922
 923 #define RX_BUF_SIZE     (PAGE_SIZE)
 924
 925 /*
 926  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 927  *   [1] the RX DMA buffer is full.
 928  *   [2] the aging timer expires
 929  *
 930  * Condition [2] is triggered when a character has been sitting in the FIFO
 931  * for at least 8 byte durations.
 932  */
 933 static void dma_rx_callback(void *data)
 934 {
 935         struct imx_port *sport = data;
 936         struct dma_chan *chan = sport->dma_chan_rx;
 937         struct scatterlist *sgl = &sport->rx_sgl;
 938         struct tty_port *port = &sport->port.state->port;
 939         struct dma_tx_state state;
 940         struct circ_buf *rx_ring = &sport->rx_ring;
 941         enum dma_status status;
 942         unsigned int w_bytes = 0;
 943         unsigned int r_bytes;
 944         unsigned int bd_size;
 945
 946         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 947
 948         if (status == DMA_ERROR) {
 949                 dev_err(sport->port.dev, "DMA transaction error.\n");
 950                 clear_rx_errors(sport);
 951                 return;
 952         }
 953
 954         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 955
 956                 /*
 957                  * The state-residue variable represents the empty space
 958                  * relative to the entire buffer. Taking this in consideration
 959                  * the head is always calculated base on the buffer total
 960                  * length - DMA transaction residue. The UART script from the
 961                  * SDMA firmware will jump to the next buffer descriptor,
 962                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
 963                  * Taking this in consideration the tail is always at the
 964                  * beginning of the buffer descriptor that contains the head.
 965                  */
 966
 967                 /* Calculate the head */
 968                 rx_ring->head = sg_dma_len(sgl) - state.residue;
 969
 970                 /* Calculate the tail. */
 971                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
 972                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
 973
 974                 if (rx_ring->head <= sg_dma_len(sgl) &&
 975                     rx_ring->head > rx_ring->tail) {
 976
 977                         /* Move data from tail to head */
 978                         r_bytes = rx_ring->head - rx_ring->tail;
 979
 980                         /* CPU claims ownership of RX DMA buffer */
 981                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
 982                                 DMA_FROM_DEVICE);
 983
 984                         w_bytes = tty_insert_flip_string(port,
 985                                 sport->rx_buf + rx_ring->tail, r_bytes);
 986
 987                         /* UART retrieves ownership of RX DMA buffer */
 988                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
 989                                 DMA_FROM_DEVICE);
 990
 991                         if (w_bytes != r_bytes)
 992                                 sport->port.icount.buf_overrun++;
 993
 994                         sport->port.icount.rx += w_bytes;
 995                 } else  {
 996                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
 997                         WARN_ON(rx_ring->head <= rx_ring->tail);
 998                 }
 999         }
1000
1001         if (w_bytes) {
1002                 tty_flip_buffer_push(port);
1003                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1004         }
1005 }
1006
1007 /* RX DMA buffer periods */
1008 #define RX_DMA_PERIODS 4
1009
1010 static int start_rx_dma(struct imx_port *sport)
1011 {
1012         struct scatterlist *sgl = &sport->rx_sgl;
1013         struct dma_chan *chan = sport->dma_chan_rx;
1014         struct device *dev = sport->port.dev;
1015         struct dma_async_tx_descriptor *desc;
1016         int ret;
1017
1018         sport->rx_ring.head = 0;
1019         sport->rx_ring.tail = 0;
1020         sport->rx_periods = RX_DMA_PERIODS;
1021
1022         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1023         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1024         if (ret == 0) {
1025                 dev_err(dev, "DMA mapping error for RX.\n");
1026                 return -EINVAL;
1027         }
1028
1029         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1030                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1031                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1032
1033         if (!desc) {
1034                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1035                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1036                 return -EINVAL;
1037         }
1038         desc->callback = dma_rx_callback;
1039         desc->callback_param = sport;
1040
1041         dev_dbg(dev, "RX: prepare for the DMA.\n");
1042         sport->dma_is_rxing = 1;
1043         sport->rx_cookie = dmaengine_submit(desc);
1044         dma_async_issue_pending(chan);
1045         return 0;
1046 }
1047
1048 static void clear_rx_errors(struct imx_port *sport)
1049 {
1050         unsigned int status_usr1, status_usr2;
1051
1052         status_usr1 = readl(sport->port.membase + USR1);
1053         status_usr2 = readl(sport->port.membase + USR2);
1054
1055         if (status_usr2 & USR2_BRCD) {
1056                 sport->port.icount.brk++;
1057                 writel(USR2_BRCD, sport->port.membase + USR2);
1058         } else if (status_usr1 & USR1_FRAMERR) {
1059                 sport->port.icount.frame++;
1060                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1061         } else if (status_usr1 & USR1_PARITYERR) {
1062                 sport->port.icount.parity++;
1063                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1064         }
1065
1066         if (status_usr2 & USR2_ORE) {
1067                 sport->port.icount.overrun++;
1068                 writel(USR2_ORE, sport->port.membase + USR2);
1069         }
1070
1071 }
1072
1073 #define TXTL_DEFAULT 2 /* reset default */
1074 #define RXTL_DEFAULT 1 /* reset default */
1075 #define TXTL_DMA 8 /* DMA burst setting */
1076 #define RXTL_DMA 9 /* DMA burst setting */
1077
1078 static void imx_setup_ufcr(struct imx_port *sport,
1079                           unsigned char txwl, unsigned char rxwl)
1080 {
1081         unsigned int val;
1082
1083         /* set receiver / transmitter trigger level */
1084         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1085         val |= txwl << UFCR_TXTL_SHF | rxwl;
1086         writel(val, sport->port.membase + UFCR);
1087 }
1088
1089 static void imx_uart_dma_exit(struct imx_port *sport)
1090 {
1091         if (sport->dma_chan_rx) {
1092                 dmaengine_terminate_sync(sport->dma_chan_rx);
1093                 dma_release_channel(sport->dma_chan_rx);
1094                 sport->dma_chan_rx = NULL;
1095                 sport->rx_cookie = -EINVAL;
1096                 kfree(sport->rx_buf);
1097                 sport->rx_buf = NULL;
1098         }
1099
1100         if (sport->dma_chan_tx) {
1101                 dmaengine_terminate_sync(sport->dma_chan_tx);
1102                 dma_release_channel(sport->dma_chan_tx);
1103                 sport->dma_chan_tx = NULL;
1104         }
1105
1106         sport->dma_is_inited = 0;
1107 }
1108
1109 static int imx_uart_dma_init(struct imx_port *sport)
1110 {
1111         struct dma_slave_config slave_config = {};
1112         struct device *dev = sport->port.dev;
1113         int ret;
1114
1115         /* Prepare for RX : */
1116         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1117         if (!sport->dma_chan_rx) {
1118                 dev_dbg(dev, "cannot get the DMA channel.\n");
1119                 ret = -EINVAL;
1120                 goto err;
1121         }
1122
1123         slave_config.direction = DMA_DEV_TO_MEM;
1124         slave_config.src_addr = sport->port.mapbase + URXD0;
1125         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1126         /* one byte less than the watermark level to enable the aging timer */
1127         slave_config.src_maxburst = RXTL_DMA - 1;
1128         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1129         if (ret) {
1130                 dev_err(dev, "error in RX dma configuration.\n");
1131                 goto err;
1132         }
1133
1134         sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1135         if (!sport->rx_buf) {
1136                 ret = -ENOMEM;
1137                 goto err;
1138         }
1139         sport->rx_ring.buf = sport->rx_buf;
1140
1141         /* Prepare for TX : */
1142         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1143         if (!sport->dma_chan_tx) {
1144                 dev_err(dev, "cannot get the TX DMA channel!\n");
1145                 ret = -EINVAL;
1146                 goto err;
1147         }
1148
1149         slave_config.direction = DMA_MEM_TO_DEV;
1150         slave_config.dst_addr = sport->port.mapbase + URTX0;
1151         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1152         slave_config.dst_maxburst = TXTL_DMA;
1153         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1154         if (ret) {
1155                 dev_err(dev, "error in TX dma configuration.");
1156                 goto err;
1157         }
1158
1159         sport->dma_is_inited = 1;
1160
1161         return 0;
1162 err:
1163         imx_uart_dma_exit(sport);
1164         return ret;
1165 }
1166
1167 static void imx_enable_dma(struct imx_port *sport)
1168 {
1169         unsigned long temp;
1170
1171         /* set UCR1 */
1172         temp = readl(sport->port.membase + UCR1);
1173         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1174         writel(temp, sport->port.membase + UCR1);
1175
1176         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1177
1178         sport->dma_is_enabled = 1;
1179 }
1180
1181 static void imx_disable_dma(struct imx_port *sport)
1182 {
1183         unsigned long temp;
1184
1185         /* clear UCR1 */
1186         temp = readl(sport->port.membase + UCR1);
1187         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1188         writel(temp, sport->port.membase + UCR1);
1189
1190         /* clear UCR2 */
1191         temp = readl(sport->port.membase + UCR2);
1192         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1193         writel(temp, sport->port.membase + UCR2);
1194
1195         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1196
1197         sport->dma_is_enabled = 0;
1198 }
1199
1200 /* half the RX buffer size */
1201 #define CTSTL 16
1202
1203 static int imx_startup(struct uart_port *port)
1204 {
1205         struct imx_port *sport = (struct imx_port *)port;
1206         int retval, i;
1207         unsigned long flags, temp;
1208
1209         retval = clk_prepare_enable(sport->clk_per);
1210         if (retval)
1211                 return retval;
1212         retval = clk_prepare_enable(sport->clk_ipg);
1213         if (retval) {
1214                 clk_disable_unprepare(sport->clk_per);
1215                 return retval;
1216         }
1217
1218         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1219
1220         /* disable the DREN bit (Data Ready interrupt enable) before
1221          * requesting IRQs
1222          */
1223         temp = readl(sport->port.membase + UCR4);
1224
1225         /* set the trigger level for CTS */
1226         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1227         temp |= CTSTL << UCR4_CTSTL_SHF;
1228
1229         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1230
1231         /* Can we enable the DMA support? */
1232         if (!uart_console(port) && !sport->dma_is_inited)
1233                 imx_uart_dma_init(sport);
1234
1235         spin_lock_irqsave(&sport->port.lock, flags);
1236         /* Reset fifo's and state machines */
1237         i = 100;
1238
1239         temp = readl(sport->port.membase + UCR2);
1240         temp &= ~UCR2_SRST;
1241         writel(temp, sport->port.membase + UCR2);
1242
1243         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1244                 udelay(1);
1245
1246         /*
1247          * Finally, clear and enable interrupts
1248          */
1249         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1250         writel(USR2_ORE, sport->port.membase + USR2);
1251
1252         if (sport->dma_is_inited && !sport->dma_is_enabled)
1253                 imx_enable_dma(sport);
1254
1255         temp = readl(sport->port.membase + UCR1);
1256         temp |= UCR1_RRDYEN | UCR1_UARTEN;
1257         if (sport->have_rtscts)
1258                         temp |= UCR1_RTSDEN;
1259
1260         writel(temp, sport->port.membase + UCR1);
1261
1262         temp = readl(sport->port.membase + UCR4);
1263         temp |= UCR4_OREN;
1264         writel(temp, sport->port.membase + UCR4);
1265
1266         temp = readl(sport->port.membase + UCR2);
1267         temp |= (UCR2_RXEN | UCR2_TXEN);
1268         if (!sport->have_rtscts)
1269                 temp |= UCR2_IRTS;
1270         /*
1271          * make sure the edge sensitive RTS-irq is disabled,
1272          * we're using RTSD instead.
1273          */
1274         if (!is_imx1_uart(sport))
1275                 temp &= ~UCR2_RTSEN;
1276         writel(temp, sport->port.membase + UCR2);
1277
1278         if (!is_imx1_uart(sport)) {
1279                 temp = readl(sport->port.membase + UCR3);
1280
1281                 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1282
1283                 if (sport->dte_mode)
1284                         /* disable broken interrupts */
1285                         temp &= ~(UCR3_RI | UCR3_DCD);
1286
1287                 writel(temp, sport->port.membase + UCR3);
1288         }
1289
1290         /*
1291          * Enable modem status interrupts
1292          */
1293         imx_enable_ms(&sport->port);
1294
1295         /*
1296          * Start RX DMA immediately instead of waiting for RX FIFO interrupts.
1297          * In our iMX53 the average delay for the first reception dropped from
1298          * approximately 35000 microseconds to 1000 microseconds.
1299          */
1300         if (sport->dma_is_enabled) {
1301                 imx_disable_rx_int(sport);
1302                 start_rx_dma(sport);
1303         }
1304
1305         spin_unlock_irqrestore(&sport->port.lock, flags);
1306
1307         return 0;
1308 }
1309
1310 static void imx_shutdown(struct uart_port *port)
1311 {
1312         struct imx_port *sport = (struct imx_port *)port;
1313         unsigned long temp;
1314         unsigned long flags;
1315
1316         if (sport->dma_is_enabled) {
1317                 sport->dma_is_rxing = 0;
1318                 sport->dma_is_txing = 0;
1319                 dmaengine_terminate_sync(sport->dma_chan_tx);
1320                 dmaengine_terminate_sync(sport->dma_chan_rx);
1321
1322                 spin_lock_irqsave(&sport->port.lock, flags);
1323                 imx_stop_tx(port);
1324                 imx_stop_rx(port);
1325                 imx_disable_dma(sport);
1326                 spin_unlock_irqrestore(&sport->port.lock, flags);
1327                 imx_uart_dma_exit(sport);
1328         }
1329
1330         mctrl_gpio_disable_ms(sport->gpios);
1331
1332         spin_lock_irqsave(&sport->port.lock, flags);
1333         temp = readl(sport->port.membase + UCR2);
1334         temp &= ~(UCR2_TXEN);
1335         writel(temp, sport->port.membase + UCR2);
1336         spin_unlock_irqrestore(&sport->port.lock, flags);
1337
1338         /*
1339          * Stop our timer.
1340          */
1341         del_timer_sync(&sport->timer);
1342
1343         /*
1344          * Disable all interrupts, port and break condition.
1345          */
1346
1347         spin_lock_irqsave(&sport->port.lock, flags);
1348         temp = readl(sport->port.membase + UCR1);
1349         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1350
1351         writel(temp, sport->port.membase + UCR1);
1352         spin_unlock_irqrestore(&sport->port.lock, flags);
1353
1354         clk_disable_unprepare(sport->clk_per);
1355         clk_disable_unprepare(sport->clk_ipg);
1356 }
1357
1358 static void imx_flush_buffer(struct uart_port *port)
1359 {
1360         struct imx_port *sport = (struct imx_port *)port;
1361         struct scatterlist *sgl = &sport->tx_sgl[0];
1362         unsigned long temp;
1363         int i = 100, ubir, ubmr, uts;
1364
1365         if (!sport->dma_chan_tx)
1366                 return;
1367
1368         sport->tx_bytes = 0;
1369         dmaengine_terminate_all(sport->dma_chan_tx);
1370         if (sport->dma_is_txing) {
1371                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1372                              DMA_TO_DEVICE);
1373                 temp = readl(sport->port.membase + UCR1);
1374                 temp &= ~UCR1_TDMAEN;
1375                 writel(temp, sport->port.membase + UCR1);
1376                 sport->dma_is_txing = 0;
1377         }
1378
1379         /*
1380          * According to the Reference Manual description of the UART SRST bit:
1381          *
1382          * "Reset the transmit and receive state machines,
1383          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1384          * and UTS[6-3]".
1385          *
1386          * We don't need to restore the old values from USR1, USR2, URXD and
1387          * UTXD. UBRC is read only, so only save/restore the other three
1388          * registers.
1389          */
1390         ubir = readl(sport->port.membase + UBIR);
1391         ubmr = readl(sport->port.membase + UBMR);
1392         uts = readl(sport->port.membase + IMX21_UTS);
1393
1394         temp = readl(sport->port.membase + UCR2);
1395         temp &= ~UCR2_SRST;
1396         writel(temp, sport->port.membase + UCR2);
1397
1398         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1399                 udelay(1);
1400
1401         /* Restore the registers */
1402         writel(ubir, sport->port.membase + UBIR);
1403         writel(ubmr, sport->port.membase + UBMR);
1404         writel(uts, sport->port.membase + IMX21_UTS);
1405 }
1406
1407 static void
1408 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1409                    struct ktermios *old)
1410 {
1411         struct imx_port *sport = (struct imx_port *)port;
1412         unsigned long flags;
1413         unsigned long ucr2, old_ucr1, old_ucr2;
1414         unsigned int baud, quot;
1415         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1416         unsigned long div, ufcr;
1417         unsigned long num, denom;
1418         uint64_t tdiv64;
1419
1420         /*
1421          * We only support CS7 and CS8.
1422          */
1423         while ((termios->c_cflag & CSIZE) != CS7 &&
1424                (termios->c_cflag & CSIZE) != CS8) {
1425                 termios->c_cflag &= ~CSIZE;
1426                 termios->c_cflag |= old_csize;
1427                 old_csize = CS8;
1428         }
1429
1430         if ((termios->c_cflag & CSIZE) == CS8)
1431                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1432         else
1433                 ucr2 = UCR2_SRST | UCR2_IRTS;
1434
1435         if (termios->c_cflag & CRTSCTS) {
1436                 if (sport->have_rtscts) {
1437                         ucr2 &= ~UCR2_IRTS;
1438
1439                         if (port->rs485.flags & SER_RS485_ENABLED) {
1440                                 /*
1441                                  * RTS is mandatory for rs485 operation, so keep
1442                                  * it under manual control and keep transmitter
1443                                  * disabled.
1444                                  */
1445                                 if (port->rs485.flags &
1446                                     SER_RS485_RTS_AFTER_SEND)
1447                                         imx_port_rts_active(sport, &ucr2);
1448                                 else
1449                                         imx_port_rts_inactive(sport, &ucr2);
1450                         } else {
1451                                 imx_port_rts_auto(sport, &ucr2);
1452                         }
1453                 } else {
1454                         termios->c_cflag &= ~CRTSCTS;
1455                 }
1456         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1457                 /* disable transmitter */
1458                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1459                         imx_port_rts_active(sport, &ucr2);
1460                 else
1461                         imx_port_rts_inactive(sport, &ucr2);
1462         }
1463
1464
1465         if (termios->c_cflag & CSTOPB)
1466                 ucr2 |= UCR2_STPB;
1467         if (termios->c_cflag & PARENB) {
1468                 ucr2 |= UCR2_PREN;
1469                 if (termios->c_cflag & PARODD)
1470                         ucr2 |= UCR2_PROE;
1471         }
1472
1473         del_timer_sync(&sport->timer);
1474
1475         /*
1476          * Ask the core to calculate the divisor for us.
1477          */
1478         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1479         quot = uart_get_divisor(port, baud);
1480
1481         spin_lock_irqsave(&sport->port.lock, flags);
1482
1483         sport->port.read_status_mask = 0;
1484         if (termios->c_iflag & INPCK)
1485                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1486         if (termios->c_iflag & (BRKINT | PARMRK))
1487                 sport->port.read_status_mask |= URXD_BRK;
1488
1489         /*
1490          * Characters to ignore
1491          */
1492         sport->port.ignore_status_mask = 0;
1493         if (termios->c_iflag & IGNPAR)
1494                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1495         if (termios->c_iflag & IGNBRK) {
1496                 sport->port.ignore_status_mask |= URXD_BRK;
1497                 /*
1498                  * If we're ignoring parity and break indicators,
1499                  * ignore overruns too (for real raw support).
1500                  */
1501                 if (termios->c_iflag & IGNPAR)
1502                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1503         }
1504
1505         if ((termios->c_cflag & CREAD) == 0)
1506                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1507
1508         /*
1509          * Update the per-port timeout.
1510          */
1511         uart_update_timeout(port, termios->c_cflag, baud);
1512
1513         /*
1514          * disable interrupts and drain transmitter
1515          */
1516         old_ucr1 = readl(sport->port.membase + UCR1);
1517         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1518                         sport->port.membase + UCR1);
1519
1520         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1521                 barrier();
1522
1523         /* then, disable everything */
1524         old_ucr2 = readl(sport->port.membase + UCR2);
1525         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1526                         sport->port.membase + UCR2);
1527         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1528
1529         /* custom-baudrate handling */
1530         div = sport->port.uartclk / (baud * 16);
1531         if (baud == 38400 && quot != div)
1532                 baud = sport->port.uartclk / (quot * 16);
1533
1534         div = sport->port.uartclk / (baud * 16);
1535         if (div > 7)
1536                 div = 7;
1537         if (!div)
1538                 div = 1;
1539
1540         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1541                 1 << 16, 1 << 16, &num, &denom);
1542
1543         tdiv64 = sport->port.uartclk;
1544         tdiv64 *= num;
1545         do_div(tdiv64, denom * 16 * div);
1546         tty_termios_encode_baud_rate(termios,
1547                                 (speed_t)tdiv64, (speed_t)tdiv64);
1548
1549         num -= 1;
1550         denom -= 1;
1551
1552         ufcr = readl(sport->port.membase + UFCR);
1553         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1554         writel(ufcr, sport->port.membase + UFCR);
1555
1556         writel(num, sport->port.membase + UBIR);
1557         writel(denom, sport->port.membase + UBMR);
1558
1559         if (!is_imx1_uart(sport))
1560                 writel(sport->port.uartclk / div / 1000,
1561                                 sport->port.membase + IMX21_ONEMS);
1562
1563         writel(old_ucr1, sport->port.membase + UCR1);
1564
1565         /* set the parity, stop bits and data size */
1566         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1567
1568         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1569                 imx_enable_ms(&sport->port);
1570
1571         spin_unlock_irqrestore(&sport->port.lock, flags);
1572 }
1573
1574 static const char *imx_type(struct uart_port *port)
1575 {
1576         struct imx_port *sport = (struct imx_port *)port;
1577
1578         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1579 }
1580
1581 /*
1582  * Configure/autoconfigure the port.
1583  */
1584 static void imx_config_port(struct uart_port *port, int flags)
1585 {
1586         struct imx_port *sport = (struct imx_port *)port;
1587
1588         if (flags & UART_CONFIG_TYPE)
1589                 sport->port.type = PORT_IMX;
1590 }
1591
1592 /*
1593  * Verify the new serial_struct (for TIOCSSERIAL).
1594  * The only change we allow are to the flags and type, and
1595  * even then only between PORT_IMX and PORT_UNKNOWN
1596  */
1597 static int
1598 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1599 {
1600         struct imx_port *sport = (struct imx_port *)port;
1601         int ret = 0;
1602
1603         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1604                 ret = -EINVAL;
1605         if (sport->port.irq != ser->irq)
1606                 ret = -EINVAL;
1607         if (ser->io_type != UPIO_MEM)
1608                 ret = -EINVAL;
1609         if (sport->port.uartclk / 16 != ser->baud_base)
1610                 ret = -EINVAL;
1611         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1612                 ret = -EINVAL;
1613         if (sport->port.iobase != ser->port)
1614                 ret = -EINVAL;
1615         if (ser->hub6 != 0)
1616                 ret = -EINVAL;
1617         return ret;
1618 }
1619
1620 #if defined(CONFIG_CONSOLE_POLL)
1621
1622 static int imx_poll_init(struct uart_port *port)
1623 {
1624         struct imx_port *sport = (struct imx_port *)port;
1625         unsigned long flags;
1626         unsigned long temp;
1627         int retval;
1628
1629         retval = clk_prepare_enable(sport->clk_ipg);
1630         if (retval)
1631                 return retval;
1632         retval = clk_prepare_enable(sport->clk_per);
1633         if (retval)
1634                 clk_disable_unprepare(sport->clk_ipg);
1635
1636         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1637
1638         spin_lock_irqsave(&sport->port.lock, flags);
1639
1640         temp = readl(sport->port.membase + UCR1);
1641         if (is_imx1_uart(sport))
1642                 temp |= IMX1_UCR1_UARTCLKEN;
1643         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1644         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1645         writel(temp, sport->port.membase + UCR1);
1646
1647         temp = readl(sport->port.membase + UCR2);
1648         temp |= UCR2_RXEN;
1649         writel(temp, sport->port.membase + UCR2);
1650
1651         spin_unlock_irqrestore(&sport->port.lock, flags);
1652
1653         return 0;
1654 }
1655
1656 static int imx_poll_get_char(struct uart_port *port)
1657 {
1658         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1659                 return NO_POLL_CHAR;
1660
1661         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1662 }
1663
1664 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1665 {
1666         unsigned int status;
1667
1668         /* drain */
1669         do {
1670                 status = readl_relaxed(port->membase + USR1);
1671         } while (~status & USR1_TRDY);
1672
1673         /* write */
1674         writel_relaxed(c, port->membase + URTX0);
1675
1676         /* flush */
1677         do {
1678                 status = readl_relaxed(port->membase + USR2);
1679         } while (~status & USR2_TXDC);
1680 }
1681 #endif
1682
1683 static int imx_rs485_config(struct uart_port *port,
1684                             struct serial_rs485 *rs485conf)
1685 {
1686         struct imx_port *sport = (struct imx_port *)port;
1687         unsigned long temp;
1688
1689         /* unimplemented */
1690         rs485conf->delay_rts_before_send = 0;
1691         rs485conf->delay_rts_after_send = 0;
1692
1693         /* RTS is required to control the transmitter */
1694         if (!sport->have_rtscts && !sport->have_rtsgpio)
1695                 rs485conf->flags &= ~SER_RS485_ENABLED;
1696
1697         if (rs485conf->flags & SER_RS485_ENABLED) {
1698                 /* disable transmitter */
1699                 temp = readl(sport->port.membase + UCR2);
1700                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1701                         imx_port_rts_active(sport, &temp);
1702                 else
1703                         imx_port_rts_inactive(sport, &temp);
1704                 writel(temp, sport->port.membase + UCR2);
1705         }
1706
1707         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1708         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1709             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1710                 temp = readl(sport->port.membase + UCR2);
1711                 temp |= UCR2_RXEN;
1712                 writel(temp, sport->port.membase + UCR2);
1713         }
1714
1715         port->rs485 = *rs485conf;
1716
1717         return 0;
1718 }
1719
1720 static const struct uart_ops imx_pops = {
1721         .tx_empty       = imx_tx_empty,
1722         .set_mctrl      = imx_set_mctrl,
1723         .get_mctrl      = imx_get_mctrl,
1724         .stop_tx        = imx_stop_tx,
1725         .start_tx       = imx_start_tx,
1726         .stop_rx        = imx_stop_rx,
1727         .enable_ms      = imx_enable_ms,
1728         .break_ctl      = imx_break_ctl,
1729         .startup        = imx_startup,
1730         .shutdown       = imx_shutdown,
1731         .flush_buffer   = imx_flush_buffer,
1732         .set_termios    = imx_set_termios,
1733         .type           = imx_type,
1734         .config_port    = imx_config_port,
1735         .verify_port    = imx_verify_port,
1736 #if defined(CONFIG_CONSOLE_POLL)
1737         .poll_init      = imx_poll_init,
1738         .poll_get_char  = imx_poll_get_char,
1739         .poll_put_char  = imx_poll_put_char,
1740 #endif
1741 };
1742
1743 static struct imx_port *imx_ports[UART_NR];
1744
1745 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1746 static void imx_console_putchar(struct uart_port *port, int ch)
1747 {
1748         struct imx_port *sport = (struct imx_port *)port;
1749
1750         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1751                 barrier();
1752
1753         writel(ch, sport->port.membase + URTX0);
1754 }
1755
1756 /*
1757  * Interrupts are disabled on entering
1758  */
1759 static void
1760 imx_console_write(struct console *co, const char *s, unsigned int count)
1761 {
1762         struct imx_port *sport = imx_ports[co->index];
1763         struct imx_port_ucrs old_ucr;
1764         unsigned int ucr1;
1765         unsigned long flags = 0;
1766         int locked = 1;
1767         int retval;
1768
1769         retval = clk_enable(sport->clk_per);
1770         if (retval)
1771                 return;
1772         retval = clk_enable(sport->clk_ipg);
1773         if (retval) {
1774                 clk_disable(sport->clk_per);
1775                 return;
1776         }
1777
1778         if (sport->port.sysrq)
1779                 locked = 0;
1780         else if (oops_in_progress)
1781                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1782         else
1783                 spin_lock_irqsave(&sport->port.lock, flags);
1784
1785         /*
1786          *      First, save UCR1/2/3 and then disable interrupts
1787          */
1788         imx_port_ucrs_save(&sport->port, &old_ucr);
1789         ucr1 = old_ucr.ucr1;
1790
1791         if (is_imx1_uart(sport))
1792                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1793         ucr1 |= UCR1_UARTEN;
1794         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1795
1796         writel(ucr1, sport->port.membase + UCR1);
1797
1798         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1799
1800         uart_console_write(&sport->port, s, count, imx_console_putchar);
1801
1802         /*
1803          *      Finally, wait for transmitter to become empty
1804          *      and restore UCR1/2/3
1805          */
1806         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1807
1808         imx_port_ucrs_restore(&sport->port, &old_ucr);
1809
1810         if (locked)
1811                 spin_unlock_irqrestore(&sport->port.lock, flags);
1812
1813         clk_disable(sport->clk_ipg);
1814         clk_disable(sport->clk_per);
1815 }
1816
1817 /*
1818  * If the port was already initialised (eg, by a boot loader),
1819  * try to determine the current setup.
1820  */
1821 static void __init
1822 imx_console_get_options(struct imx_port *sport, int *baud,
1823                            int *parity, int *bits)
1824 {
1825
1826         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1827                 /* ok, the port was enabled */
1828                 unsigned int ucr2, ubir, ubmr, uartclk;
1829                 unsigned int baud_raw;
1830                 unsigned int ucfr_rfdiv;
1831
1832                 ucr2 = readl(sport->port.membase + UCR2);
1833
1834                 *parity = 'n';
1835                 if (ucr2 & UCR2_PREN) {
1836                         if (ucr2 & UCR2_PROE)
1837                                 *parity = 'o';
1838                         else
1839                                 *parity = 'e';
1840                 }
1841
1842                 if (ucr2 & UCR2_WS)
1843                         *bits = 8;
1844                 else
1845                         *bits = 7;
1846
1847                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1848                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1849
1850                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1851                 if (ucfr_rfdiv == 6)
1852                         ucfr_rfdiv = 7;
1853                 else
1854                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1855
1856                 uartclk = clk_get_rate(sport->clk_per);
1857                 uartclk /= ucfr_rfdiv;
1858
1859                 {       /*
1860                          * The next code provides exact computation of
1861                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1862                          * without need of float support or long long division,
1863                          * which would be required to prevent 32bit arithmetic overflow
1864                          */
1865                         unsigned int mul = ubir + 1;
1866                         unsigned int div = 16 * (ubmr + 1);
1867                         unsigned int rem = uartclk % div;
1868
1869                         baud_raw = (uartclk / div) * mul;
1870                         baud_raw += (rem * mul + div / 2) / div;
1871                         *baud = (baud_raw + 50) / 100 * 100;
1872                 }
1873
1874                 if (*baud != baud_raw)
1875                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1876                                 baud_raw, *baud);
1877         }
1878 }
1879
1880 static int __init
1881 imx_console_setup(struct console *co, char *options)
1882 {
1883         struct imx_port *sport;
1884         int baud = 9600;
1885         int bits = 8;
1886         int parity = 'n';
1887         int flow = 'n';
1888         int retval;
1889
1890         /*
1891          * Check whether an invalid uart number has been specified, and
1892          * if so, search for the first available port that does have
1893          * console support.
1894          */
1895         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1896                 co->index = 0;
1897         sport = imx_ports[co->index];
1898         if (sport == NULL)
1899                 return -ENODEV;
1900
1901         /* For setting the registers, we only need to enable the ipg clock. */
1902         retval = clk_prepare_enable(sport->clk_ipg);
1903         if (retval)
1904                 goto error_console;
1905
1906         if (options)
1907                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1908         else
1909                 imx_console_get_options(sport, &baud, &parity, &bits);
1910
1911         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1912
1913         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1914
1915         clk_disable(sport->clk_ipg);
1916         if (retval) {
1917                 clk_unprepare(sport->clk_ipg);
1918                 goto error_console;
1919         }
1920
1921         retval = clk_prepare(sport->clk_per);
1922         if (retval)
1923                 clk_disable_unprepare(sport->clk_ipg);
1924
1925 error_console:
1926         return retval;
1927 }
1928
1929 static struct uart_driver imx_reg;
1930 static struct console imx_console = {
1931         .name           = DEV_NAME,
1932         .write          = imx_console_write,
1933         .device         = uart_console_device,
1934         .setup          = imx_console_setup,
1935         .flags          = CON_PRINTBUFFER,
1936         .index          = -1,
1937         .data           = &imx_reg,
1938 };
1939
1940 #define IMX_CONSOLE     &imx_console
1941
1942 #ifdef CONFIG_OF
1943 static void imx_console_early_putchar(struct uart_port *port, int ch)
1944 {
1945         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1946                 cpu_relax();
1947
1948         writel_relaxed(ch, port->membase + URTX0);
1949 }
1950
1951 static void imx_console_early_write(struct console *con, const char *s,
1952                                     unsigned count)
1953 {
1954         struct earlycon_device *dev = con->data;
1955
1956         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1957 }
1958
1959 static int __init
1960 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1961 {
1962         if (!dev->port.membase)
1963                 return -ENODEV;
1964
1965         dev->con->write = imx_console_early_write;
1966
1967         return 0;
1968 }
1969 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1970 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1971 #endif
1972
1973 #else
1974 #define IMX_CONSOLE     NULL
1975 #endif
1976
1977 static struct uart_driver imx_reg = {
1978         .owner          = THIS_MODULE,
1979         .driver_name    = DRIVER_NAME,
1980         .dev_name       = DEV_NAME,
1981         .major          = SERIAL_IMX_MAJOR,
1982         .minor          = MINOR_START,
1983         .nr             = ARRAY_SIZE(imx_ports),
1984         .cons           = IMX_CONSOLE,
1985 };
1986
1987 #ifdef CONFIG_OF
1988 /*
1989  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1990  * could successfully get all information from dt or a negative errno.
1991  */
1992 static int serial_imx_probe_dt(struct imx_port *sport,
1993                 struct platform_device *pdev)
1994 {
1995         struct device_node *np = pdev->dev.of_node;
1996         int ret;
1997
1998         sport->devdata = of_device_get_match_data(&pdev->dev);
1999         if (!sport->devdata)
2000                 /* no device tree device */
2001                 return 1;
2002
2003         ret = of_alias_get_id(np, "serial");
2004         if (ret < 0) {
2005                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2006                 return ret;
2007         }
2008         sport->port.line = ret;
2009
2010         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2011             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2012                 sport->have_rtscts = 1;
2013
2014         if (of_get_property(np, "fsl,dte-mode", NULL))
2015                 sport->dte_mode = 1;
2016
2017         if (of_get_property(np, "rts-gpios", NULL))
2018                 sport->have_rtsgpio = 1;
2019
2020         of_get_rs485_mode(np, &sport->port.rs485);
2021
2022         return 0;
2023 }
2024 #else
2025 static inline int serial_imx_probe_dt(struct imx_port *sport,
2026                 struct platform_device *pdev)
2027 {
2028         return 1;
2029 }
2030 #endif
2031
2032 static void serial_imx_probe_pdata(struct imx_port *sport,
2033                 struct platform_device *pdev)
2034 {
2035         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2036
2037         sport->port.line = pdev->id;
2038         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2039
2040         if (!pdata)
2041                 return;
2042
2043         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2044                 sport->have_rtscts = 1;
2045 }
2046
2047 static int serial_imx_probe(struct platform_device *pdev)
2048 {
2049         struct imx_port *sport;
2050         void __iomem *base;
2051         int ret = 0, reg;
2052         struct resource *res;
2053         int txirq, rxirq, rtsirq;
2054
2055         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2056         if (!sport)
2057                 return -ENOMEM;
2058
2059         ret = serial_imx_probe_dt(sport, pdev);
2060         if (ret > 0)
2061                 serial_imx_probe_pdata(sport, pdev);
2062         else if (ret < 0)
2063                 return ret;
2064
2065         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2066         base = devm_ioremap_resource(&pdev->dev, res);
2067         if (IS_ERR(base))
2068                 return PTR_ERR(base);
2069
2070         rxirq = platform_get_irq(pdev, 0);
2071         txirq = platform_get_irq(pdev, 1);
2072         rtsirq = platform_get_irq(pdev, 2);
2073
2074         sport->port.dev = &pdev->dev;
2075         sport->port.mapbase = res->start;
2076         sport->port.membase = base;
2077         sport->port.type = PORT_IMX,
2078         sport->port.iotype = UPIO_MEM;
2079         sport->port.irq = rxirq;
2080         sport->port.fifosize = 32;
2081         sport->port.ops = &imx_pops;
2082         sport->port.rs485_config = imx_rs485_config;
2083         sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2084         sport->port.flags = UPF_BOOT_AUTOCONF;
2085         timer_setup(&sport->timer, imx_timeout, 0);
2086
2087         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2088         if (IS_ERR(sport->gpios))
2089                 return PTR_ERR(sport->gpios);
2090
2091         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2092         if (IS_ERR(sport->clk_ipg)) {
2093                 ret = PTR_ERR(sport->clk_ipg);
2094                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2095                 return ret;
2096         }
2097
2098         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2099         if (IS_ERR(sport->clk_per)) {
2100                 ret = PTR_ERR(sport->clk_per);
2101                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2102                 return ret;
2103         }
2104
2105         sport->port.uartclk = clk_get_rate(sport->clk_per);
2106
2107         /* For register access, we only need to enable the ipg clock. */
2108         ret = clk_prepare_enable(sport->clk_ipg);
2109         if (ret) {
2110                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2111                 return ret;
2112         }
2113
2114         /* Disable interrupts before requesting them */
2115         reg = readl_relaxed(sport->port.membase + UCR1);
2116         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2117                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2118         writel_relaxed(reg, sport->port.membase + UCR1);
2119
2120         if (!is_imx1_uart(sport) && sport->dte_mode) {
2121                 /*
2122                  * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2123                  * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2124                  * and DCD (when they are outputs) or enables the respective
2125                  * irqs. So set this bit early, i.e. before requesting irqs.
2126                  */
2127                 reg = readl(sport->port.membase + UFCR);
2128                 if (!(reg & UFCR_DCEDTE))
2129                         writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
2130
2131                 /*
2132                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2133                  * enabled later because they cannot be cleared
2134                  * (confirmed on i.MX25) which makes them unusable.
2135                  */
2136                 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2137                        sport->port.membase + UCR3);
2138
2139         } else {
2140                 unsigned long ucr3 = UCR3_DSR;
2141
2142                 reg = readl(sport->port.membase + UFCR);
2143                 if (reg & UFCR_DCEDTE)
2144                         writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
2145
2146                 if (!is_imx1_uart(sport))
2147                         ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2148                 writel(ucr3, sport->port.membase + UCR3);
2149         }
2150
2151         clk_disable_unprepare(sport->clk_ipg);
2152
2153         /*
2154          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2155          * chips only have one interrupt.
2156          */
2157         if (txirq > 0) {
2158                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2159                                        dev_name(&pdev->dev), sport);
2160                 if (ret) {
2161                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2162                                 ret);
2163                         return ret;
2164                 }
2165
2166                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2167                                        dev_name(&pdev->dev), sport);
2168                 if (ret) {
2169                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2170                                 ret);
2171                         return ret;
2172                 }
2173         } else {
2174                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2175                                        dev_name(&pdev->dev), sport);
2176                 if (ret) {
2177                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2178                         return ret;
2179                 }
2180         }
2181
2182         imx_ports[sport->port.line] = sport;
2183
2184         platform_set_drvdata(pdev, sport);
2185
2186         return uart_add_one_port(&imx_reg, &sport->port);
2187 }
2188
2189 static int serial_imx_remove(struct platform_device *pdev)
2190 {
2191         struct imx_port *sport = platform_get_drvdata(pdev);
2192
2193         return uart_remove_one_port(&imx_reg, &sport->port);
2194 }
2195
2196 static void serial_imx_restore_context(struct imx_port *sport)
2197 {
2198         if (!sport->context_saved)
2199                 return;
2200
2201         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2202         writel(sport->saved_reg[5], sport->port.membase + UESC);
2203         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2204         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2205         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2206         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2207         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2208         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2209         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2210         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2211         sport->context_saved = false;
2212 }
2213
2214 static void serial_imx_save_context(struct imx_port *sport)
2215 {
2216         /* Save necessary regs */
2217         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2218         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2219         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2220         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2221         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2222         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2223         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2224         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2225         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2226         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2227         sport->context_saved = true;
2228 }
2229
2230 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2231 {
2232         unsigned int val;
2233
2234         val = readl(sport->port.membase + UCR3);
2235         if (on)
2236                 val |= UCR3_AWAKEN;
2237         else
2238                 val &= ~UCR3_AWAKEN;
2239         writel(val, sport->port.membase + UCR3);
2240
2241         val = readl(sport->port.membase + UCR1);
2242         if (on)
2243                 val |= UCR1_RTSDEN;
2244         else
2245                 val &= ~UCR1_RTSDEN;
2246         writel(val, sport->port.membase + UCR1);
2247 }
2248
2249 static int imx_serial_port_suspend_noirq(struct device *dev)
2250 {
2251         struct platform_device *pdev = to_platform_device(dev);
2252         struct imx_port *sport = platform_get_drvdata(pdev);
2253         int ret;
2254
2255         ret = clk_enable(sport->clk_ipg);
2256         if (ret)
2257                 return ret;
2258
2259         serial_imx_save_context(sport);
2260
2261         clk_disable(sport->clk_ipg);
2262
2263         return 0;
2264 }
2265
2266 static int imx_serial_port_resume_noirq(struct device *dev)
2267 {
2268         struct platform_device *pdev = to_platform_device(dev);
2269         struct imx_port *sport = platform_get_drvdata(pdev);
2270         int ret;
2271
2272         ret = clk_enable(sport->clk_ipg);
2273         if (ret)
2274                 return ret;
2275
2276         serial_imx_restore_context(sport);
2277
2278         clk_disable(sport->clk_ipg);
2279
2280         return 0;
2281 }
2282
2283 static int imx_serial_port_suspend(struct device *dev)
2284 {
2285         struct platform_device *pdev = to_platform_device(dev);
2286         struct imx_port *sport = platform_get_drvdata(pdev);
2287
2288         /* enable wakeup from i.MX UART */
2289         serial_imx_enable_wakeup(sport, true);
2290
2291         uart_suspend_port(&imx_reg, &sport->port);
2292         disable_irq(sport->port.irq);
2293
2294         /* Needed to enable clock in suspend_noirq */
2295         return clk_prepare(sport->clk_ipg);
2296 }
2297
2298 static int imx_serial_port_resume(struct device *dev)
2299 {
2300         struct platform_device *pdev = to_platform_device(dev);
2301         struct imx_port *sport = platform_get_drvdata(pdev);
2302
2303         /* disable wakeup from i.MX UART */
2304         serial_imx_enable_wakeup(sport, false);
2305
2306         uart_resume_port(&imx_reg, &sport->port);
2307         enable_irq(sport->port.irq);
2308
2309         clk_unprepare(sport->clk_ipg);
2310
2311         return 0;
2312 }
2313
2314 static int imx_serial_port_freeze(struct device *dev)
2315 {
2316         struct platform_device *pdev = to_platform_device(dev);
2317         struct imx_port *sport = platform_get_drvdata(pdev);
2318
2319         uart_suspend_port(&imx_reg, &sport->port);
2320
2321         /* Needed to enable clock in suspend_noirq */
2322         return clk_prepare(sport->clk_ipg);
2323 }
2324
2325 static int imx_serial_port_thaw(struct device *dev)
2326 {
2327         struct platform_device *pdev = to_platform_device(dev);
2328         struct imx_port *sport = platform_get_drvdata(pdev);
2329
2330         uart_resume_port(&imx_reg, &sport->port);
2331
2332         clk_unprepare(sport->clk_ipg);
2333
2334         return 0;
2335 }
2336
2337 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2338         .suspend_noirq = imx_serial_port_suspend_noirq,
2339         .resume_noirq = imx_serial_port_resume_noirq,
2340         .freeze_noirq = imx_serial_port_suspend_noirq,
2341         .restore_noirq = imx_serial_port_resume_noirq,
2342         .suspend = imx_serial_port_suspend,
2343         .resume = imx_serial_port_resume,
2344         .freeze = imx_serial_port_freeze,
2345         .thaw = imx_serial_port_thaw,
2346         .restore = imx_serial_port_thaw,
2347 };
2348
2349 static struct platform_driver serial_imx_driver = {
2350         .probe          = serial_imx_probe,
2351         .remove         = serial_imx_remove,
2352
2353         .id_table       = imx_uart_devtype,
2354         .driver         = {
2355                 .name   = "imx-uart",
2356                 .of_match_table = imx_uart_dt_ids,
2357                 .pm     = &imx_serial_port_pm_ops,
2358         },
2359 };
2360
2361 static int __init imx_serial_init(void)
2362 {
2363         int ret = uart_register_driver(&imx_reg);
2364
2365         if (ret)
2366                 return ret;
2367
2368         ret = platform_driver_register(&serial_imx_driver);
2369         if (ret != 0)
2370                 uart_unregister_driver(&imx_reg);
2371
2372         return ret;
2373 }
2374
2375 static void __exit imx_serial_exit(void)
2376 {
2377         platform_driver_unregister(&serial_imx_driver);
2378         uart_unregister_driver(&imx_reg);
2379 }
2380
2381 module_init(imx_serial_init);
2382 module_exit(imx_serial_exit);
2383
2384 MODULE_AUTHOR("Sascha Hauer");
2385 MODULE_DESCRIPTION("IMX generic serial port driver");
2386 MODULE_LICENSE("GPL");
2387 MODULE_ALIAS("platform:imx-uart");