drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 #include "serial_mctrl_gpio.h"
  48
  49 /* Register definitions */
  50 #define URXD0 0x0  /* Receiver Register */
  51 #define URTX0 0x40 /* Transmitter Register */
  52 #define UCR1  0x80 /* Control Register 1 */
  53 #define UCR2  0x84 /* Control Register 2 */
  54 #define UCR3  0x88 /* Control Register 3 */
  55 #define UCR4  0x8c /* Control Register 4 */
  56 #define UFCR  0x90 /* FIFO Control Register */
  57 #define USR1  0x94 /* Status Register 1 */
  58 #define USR2  0x98 /* Status Register 2 */
  59 #define UESC  0x9c /* Escape Character Register */
  60 #define UTIM  0xa0 /* Escape Timer Register */
  61 #define UBIR  0xa4 /* BRM Incremental Register */
  62 #define UBMR  0xa8 /* BRM Modulator Register */
  63 #define UBRC  0xac /* Baud Rate Count Register */
  64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  67
  68 /* UART Control Register Bit Fields.*/
  69 #define URXD_DUMMY_READ (1<<16)
  70 #define URXD_CHARRDY    (1<<15)
  71 #define URXD_ERR        (1<<14)
  72 #define URXD_OVRRUN     (1<<13)
  73 #define URXD_FRMERR     (1<<12)
  74 #define URXD_BRK        (1<<11)
  75 #define URXD_PRERR      (1<<10)
  76 #define URXD_RX_DATA    (0xFF<<0)
  77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  83 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  91 #define UCR1_DOZE       (1<<1)  /* Doze */
  92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  96 #define UCR2_CTS        (1<<12) /* Clear to send */
  97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  98 #define UCR2_PREN       (1<<8)  /* Parity enable */
  99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
 100 #define UCR2_STPB       (1<<6)  /* Stop */
 101 #define UCR2_WS         (1<<5)  /* Word size */
 102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 106 #define UCR2_SRST       (1<<0)  /* SW reset */
 107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 110 #define UCR3_DSR        (1<<10) /* Data set ready */
 111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 112 #define UCR3_RI         (1<<8)  /* Ring indicator */
 113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 117 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 118 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 119 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 120 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 121 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 122 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 123 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 124 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 125 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 126 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 127 #define UCR4_IRSC       (1<<5)  /* IR special case */
 128 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 129 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 130 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 131 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 132 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 133 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 134 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 135 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 136 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 137 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 138 #define USR1_RTSS       (1<<14) /* RTS pin status */
 139 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 140 #define USR1_RTSD       (1<<12) /* RTS delta */
 141 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 142 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 143 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 144 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 145 #define USR1_TIMEOUT    (1<<7)   /* Receive timeout interrupt status */
 146 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 147 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 148 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 149 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 150 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 151 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 152 #define USR2_IDLE        (1<<12) /* Idle condition */
 153 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 154 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 155 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 156 #define USR2_WAKE        (1<<7)  /* Wake */
 157 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 158 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 159 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 160 #define USR2_BRCD        (1<<2)  /* Break condition */
 161 #define USR2_ORE        (1<<1)   /* Overrun error */
 162 #define USR2_RDR        (1<<0)   /* Recv data ready */
 163 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 164 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 165 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 166 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 167 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 168 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 169 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 170
 171 /* We've been assigned a range on the "Low-density serial ports" major */
 172 #define SERIAL_IMX_MAJOR        207
 173 #define MINOR_START             16
 174 #define DEV_NAME                "ttymxc"
 175
 176 /*
 177  * This determines how often we check the modem status signals
 178  * for any change.  They generally aren't connected to an IRQ
 179  * so we have to poll them.  We also check immediately before
 180  * filling the TX fifo incase CTS has been dropped.
 181  */
 182 #define MCTRL_TIMEOUT   (250*HZ/1000)
 183
 184 #define DRIVER_NAME "IMX-uart"
 185
 186 #define UART_NR 8
 187
 188 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 189 enum imx_uart_type {
 190         IMX1_UART,
 191         IMX21_UART,
 192         IMX6Q_UART,
 193 };
 194
 195 /* device type dependent stuff */
 196 struct imx_uart_data {
 197         unsigned uts_reg;
 198         enum imx_uart_type devtype;
 199 };
 200
 201 struct imx_port {
 202         struct uart_port        port;
 203         struct timer_list       timer;
 204         unsigned int            old_status;
 205         unsigned int            have_rtscts:1;
 206         unsigned int            dte_mode:1;
 207         unsigned int            irda_inv_rx:1;
 208         unsigned int            irda_inv_tx:1;
 209         unsigned short          trcv_delay; /* transceiver delay */
 210         struct clk              *clk_ipg;
 211         struct clk              *clk_per;
 212         const struct imx_uart_data *devdata;
 213
 214         struct mctrl_gpios *gpios;
 215
 216         /* DMA fields */
 217         unsigned int            dma_is_inited:1;
 218         unsigned int            dma_is_enabled:1;
 219         unsigned int            dma_is_rxing:1;
 220         unsigned int            dma_is_txing:1;
 221         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 222         struct scatterlist      rx_sgl, tx_sgl[2];
 223         void                    *rx_buf;
 224         unsigned int            tx_bytes;
 225         unsigned int            dma_tx_nents;
 226         wait_queue_head_t       dma_wait;
 227         unsigned int            saved_reg[10];
 228         bool                    context_saved;
 229 };
 230
 231 struct imx_port_ucrs {
 232         unsigned int    ucr1;
 233         unsigned int    ucr2;
 234         unsigned int    ucr3;
 235 };
 236
 237 static struct imx_uart_data imx_uart_devdata[] = {
 238         [IMX1_UART] = {
 239                 .uts_reg = IMX1_UTS,
 240                 .devtype = IMX1_UART,
 241         },
 242         [IMX21_UART] = {
 243                 .uts_reg = IMX21_UTS,
 244                 .devtype = IMX21_UART,
 245         },
 246         [IMX6Q_UART] = {
 247                 .uts_reg = IMX21_UTS,
 248                 .devtype = IMX6Q_UART,
 249         },
 250 };
 251
 252 static const struct platform_device_id imx_uart_devtype[] = {
 253         {
 254                 .name = "imx1-uart",
 255                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 256         }, {
 257                 .name = "imx21-uart",
 258                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 259         }, {
 260                 .name = "imx6q-uart",
 261                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 262         }, {
 263                 /* sentinel */
 264         }
 265 };
 266 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 267
 268 static const struct of_device_id imx_uart_dt_ids[] = {
 269         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 270         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 271         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 272         { /* sentinel */ }
 273 };
 274 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 275
 276 static inline unsigned uts_reg(struct imx_port *sport)
 277 {
 278         return sport->devdata->uts_reg;
 279 }
 280
 281 static inline int is_imx1_uart(struct imx_port *sport)
 282 {
 283         return sport->devdata->devtype == IMX1_UART;
 284 }
 285
 286 static inline int is_imx21_uart(struct imx_port *sport)
 287 {
 288         return sport->devdata->devtype == IMX21_UART;
 289 }
 290
 291 static inline int is_imx6q_uart(struct imx_port *sport)
 292 {
 293         return sport->devdata->devtype == IMX6Q_UART;
 294 }
 295 /*
 296  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 297  */
 298 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 299 static void imx_port_ucrs_save(struct uart_port *port,
 300                                struct imx_port_ucrs *ucr)
 301 {
 302         /* save control registers */
 303         ucr->ucr1 = readl(port->membase + UCR1);
 304         ucr->ucr2 = readl(port->membase + UCR2);
 305         ucr->ucr3 = readl(port->membase + UCR3);
 306 }
 307
 308 static void imx_port_ucrs_restore(struct uart_port *port,
 309                                   struct imx_port_ucrs *ucr)
 310 {
 311         /* restore control registers */
 312         writel(ucr->ucr1, port->membase + UCR1);
 313         writel(ucr->ucr2, port->membase + UCR2);
 314         writel(ucr->ucr3, port->membase + UCR3);
 315 }
 316 #endif
 317
 318 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 319 {
 320         *ucr2 &= ~UCR2_CTSC;
 321         *ucr2 |= UCR2_CTS;
 322
 323         mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
 324 }
 325
 326 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 327 {
 328         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 329
 330         mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
 331 }
 332
 333 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 334 {
 335         *ucr2 |= UCR2_CTSC;
 336 }
 337
 338 /*
 339  * interrupts disabled on entry
 340  */
 341 static void imx_stop_tx(struct uart_port *port)
 342 {
 343         struct imx_port *sport = (struct imx_port *)port;
 344         unsigned long temp;
 345
 346         /*
 347          * We are maybe in the SMP context, so if the DMA TX thread is running
 348          * on other cpu, we have to wait for it to finish.
 349          */
 350         if (sport->dma_is_enabled && sport->dma_is_txing)
 351                 return;
 352
 353         temp = readl(port->membase + UCR1);
 354         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 355
 356         /* in rs485 mode disable transmitter if shifter is empty */
 357         if (port->rs485.flags & SER_RS485_ENABLED &&
 358             readl(port->membase + USR2) & USR2_TXDC) {
 359                 temp = readl(port->membase + UCR2);
 360                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 361                         imx_port_rts_inactive(sport, &temp);
 362                 else
 363                         imx_port_rts_active(sport, &temp);
 364                 temp |= UCR2_RXEN;
 365                 writel(temp, port->membase + UCR2);
 366
 367                 temp = readl(port->membase + UCR4);
 368                 temp &= ~UCR4_TCEN;
 369                 writel(temp, port->membase + UCR4);
 370         }
 371 }
 372
 373 /*
 374  * interrupts disabled on entry
 375  */
 376 static void imx_stop_rx(struct uart_port *port)
 377 {
 378         struct imx_port *sport = (struct imx_port *)port;
 379         unsigned long temp;
 380
 381         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 382                 if (sport->port.suspended) {
 383                         dmaengine_terminate_all(sport->dma_chan_rx);
 384                         sport->dma_is_rxing = 0;
 385                 } else {
 386                         return;
 387                 }
 388         }
 389
 390         temp = readl(sport->port.membase + UCR2);
 391         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 392
 393         /* disable the `Receiver Ready Interrrupt` */
 394         temp = readl(sport->port.membase + UCR1);
 395         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 396 }
 397
 398 /*
 399  * Set the modem control timer to fire immediately.
 400  */
 401 static void imx_enable_ms(struct uart_port *port)
 402 {
 403         struct imx_port *sport = (struct imx_port *)port;
 404
 405         mod_timer(&sport->timer, jiffies);
 406
 407         mctrl_gpio_enable_ms(sport->gpios);
 408 }
 409
 410 static void imx_dma_tx(struct imx_port *sport);
 411 static inline void imx_transmit_buffer(struct imx_port *sport)
 412 {
 413         struct circ_buf *xmit = &sport->port.state->xmit;
 414         unsigned long temp;
 415
 416         if (sport->port.x_char) {
 417                 /* Send next char */
 418                 writel(sport->port.x_char, sport->port.membase + URTX0);
 419                 sport->port.icount.tx++;
 420                 sport->port.x_char = 0;
 421                 return;
 422         }
 423
 424         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 425                 imx_stop_tx(&sport->port);
 426                 return;
 427         }
 428
 429         if (sport->dma_is_enabled) {
 430                 /*
 431                  * We've just sent a X-char Ensure the TX DMA is enabled
 432                  * and the TX IRQ is disabled.
 433                  **/
 434                 temp = readl(sport->port.membase + UCR1);
 435                 temp &= ~UCR1_TXMPTYEN;
 436                 if (sport->dma_is_txing) {
 437                         temp |= UCR1_TDMAEN;
 438                         writel(temp, sport->port.membase + UCR1);
 439                 } else {
 440                         writel(temp, sport->port.membase + UCR1);
 441                         imx_dma_tx(sport);
 442                 }
 443         }
 444
 445         while (!uart_circ_empty(xmit) &&
 446                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 447                 /* send xmit->buf[xmit->tail]
 448                  * out the port here */
 449                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 450                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 451                 sport->port.icount.tx++;
 452         }
 453
 454         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 455                 uart_write_wakeup(&sport->port);
 456
 457         if (uart_circ_empty(xmit))
 458                 imx_stop_tx(&sport->port);
 459 }
 460
 461 static void dma_tx_callback(void *data)
 462 {
 463         struct imx_port *sport = data;
 464         struct scatterlist *sgl = &sport->tx_sgl[0];
 465         struct circ_buf *xmit = &sport->port.state->xmit;
 466         unsigned long flags;
 467         unsigned long temp;
 468
 469         spin_lock_irqsave(&sport->port.lock, flags);
 470
 471         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 472
 473         temp = readl(sport->port.membase + UCR1);
 474         temp &= ~UCR1_TDMAEN;
 475         writel(temp, sport->port.membase + UCR1);
 476
 477         /* update the stat */
 478         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 479         sport->port.icount.tx += sport->tx_bytes;
 480
 481         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 482
 483         sport->dma_is_txing = 0;
 484
 485         spin_unlock_irqrestore(&sport->port.lock, flags);
 486
 487         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 488                 uart_write_wakeup(&sport->port);
 489
 490         if (waitqueue_active(&sport->dma_wait)) {
 491                 wake_up(&sport->dma_wait);
 492                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 493                 return;
 494         }
 495
 496         spin_lock_irqsave(&sport->port.lock, flags);
 497         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 498                 imx_dma_tx(sport);
 499         spin_unlock_irqrestore(&sport->port.lock, flags);
 500 }
 501
 502 static void imx_dma_tx(struct imx_port *sport)
 503 {
 504         struct circ_buf *xmit = &sport->port.state->xmit;
 505         struct scatterlist *sgl = sport->tx_sgl;
 506         struct dma_async_tx_descriptor *desc;
 507         struct dma_chan *chan = sport->dma_chan_tx;
 508         struct device *dev = sport->port.dev;
 509         unsigned long temp;
 510         int ret;
 511
 512         if (sport->dma_is_txing)
 513                 return;
 514
 515         sport->tx_bytes = uart_circ_chars_pending(xmit);
 516
 517         if (xmit->tail < xmit->head) {
 518                 sport->dma_tx_nents = 1;
 519                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 520         } else {
 521                 sport->dma_tx_nents = 2;
 522                 sg_init_table(sgl, 2);
 523                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 524                                 UART_XMIT_SIZE - xmit->tail);
 525                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 526         }
 527
 528         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 529         if (ret == 0) {
 530                 dev_err(dev, "DMA mapping error for TX.\n");
 531                 return;
 532         }
 533         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 534                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 535         if (!desc) {
 536                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 537                              DMA_TO_DEVICE);
 538                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 539                 return;
 540         }
 541         desc->callback = dma_tx_callback;
 542         desc->callback_param = sport;
 543
 544         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 545                         uart_circ_chars_pending(xmit));
 546
 547         temp = readl(sport->port.membase + UCR1);
 548         temp |= UCR1_TDMAEN;
 549         writel(temp, sport->port.membase + UCR1);
 550
 551         /* fire it */
 552         sport->dma_is_txing = 1;
 553         dmaengine_submit(desc);
 554         dma_async_issue_pending(chan);
 555         return;
 556 }
 557
 558 /*
 559  * interrupts disabled on entry
 560  */
 561 static void imx_start_tx(struct uart_port *port)
 562 {
 563         struct imx_port *sport = (struct imx_port *)port;
 564         unsigned long temp;
 565
 566         if (port->rs485.flags & SER_RS485_ENABLED) {
 567                 temp = readl(port->membase + UCR2);
 568                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 569                         imx_port_rts_inactive(sport, &temp);
 570                 else
 571                         imx_port_rts_active(sport, &temp);
 572                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 573                         temp &= ~UCR2_RXEN;
 574                 writel(temp, port->membase + UCR2);
 575
 576                 /* enable transmitter and shifter empty irq */
 577                 temp = readl(port->membase + UCR4);
 578                 temp |= UCR4_TCEN;
 579                 writel(temp, port->membase + UCR4);
 580         }
 581
 582         if (!sport->dma_is_enabled) {
 583                 temp = readl(sport->port.membase + UCR1);
 584                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 585         }
 586
 587         if (sport->dma_is_enabled) {
 588                 if (sport->port.x_char) {
 589                         /* We have X-char to send, so enable TX IRQ and
 590                          * disable TX DMA to let TX interrupt to send X-char */
 591                         temp = readl(sport->port.membase + UCR1);
 592                         temp &= ~UCR1_TDMAEN;
 593                         temp |= UCR1_TXMPTYEN;
 594                         writel(temp, sport->port.membase + UCR1);
 595                         return;
 596                 }
 597
 598                 if (!uart_circ_empty(&port->state->xmit) &&
 599                     !uart_tx_stopped(port))
 600                         imx_dma_tx(sport);
 601                 return;
 602         }
 603 }
 604
 605 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 606 {
 607         struct imx_port *sport = dev_id;
 608         unsigned int val;
 609         unsigned long flags;
 610
 611         spin_lock_irqsave(&sport->port.lock, flags);
 612
 613         writel(USR1_RTSD, sport->port.membase + USR1);
 614         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 615         uart_handle_cts_change(&sport->port, !!val);
 616         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 617
 618         spin_unlock_irqrestore(&sport->port.lock, flags);
 619         return IRQ_HANDLED;
 620 }
 621
 622 static irqreturn_t imx_txint(int irq, void *dev_id)
 623 {
 624         struct imx_port *sport = dev_id;
 625         unsigned long flags;
 626
 627         spin_lock_irqsave(&sport->port.lock, flags);
 628         imx_transmit_buffer(sport);
 629         spin_unlock_irqrestore(&sport->port.lock, flags);
 630         return IRQ_HANDLED;
 631 }
 632
 633 static irqreturn_t imx_rxint(int irq, void *dev_id)
 634 {
 635         struct imx_port *sport = dev_id;
 636         unsigned int rx, flg, ignored = 0;
 637         struct tty_port *port = &sport->port.state->port;
 638         unsigned long flags, temp;
 639
 640         spin_lock_irqsave(&sport->port.lock, flags);
 641
 642         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 643                 flg = TTY_NORMAL;
 644                 sport->port.icount.rx++;
 645
 646                 rx = readl(sport->port.membase + URXD0);
 647
 648                 temp = readl(sport->port.membase + USR2);
 649                 if (temp & USR2_BRCD) {
 650                         writel(USR2_BRCD, sport->port.membase + USR2);
 651                         if (uart_handle_break(&sport->port))
 652                                 continue;
 653                 }
 654
 655                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 656                         continue;
 657
 658                 if (unlikely(rx & URXD_ERR)) {
 659                         if (rx & URXD_BRK)
 660                                 sport->port.icount.brk++;
 661                         else if (rx & URXD_PRERR)
 662                                 sport->port.icount.parity++;
 663                         else if (rx & URXD_FRMERR)
 664                                 sport->port.icount.frame++;
 665                         if (rx & URXD_OVRRUN)
 666                                 sport->port.icount.overrun++;
 667
 668                         if (rx & sport->port.ignore_status_mask) {
 669                                 if (++ignored > 100)
 670                                         goto out;
 671                                 continue;
 672                         }
 673
 674                         rx &= (sport->port.read_status_mask | 0xFF);
 675
 676                         if (rx & URXD_BRK)
 677                                 flg = TTY_BREAK;
 678                         else if (rx & URXD_PRERR)
 679                                 flg = TTY_PARITY;
 680                         else if (rx & URXD_FRMERR)
 681                                 flg = TTY_FRAME;
 682                         if (rx & URXD_OVRRUN)
 683                                 flg = TTY_OVERRUN;
 684
 685 #ifdef SUPPORT_SYSRQ
 686                         sport->port.sysrq = 0;
 687 #endif
 688                 }
 689
 690                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 691                         goto out;
 692
 693                 if (tty_insert_flip_char(port, rx, flg) == 0)
 694                         sport->port.icount.buf_overrun++;
 695         }
 696
 697 out:
 698         spin_unlock_irqrestore(&sport->port.lock, flags);
 699         tty_flip_buffer_push(port);
 700         return IRQ_HANDLED;
 701 }
 702
 703 static int start_rx_dma(struct imx_port *sport);
 704 /*
 705  * If the RXFIFO is filled with some data, and then we
 706  * arise a DMA operation to receive them.
 707  */
 708 static void imx_dma_rxint(struct imx_port *sport)
 709 {
 710         unsigned long temp;
 711         unsigned long flags;
 712
 713         spin_lock_irqsave(&sport->port.lock, flags);
 714
 715         temp = readl(sport->port.membase + USR2);
 716         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 717                 sport->dma_is_rxing = 1;
 718
 719                 /* disable the receiver ready and aging timer interrupts */
 720                 temp = readl(sport->port.membase + UCR1);
 721                 temp &= ~(UCR1_RRDYEN);
 722                 writel(temp, sport->port.membase + UCR1);
 723
 724                 temp = readl(sport->port.membase + UCR2);
 725                 temp &= ~(UCR2_ATEN);
 726                 writel(temp, sport->port.membase + UCR2);
 727
 728                 /* tell the DMA to receive the data. */
 729                 start_rx_dma(sport);
 730         }
 731
 732         spin_unlock_irqrestore(&sport->port.lock, flags);
 733 }
 734
 735 static irqreturn_t imx_int(int irq, void *dev_id)
 736 {
 737         struct imx_port *sport = dev_id;
 738         unsigned int sts;
 739         unsigned int sts2;
 740
 741         sts = readl(sport->port.membase + USR1);
 742         sts2 = readl(sport->port.membase + USR2);
 743
 744         if (sts & (USR1_RRDY | USR1_AGTIM)) {
 745                 if (sport->dma_is_enabled)
 746                         imx_dma_rxint(sport);
 747                 else
 748                         imx_rxint(irq, dev_id);
 749         }
 750
 751         if ((sts & USR1_TRDY &&
 752              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 753             (sts2 & USR2_TXDC &&
 754              readl(sport->port.membase + UCR4) & UCR4_TCEN))
 755                 imx_txint(irq, dev_id);
 756
 757         if (sts & USR1_RTSD)
 758                 imx_rtsint(irq, dev_id);
 759
 760         if (sts & USR1_AWAKE)
 761                 writel(USR1_AWAKE, sport->port.membase + USR1);
 762
 763         if (sts2 & USR2_ORE) {
 764                 sport->port.icount.overrun++;
 765                 writel(USR2_ORE, sport->port.membase + USR2);
 766         }
 767
 768         return IRQ_HANDLED;
 769 }
 770
 771 /*
 772  * Return TIOCSER_TEMT when transmitter is not busy.
 773  */
 774 static unsigned int imx_tx_empty(struct uart_port *port)
 775 {
 776         struct imx_port *sport = (struct imx_port *)port;
 777         unsigned int ret;
 778
 779         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 780
 781         /* If the TX DMA is working, return 0. */
 782         if (sport->dma_is_enabled && sport->dma_is_txing)
 783                 ret = 0;
 784
 785         return ret;
 786 }
 787
 788 /*
 789  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 790  */
 791 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 792 {
 793         unsigned int tmp = TIOCM_DSR;
 794         unsigned usr1 = readl(sport->port.membase + USR1);
 795
 796         if (usr1 & USR1_RTSS)
 797                 tmp |= TIOCM_CTS;
 798
 799         /* in DCE mode DCDIN is always 0 */
 800         if (!(usr1 & USR2_DCDIN))
 801                 tmp |= TIOCM_CAR;
 802
 803         if (sport->dte_mode)
 804                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 805                         tmp |= TIOCM_RI;
 806
 807         return tmp;
 808 }
 809
 810 static unsigned int imx_get_mctrl(struct uart_port *port)
 811 {
 812         struct imx_port *sport = (struct imx_port *)port;
 813         unsigned int ret = imx_get_hwmctrl(sport);
 814
 815         mctrl_gpio_get(sport->gpios, &ret);
 816
 817         return ret;
 818 }
 819
 820 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 821 {
 822         struct imx_port *sport = (struct imx_port *)port;
 823         unsigned long temp;
 824
 825         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 826                 temp = readl(sport->port.membase + UCR2);
 827                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 828                 if (mctrl & TIOCM_RTS)
 829                         temp |= UCR2_CTS | UCR2_CTSC;
 830                 writel(temp, sport->port.membase + UCR2);
 831         }
 832
 833         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 834         if (!(mctrl & TIOCM_DTR))
 835                 temp |= UCR3_DSR;
 836         writel(temp, sport->port.membase + UCR3);
 837
 838         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 839         if (mctrl & TIOCM_LOOP)
 840                 temp |= UTS_LOOP;
 841         writel(temp, sport->port.membase + uts_reg(sport));
 842
 843         mctrl_gpio_set(sport->gpios, mctrl);
 844 }
 845
 846 /*
 847  * Interrupts always disabled.
 848  */
 849 static void imx_break_ctl(struct uart_port *port, int break_state)
 850 {
 851         struct imx_port *sport = (struct imx_port *)port;
 852         unsigned long flags, temp;
 853
 854         spin_lock_irqsave(&sport->port.lock, flags);
 855
 856         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 857
 858         if (break_state != 0)
 859                 temp |= UCR1_SNDBRK;
 860
 861         writel(temp, sport->port.membase + UCR1);
 862
 863         spin_unlock_irqrestore(&sport->port.lock, flags);
 864 }
 865
 866 /*
 867  * Handle any change of modem status signal since we were last called.
 868  */
 869 static void imx_mctrl_check(struct imx_port *sport)
 870 {
 871         unsigned int status, changed;
 872
 873         status = imx_get_hwmctrl(sport);
 874         changed = status ^ sport->old_status;
 875
 876         if (changed == 0)
 877                 return;
 878
 879         sport->old_status = status;
 880
 881         if (changed & TIOCM_RI)
 882                 sport->port.icount.rng++;
 883         if (changed & TIOCM_DSR)
 884                 sport->port.icount.dsr++;
 885         if (changed & TIOCM_CAR)
 886                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 887         if (changed & TIOCM_CTS)
 888                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 889
 890         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 891 }
 892
 893 /*
 894  * This is our per-port timeout handler, for checking the
 895  * modem status signals.
 896  */
 897 static void imx_timeout(unsigned long data)
 898 {
 899         struct imx_port *sport = (struct imx_port *)data;
 900         unsigned long flags;
 901
 902         if (sport->port.state) {
 903                 spin_lock_irqsave(&sport->port.lock, flags);
 904                 imx_mctrl_check(sport);
 905                 spin_unlock_irqrestore(&sport->port.lock, flags);
 906
 907                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 908         }
 909 }
 910
 911 #define RX_BUF_SIZE     (PAGE_SIZE)
 912 static void imx_rx_dma_done(struct imx_port *sport)
 913 {
 914         unsigned long temp;
 915         unsigned long flags;
 916
 917         spin_lock_irqsave(&sport->port.lock, flags);
 918
 919         /* re-enable interrupts to get notified when new symbols are incoming */
 920         temp = readl(sport->port.membase + UCR1);
 921         temp |= UCR1_RRDYEN;
 922         writel(temp, sport->port.membase + UCR1);
 923
 924         temp = readl(sport->port.membase + UCR2);
 925         temp |= UCR2_ATEN;
 926         writel(temp, sport->port.membase + UCR2);
 927
 928         sport->dma_is_rxing = 0;
 929
 930         /* Is the shutdown waiting for us? */
 931         if (waitqueue_active(&sport->dma_wait))
 932                 wake_up(&sport->dma_wait);
 933
 934         spin_unlock_irqrestore(&sport->port.lock, flags);
 935 }
 936
 937 /*
 938  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 939  *   [1] the RX DMA buffer is full.
 940  *   [2] the aging timer expires
 941  *
 942  * Condition [2] is triggered when a character has been sitting in the FIFO
 943  * for at least 8 byte durations.
 944  */
 945 static void dma_rx_callback(void *data)
 946 {
 947         struct imx_port *sport = data;
 948         struct dma_chan *chan = sport->dma_chan_rx;
 949         struct scatterlist *sgl = &sport->rx_sgl;
 950         struct tty_port *port = &sport->port.state->port;
 951         struct dma_tx_state state;
 952         enum dma_status status;
 953         unsigned int count;
 954
 955         /* unmap it first */
 956         dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
 957
 958         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 959         count = RX_BUF_SIZE - state.residue;
 960
 961         dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
 962
 963         if (count) {
 964                 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 965                         int bytes = tty_insert_flip_string(port, sport->rx_buf,
 966                                         count);
 967
 968                         if (bytes != count)
 969                                 sport->port.icount.buf_overrun++;
 970                 }
 971                 tty_flip_buffer_push(port);
 972                 sport->port.icount.rx += count;
 973         }
 974
 975         /*
 976          * Restart RX DMA directly if more data is available in order to skip
 977          * the roundtrip through the IRQ handler. If there is some data already
 978          * in the FIFO, DMA needs to be restarted soon anyways.
 979          *
 980          * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
 981          * data starts to arrive again.
 982          */
 983         if (readl(sport->port.membase + USR2) & USR2_RDR)
 984                 start_rx_dma(sport);
 985         else
 986                 imx_rx_dma_done(sport);
 987 }
 988
 989 static int start_rx_dma(struct imx_port *sport)
 990 {
 991         struct scatterlist *sgl = &sport->rx_sgl;
 992         struct dma_chan *chan = sport->dma_chan_rx;
 993         struct device *dev = sport->port.dev;
 994         struct dma_async_tx_descriptor *desc;
 995         int ret;
 996
 997         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
 998         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
 999         if (ret == 0) {
1000                 dev_err(dev, "DMA mapping error for RX.\n");
1001                 return -EINVAL;
1002         }
1003         desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
1004                                         DMA_PREP_INTERRUPT);
1005         if (!desc) {
1006                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1007                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1008                 return -EINVAL;
1009         }
1010         desc->callback = dma_rx_callback;
1011         desc->callback_param = sport;
1012
1013         dev_dbg(dev, "RX: prepare for the DMA.\n");
1014         dmaengine_submit(desc);
1015         dma_async_issue_pending(chan);
1016         return 0;
1017 }
1018
1019 #define TXTL_DEFAULT 2 /* reset default */
1020 #define RXTL_DEFAULT 1 /* reset default */
1021 #define TXTL_DMA 8 /* DMA burst setting */
1022 #define RXTL_DMA 9 /* DMA burst setting */
1023
1024 static void imx_setup_ufcr(struct imx_port *sport,
1025                           unsigned char txwl, unsigned char rxwl)
1026 {
1027         unsigned int val;
1028
1029         /* set receiver / transmitter trigger level */
1030         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1031         val |= txwl << UFCR_TXTL_SHF | rxwl;
1032         writel(val, sport->port.membase + UFCR);
1033 }
1034
1035 static void imx_uart_dma_exit(struct imx_port *sport)
1036 {
1037         if (sport->dma_chan_rx) {
1038                 dma_release_channel(sport->dma_chan_rx);
1039                 sport->dma_chan_rx = NULL;
1040
1041                 kfree(sport->rx_buf);
1042                 sport->rx_buf = NULL;
1043         }
1044
1045         if (sport->dma_chan_tx) {
1046                 dma_release_channel(sport->dma_chan_tx);
1047                 sport->dma_chan_tx = NULL;
1048         }
1049
1050         sport->dma_is_inited = 0;
1051 }
1052
1053 static int imx_uart_dma_init(struct imx_port *sport)
1054 {
1055         struct dma_slave_config slave_config = {};
1056         struct device *dev = sport->port.dev;
1057         int ret;
1058
1059         /* Prepare for RX : */
1060         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1061         if (!sport->dma_chan_rx) {
1062                 dev_dbg(dev, "cannot get the DMA channel.\n");
1063                 ret = -EINVAL;
1064                 goto err;
1065         }
1066
1067         slave_config.direction = DMA_DEV_TO_MEM;
1068         slave_config.src_addr = sport->port.mapbase + URXD0;
1069         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1070         /* one byte less than the watermark level to enable the aging timer */
1071         slave_config.src_maxburst = RXTL_DMA - 1;
1072         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1073         if (ret) {
1074                 dev_err(dev, "error in RX dma configuration.\n");
1075                 goto err;
1076         }
1077
1078         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1079         if (!sport->rx_buf) {
1080                 ret = -ENOMEM;
1081                 goto err;
1082         }
1083
1084         /* Prepare for TX : */
1085         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1086         if (!sport->dma_chan_tx) {
1087                 dev_err(dev, "cannot get the TX DMA channel!\n");
1088                 ret = -EINVAL;
1089                 goto err;
1090         }
1091
1092         slave_config.direction = DMA_MEM_TO_DEV;
1093         slave_config.dst_addr = sport->port.mapbase + URTX0;
1094         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1095         slave_config.dst_maxburst = TXTL_DMA;
1096         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1097         if (ret) {
1098                 dev_err(dev, "error in TX dma configuration.");
1099                 goto err;
1100         }
1101
1102         sport->dma_is_inited = 1;
1103
1104         return 0;
1105 err:
1106         imx_uart_dma_exit(sport);
1107         return ret;
1108 }
1109
1110 static void imx_enable_dma(struct imx_port *sport)
1111 {
1112         unsigned long temp;
1113
1114         init_waitqueue_head(&sport->dma_wait);
1115
1116         /* set UCR1 */
1117         temp = readl(sport->port.membase + UCR1);
1118         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1119         writel(temp, sport->port.membase + UCR1);
1120
1121         temp = readl(sport->port.membase + UCR2);
1122         temp |= UCR2_ATEN;
1123         writel(temp, sport->port.membase + UCR2);
1124
1125         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1126
1127         sport->dma_is_enabled = 1;
1128 }
1129
1130 static void imx_disable_dma(struct imx_port *sport)
1131 {
1132         unsigned long temp;
1133
1134         /* clear UCR1 */
1135         temp = readl(sport->port.membase + UCR1);
1136         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1137         writel(temp, sport->port.membase + UCR1);
1138
1139         /* clear UCR2 */
1140         temp = readl(sport->port.membase + UCR2);
1141         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1142         writel(temp, sport->port.membase + UCR2);
1143
1144         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1145
1146         sport->dma_is_enabled = 0;
1147 }
1148
1149 /* half the RX buffer size */
1150 #define CTSTL 16
1151
1152 static int imx_startup(struct uart_port *port)
1153 {
1154         struct imx_port *sport = (struct imx_port *)port;
1155         int retval, i;
1156         unsigned long flags, temp;
1157
1158         retval = clk_prepare_enable(sport->clk_per);
1159         if (retval)
1160                 return retval;
1161         retval = clk_prepare_enable(sport->clk_ipg);
1162         if (retval) {
1163                 clk_disable_unprepare(sport->clk_per);
1164                 return retval;
1165         }
1166
1167         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1168
1169         /* disable the DREN bit (Data Ready interrupt enable) before
1170          * requesting IRQs
1171          */
1172         temp = readl(sport->port.membase + UCR4);
1173
1174         /* set the trigger level for CTS */
1175         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1176         temp |= CTSTL << UCR4_CTSTL_SHF;
1177
1178         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1179
1180         /* Can we enable the DMA support? */
1181         if (is_imx6q_uart(sport) && !uart_console(port) &&
1182             !sport->dma_is_inited)
1183                 imx_uart_dma_init(sport);
1184
1185         spin_lock_irqsave(&sport->port.lock, flags);
1186         /* Reset fifo's and state machines */
1187         i = 100;
1188
1189         temp = readl(sport->port.membase + UCR2);
1190         temp &= ~UCR2_SRST;
1191         writel(temp, sport->port.membase + UCR2);
1192
1193         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1194                 udelay(1);
1195
1196         /*
1197          * Finally, clear and enable interrupts
1198          */
1199         writel(USR1_RTSD, sport->port.membase + USR1);
1200         writel(USR2_ORE, sport->port.membase + USR2);
1201
1202         if (sport->dma_is_inited && !sport->dma_is_enabled)
1203                 imx_enable_dma(sport);
1204
1205         temp = readl(sport->port.membase + UCR1);
1206         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1207
1208         writel(temp, sport->port.membase + UCR1);
1209
1210         temp = readl(sport->port.membase + UCR4);
1211         temp |= UCR4_OREN;
1212         writel(temp, sport->port.membase + UCR4);
1213
1214         temp = readl(sport->port.membase + UCR2);
1215         temp |= (UCR2_RXEN | UCR2_TXEN);
1216         if (!sport->have_rtscts)
1217                 temp |= UCR2_IRTS;
1218         writel(temp, sport->port.membase + UCR2);
1219
1220         if (!is_imx1_uart(sport)) {
1221                 temp = readl(sport->port.membase + UCR3);
1222                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1223                 writel(temp, sport->port.membase + UCR3);
1224         }
1225
1226         /*
1227          * Enable modem status interrupts
1228          */
1229         imx_enable_ms(&sport->port);
1230         spin_unlock_irqrestore(&sport->port.lock, flags);
1231
1232         return 0;
1233 }
1234
1235 static void imx_shutdown(struct uart_port *port)
1236 {
1237         struct imx_port *sport = (struct imx_port *)port;
1238         unsigned long temp;
1239         unsigned long flags;
1240
1241         if (sport->dma_is_enabled) {
1242                 int ret;
1243
1244                 /* We have to wait for the DMA to finish. */
1245                 ret = wait_event_interruptible(sport->dma_wait,
1246                         !sport->dma_is_rxing && !sport->dma_is_txing);
1247                 if (ret != 0) {
1248                         sport->dma_is_rxing = 0;
1249                         sport->dma_is_txing = 0;
1250                         dmaengine_terminate_all(sport->dma_chan_tx);
1251                         dmaengine_terminate_all(sport->dma_chan_rx);
1252                 }
1253                 spin_lock_irqsave(&sport->port.lock, flags);
1254                 imx_stop_tx(port);
1255                 imx_stop_rx(port);
1256                 imx_disable_dma(sport);
1257                 spin_unlock_irqrestore(&sport->port.lock, flags);
1258                 imx_uart_dma_exit(sport);
1259         }
1260
1261         mctrl_gpio_disable_ms(sport->gpios);
1262
1263         spin_lock_irqsave(&sport->port.lock, flags);
1264         temp = readl(sport->port.membase + UCR2);
1265         temp &= ~(UCR2_TXEN);
1266         writel(temp, sport->port.membase + UCR2);
1267         spin_unlock_irqrestore(&sport->port.lock, flags);
1268
1269         /*
1270          * Stop our timer.
1271          */
1272         del_timer_sync(&sport->timer);
1273
1274         /*
1275          * Disable all interrupts, port and break condition.
1276          */
1277
1278         spin_lock_irqsave(&sport->port.lock, flags);
1279         temp = readl(sport->port.membase + UCR1);
1280         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1281
1282         writel(temp, sport->port.membase + UCR1);
1283         spin_unlock_irqrestore(&sport->port.lock, flags);
1284
1285         clk_disable_unprepare(sport->clk_per);
1286         clk_disable_unprepare(sport->clk_ipg);
1287 }
1288
1289 static void imx_flush_buffer(struct uart_port *port)
1290 {
1291         struct imx_port *sport = (struct imx_port *)port;
1292         struct scatterlist *sgl = &sport->tx_sgl[0];
1293         unsigned long temp;
1294         int i = 100, ubir, ubmr, uts;
1295
1296         if (!sport->dma_chan_tx)
1297                 return;
1298
1299         sport->tx_bytes = 0;
1300         dmaengine_terminate_all(sport->dma_chan_tx);
1301         if (sport->dma_is_txing) {
1302                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1303                              DMA_TO_DEVICE);
1304                 temp = readl(sport->port.membase + UCR1);
1305                 temp &= ~UCR1_TDMAEN;
1306                 writel(temp, sport->port.membase + UCR1);
1307                 sport->dma_is_txing = false;
1308         }
1309
1310         /*
1311          * According to the Reference Manual description of the UART SRST bit:
1312          * "Reset the transmit and receive state machines,
1313          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1314          * and UTS[6-3]". As we don't need to restore the old values from
1315          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1316          */
1317         ubir = readl(sport->port.membase + UBIR);
1318         ubmr = readl(sport->port.membase + UBMR);
1319         uts = readl(sport->port.membase + IMX21_UTS);
1320
1321         temp = readl(sport->port.membase + UCR2);
1322         temp &= ~UCR2_SRST;
1323         writel(temp, sport->port.membase + UCR2);
1324
1325         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1326                 udelay(1);
1327
1328         /* Restore the registers */
1329         writel(ubir, sport->port.membase + UBIR);
1330         writel(ubmr, sport->port.membase + UBMR);
1331         writel(uts, sport->port.membase + IMX21_UTS);
1332 }
1333
1334 static void
1335 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1336                    struct ktermios *old)
1337 {
1338         struct imx_port *sport = (struct imx_port *)port;
1339         unsigned long flags;
1340         unsigned long ucr2, old_ucr1, old_ucr2;
1341         unsigned int baud, quot;
1342         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1343         unsigned long div, ufcr;
1344         unsigned long num, denom;
1345         uint64_t tdiv64;
1346
1347         /*
1348          * We only support CS7 and CS8.
1349          */
1350         while ((termios->c_cflag & CSIZE) != CS7 &&
1351                (termios->c_cflag & CSIZE) != CS8) {
1352                 termios->c_cflag &= ~CSIZE;
1353                 termios->c_cflag |= old_csize;
1354                 old_csize = CS8;
1355         }
1356
1357         if ((termios->c_cflag & CSIZE) == CS8)
1358                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1359         else
1360                 ucr2 = UCR2_SRST | UCR2_IRTS;
1361
1362         if (termios->c_cflag & CRTSCTS) {
1363                 if (sport->have_rtscts) {
1364                         ucr2 &= ~UCR2_IRTS;
1365
1366                         if (port->rs485.flags & SER_RS485_ENABLED) {
1367                                 /*
1368                                  * RTS is mandatory for rs485 operation, so keep
1369                                  * it under manual control and keep transmitter
1370                                  * disabled.
1371                                  */
1372                                 if (port->rs485.flags &
1373                                     SER_RS485_RTS_AFTER_SEND)
1374                                         imx_port_rts_inactive(sport, &ucr2);
1375                                 else
1376                                         imx_port_rts_active(sport, &ucr2);
1377                         } else {
1378                                 imx_port_rts_auto(sport, &ucr2);
1379                         }
1380                 } else {
1381                         termios->c_cflag &= ~CRTSCTS;
1382                 }
1383         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1384                 /* disable transmitter */
1385                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1386                         imx_port_rts_inactive(sport, &ucr2);
1387                 else
1388                         imx_port_rts_active(sport, &ucr2);
1389         }
1390
1391
1392         if (termios->c_cflag & CSTOPB)
1393                 ucr2 |= UCR2_STPB;
1394         if (termios->c_cflag & PARENB) {
1395                 ucr2 |= UCR2_PREN;
1396                 if (termios->c_cflag & PARODD)
1397                         ucr2 |= UCR2_PROE;
1398         }
1399
1400         del_timer_sync(&sport->timer);
1401
1402         /*
1403          * Ask the core to calculate the divisor for us.
1404          */
1405         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1406         quot = uart_get_divisor(port, baud);
1407
1408         spin_lock_irqsave(&sport->port.lock, flags);
1409
1410         sport->port.read_status_mask = 0;
1411         if (termios->c_iflag & INPCK)
1412                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1413         if (termios->c_iflag & (BRKINT | PARMRK))
1414                 sport->port.read_status_mask |= URXD_BRK;
1415
1416         /*
1417          * Characters to ignore
1418          */
1419         sport->port.ignore_status_mask = 0;
1420         if (termios->c_iflag & IGNPAR)
1421                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1422         if (termios->c_iflag & IGNBRK) {
1423                 sport->port.ignore_status_mask |= URXD_BRK;
1424                 /*
1425                  * If we're ignoring parity and break indicators,
1426                  * ignore overruns too (for real raw support).
1427                  */
1428                 if (termios->c_iflag & IGNPAR)
1429                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1430         }
1431
1432         if ((termios->c_cflag & CREAD) == 0)
1433                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1434
1435         /*
1436          * Update the per-port timeout.
1437          */
1438         uart_update_timeout(port, termios->c_cflag, baud);
1439
1440         /*
1441          * disable interrupts and drain transmitter
1442          */
1443         old_ucr1 = readl(sport->port.membase + UCR1);
1444         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1445                         sport->port.membase + UCR1);
1446
1447         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1448                 barrier();
1449
1450         /* then, disable everything */
1451         old_ucr2 = readl(sport->port.membase + UCR2);
1452         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1453                         sport->port.membase + UCR2);
1454         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1455
1456         /* custom-baudrate handling */
1457         div = sport->port.uartclk / (baud * 16);
1458         if (baud == 38400 && quot != div)
1459                 baud = sport->port.uartclk / (quot * 16);
1460
1461         div = sport->port.uartclk / (baud * 16);
1462         if (div > 7)
1463                 div = 7;
1464         if (!div)
1465                 div = 1;
1466
1467         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1468                 1 << 16, 1 << 16, &num, &denom);
1469
1470         tdiv64 = sport->port.uartclk;
1471         tdiv64 *= num;
1472         do_div(tdiv64, denom * 16 * div);
1473         tty_termios_encode_baud_rate(termios,
1474                                 (speed_t)tdiv64, (speed_t)tdiv64);
1475
1476         num -= 1;
1477         denom -= 1;
1478
1479         ufcr = readl(sport->port.membase + UFCR);
1480         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1481         if (sport->dte_mode)
1482                 ufcr |= UFCR_DCEDTE;
1483         writel(ufcr, sport->port.membase + UFCR);
1484
1485         writel(num, sport->port.membase + UBIR);
1486         writel(denom, sport->port.membase + UBMR);
1487
1488         if (!is_imx1_uart(sport))
1489                 writel(sport->port.uartclk / div / 1000,
1490                                 sport->port.membase + IMX21_ONEMS);
1491
1492         writel(old_ucr1, sport->port.membase + UCR1);
1493
1494         /* set the parity, stop bits and data size */
1495         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1496
1497         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1498                 imx_enable_ms(&sport->port);
1499
1500         spin_unlock_irqrestore(&sport->port.lock, flags);
1501 }
1502
1503 static const char *imx_type(struct uart_port *port)
1504 {
1505         struct imx_port *sport = (struct imx_port *)port;
1506
1507         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1508 }
1509
1510 /*
1511  * Configure/autoconfigure the port.
1512  */
1513 static void imx_config_port(struct uart_port *port, int flags)
1514 {
1515         struct imx_port *sport = (struct imx_port *)port;
1516
1517         if (flags & UART_CONFIG_TYPE)
1518                 sport->port.type = PORT_IMX;
1519 }
1520
1521 /*
1522  * Verify the new serial_struct (for TIOCSSERIAL).
1523  * The only change we allow are to the flags and type, and
1524  * even then only between PORT_IMX and PORT_UNKNOWN
1525  */
1526 static int
1527 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1528 {
1529         struct imx_port *sport = (struct imx_port *)port;
1530         int ret = 0;
1531
1532         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1533                 ret = -EINVAL;
1534         if (sport->port.irq != ser->irq)
1535                 ret = -EINVAL;
1536         if (ser->io_type != UPIO_MEM)
1537                 ret = -EINVAL;
1538         if (sport->port.uartclk / 16 != ser->baud_base)
1539                 ret = -EINVAL;
1540         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1541                 ret = -EINVAL;
1542         if (sport->port.iobase != ser->port)
1543                 ret = -EINVAL;
1544         if (ser->hub6 != 0)
1545                 ret = -EINVAL;
1546         return ret;
1547 }
1548
1549 #if defined(CONFIG_CONSOLE_POLL)
1550
1551 static int imx_poll_init(struct uart_port *port)
1552 {
1553         struct imx_port *sport = (struct imx_port *)port;
1554         unsigned long flags;
1555         unsigned long temp;
1556         int retval;
1557
1558         retval = clk_prepare_enable(sport->clk_ipg);
1559         if (retval)
1560                 return retval;
1561         retval = clk_prepare_enable(sport->clk_per);
1562         if (retval)
1563                 clk_disable_unprepare(sport->clk_ipg);
1564
1565         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1566
1567         spin_lock_irqsave(&sport->port.lock, flags);
1568
1569         temp = readl(sport->port.membase + UCR1);
1570         if (is_imx1_uart(sport))
1571                 temp |= IMX1_UCR1_UARTCLKEN;
1572         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1573         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1574         writel(temp, sport->port.membase + UCR1);
1575
1576         temp = readl(sport->port.membase + UCR2);
1577         temp |= UCR2_RXEN;
1578         writel(temp, sport->port.membase + UCR2);
1579
1580         spin_unlock_irqrestore(&sport->port.lock, flags);
1581
1582         return 0;
1583 }
1584
1585 static int imx_poll_get_char(struct uart_port *port)
1586 {
1587         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1588                 return NO_POLL_CHAR;
1589
1590         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1591 }
1592
1593 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1594 {
1595         unsigned int status;
1596
1597         /* drain */
1598         do {
1599                 status = readl_relaxed(port->membase + USR1);
1600         } while (~status & USR1_TRDY);
1601
1602         /* write */
1603         writel_relaxed(c, port->membase + URTX0);
1604
1605         /* flush */
1606         do {
1607                 status = readl_relaxed(port->membase + USR2);
1608         } while (~status & USR2_TXDC);
1609 }
1610 #endif
1611
1612 static int imx_rs485_config(struct uart_port *port,
1613                             struct serial_rs485 *rs485conf)
1614 {
1615         struct imx_port *sport = (struct imx_port *)port;
1616         unsigned long temp;
1617
1618         /* unimplemented */
1619         rs485conf->delay_rts_before_send = 0;
1620         rs485conf->delay_rts_after_send = 0;
1621
1622         /* RTS is required to control the transmitter */
1623         if (!sport->have_rtscts)
1624                 rs485conf->flags &= ~SER_RS485_ENABLED;
1625
1626         if (rs485conf->flags & SER_RS485_ENABLED) {
1627                 /* disable transmitter */
1628                 temp = readl(sport->port.membase + UCR2);
1629                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1630                         imx_port_rts_inactive(sport, &temp);
1631                 else
1632                         imx_port_rts_active(sport, &temp);
1633                 writel(temp, sport->port.membase + UCR2);
1634         }
1635
1636         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1637         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1638             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1639                 temp = readl(sport->port.membase + UCR2);
1640                 temp |= UCR2_RXEN;
1641                 writel(temp, sport->port.membase + UCR2);
1642         }
1643
1644         port->rs485 = *rs485conf;
1645
1646         return 0;
1647 }
1648
1649 static struct uart_ops imx_pops = {
1650         .tx_empty       = imx_tx_empty,
1651         .set_mctrl      = imx_set_mctrl,
1652         .get_mctrl      = imx_get_mctrl,
1653         .stop_tx        = imx_stop_tx,
1654         .start_tx       = imx_start_tx,
1655         .stop_rx        = imx_stop_rx,
1656         .enable_ms      = imx_enable_ms,
1657         .break_ctl      = imx_break_ctl,
1658         .startup        = imx_startup,
1659         .shutdown       = imx_shutdown,
1660         .flush_buffer   = imx_flush_buffer,
1661         .set_termios    = imx_set_termios,
1662         .type           = imx_type,
1663         .config_port    = imx_config_port,
1664         .verify_port    = imx_verify_port,
1665 #if defined(CONFIG_CONSOLE_POLL)
1666         .poll_init      = imx_poll_init,
1667         .poll_get_char  = imx_poll_get_char,
1668         .poll_put_char  = imx_poll_put_char,
1669 #endif
1670 };
1671
1672 static struct imx_port *imx_ports[UART_NR];
1673
1674 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1675 static void imx_console_putchar(struct uart_port *port, int ch)
1676 {
1677         struct imx_port *sport = (struct imx_port *)port;
1678
1679         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1680                 barrier();
1681
1682         writel(ch, sport->port.membase + URTX0);
1683 }
1684
1685 /*
1686  * Interrupts are disabled on entering
1687  */
1688 static void
1689 imx_console_write(struct console *co, const char *s, unsigned int count)
1690 {
1691         struct imx_port *sport = imx_ports[co->index];
1692         struct imx_port_ucrs old_ucr;
1693         unsigned int ucr1;
1694         unsigned long flags = 0;
1695         int locked = 1;
1696         int retval;
1697
1698         retval = clk_enable(sport->clk_per);
1699         if (retval)
1700                 return;
1701         retval = clk_enable(sport->clk_ipg);
1702         if (retval) {
1703                 clk_disable(sport->clk_per);
1704                 return;
1705         }
1706
1707         if (sport->port.sysrq)
1708                 locked = 0;
1709         else if (oops_in_progress)
1710                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1711         else
1712                 spin_lock_irqsave(&sport->port.lock, flags);
1713
1714         /*
1715          *      First, save UCR1/2/3 and then disable interrupts
1716          */
1717         imx_port_ucrs_save(&sport->port, &old_ucr);
1718         ucr1 = old_ucr.ucr1;
1719
1720         if (is_imx1_uart(sport))
1721                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1722         ucr1 |= UCR1_UARTEN;
1723         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1724
1725         writel(ucr1, sport->port.membase + UCR1);
1726
1727         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1728
1729         uart_console_write(&sport->port, s, count, imx_console_putchar);
1730
1731         /*
1732          *      Finally, wait for transmitter to become empty
1733          *      and restore UCR1/2/3
1734          */
1735         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1736
1737         imx_port_ucrs_restore(&sport->port, &old_ucr);
1738
1739         if (locked)
1740                 spin_unlock_irqrestore(&sport->port.lock, flags);
1741
1742         clk_disable(sport->clk_ipg);
1743         clk_disable(sport->clk_per);
1744 }
1745
1746 /*
1747  * If the port was already initialised (eg, by a boot loader),
1748  * try to determine the current setup.
1749  */
1750 static void __init
1751 imx_console_get_options(struct imx_port *sport, int *baud,
1752                            int *parity, int *bits)
1753 {
1754
1755         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1756                 /* ok, the port was enabled */
1757                 unsigned int ucr2, ubir, ubmr, uartclk;
1758                 unsigned int baud_raw;
1759                 unsigned int ucfr_rfdiv;
1760
1761                 ucr2 = readl(sport->port.membase + UCR2);
1762
1763                 *parity = 'n';
1764                 if (ucr2 & UCR2_PREN) {
1765                         if (ucr2 & UCR2_PROE)
1766                                 *parity = 'o';
1767                         else
1768                                 *parity = 'e';
1769                 }
1770
1771                 if (ucr2 & UCR2_WS)
1772                         *bits = 8;
1773                 else
1774                         *bits = 7;
1775
1776                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1777                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1778
1779                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1780                 if (ucfr_rfdiv == 6)
1781                         ucfr_rfdiv = 7;
1782                 else
1783                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1784
1785                 uartclk = clk_get_rate(sport->clk_per);
1786                 uartclk /= ucfr_rfdiv;
1787
1788                 {       /*
1789                          * The next code provides exact computation of
1790                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1791                          * without need of float support or long long division,
1792                          * which would be required to prevent 32bit arithmetic overflow
1793                          */
1794                         unsigned int mul = ubir + 1;
1795                         unsigned int div = 16 * (ubmr + 1);
1796                         unsigned int rem = uartclk % div;
1797
1798                         baud_raw = (uartclk / div) * mul;
1799                         baud_raw += (rem * mul + div / 2) / div;
1800                         *baud = (baud_raw + 50) / 100 * 100;
1801                 }
1802
1803                 if (*baud != baud_raw)
1804                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1805                                 baud_raw, *baud);
1806         }
1807 }
1808
1809 static int __init
1810 imx_console_setup(struct console *co, char *options)
1811 {
1812         struct imx_port *sport;
1813         int baud = 9600;
1814         int bits = 8;
1815         int parity = 'n';
1816         int flow = 'n';
1817         int retval;
1818
1819         /*
1820          * Check whether an invalid uart number has been specified, and
1821          * if so, search for the first available port that does have
1822          * console support.
1823          */
1824         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1825                 co->index = 0;
1826         sport = imx_ports[co->index];
1827         if (sport == NULL)
1828                 return -ENODEV;
1829
1830         /* For setting the registers, we only need to enable the ipg clock. */
1831         retval = clk_prepare_enable(sport->clk_ipg);
1832         if (retval)
1833                 goto error_console;
1834
1835         if (options)
1836                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1837         else
1838                 imx_console_get_options(sport, &baud, &parity, &bits);
1839
1840         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1841
1842         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1843
1844         clk_disable(sport->clk_ipg);
1845         if (retval) {
1846                 clk_unprepare(sport->clk_ipg);
1847                 goto error_console;
1848         }
1849
1850         retval = clk_prepare(sport->clk_per);
1851         if (retval)
1852                 clk_disable_unprepare(sport->clk_ipg);
1853
1854 error_console:
1855         return retval;
1856 }
1857
1858 static struct uart_driver imx_reg;
1859 static struct console imx_console = {
1860         .name           = DEV_NAME,
1861         .write          = imx_console_write,
1862         .device         = uart_console_device,
1863         .setup          = imx_console_setup,
1864         .flags          = CON_PRINTBUFFER,
1865         .index          = -1,
1866         .data           = &imx_reg,
1867 };
1868
1869 #define IMX_CONSOLE     &imx_console
1870
1871 #ifdef CONFIG_OF
1872 static void imx_console_early_putchar(struct uart_port *port, int ch)
1873 {
1874         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1875                 cpu_relax();
1876
1877         writel_relaxed(ch, port->membase + URTX0);
1878 }
1879
1880 static void imx_console_early_write(struct console *con, const char *s,
1881                                     unsigned count)
1882 {
1883         struct earlycon_device *dev = con->data;
1884
1885         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1886 }
1887
1888 static int __init
1889 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1890 {
1891         if (!dev->port.membase)
1892                 return -ENODEV;
1893
1894         dev->con->write = imx_console_early_write;
1895
1896         return 0;
1897 }
1898 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1899 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1900 #endif
1901
1902 #else
1903 #define IMX_CONSOLE     NULL
1904 #endif
1905
1906 static struct uart_driver imx_reg = {
1907         .owner          = THIS_MODULE,
1908         .driver_name    = DRIVER_NAME,
1909         .dev_name       = DEV_NAME,
1910         .major          = SERIAL_IMX_MAJOR,
1911         .minor          = MINOR_START,
1912         .nr             = ARRAY_SIZE(imx_ports),
1913         .cons           = IMX_CONSOLE,
1914 };
1915
1916 #ifdef CONFIG_OF
1917 /*
1918  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1919  * could successfully get all information from dt or a negative errno.
1920  */
1921 static int serial_imx_probe_dt(struct imx_port *sport,
1922                 struct platform_device *pdev)
1923 {
1924         struct device_node *np = pdev->dev.of_node;
1925         int ret;
1926
1927         sport->devdata = of_device_get_match_data(&pdev->dev);
1928         if (!sport->devdata)
1929                 /* no device tree device */
1930                 return 1;
1931
1932         ret = of_alias_get_id(np, "serial");
1933         if (ret < 0) {
1934                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1935                 return ret;
1936         }
1937         sport->port.line = ret;
1938
1939         if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1940                 sport->have_rtscts = 1;
1941
1942         if (of_get_property(np, "fsl,dte-mode", NULL))
1943                 sport->dte_mode = 1;
1944
1945         return 0;
1946 }
1947 #else
1948 static inline int serial_imx_probe_dt(struct imx_port *sport,
1949                 struct platform_device *pdev)
1950 {
1951         return 1;
1952 }
1953 #endif
1954
1955 static void serial_imx_probe_pdata(struct imx_port *sport,
1956                 struct platform_device *pdev)
1957 {
1958         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1959
1960         sport->port.line = pdev->id;
1961         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
1962
1963         if (!pdata)
1964                 return;
1965
1966         if (pdata->flags & IMXUART_HAVE_RTSCTS)
1967                 sport->have_rtscts = 1;
1968 }
1969
1970 static int serial_imx_probe(struct platform_device *pdev)
1971 {
1972         struct imx_port *sport;
1973         void __iomem *base;
1974         int ret = 0, reg;
1975         struct resource *res;
1976         int txirq, rxirq, rtsirq;
1977
1978         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1979         if (!sport)
1980                 return -ENOMEM;
1981
1982         ret = serial_imx_probe_dt(sport, pdev);
1983         if (ret > 0)
1984                 serial_imx_probe_pdata(sport, pdev);
1985         else if (ret < 0)
1986                 return ret;
1987
1988         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1989         base = devm_ioremap_resource(&pdev->dev, res);
1990         if (IS_ERR(base))
1991                 return PTR_ERR(base);
1992
1993         rxirq = platform_get_irq(pdev, 0);
1994         txirq = platform_get_irq(pdev, 1);
1995         rtsirq = platform_get_irq(pdev, 2);
1996
1997         sport->port.dev = &pdev->dev;
1998         sport->port.mapbase = res->start;
1999         sport->port.membase = base;
2000         sport->port.type = PORT_IMX,
2001         sport->port.iotype = UPIO_MEM;
2002         sport->port.irq = rxirq;
2003         sport->port.fifosize = 32;
2004         sport->port.ops = &imx_pops;
2005         sport->port.rs485_config = imx_rs485_config;
2006         sport->port.rs485.flags =
2007                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2008         sport->port.flags = UPF_BOOT_AUTOCONF;
2009         init_timer(&sport->timer);
2010         sport->timer.function = imx_timeout;
2011         sport->timer.data     = (unsigned long)sport;
2012
2013         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2014         if (IS_ERR(sport->gpios))
2015                 return PTR_ERR(sport->gpios);
2016
2017         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2018         if (IS_ERR(sport->clk_ipg)) {
2019                 ret = PTR_ERR(sport->clk_ipg);
2020                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2021                 return ret;
2022         }
2023
2024         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2025         if (IS_ERR(sport->clk_per)) {
2026                 ret = PTR_ERR(sport->clk_per);
2027                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2028                 return ret;
2029         }
2030
2031         sport->port.uartclk = clk_get_rate(sport->clk_per);
2032
2033         /* For register access, we only need to enable the ipg clock. */
2034         ret = clk_prepare_enable(sport->clk_ipg);
2035         if (ret)
2036                 return ret;
2037
2038         /* Disable interrupts before requesting them */
2039         reg = readl_relaxed(sport->port.membase + UCR1);
2040         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2041                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2042         writel_relaxed(reg, sport->port.membase + UCR1);
2043
2044         clk_disable_unprepare(sport->clk_ipg);
2045
2046         /*
2047          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2048          * chips only have one interrupt.
2049          */
2050         if (txirq > 0) {
2051                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2052                                        dev_name(&pdev->dev), sport);
2053                 if (ret)
2054                         return ret;
2055
2056                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2057                                        dev_name(&pdev->dev), sport);
2058                 if (ret)
2059                         return ret;
2060         } else {
2061                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2062                                        dev_name(&pdev->dev), sport);
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         imx_ports[sport->port.line] = sport;
2068
2069         platform_set_drvdata(pdev, sport);
2070
2071         return uart_add_one_port(&imx_reg, &sport->port);
2072 }
2073
2074 static int serial_imx_remove(struct platform_device *pdev)
2075 {
2076         struct imx_port *sport = platform_get_drvdata(pdev);
2077
2078         return uart_remove_one_port(&imx_reg, &sport->port);
2079 }
2080
2081 static void serial_imx_restore_context(struct imx_port *sport)
2082 {
2083         if (!sport->context_saved)
2084                 return;
2085
2086         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2087         writel(sport->saved_reg[5], sport->port.membase + UESC);
2088         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2089         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2090         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2091         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2092         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2093         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2094         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2095         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2096         sport->context_saved = false;
2097 }
2098
2099 static void serial_imx_save_context(struct imx_port *sport)
2100 {
2101         /* Save necessary regs */
2102         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2103         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2104         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2105         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2106         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2107         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2108         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2109         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2110         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2111         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2112         sport->context_saved = true;
2113 }
2114
2115 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2116 {
2117         unsigned int val;
2118
2119         val = readl(sport->port.membase + UCR3);
2120         if (on)
2121                 val |= UCR3_AWAKEN;
2122         else
2123                 val &= ~UCR3_AWAKEN;
2124         writel(val, sport->port.membase + UCR3);
2125
2126         val = readl(sport->port.membase + UCR1);
2127         if (on)
2128                 val |= UCR1_RTSDEN;
2129         else
2130                 val &= ~UCR1_RTSDEN;
2131         writel(val, sport->port.membase + UCR1);
2132 }
2133
2134 static int imx_serial_port_suspend_noirq(struct device *dev)
2135 {
2136         struct platform_device *pdev = to_platform_device(dev);
2137         struct imx_port *sport = platform_get_drvdata(pdev);
2138         int ret;
2139
2140         ret = clk_enable(sport->clk_ipg);
2141         if (ret)
2142                 return ret;
2143
2144         serial_imx_save_context(sport);
2145
2146         clk_disable(sport->clk_ipg);
2147
2148         return 0;
2149 }
2150
2151 static int imx_serial_port_resume_noirq(struct device *dev)
2152 {
2153         struct platform_device *pdev = to_platform_device(dev);
2154         struct imx_port *sport = platform_get_drvdata(pdev);
2155         int ret;
2156
2157         ret = clk_enable(sport->clk_ipg);
2158         if (ret)
2159                 return ret;
2160
2161         serial_imx_restore_context(sport);
2162
2163         clk_disable(sport->clk_ipg);
2164
2165         return 0;
2166 }
2167
2168 static int imx_serial_port_suspend(struct device *dev)
2169 {
2170         struct platform_device *pdev = to_platform_device(dev);
2171         struct imx_port *sport = platform_get_drvdata(pdev);
2172
2173         /* enable wakeup from i.MX UART */
2174         serial_imx_enable_wakeup(sport, true);
2175
2176         uart_suspend_port(&imx_reg, &sport->port);
2177
2178         /* Needed to enable clock in suspend_noirq */
2179         return clk_prepare(sport->clk_ipg);
2180 }
2181
2182 static int imx_serial_port_resume(struct device *dev)
2183 {
2184         struct platform_device *pdev = to_platform_device(dev);
2185         struct imx_port *sport = platform_get_drvdata(pdev);
2186
2187         /* disable wakeup from i.MX UART */
2188         serial_imx_enable_wakeup(sport, false);
2189
2190         uart_resume_port(&imx_reg, &sport->port);
2191
2192         clk_unprepare(sport->clk_ipg);
2193
2194         return 0;
2195 }
2196
2197 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2198         .suspend_noirq = imx_serial_port_suspend_noirq,
2199         .resume_noirq = imx_serial_port_resume_noirq,
2200         .suspend = imx_serial_port_suspend,
2201         .resume = imx_serial_port_resume,
2202 };
2203
2204 static struct platform_driver serial_imx_driver = {
2205         .probe          = serial_imx_probe,
2206         .remove         = serial_imx_remove,
2207
2208         .id_table       = imx_uart_devtype,
2209         .driver         = {
2210                 .name   = "imx-uart",
2211                 .of_match_table = imx_uart_dt_ids,
2212                 .pm     = &imx_serial_port_pm_ops,
2213         },
2214 };
2215
2216 static int __init imx_serial_init(void)
2217 {
2218         int ret = uart_register_driver(&imx_reg);
2219
2220         if (ret)
2221                 return ret;
2222
2223         ret = platform_driver_register(&serial_imx_driver);
2224         if (ret != 0)
2225                 uart_unregister_driver(&imx_reg);
2226
2227         return ret;
2228 }
2229
2230 static void __exit imx_serial_exit(void)
2231 {
2232         platform_driver_unregister(&serial_imx_driver);
2233         uart_unregister_driver(&imx_reg);
2234 }
2235
2236 module_init(imx_serial_init);
2237 module_exit(imx_serial_exit);
2238
2239 MODULE_AUTHOR("Sascha Hauer");
2240 MODULE_DESCRIPTION("IMX generic serial port driver");
2241 MODULE_LICENSE("GPL");
2242 MODULE_ALIAS("platform:imx-uart");