drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 /* Register definitions */
  48 #define URXD0 0x0  /* Receiver Register */
  49 #define URTX0 0x40 /* Transmitter Register */
  50 #define UCR1  0x80 /* Control Register 1 */
  51 #define UCR2  0x84 /* Control Register 2 */
  52 #define UCR3  0x88 /* Control Register 3 */
  53 #define UCR4  0x8c /* Control Register 4 */
  54 #define UFCR  0x90 /* FIFO Control Register */
  55 #define USR1  0x94 /* Status Register 1 */
  56 #define USR2  0x98 /* Status Register 2 */
  57 #define UESC  0x9c /* Escape Character Register */
  58 #define UTIM  0xa0 /* Escape Timer Register */
  59 #define UBIR  0xa4 /* BRM Incremental Register */
  60 #define UBMR  0xa8 /* BRM Modulator Register */
  61 #define UBRC  0xac /* Baud Rate Count Register */
  62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  65
  66 /* UART Control Register Bit Fields.*/
  67 #define URXD_DUMMY_READ (1<<16)
  68 #define URXD_CHARRDY    (1<<15)
  69 #define URXD_ERR        (1<<14)
  70 #define URXD_OVRRUN     (1<<13)
  71 #define URXD_FRMERR     (1<<12)
  72 #define URXD_BRK        (1<<11)
  73 #define URXD_PRERR      (1<<10)
  74 #define URXD_RX_DATA    (0xFF<<0)
  75 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  76 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  77 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  78 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  80 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  81 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  82 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  83 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  84 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  85 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  86 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  88 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  89 #define UCR1_DOZE       (1<<1)  /* Doze */
  90 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  91 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  92 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  93 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  94 #define UCR2_CTS        (1<<12) /* Clear to send */
  95 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  96 #define UCR2_PREN       (1<<8)  /* Parity enable */
  97 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
  98 #define UCR2_STPB       (1<<6)  /* Stop */
  99 #define UCR2_WS         (1<<5)  /* Word size */
 100 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 101 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 102 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 103 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 104 #define UCR2_SRST       (1<<0)  /* SW reset */
 105 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 106 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 107 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 108 #define UCR3_DSR        (1<<10) /* Data set ready */
 109 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 110 #define UCR3_RI         (1<<8)  /* Ring indicator */
 111 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 112 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 113 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 114 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 115 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 116 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 117 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 118 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 119 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 120 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 121 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 122 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 123 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 124 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 125 #define UCR4_IRSC       (1<<5)  /* IR special case */
 126 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 127 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 128 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 129 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 130 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 131 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 132 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 133 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 134 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 135 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 136 #define USR1_RTSS       (1<<14) /* RTS pin status */
 137 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 138 #define USR1_RTSD       (1<<12) /* RTS delta */
 139 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 140 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 141 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 142 #define USR1_TIMEOUT    (1<<7)   /* Receive timeout interrupt status */
 143 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 144 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 145 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 146 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 147 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 148 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 149 #define USR2_IDLE        (1<<12) /* Idle condition */
 150 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 151 #define USR2_WAKE        (1<<7)  /* Wake */
 152 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 153 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 154 #define USR2_BRCD        (1<<2)  /* Break condition */
 155 #define USR2_ORE        (1<<1)   /* Overrun error */
 156 #define USR2_RDR        (1<<0)   /* Recv data ready */
 157 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 158 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 159 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 160 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 161 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 162 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 163 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 164
 165 /* We've been assigned a range on the "Low-density serial ports" major */
 166 #define SERIAL_IMX_MAJOR        207
 167 #define MINOR_START             16
 168 #define DEV_NAME                "ttymxc"
 169
 170 /*
 171  * This determines how often we check the modem status signals
 172  * for any change.  They generally aren't connected to an IRQ
 173  * so we have to poll them.  We also check immediately before
 174  * filling the TX fifo incase CTS has been dropped.
 175  */
 176 #define MCTRL_TIMEOUT   (250*HZ/1000)
 177
 178 #define DRIVER_NAME "IMX-uart"
 179
 180 #define UART_NR 8
 181
 182 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 183 enum imx_uart_type {
 184         IMX1_UART,
 185         IMX21_UART,
 186         IMX6Q_UART,
 187 };
 188
 189 /* device type dependent stuff */
 190 struct imx_uart_data {
 191         unsigned uts_reg;
 192         enum imx_uart_type devtype;
 193 };
 194
 195 struct imx_port {
 196         struct uart_port        port;
 197         struct timer_list       timer;
 198         unsigned int            old_status;
 199         unsigned int            have_rtscts:1;
 200         unsigned int            dte_mode:1;
 201         unsigned int            irda_inv_rx:1;
 202         unsigned int            irda_inv_tx:1;
 203         unsigned short          trcv_delay; /* transceiver delay */
 204         struct clk              *clk_ipg;
 205         struct clk              *clk_per;
 206         const struct imx_uart_data *devdata;
 207
 208         /* DMA fields */
 209         unsigned int            dma_is_inited:1;
 210         unsigned int            dma_is_enabled:1;
 211         unsigned int            dma_is_rxing:1;
 212         unsigned int            dma_is_txing:1;
 213         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 214         struct scatterlist      rx_sgl, tx_sgl[2];
 215         void                    *rx_buf;
 216         unsigned int            tx_bytes;
 217         unsigned int            dma_tx_nents;
 218         wait_queue_head_t       dma_wait;
 219         unsigned int            saved_reg[10];
 220 };
 221
 222 struct imx_port_ucrs {
 223         unsigned int    ucr1;
 224         unsigned int    ucr2;
 225         unsigned int    ucr3;
 226 };
 227
 228 static struct imx_uart_data imx_uart_devdata[] = {
 229         [IMX1_UART] = {
 230                 .uts_reg = IMX1_UTS,
 231                 .devtype = IMX1_UART,
 232         },
 233         [IMX21_UART] = {
 234                 .uts_reg = IMX21_UTS,
 235                 .devtype = IMX21_UART,
 236         },
 237         [IMX6Q_UART] = {
 238                 .uts_reg = IMX21_UTS,
 239                 .devtype = IMX6Q_UART,
 240         },
 241 };
 242
 243 static const struct platform_device_id imx_uart_devtype[] = {
 244         {
 245                 .name = "imx1-uart",
 246                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 247         }, {
 248                 .name = "imx21-uart",
 249                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 250         }, {
 251                 .name = "imx6q-uart",
 252                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 253         }, {
 254                 /* sentinel */
 255         }
 256 };
 257 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 258
 259 static const struct of_device_id imx_uart_dt_ids[] = {
 260         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 261         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 262         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 263         { /* sentinel */ }
 264 };
 265 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 266
 267 static inline unsigned uts_reg(struct imx_port *sport)
 268 {
 269         return sport->devdata->uts_reg;
 270 }
 271
 272 static inline int is_imx1_uart(struct imx_port *sport)
 273 {
 274         return sport->devdata->devtype == IMX1_UART;
 275 }
 276
 277 static inline int is_imx21_uart(struct imx_port *sport)
 278 {
 279         return sport->devdata->devtype == IMX21_UART;
 280 }
 281
 282 static inline int is_imx6q_uart(struct imx_port *sport)
 283 {
 284         return sport->devdata->devtype == IMX6Q_UART;
 285 }
 286 /*
 287  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 288  */
 289 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 290 static void imx_port_ucrs_save(struct uart_port *port,
 291                                struct imx_port_ucrs *ucr)
 292 {
 293         /* save control registers */
 294         ucr->ucr1 = readl(port->membase + UCR1);
 295         ucr->ucr2 = readl(port->membase + UCR2);
 296         ucr->ucr3 = readl(port->membase + UCR3);
 297 }
 298
 299 static void imx_port_ucrs_restore(struct uart_port *port,
 300                                   struct imx_port_ucrs *ucr)
 301 {
 302         /* restore control registers */
 303         writel(ucr->ucr1, port->membase + UCR1);
 304         writel(ucr->ucr2, port->membase + UCR2);
 305         writel(ucr->ucr3, port->membase + UCR3);
 306 }
 307 #endif
 308
 309 /*
 310  * Handle any change of modem status signal since we were last called.
 311  */
 312 static void imx_mctrl_check(struct imx_port *sport)
 313 {
 314         unsigned int status, changed;
 315
 316         status = sport->port.ops->get_mctrl(&sport->port);
 317         changed = status ^ sport->old_status;
 318
 319         if (changed == 0)
 320                 return;
 321
 322         sport->old_status = status;
 323
 324         if (changed & TIOCM_RI)
 325                 sport->port.icount.rng++;
 326         if (changed & TIOCM_DSR)
 327                 sport->port.icount.dsr++;
 328         if (changed & TIOCM_CAR)
 329                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 330         if (changed & TIOCM_CTS)
 331                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 332
 333         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 334 }
 335
 336 /*
 337  * This is our per-port timeout handler, for checking the
 338  * modem status signals.
 339  */
 340 static void imx_timeout(unsigned long data)
 341 {
 342         struct imx_port *sport = (struct imx_port *)data;
 343         unsigned long flags;
 344
 345         if (sport->port.state) {
 346                 spin_lock_irqsave(&sport->port.lock, flags);
 347                 imx_mctrl_check(sport);
 348                 spin_unlock_irqrestore(&sport->port.lock, flags);
 349
 350                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 351         }
 352 }
 353
 354 /*
 355  * interrupts disabled on entry
 356  */
 357 static void imx_stop_tx(struct uart_port *port)
 358 {
 359         struct imx_port *sport = (struct imx_port *)port;
 360         unsigned long temp;
 361
 362         /*
 363          * We are maybe in the SMP context, so if the DMA TX thread is running
 364          * on other cpu, we have to wait for it to finish.
 365          */
 366         if (sport->dma_is_enabled && sport->dma_is_txing)
 367                 return;
 368
 369         temp = readl(port->membase + UCR1);
 370         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 371
 372         /* in rs485 mode disable transmitter if shifter is empty */
 373         if (port->rs485.flags & SER_RS485_ENABLED &&
 374             readl(port->membase + USR2) & USR2_TXDC) {
 375                 temp = readl(port->membase + UCR2);
 376                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 377                         temp &= ~UCR2_CTS;
 378                 else
 379                         temp |= UCR2_CTS;
 380                 writel(temp, port->membase + UCR2);
 381
 382                 temp = readl(port->membase + UCR4);
 383                 temp &= ~UCR4_TCEN;
 384                 writel(temp, port->membase + UCR4);
 385         }
 386 }
 387
 388 /*
 389  * interrupts disabled on entry
 390  */
 391 static void imx_stop_rx(struct uart_port *port)
 392 {
 393         struct imx_port *sport = (struct imx_port *)port;
 394         unsigned long temp;
 395
 396         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 397                 if (sport->port.suspended) {
 398                         dmaengine_terminate_all(sport->dma_chan_rx);
 399                         sport->dma_is_rxing = 0;
 400                 } else {
 401                         return;
 402                 }
 403         }
 404
 405         temp = readl(sport->port.membase + UCR2);
 406         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 407
 408         /* disable the `Receiver Ready Interrrupt` */
 409         temp = readl(sport->port.membase + UCR1);
 410         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 411 }
 412
 413 /*
 414  * Set the modem control timer to fire immediately.
 415  */
 416 static void imx_enable_ms(struct uart_port *port)
 417 {
 418         struct imx_port *sport = (struct imx_port *)port;
 419
 420         mod_timer(&sport->timer, jiffies);
 421 }
 422
 423 static void imx_dma_tx(struct imx_port *sport);
 424 static inline void imx_transmit_buffer(struct imx_port *sport)
 425 {
 426         struct circ_buf *xmit = &sport->port.state->xmit;
 427         unsigned long temp;
 428
 429         if (sport->port.x_char) {
 430                 /* Send next char */
 431                 writel(sport->port.x_char, sport->port.membase + URTX0);
 432                 sport->port.icount.tx++;
 433                 sport->port.x_char = 0;
 434                 return;
 435         }
 436
 437         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 438                 imx_stop_tx(&sport->port);
 439                 return;
 440         }
 441
 442         if (sport->dma_is_enabled) {
 443                 /*
 444                  * We've just sent a X-char Ensure the TX DMA is enabled
 445                  * and the TX IRQ is disabled.
 446                  **/
 447                 temp = readl(sport->port.membase + UCR1);
 448                 temp &= ~UCR1_TXMPTYEN;
 449                 if (sport->dma_is_txing) {
 450                         temp |= UCR1_TDMAEN;
 451                         writel(temp, sport->port.membase + UCR1);
 452                 } else {
 453                         writel(temp, sport->port.membase + UCR1);
 454                         imx_dma_tx(sport);
 455                 }
 456         }
 457
 458         while (!uart_circ_empty(xmit) &&
 459                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 460                 /* send xmit->buf[xmit->tail]
 461                  * out the port here */
 462                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 463                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 464                 sport->port.icount.tx++;
 465         }
 466
 467         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 468                 uart_write_wakeup(&sport->port);
 469
 470         if (uart_circ_empty(xmit))
 471                 imx_stop_tx(&sport->port);
 472 }
 473
 474 static void dma_tx_callback(void *data)
 475 {
 476         struct imx_port *sport = data;
 477         struct scatterlist *sgl = &sport->tx_sgl[0];
 478         struct circ_buf *xmit = &sport->port.state->xmit;
 479         unsigned long flags;
 480         unsigned long temp;
 481
 482         spin_lock_irqsave(&sport->port.lock, flags);
 483
 484         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 485
 486         temp = readl(sport->port.membase + UCR1);
 487         temp &= ~UCR1_TDMAEN;
 488         writel(temp, sport->port.membase + UCR1);
 489
 490         /* update the stat */
 491         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 492         sport->port.icount.tx += sport->tx_bytes;
 493
 494         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 495
 496         sport->dma_is_txing = 0;
 497
 498         spin_unlock_irqrestore(&sport->port.lock, flags);
 499
 500         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 501                 uart_write_wakeup(&sport->port);
 502
 503         if (waitqueue_active(&sport->dma_wait)) {
 504                 wake_up(&sport->dma_wait);
 505                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 506                 return;
 507         }
 508
 509         spin_lock_irqsave(&sport->port.lock, flags);
 510         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 511                 imx_dma_tx(sport);
 512         spin_unlock_irqrestore(&sport->port.lock, flags);
 513 }
 514
 515 static void imx_dma_tx(struct imx_port *sport)
 516 {
 517         struct circ_buf *xmit = &sport->port.state->xmit;
 518         struct scatterlist *sgl = sport->tx_sgl;
 519         struct dma_async_tx_descriptor *desc;
 520         struct dma_chan *chan = sport->dma_chan_tx;
 521         struct device *dev = sport->port.dev;
 522         unsigned long temp;
 523         int ret;
 524
 525         if (sport->dma_is_txing)
 526                 return;
 527
 528         sport->tx_bytes = uart_circ_chars_pending(xmit);
 529
 530         if (xmit->tail < xmit->head) {
 531                 sport->dma_tx_nents = 1;
 532                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 533         } else {
 534                 sport->dma_tx_nents = 2;
 535                 sg_init_table(sgl, 2);
 536                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 537                                 UART_XMIT_SIZE - xmit->tail);
 538                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 539         }
 540
 541         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 542         if (ret == 0) {
 543                 dev_err(dev, "DMA mapping error for TX.\n");
 544                 return;
 545         }
 546         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 547                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 548         if (!desc) {
 549                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 550                              DMA_TO_DEVICE);
 551                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 552                 return;
 553         }
 554         desc->callback = dma_tx_callback;
 555         desc->callback_param = sport;
 556
 557         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 558                         uart_circ_chars_pending(xmit));
 559
 560         temp = readl(sport->port.membase + UCR1);
 561         temp |= UCR1_TDMAEN;
 562         writel(temp, sport->port.membase + UCR1);
 563
 564         /* fire it */
 565         sport->dma_is_txing = 1;
 566         dmaengine_submit(desc);
 567         dma_async_issue_pending(chan);
 568         return;
 569 }
 570
 571 /*
 572  * interrupts disabled on entry
 573  */
 574 static void imx_start_tx(struct uart_port *port)
 575 {
 576         struct imx_port *sport = (struct imx_port *)port;
 577         unsigned long temp;
 578
 579         if (port->rs485.flags & SER_RS485_ENABLED) {
 580                 /* enable transmitter and shifter empty irq */
 581                 temp = readl(port->membase + UCR2);
 582                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 583                         temp &= ~UCR2_CTS;
 584                 else
 585                         temp |= UCR2_CTS;
 586                 writel(temp, port->membase + UCR2);
 587
 588                 temp = readl(port->membase + UCR4);
 589                 temp |= UCR4_TCEN;
 590                 writel(temp, port->membase + UCR4);
 591         }
 592
 593         if (!sport->dma_is_enabled) {
 594                 temp = readl(sport->port.membase + UCR1);
 595                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 596         }
 597
 598         if (sport->dma_is_enabled) {
 599                 if (sport->port.x_char) {
 600                         /* We have X-char to send, so enable TX IRQ and
 601                          * disable TX DMA to let TX interrupt to send X-char */
 602                         temp = readl(sport->port.membase + UCR1);
 603                         temp &= ~UCR1_TDMAEN;
 604                         temp |= UCR1_TXMPTYEN;
 605                         writel(temp, sport->port.membase + UCR1);
 606                         return;
 607                 }
 608
 609                 if (!uart_circ_empty(&port->state->xmit) &&
 610                     !uart_tx_stopped(port))
 611                         imx_dma_tx(sport);
 612                 return;
 613         }
 614 }
 615
 616 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 617 {
 618         struct imx_port *sport = dev_id;
 619         unsigned int val;
 620         unsigned long flags;
 621
 622         spin_lock_irqsave(&sport->port.lock, flags);
 623
 624         writel(USR1_RTSD, sport->port.membase + USR1);
 625         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 626         uart_handle_cts_change(&sport->port, !!val);
 627         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 628
 629         spin_unlock_irqrestore(&sport->port.lock, flags);
 630         return IRQ_HANDLED;
 631 }
 632
 633 static irqreturn_t imx_txint(int irq, void *dev_id)
 634 {
 635         struct imx_port *sport = dev_id;
 636         unsigned long flags;
 637
 638         spin_lock_irqsave(&sport->port.lock, flags);
 639         imx_transmit_buffer(sport);
 640         spin_unlock_irqrestore(&sport->port.lock, flags);
 641         return IRQ_HANDLED;
 642 }
 643
 644 static irqreturn_t imx_rxint(int irq, void *dev_id)
 645 {
 646         struct imx_port *sport = dev_id;
 647         unsigned int rx, flg, ignored = 0;
 648         struct tty_port *port = &sport->port.state->port;
 649         unsigned long flags, temp;
 650
 651         spin_lock_irqsave(&sport->port.lock, flags);
 652
 653         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 654                 flg = TTY_NORMAL;
 655                 sport->port.icount.rx++;
 656
 657                 rx = readl(sport->port.membase + URXD0);
 658
 659                 temp = readl(sport->port.membase + USR2);
 660                 if (temp & USR2_BRCD) {
 661                         writel(USR2_BRCD, sport->port.membase + USR2);
 662                         if (uart_handle_break(&sport->port))
 663                                 continue;
 664                 }
 665
 666                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 667                         continue;
 668
 669                 if (unlikely(rx & URXD_ERR)) {
 670                         if (rx & URXD_BRK)
 671                                 sport->port.icount.brk++;
 672                         else if (rx & URXD_PRERR)
 673                                 sport->port.icount.parity++;
 674                         else if (rx & URXD_FRMERR)
 675                                 sport->port.icount.frame++;
 676                         if (rx & URXD_OVRRUN)
 677                                 sport->port.icount.overrun++;
 678
 679                         if (rx & sport->port.ignore_status_mask) {
 680                                 if (++ignored > 100)
 681                                         goto out;
 682                                 continue;
 683                         }
 684
 685                         rx &= (sport->port.read_status_mask | 0xFF);
 686
 687                         if (rx & URXD_BRK)
 688                                 flg = TTY_BREAK;
 689                         else if (rx & URXD_PRERR)
 690                                 flg = TTY_PARITY;
 691                         else if (rx & URXD_FRMERR)
 692                                 flg = TTY_FRAME;
 693                         if (rx & URXD_OVRRUN)
 694                                 flg = TTY_OVERRUN;
 695
 696 #ifdef SUPPORT_SYSRQ
 697                         sport->port.sysrq = 0;
 698 #endif
 699                 }
 700
 701                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 702                         goto out;
 703
 704                 if (tty_insert_flip_char(port, rx, flg) == 0)
 705                         sport->port.icount.buf_overrun++;
 706         }
 707
 708 out:
 709         spin_unlock_irqrestore(&sport->port.lock, flags);
 710         tty_flip_buffer_push(port);
 711         return IRQ_HANDLED;
 712 }
 713
 714 static int start_rx_dma(struct imx_port *sport);
 715 /*
 716  * If the RXFIFO is filled with some data, and then we
 717  * arise a DMA operation to receive them.
 718  */
 719 static void imx_dma_rxint(struct imx_port *sport)
 720 {
 721         unsigned long temp;
 722         unsigned long flags;
 723
 724         spin_lock_irqsave(&sport->port.lock, flags);
 725
 726         temp = readl(sport->port.membase + USR2);
 727         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 728                 sport->dma_is_rxing = 1;
 729
 730                 /* disable the `Recerver Ready Interrrupt` */
 731                 temp = readl(sport->port.membase + UCR1);
 732                 temp &= ~(UCR1_RRDYEN);
 733                 writel(temp, sport->port.membase + UCR1);
 734
 735                 /* tell the DMA to receive the data. */
 736                 start_rx_dma(sport);
 737         }
 738
 739         spin_unlock_irqrestore(&sport->port.lock, flags);
 740 }
 741
 742 static irqreturn_t imx_int(int irq, void *dev_id)
 743 {
 744         struct imx_port *sport = dev_id;
 745         unsigned int sts;
 746         unsigned int sts2;
 747
 748         sts = readl(sport->port.membase + USR1);
 749         sts2 = readl(sport->port.membase + USR2);
 750
 751         if (sts & USR1_RRDY) {
 752                 if (sport->dma_is_enabled)
 753                         imx_dma_rxint(sport);
 754                 else
 755                         imx_rxint(irq, dev_id);
 756         }
 757
 758         if ((sts & USR1_TRDY &&
 759              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 760             (sts2 & USR2_TXDC &&
 761              readl(sport->port.membase + UCR4) & UCR4_TCEN))
 762                 imx_txint(irq, dev_id);
 763
 764         if (sts & USR1_RTSD)
 765                 imx_rtsint(irq, dev_id);
 766
 767         if (sts & USR1_AWAKE)
 768                 writel(USR1_AWAKE, sport->port.membase + USR1);
 769
 770         if (sts2 & USR2_ORE) {
 771                 sport->port.icount.overrun++;
 772                 writel(USR2_ORE, sport->port.membase + USR2);
 773         }
 774
 775         return IRQ_HANDLED;
 776 }
 777
 778 /*
 779  * Return TIOCSER_TEMT when transmitter is not busy.
 780  */
 781 static unsigned int imx_tx_empty(struct uart_port *port)
 782 {
 783         struct imx_port *sport = (struct imx_port *)port;
 784         unsigned int ret;
 785
 786         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 787
 788         /* If the TX DMA is working, return 0. */
 789         if (sport->dma_is_enabled && sport->dma_is_txing)
 790                 ret = 0;
 791
 792         return ret;
 793 }
 794
 795 /*
 796  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 797  */
 798 static unsigned int imx_get_mctrl(struct uart_port *port)
 799 {
 800         struct imx_port *sport = (struct imx_port *)port;
 801         unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
 802
 803         if (readl(sport->port.membase + USR1) & USR1_RTSS)
 804                 tmp |= TIOCM_CTS;
 805
 806         if (readl(sport->port.membase + UCR2) & UCR2_CTS)
 807                 tmp |= TIOCM_RTS;
 808
 809         if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
 810                 tmp |= TIOCM_LOOP;
 811
 812         return tmp;
 813 }
 814
 815 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 816 {
 817         struct imx_port *sport = (struct imx_port *)port;
 818         unsigned long temp;
 819
 820         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 821                 temp = readl(sport->port.membase + UCR2);
 822                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 823                 if (mctrl & TIOCM_RTS)
 824                         temp |= UCR2_CTS | UCR2_CTSC;
 825                 writel(temp, sport->port.membase + UCR2);
 826         }
 827
 828         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 829         if (mctrl & TIOCM_LOOP)
 830                 temp |= UTS_LOOP;
 831         writel(temp, sport->port.membase + uts_reg(sport));
 832 }
 833
 834 /*
 835  * Interrupts always disabled.
 836  */
 837 static void imx_break_ctl(struct uart_port *port, int break_state)
 838 {
 839         struct imx_port *sport = (struct imx_port *)port;
 840         unsigned long flags, temp;
 841
 842         spin_lock_irqsave(&sport->port.lock, flags);
 843
 844         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 845
 846         if (break_state != 0)
 847                 temp |= UCR1_SNDBRK;
 848
 849         writel(temp, sport->port.membase + UCR1);
 850
 851         spin_unlock_irqrestore(&sport->port.lock, flags);
 852 }
 853
 854 #define TXTL 2 /* reset default */
 855 #define RXTL 1 /* reset default */
 856
 857 static void imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
 858 {
 859         unsigned int val;
 860
 861         /* set receiver / transmitter trigger level */
 862         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
 863         val |= TXTL << UFCR_TXTL_SHF | RXTL;
 864         writel(val, sport->port.membase + UFCR);
 865 }
 866
 867 #define RX_BUF_SIZE     (PAGE_SIZE)
 868 static void imx_rx_dma_done(struct imx_port *sport)
 869 {
 870         unsigned long temp;
 871         unsigned long flags;
 872
 873         spin_lock_irqsave(&sport->port.lock, flags);
 874
 875         /* Enable this interrupt when the RXFIFO is empty. */
 876         temp = readl(sport->port.membase + UCR1);
 877         temp |= UCR1_RRDYEN;
 878         writel(temp, sport->port.membase + UCR1);
 879
 880         sport->dma_is_rxing = 0;
 881
 882         /* Is the shutdown waiting for us? */
 883         if (waitqueue_active(&sport->dma_wait))
 884                 wake_up(&sport->dma_wait);
 885
 886         spin_unlock_irqrestore(&sport->port.lock, flags);
 887 }
 888
 889 /*
 890  * There are three kinds of RX DMA interrupts(such as in the MX6Q):
 891  *   [1] the RX DMA buffer is full.
 892  *   [2] the Aging timer expires(wait for 8 bytes long)
 893  *   [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
 894  *
 895  * The [2] is trigger when a character was been sitting in the FIFO
 896  * meanwhile [3] can wait for 32 bytes long when the RX line is
 897  * on IDLE state and RxFIFO is empty.
 898  */
 899 static void dma_rx_callback(void *data)
 900 {
 901         struct imx_port *sport = data;
 902         struct dma_chan *chan = sport->dma_chan_rx;
 903         struct scatterlist *sgl = &sport->rx_sgl;
 904         struct tty_port *port = &sport->port.state->port;
 905         struct dma_tx_state state;
 906         enum dma_status status;
 907         unsigned int count;
 908
 909         /* unmap it first */
 910         dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
 911
 912         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 913         count = RX_BUF_SIZE - state.residue;
 914
 915         if (readl(sport->port.membase + USR2) & USR2_IDLE) {
 916                 /* In condition [3] the SDMA counted up too early */
 917                 count--;
 918
 919                 writel(USR2_IDLE, sport->port.membase + USR2);
 920         }
 921
 922         dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
 923
 924         if (count) {
 925                 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 926                         int bytes = tty_insert_flip_string(port, sport->rx_buf,
 927                                         count);
 928
 929                         if (bytes != count)
 930                                 sport->port.icount.buf_overrun++;
 931                 }
 932                 tty_flip_buffer_push(port);
 933
 934                 start_rx_dma(sport);
 935         } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
 936                 /*
 937                  * start rx_dma directly once data in RXFIFO, more efficient
 938                  * than before:
 939                  *      1. call imx_rx_dma_done to stop dma if no data received
 940                  *      2. wait next  RDR interrupt to start dma transfer.
 941                  */
 942                 start_rx_dma(sport);
 943         } else {
 944                 /*
 945                  * stop dma to prevent too many IDLE event trigged if no data
 946                  * in RXFIFO
 947                  */
 948                 imx_rx_dma_done(sport);
 949         }
 950 }
 951
 952 static int start_rx_dma(struct imx_port *sport)
 953 {
 954         struct scatterlist *sgl = &sport->rx_sgl;
 955         struct dma_chan *chan = sport->dma_chan_rx;
 956         struct device *dev = sport->port.dev;
 957         struct dma_async_tx_descriptor *desc;
 958         int ret;
 959
 960         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
 961         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
 962         if (ret == 0) {
 963                 dev_err(dev, "DMA mapping error for RX.\n");
 964                 return -EINVAL;
 965         }
 966         desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
 967                                         DMA_PREP_INTERRUPT);
 968         if (!desc) {
 969                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
 970                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
 971                 return -EINVAL;
 972         }
 973         desc->callback = dma_rx_callback;
 974         desc->callback_param = sport;
 975
 976         dev_dbg(dev, "RX: prepare for the DMA.\n");
 977         dmaengine_submit(desc);
 978         dma_async_issue_pending(chan);
 979         return 0;
 980 }
 981
 982 static void imx_uart_dma_exit(struct imx_port *sport)
 983 {
 984         if (sport->dma_chan_rx) {
 985                 dma_release_channel(sport->dma_chan_rx);
 986                 sport->dma_chan_rx = NULL;
 987
 988                 kfree(sport->rx_buf);
 989                 sport->rx_buf = NULL;
 990         }
 991
 992         if (sport->dma_chan_tx) {
 993                 dma_release_channel(sport->dma_chan_tx);
 994                 sport->dma_chan_tx = NULL;
 995         }
 996
 997         sport->dma_is_inited = 0;
 998 }
 999
1000 static int imx_uart_dma_init(struct imx_port *sport)
1001 {
1002         struct dma_slave_config slave_config = {};
1003         struct device *dev = sport->port.dev;
1004         int ret;
1005
1006         /* Prepare for RX : */
1007         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1008         if (!sport->dma_chan_rx) {
1009                 dev_dbg(dev, "cannot get the DMA channel.\n");
1010                 ret = -EINVAL;
1011                 goto err;
1012         }
1013
1014         slave_config.direction = DMA_DEV_TO_MEM;
1015         slave_config.src_addr = sport->port.mapbase + URXD0;
1016         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1017         slave_config.src_maxburst = RXTL;
1018         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1019         if (ret) {
1020                 dev_err(dev, "error in RX dma configuration.\n");
1021                 goto err;
1022         }
1023
1024         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1025         if (!sport->rx_buf) {
1026                 ret = -ENOMEM;
1027                 goto err;
1028         }
1029
1030         /* Prepare for TX : */
1031         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1032         if (!sport->dma_chan_tx) {
1033                 dev_err(dev, "cannot get the TX DMA channel!\n");
1034                 ret = -EINVAL;
1035                 goto err;
1036         }
1037
1038         slave_config.direction = DMA_MEM_TO_DEV;
1039         slave_config.dst_addr = sport->port.mapbase + URTX0;
1040         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1041         slave_config.dst_maxburst = TXTL;
1042         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1043         if (ret) {
1044                 dev_err(dev, "error in TX dma configuration.");
1045                 goto err;
1046         }
1047
1048         sport->dma_is_inited = 1;
1049
1050         return 0;
1051 err:
1052         imx_uart_dma_exit(sport);
1053         return ret;
1054 }
1055
1056 static void imx_enable_dma(struct imx_port *sport)
1057 {
1058         unsigned long temp;
1059
1060         init_waitqueue_head(&sport->dma_wait);
1061
1062         /* set UCR1 */
1063         temp = readl(sport->port.membase + UCR1);
1064         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1065                 /* wait for 32 idle frames for IDDMA interrupt */
1066                 UCR1_ICD_REG(3);
1067         writel(temp, sport->port.membase + UCR1);
1068
1069         /* set UCR4 */
1070         temp = readl(sport->port.membase + UCR4);
1071         temp |= UCR4_IDDMAEN;
1072         writel(temp, sport->port.membase + UCR4);
1073
1074         sport->dma_is_enabled = 1;
1075 }
1076
1077 static void imx_disable_dma(struct imx_port *sport)
1078 {
1079         unsigned long temp;
1080
1081         /* clear UCR1 */
1082         temp = readl(sport->port.membase + UCR1);
1083         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1084         writel(temp, sport->port.membase + UCR1);
1085
1086         /* clear UCR2 */
1087         temp = readl(sport->port.membase + UCR2);
1088         temp &= ~(UCR2_CTSC | UCR2_CTS);
1089         writel(temp, sport->port.membase + UCR2);
1090
1091         /* clear UCR4 */
1092         temp = readl(sport->port.membase + UCR4);
1093         temp &= ~UCR4_IDDMAEN;
1094         writel(temp, sport->port.membase + UCR4);
1095
1096         sport->dma_is_enabled = 0;
1097 }
1098
1099 /* half the RX buffer size */
1100 #define CTSTL 16
1101
1102 static int imx_startup(struct uart_port *port)
1103 {
1104         struct imx_port *sport = (struct imx_port *)port;
1105         int retval, i;
1106         unsigned long flags, temp;
1107
1108         retval = clk_prepare_enable(sport->clk_per);
1109         if (retval)
1110                 return retval;
1111         retval = clk_prepare_enable(sport->clk_ipg);
1112         if (retval) {
1113                 clk_disable_unprepare(sport->clk_per);
1114                 return retval;
1115         }
1116
1117         imx_setup_ufcr(sport, 0);
1118
1119         /* disable the DREN bit (Data Ready interrupt enable) before
1120          * requesting IRQs
1121          */
1122         temp = readl(sport->port.membase + UCR4);
1123
1124         /* set the trigger level for CTS */
1125         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1126         temp |= CTSTL << UCR4_CTSTL_SHF;
1127
1128         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1129
1130         spin_lock_irqsave(&sport->port.lock, flags);
1131         /* Reset fifo's and state machines */
1132         i = 100;
1133
1134         temp = readl(sport->port.membase + UCR2);
1135         temp &= ~UCR2_SRST;
1136         writel(temp, sport->port.membase + UCR2);
1137
1138         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1139                 udelay(1);
1140
1141         /*
1142          * Finally, clear and enable interrupts
1143          */
1144         writel(USR1_RTSD, sport->port.membase + USR1);
1145         writel(USR2_ORE, sport->port.membase + USR2);
1146
1147         temp = readl(sport->port.membase + UCR1);
1148         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1149
1150         writel(temp, sport->port.membase + UCR1);
1151
1152         temp = readl(sport->port.membase + UCR4);
1153         temp |= UCR4_OREN;
1154         writel(temp, sport->port.membase + UCR4);
1155
1156         temp = readl(sport->port.membase + UCR2);
1157         temp |= (UCR2_RXEN | UCR2_TXEN);
1158         if (!sport->have_rtscts)
1159                 temp |= UCR2_IRTS;
1160         writel(temp, sport->port.membase + UCR2);
1161
1162         if (!is_imx1_uart(sport)) {
1163                 temp = readl(sport->port.membase + UCR3);
1164                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1165                 writel(temp, sport->port.membase + UCR3);
1166         }
1167
1168         /*
1169          * Enable modem status interrupts
1170          */
1171         imx_enable_ms(&sport->port);
1172         spin_unlock_irqrestore(&sport->port.lock, flags);
1173
1174         return 0;
1175 }
1176
1177 static void imx_shutdown(struct uart_port *port)
1178 {
1179         struct imx_port *sport = (struct imx_port *)port;
1180         unsigned long temp;
1181         unsigned long flags;
1182
1183         if (sport->dma_is_enabled) {
1184                 int ret;
1185
1186                 /* We have to wait for the DMA to finish. */
1187                 ret = wait_event_interruptible(sport->dma_wait,
1188                         !sport->dma_is_rxing && !sport->dma_is_txing);
1189                 if (ret != 0) {
1190                         sport->dma_is_rxing = 0;
1191                         sport->dma_is_txing = 0;
1192                         dmaengine_terminate_all(sport->dma_chan_tx);
1193                         dmaengine_terminate_all(sport->dma_chan_rx);
1194                 }
1195                 spin_lock_irqsave(&sport->port.lock, flags);
1196                 imx_stop_tx(port);
1197                 imx_stop_rx(port);
1198                 imx_disable_dma(sport);
1199                 spin_unlock_irqrestore(&sport->port.lock, flags);
1200                 imx_uart_dma_exit(sport);
1201         }
1202
1203         spin_lock_irqsave(&sport->port.lock, flags);
1204         temp = readl(sport->port.membase + UCR2);
1205         temp &= ~(UCR2_TXEN);
1206         writel(temp, sport->port.membase + UCR2);
1207         spin_unlock_irqrestore(&sport->port.lock, flags);
1208
1209         /*
1210          * Stop our timer.
1211          */
1212         del_timer_sync(&sport->timer);
1213
1214         /*
1215          * Disable all interrupts, port and break condition.
1216          */
1217
1218         spin_lock_irqsave(&sport->port.lock, flags);
1219         temp = readl(sport->port.membase + UCR1);
1220         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1221
1222         writel(temp, sport->port.membase + UCR1);
1223         spin_unlock_irqrestore(&sport->port.lock, flags);
1224
1225         clk_disable_unprepare(sport->clk_per);
1226         clk_disable_unprepare(sport->clk_ipg);
1227 }
1228
1229 static void imx_flush_buffer(struct uart_port *port)
1230 {
1231         struct imx_port *sport = (struct imx_port *)port;
1232         struct scatterlist *sgl = &sport->tx_sgl[0];
1233         unsigned long temp;
1234         int i = 100, ubir, ubmr, uts;
1235
1236         if (!sport->dma_chan_tx)
1237                 return;
1238
1239         sport->tx_bytes = 0;
1240         dmaengine_terminate_all(sport->dma_chan_tx);
1241         if (sport->dma_is_txing) {
1242                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1243                              DMA_TO_DEVICE);
1244                 temp = readl(sport->port.membase + UCR1);
1245                 temp &= ~UCR1_TDMAEN;
1246                 writel(temp, sport->port.membase + UCR1);
1247                 sport->dma_is_txing = false;
1248         }
1249
1250         /*
1251          * According to the Reference Manual description of the UART SRST bit:
1252          * "Reset the transmit and receive state machines,
1253          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1254          * and UTS[6-3]". As we don't need to restore the old values from
1255          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1256          */
1257         ubir = readl(sport->port.membase + UBIR);
1258         ubmr = readl(sport->port.membase + UBMR);
1259         uts = readl(sport->port.membase + IMX21_UTS);
1260
1261         temp = readl(sport->port.membase + UCR2);
1262         temp &= ~UCR2_SRST;
1263         writel(temp, sport->port.membase + UCR2);
1264
1265         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1266                 udelay(1);
1267
1268         /* Restore the registers */
1269         writel(ubir, sport->port.membase + UBIR);
1270         writel(ubmr, sport->port.membase + UBMR);
1271         writel(uts, sport->port.membase + IMX21_UTS);
1272 }
1273
1274 static void
1275 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1276                    struct ktermios *old)
1277 {
1278         struct imx_port *sport = (struct imx_port *)port;
1279         unsigned long flags;
1280         unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1281         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1282         unsigned int div, ufcr;
1283         unsigned long num, denom;
1284         uint64_t tdiv64;
1285
1286         /*
1287          * We only support CS7 and CS8.
1288          */
1289         while ((termios->c_cflag & CSIZE) != CS7 &&
1290                (termios->c_cflag & CSIZE) != CS8) {
1291                 termios->c_cflag &= ~CSIZE;
1292                 termios->c_cflag |= old_csize;
1293                 old_csize = CS8;
1294         }
1295
1296         if ((termios->c_cflag & CSIZE) == CS8)
1297                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1298         else
1299                 ucr2 = UCR2_SRST | UCR2_IRTS;
1300
1301         if (termios->c_cflag & CRTSCTS) {
1302                 if (sport->have_rtscts) {
1303                         ucr2 &= ~UCR2_IRTS;
1304
1305                         if (port->rs485.flags & SER_RS485_ENABLED) {
1306                                 /*
1307                                  * RTS is mandatory for rs485 operation, so keep
1308                                  * it under manual control and keep transmitter
1309                                  * disabled.
1310                                  */
1311                                 if (!(port->rs485.flags &
1312                                       SER_RS485_RTS_AFTER_SEND))
1313                                         ucr2 |= UCR2_CTS;
1314                         } else {
1315                                 ucr2 |= UCR2_CTSC;
1316                         }
1317
1318                         /* Can we enable the DMA support? */
1319                         if (is_imx6q_uart(sport) && !uart_console(port)
1320                                 && !sport->dma_is_inited)
1321                                 imx_uart_dma_init(sport);
1322                 } else {
1323                         termios->c_cflag &= ~CRTSCTS;
1324                 }
1325         } else if (port->rs485.flags & SER_RS485_ENABLED)
1326                 /* disable transmitter */
1327                 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1328                         ucr2 |= UCR2_CTS;
1329
1330         if (termios->c_cflag & CSTOPB)
1331                 ucr2 |= UCR2_STPB;
1332         if (termios->c_cflag & PARENB) {
1333                 ucr2 |= UCR2_PREN;
1334                 if (termios->c_cflag & PARODD)
1335                         ucr2 |= UCR2_PROE;
1336         }
1337
1338         del_timer_sync(&sport->timer);
1339
1340         /*
1341          * Ask the core to calculate the divisor for us.
1342          */
1343         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1344         quot = uart_get_divisor(port, baud);
1345
1346         spin_lock_irqsave(&sport->port.lock, flags);
1347
1348         sport->port.read_status_mask = 0;
1349         if (termios->c_iflag & INPCK)
1350                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1351         if (termios->c_iflag & (BRKINT | PARMRK))
1352                 sport->port.read_status_mask |= URXD_BRK;
1353
1354         /*
1355          * Characters to ignore
1356          */
1357         sport->port.ignore_status_mask = 0;
1358         if (termios->c_iflag & IGNPAR)
1359                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1360         if (termios->c_iflag & IGNBRK) {
1361                 sport->port.ignore_status_mask |= URXD_BRK;
1362                 /*
1363                  * If we're ignoring parity and break indicators,
1364                  * ignore overruns too (for real raw support).
1365                  */
1366                 if (termios->c_iflag & IGNPAR)
1367                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1368         }
1369
1370         if ((termios->c_cflag & CREAD) == 0)
1371                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1372
1373         /*
1374          * Update the per-port timeout.
1375          */
1376         uart_update_timeout(port, termios->c_cflag, baud);
1377
1378         /*
1379          * disable interrupts and drain transmitter
1380          */
1381         old_ucr1 = readl(sport->port.membase + UCR1);
1382         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1383                         sport->port.membase + UCR1);
1384
1385         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1386                 barrier();
1387
1388         /* then, disable everything */
1389         old_txrxen = readl(sport->port.membase + UCR2);
1390         writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1391                         sport->port.membase + UCR2);
1392         old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1393
1394         /* custom-baudrate handling */
1395         div = sport->port.uartclk / (baud * 16);
1396         if (baud == 38400 && quot != div)
1397                 baud = sport->port.uartclk / (quot * 16);
1398
1399         div = sport->port.uartclk / (baud * 16);
1400         if (div > 7)
1401                 div = 7;
1402         if (!div)
1403                 div = 1;
1404
1405         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1406                 1 << 16, 1 << 16, &num, &denom);
1407
1408         tdiv64 = sport->port.uartclk;
1409         tdiv64 *= num;
1410         do_div(tdiv64, denom * 16 * div);
1411         tty_termios_encode_baud_rate(termios,
1412                                 (speed_t)tdiv64, (speed_t)tdiv64);
1413
1414         num -= 1;
1415         denom -= 1;
1416
1417         ufcr = readl(sport->port.membase + UFCR);
1418         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1419         if (sport->dte_mode)
1420                 ufcr |= UFCR_DCEDTE;
1421         writel(ufcr, sport->port.membase + UFCR);
1422
1423         writel(num, sport->port.membase + UBIR);
1424         writel(denom, sport->port.membase + UBMR);
1425
1426         if (!is_imx1_uart(sport))
1427                 writel(sport->port.uartclk / div / 1000,
1428                                 sport->port.membase + IMX21_ONEMS);
1429
1430         writel(old_ucr1, sport->port.membase + UCR1);
1431
1432         /* set the parity, stop bits and data size */
1433         writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1434
1435         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1436                 imx_enable_ms(&sport->port);
1437
1438         if (sport->dma_is_inited && !sport->dma_is_enabled)
1439                 imx_enable_dma(sport);
1440         spin_unlock_irqrestore(&sport->port.lock, flags);
1441 }
1442
1443 static const char *imx_type(struct uart_port *port)
1444 {
1445         struct imx_port *sport = (struct imx_port *)port;
1446
1447         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1448 }
1449
1450 /*
1451  * Configure/autoconfigure the port.
1452  */
1453 static void imx_config_port(struct uart_port *port, int flags)
1454 {
1455         struct imx_port *sport = (struct imx_port *)port;
1456
1457         if (flags & UART_CONFIG_TYPE)
1458                 sport->port.type = PORT_IMX;
1459 }
1460
1461 /*
1462  * Verify the new serial_struct (for TIOCSSERIAL).
1463  * The only change we allow are to the flags and type, and
1464  * even then only between PORT_IMX and PORT_UNKNOWN
1465  */
1466 static int
1467 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1468 {
1469         struct imx_port *sport = (struct imx_port *)port;
1470         int ret = 0;
1471
1472         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1473                 ret = -EINVAL;
1474         if (sport->port.irq != ser->irq)
1475                 ret = -EINVAL;
1476         if (ser->io_type != UPIO_MEM)
1477                 ret = -EINVAL;
1478         if (sport->port.uartclk / 16 != ser->baud_base)
1479                 ret = -EINVAL;
1480         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1481                 ret = -EINVAL;
1482         if (sport->port.iobase != ser->port)
1483                 ret = -EINVAL;
1484         if (ser->hub6 != 0)
1485                 ret = -EINVAL;
1486         return ret;
1487 }
1488
1489 #if defined(CONFIG_CONSOLE_POLL)
1490
1491 static int imx_poll_init(struct uart_port *port)
1492 {
1493         struct imx_port *sport = (struct imx_port *)port;
1494         unsigned long flags;
1495         unsigned long temp;
1496         int retval;
1497
1498         retval = clk_prepare_enable(sport->clk_ipg);
1499         if (retval)
1500                 return retval;
1501         retval = clk_prepare_enable(sport->clk_per);
1502         if (retval)
1503                 clk_disable_unprepare(sport->clk_ipg);
1504
1505         imx_setup_ufcr(sport, 0);
1506
1507         spin_lock_irqsave(&sport->port.lock, flags);
1508
1509         temp = readl(sport->port.membase + UCR1);
1510         if (is_imx1_uart(sport))
1511                 temp |= IMX1_UCR1_UARTCLKEN;
1512         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1513         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1514         writel(temp, sport->port.membase + UCR1);
1515
1516         temp = readl(sport->port.membase + UCR2);
1517         temp |= UCR2_RXEN;
1518         writel(temp, sport->port.membase + UCR2);
1519
1520         spin_unlock_irqrestore(&sport->port.lock, flags);
1521
1522         return 0;
1523 }
1524
1525 static int imx_poll_get_char(struct uart_port *port)
1526 {
1527         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1528                 return NO_POLL_CHAR;
1529
1530         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1531 }
1532
1533 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1534 {
1535         unsigned int status;
1536
1537         /* drain */
1538         do {
1539                 status = readl_relaxed(port->membase + USR1);
1540         } while (~status & USR1_TRDY);
1541
1542         /* write */
1543         writel_relaxed(c, port->membase + URTX0);
1544
1545         /* flush */
1546         do {
1547                 status = readl_relaxed(port->membase + USR2);
1548         } while (~status & USR2_TXDC);
1549 }
1550 #endif
1551
1552 static int imx_rs485_config(struct uart_port *port,
1553                             struct serial_rs485 *rs485conf)
1554 {
1555         struct imx_port *sport = (struct imx_port *)port;
1556
1557         /* unimplemented */
1558         rs485conf->delay_rts_before_send = 0;
1559         rs485conf->delay_rts_after_send = 0;
1560         rs485conf->flags |= SER_RS485_RX_DURING_TX;
1561
1562         /* RTS is required to control the transmitter */
1563         if (!sport->have_rtscts)
1564                 rs485conf->flags &= ~SER_RS485_ENABLED;
1565
1566         if (rs485conf->flags & SER_RS485_ENABLED) {
1567                 unsigned long temp;
1568
1569                 /* disable transmitter */
1570                 temp = readl(sport->port.membase + UCR2);
1571                 temp &= ~UCR2_CTSC;
1572                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1573                         temp &= ~UCR2_CTS;
1574                 else
1575                         temp |= UCR2_CTS;
1576                 writel(temp, sport->port.membase + UCR2);
1577         }
1578
1579         port->rs485 = *rs485conf;
1580
1581         return 0;
1582 }
1583
1584 static struct uart_ops imx_pops = {
1585         .tx_empty       = imx_tx_empty,
1586         .set_mctrl      = imx_set_mctrl,
1587         .get_mctrl      = imx_get_mctrl,
1588         .stop_tx        = imx_stop_tx,
1589         .start_tx       = imx_start_tx,
1590         .stop_rx        = imx_stop_rx,
1591         .enable_ms      = imx_enable_ms,
1592         .break_ctl      = imx_break_ctl,
1593         .startup        = imx_startup,
1594         .shutdown       = imx_shutdown,
1595         .flush_buffer   = imx_flush_buffer,
1596         .set_termios    = imx_set_termios,
1597         .type           = imx_type,
1598         .config_port    = imx_config_port,
1599         .verify_port    = imx_verify_port,
1600 #if defined(CONFIG_CONSOLE_POLL)
1601         .poll_init      = imx_poll_init,
1602         .poll_get_char  = imx_poll_get_char,
1603         .poll_put_char  = imx_poll_put_char,
1604 #endif
1605 };
1606
1607 static struct imx_port *imx_ports[UART_NR];
1608
1609 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1610 static void imx_console_putchar(struct uart_port *port, int ch)
1611 {
1612         struct imx_port *sport = (struct imx_port *)port;
1613
1614         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1615                 barrier();
1616
1617         writel(ch, sport->port.membase + URTX0);
1618 }
1619
1620 /*
1621  * Interrupts are disabled on entering
1622  */
1623 static void
1624 imx_console_write(struct console *co, const char *s, unsigned int count)
1625 {
1626         struct imx_port *sport = imx_ports[co->index];
1627         struct imx_port_ucrs old_ucr;
1628         unsigned int ucr1;
1629         unsigned long flags = 0;
1630         int locked = 1;
1631         int retval;
1632
1633         retval = clk_prepare_enable(sport->clk_per);
1634         if (retval)
1635                 return;
1636         retval = clk_prepare_enable(sport->clk_ipg);
1637         if (retval) {
1638                 clk_disable_unprepare(sport->clk_per);
1639                 return;
1640         }
1641
1642         if (sport->port.sysrq)
1643                 locked = 0;
1644         else if (oops_in_progress)
1645                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1646         else
1647                 spin_lock_irqsave(&sport->port.lock, flags);
1648
1649         /*
1650          *      First, save UCR1/2/3 and then disable interrupts
1651          */
1652         imx_port_ucrs_save(&sport->port, &old_ucr);
1653         ucr1 = old_ucr.ucr1;
1654
1655         if (is_imx1_uart(sport))
1656                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1657         ucr1 |= UCR1_UARTEN;
1658         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1659
1660         writel(ucr1, sport->port.membase + UCR1);
1661
1662         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1663
1664         uart_console_write(&sport->port, s, count, imx_console_putchar);
1665
1666         /*
1667          *      Finally, wait for transmitter to become empty
1668          *      and restore UCR1/2/3
1669          */
1670         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1671
1672         imx_port_ucrs_restore(&sport->port, &old_ucr);
1673
1674         if (locked)
1675                 spin_unlock_irqrestore(&sport->port.lock, flags);
1676
1677         clk_disable_unprepare(sport->clk_ipg);
1678         clk_disable_unprepare(sport->clk_per);
1679 }
1680
1681 /*
1682  * If the port was already initialised (eg, by a boot loader),
1683  * try to determine the current setup.
1684  */
1685 static void __init
1686 imx_console_get_options(struct imx_port *sport, int *baud,
1687                            int *parity, int *bits)
1688 {
1689
1690         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1691                 /* ok, the port was enabled */
1692                 unsigned int ucr2, ubir, ubmr, uartclk;
1693                 unsigned int baud_raw;
1694                 unsigned int ucfr_rfdiv;
1695
1696                 ucr2 = readl(sport->port.membase + UCR2);
1697
1698                 *parity = 'n';
1699                 if (ucr2 & UCR2_PREN) {
1700                         if (ucr2 & UCR2_PROE)
1701                                 *parity = 'o';
1702                         else
1703                                 *parity = 'e';
1704                 }
1705
1706                 if (ucr2 & UCR2_WS)
1707                         *bits = 8;
1708                 else
1709                         *bits = 7;
1710
1711                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1712                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1713
1714                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1715                 if (ucfr_rfdiv == 6)
1716                         ucfr_rfdiv = 7;
1717                 else
1718                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1719
1720                 uartclk = clk_get_rate(sport->clk_per);
1721                 uartclk /= ucfr_rfdiv;
1722
1723                 {       /*
1724                          * The next code provides exact computation of
1725                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1726                          * without need of float support or long long division,
1727                          * which would be required to prevent 32bit arithmetic overflow
1728                          */
1729                         unsigned int mul = ubir + 1;
1730                         unsigned int div = 16 * (ubmr + 1);
1731                         unsigned int rem = uartclk % div;
1732
1733                         baud_raw = (uartclk / div) * mul;
1734                         baud_raw += (rem * mul + div / 2) / div;
1735                         *baud = (baud_raw + 50) / 100 * 100;
1736                 }
1737
1738                 if (*baud != baud_raw)
1739                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1740                                 baud_raw, *baud);
1741         }
1742 }
1743
1744 static int __init
1745 imx_console_setup(struct console *co, char *options)
1746 {
1747         struct imx_port *sport;
1748         int baud = 9600;
1749         int bits = 8;
1750         int parity = 'n';
1751         int flow = 'n';
1752         int retval;
1753
1754         /*
1755          * Check whether an invalid uart number has been specified, and
1756          * if so, search for the first available port that does have
1757          * console support.
1758          */
1759         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1760                 co->index = 0;
1761         sport = imx_ports[co->index];
1762         if (sport == NULL)
1763                 return -ENODEV;
1764
1765         /* For setting the registers, we only need to enable the ipg clock. */
1766         retval = clk_prepare_enable(sport->clk_ipg);
1767         if (retval)
1768                 goto error_console;
1769
1770         if (options)
1771                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1772         else
1773                 imx_console_get_options(sport, &baud, &parity, &bits);
1774
1775         imx_setup_ufcr(sport, 0);
1776
1777         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1778
1779         clk_disable_unprepare(sport->clk_ipg);
1780
1781 error_console:
1782         return retval;
1783 }
1784
1785 static struct uart_driver imx_reg;
1786 static struct console imx_console = {
1787         .name           = DEV_NAME,
1788         .write          = imx_console_write,
1789         .device         = uart_console_device,
1790         .setup          = imx_console_setup,
1791         .flags          = CON_PRINTBUFFER,
1792         .index          = -1,
1793         .data           = &imx_reg,
1794 };
1795
1796 #define IMX_CONSOLE     &imx_console
1797 #else
1798 #define IMX_CONSOLE     NULL
1799 #endif
1800
1801 static struct uart_driver imx_reg = {
1802         .owner          = THIS_MODULE,
1803         .driver_name    = DRIVER_NAME,
1804         .dev_name       = DEV_NAME,
1805         .major          = SERIAL_IMX_MAJOR,
1806         .minor          = MINOR_START,
1807         .nr             = ARRAY_SIZE(imx_ports),
1808         .cons           = IMX_CONSOLE,
1809 };
1810
1811 #ifdef CONFIG_OF
1812 /*
1813  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1814  * could successfully get all information from dt or a negative errno.
1815  */
1816 static int serial_imx_probe_dt(struct imx_port *sport,
1817                 struct platform_device *pdev)
1818 {
1819         struct device_node *np = pdev->dev.of_node;
1820         const struct of_device_id *of_id =
1821                         of_match_device(imx_uart_dt_ids, &pdev->dev);
1822         int ret;
1823
1824         if (!np)
1825                 /* no device tree device */
1826                 return 1;
1827
1828         ret = of_alias_get_id(np, "serial");
1829         if (ret < 0) {
1830                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1831                 return ret;
1832         }
1833         sport->port.line = ret;
1834
1835         if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1836                 sport->have_rtscts = 1;
1837
1838         if (of_get_property(np, "fsl,dte-mode", NULL))
1839                 sport->dte_mode = 1;
1840
1841         sport->devdata = of_id->data;
1842
1843         return 0;
1844 }
1845 #else
1846 static inline int serial_imx_probe_dt(struct imx_port *sport,
1847                 struct platform_device *pdev)
1848 {
1849         return 1;
1850 }
1851 #endif
1852
1853 static void serial_imx_probe_pdata(struct imx_port *sport,
1854                 struct platform_device *pdev)
1855 {
1856         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1857
1858         sport->port.line = pdev->id;
1859         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
1860
1861         if (!pdata)
1862                 return;
1863
1864         if (pdata->flags & IMXUART_HAVE_RTSCTS)
1865                 sport->have_rtscts = 1;
1866 }
1867
1868 static int serial_imx_probe(struct platform_device *pdev)
1869 {
1870         struct imx_port *sport;
1871         void __iomem *base;
1872         int ret = 0, reg;
1873         struct resource *res;
1874         int txirq, rxirq, rtsirq;
1875
1876         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1877         if (!sport)
1878                 return -ENOMEM;
1879
1880         ret = serial_imx_probe_dt(sport, pdev);
1881         if (ret > 0)
1882                 serial_imx_probe_pdata(sport, pdev);
1883         else if (ret < 0)
1884                 return ret;
1885
1886         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1887         base = devm_ioremap_resource(&pdev->dev, res);
1888         if (IS_ERR(base))
1889                 return PTR_ERR(base);
1890
1891         rxirq = platform_get_irq(pdev, 0);
1892         txirq = platform_get_irq(pdev, 1);
1893         rtsirq = platform_get_irq(pdev, 2);
1894
1895         sport->port.dev = &pdev->dev;
1896         sport->port.mapbase = res->start;
1897         sport->port.membase = base;
1898         sport->port.type = PORT_IMX,
1899         sport->port.iotype = UPIO_MEM;
1900         sport->port.irq = rxirq;
1901         sport->port.fifosize = 32;
1902         sport->port.ops = &imx_pops;
1903         sport->port.rs485_config = imx_rs485_config;
1904         sport->port.rs485.flags =
1905                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1906         sport->port.flags = UPF_BOOT_AUTOCONF;
1907         init_timer(&sport->timer);
1908         sport->timer.function = imx_timeout;
1909         sport->timer.data     = (unsigned long)sport;
1910
1911         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1912         if (IS_ERR(sport->clk_ipg)) {
1913                 ret = PTR_ERR(sport->clk_ipg);
1914                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1915                 return ret;
1916         }
1917
1918         sport->clk_per = devm_clk_get(&pdev->dev, "per");
1919         if (IS_ERR(sport->clk_per)) {
1920                 ret = PTR_ERR(sport->clk_per);
1921                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1922                 return ret;
1923         }
1924
1925         sport->port.uartclk = clk_get_rate(sport->clk_per);
1926
1927         /* For register access, we only need to enable the ipg clock. */
1928         ret = clk_prepare_enable(sport->clk_ipg);
1929         if (ret)
1930                 return ret;
1931
1932         /* Disable interrupts before requesting them */
1933         reg = readl_relaxed(sport->port.membase + UCR1);
1934         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
1935                  UCR1_TXMPTYEN | UCR1_RTSDEN);
1936         writel_relaxed(reg, sport->port.membase + UCR1);
1937
1938         clk_disable_unprepare(sport->clk_ipg);
1939
1940         /*
1941          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1942          * chips only have one interrupt.
1943          */
1944         if (txirq > 0) {
1945                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1946                                        dev_name(&pdev->dev), sport);
1947                 if (ret)
1948                         return ret;
1949
1950                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1951                                        dev_name(&pdev->dev), sport);
1952                 if (ret)
1953                         return ret;
1954         } else {
1955                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1956                                        dev_name(&pdev->dev), sport);
1957                 if (ret)
1958                         return ret;
1959         }
1960
1961         imx_ports[sport->port.line] = sport;
1962
1963         platform_set_drvdata(pdev, sport);
1964
1965         return uart_add_one_port(&imx_reg, &sport->port);
1966 }
1967
1968 static int serial_imx_remove(struct platform_device *pdev)
1969 {
1970         struct imx_port *sport = platform_get_drvdata(pdev);
1971
1972         return uart_remove_one_port(&imx_reg, &sport->port);
1973 }
1974
1975 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
1976 {
1977         unsigned int val;
1978
1979         val = readl(sport->port.membase + UCR3);
1980         if (on)
1981                 val |= UCR3_AWAKEN;
1982         else
1983                 val &= ~UCR3_AWAKEN;
1984         writel(val, sport->port.membase + UCR3);
1985 }
1986
1987 static int imx_serial_port_suspend_noirq(struct device *dev)
1988 {
1989         struct platform_device *pdev = to_platform_device(dev);
1990         struct imx_port *sport = platform_get_drvdata(pdev);
1991         int ret;
1992
1993         ret = clk_enable(sport->clk_ipg);
1994         if (ret)
1995                 return ret;
1996
1997         /* Save necessary regs */
1998         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
1999         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2000         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2001         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2002         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2003         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2004         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2005         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2006         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2007         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2008
2009         clk_disable(sport->clk_ipg);
2010
2011         return 0;
2012 }
2013
2014 static int imx_serial_port_resume_noirq(struct device *dev)
2015 {
2016         struct platform_device *pdev = to_platform_device(dev);
2017         struct imx_port *sport = platform_get_drvdata(pdev);
2018         int ret;
2019
2020         ret = clk_enable(sport->clk_ipg);
2021         if (ret)
2022                 return ret;
2023
2024         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2025         writel(sport->saved_reg[5], sport->port.membase + UESC);
2026         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2027         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2028         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2029         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2030         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2031         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2032         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2033         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2034
2035         clk_disable(sport->clk_ipg);
2036
2037         return 0;
2038 }
2039
2040 static int imx_serial_port_suspend(struct device *dev)
2041 {
2042         struct platform_device *pdev = to_platform_device(dev);
2043         struct imx_port *sport = platform_get_drvdata(pdev);
2044
2045         /* enable wakeup from i.MX UART */
2046         serial_imx_enable_wakeup(sport, true);
2047
2048         uart_suspend_port(&imx_reg, &sport->port);
2049
2050         return 0;
2051 }
2052
2053 static int imx_serial_port_resume(struct device *dev)
2054 {
2055         struct platform_device *pdev = to_platform_device(dev);
2056         struct imx_port *sport = platform_get_drvdata(pdev);
2057
2058         /* disable wakeup from i.MX UART */
2059         serial_imx_enable_wakeup(sport, false);
2060
2061         uart_resume_port(&imx_reg, &sport->port);
2062
2063         return 0;
2064 }
2065
2066 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2067         .suspend_noirq = imx_serial_port_suspend_noirq,
2068         .resume_noirq = imx_serial_port_resume_noirq,
2069         .suspend = imx_serial_port_suspend,
2070         .resume = imx_serial_port_resume,
2071 };
2072
2073 static struct platform_driver serial_imx_driver = {
2074         .probe          = serial_imx_probe,
2075         .remove         = serial_imx_remove,
2076
2077         .id_table       = imx_uart_devtype,
2078         .driver         = {
2079                 .name   = "imx-uart",
2080                 .of_match_table = imx_uart_dt_ids,
2081                 .pm     = &imx_serial_port_pm_ops,
2082         },
2083 };
2084
2085 static int __init imx_serial_init(void)
2086 {
2087         int ret = uart_register_driver(&imx_reg);
2088
2089         if (ret)
2090                 return ret;
2091
2092         ret = platform_driver_register(&serial_imx_driver);
2093         if (ret != 0)
2094                 uart_unregister_driver(&imx_reg);
2095
2096         return ret;
2097 }
2098
2099 static void __exit imx_serial_exit(void)
2100 {
2101         platform_driver_unregister(&serial_imx_driver);
2102         uart_unregister_driver(&imx_reg);
2103 }
2104
2105 module_init(imx_serial_init);
2106 module_exit(imx_serial_exit);
2107
2108 MODULE_AUTHOR("Sascha Hauer");
2109 MODULE_DESCRIPTION("IMX generic serial port driver");
2110 MODULE_LICENSE("GPL");
2111 MODULE_ALIAS("platform:imx-uart");