1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale lpuart serial port driver
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
9 #include <linux/console.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dmapool.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_dma.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty_flip.h>
23 /* All registers are 8-bit width */
33 #define UARTMODEM 0x0d
34 #define UARTPFIFO 0x10
35 #define UARTCFIFO 0x11
36 #define UARTSFIFO 0x12
37 #define UARTTWFIFO 0x13
38 #define UARTTCFIFO 0x14
39 #define UARTRWFIFO 0x15
41 #define UARTBDH_LBKDIE 0x80
42 #define UARTBDH_RXEDGIE 0x40
43 #define UARTBDH_SBR_MASK 0x1f
45 #define UARTCR1_LOOPS 0x80
46 #define UARTCR1_RSRC 0x20
47 #define UARTCR1_M 0x10
48 #define UARTCR1_WAKE 0x08
49 #define UARTCR1_ILT 0x04
50 #define UARTCR1_PE 0x02
51 #define UARTCR1_PT 0x01
53 #define UARTCR2_TIE 0x80
54 #define UARTCR2_TCIE 0x40
55 #define UARTCR2_RIE 0x20
56 #define UARTCR2_ILIE 0x10
57 #define UARTCR2_TE 0x08
58 #define UARTCR2_RE 0x04
59 #define UARTCR2_RWU 0x02
60 #define UARTCR2_SBK 0x01
62 #define UARTSR1_TDRE 0x80
63 #define UARTSR1_TC 0x40
64 #define UARTSR1_RDRF 0x20
65 #define UARTSR1_IDLE 0x10
66 #define UARTSR1_OR 0x08
67 #define UARTSR1_NF 0x04
68 #define UARTSR1_FE 0x02
69 #define UARTSR1_PE 0x01
71 #define UARTCR3_R8 0x80
72 #define UARTCR3_T8 0x40
73 #define UARTCR3_TXDIR 0x20
74 #define UARTCR3_TXINV 0x10
75 #define UARTCR3_ORIE 0x08
76 #define UARTCR3_NEIE 0x04
77 #define UARTCR3_FEIE 0x02
78 #define UARTCR3_PEIE 0x01
80 #define UARTCR4_MAEN1 0x80
81 #define UARTCR4_MAEN2 0x40
82 #define UARTCR4_M10 0x20
83 #define UARTCR4_BRFA_MASK 0x1f
84 #define UARTCR4_BRFA_OFF 0
86 #define UARTCR5_TDMAS 0x80
87 #define UARTCR5_RDMAS 0x20
89 #define UARTMODEM_RXRTSE 0x08
90 #define UARTMODEM_TXRTSPOL 0x04
91 #define UARTMODEM_TXRTSE 0x02
92 #define UARTMODEM_TXCTSE 0x01
94 #define UARTPFIFO_TXFE 0x80
95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
96 #define UARTPFIFO_TXSIZE_OFF 4
97 #define UARTPFIFO_RXFE 0x08
98 #define UARTPFIFO_RXSIZE_OFF 0
100 #define UARTCFIFO_TXFLUSH 0x80
101 #define UARTCFIFO_RXFLUSH 0x40
102 #define UARTCFIFO_RXOFE 0x04
103 #define UARTCFIFO_TXOFE 0x02
104 #define UARTCFIFO_RXUFE 0x01
106 #define UARTSFIFO_TXEMPT 0x80
107 #define UARTSFIFO_RXEMPT 0x40
108 #define UARTSFIFO_RXOF 0x04
109 #define UARTSFIFO_TXOF 0x02
110 #define UARTSFIFO_RXUF 0x01
112 /* 32-bit register definition */
113 #define UARTBAUD 0x00
114 #define UARTSTAT 0x04
115 #define UARTCTRL 0x08
116 #define UARTDATA 0x0C
117 #define UARTMATCH 0x10
118 #define UARTMODIR 0x14
119 #define UARTFIFO 0x18
120 #define UARTWATER 0x1c
122 #define UARTBAUD_MAEN1 0x80000000
123 #define UARTBAUD_MAEN2 0x40000000
124 #define UARTBAUD_M10 0x20000000
125 #define UARTBAUD_TDMAE 0x00800000
126 #define UARTBAUD_RDMAE 0x00200000
127 #define UARTBAUD_MATCFG 0x00400000
128 #define UARTBAUD_BOTHEDGE 0x00020000
129 #define UARTBAUD_RESYNCDIS 0x00010000
130 #define UARTBAUD_LBKDIE 0x00008000
131 #define UARTBAUD_RXEDGIE 0x00004000
132 #define UARTBAUD_SBNS 0x00002000
133 #define UARTBAUD_SBR 0x00000000
134 #define UARTBAUD_SBR_MASK 0x1fff
135 #define UARTBAUD_OSR_MASK 0x1f
136 #define UARTBAUD_OSR_SHIFT 24
138 #define UARTSTAT_LBKDIF 0x80000000
139 #define UARTSTAT_RXEDGIF 0x40000000
140 #define UARTSTAT_MSBF 0x20000000
141 #define UARTSTAT_RXINV 0x10000000
142 #define UARTSTAT_RWUID 0x08000000
143 #define UARTSTAT_BRK13 0x04000000
144 #define UARTSTAT_LBKDE 0x02000000
145 #define UARTSTAT_RAF 0x01000000
146 #define UARTSTAT_TDRE 0x00800000
147 #define UARTSTAT_TC 0x00400000
148 #define UARTSTAT_RDRF 0x00200000
149 #define UARTSTAT_IDLE 0x00100000
150 #define UARTSTAT_OR 0x00080000
151 #define UARTSTAT_NF 0x00040000
152 #define UARTSTAT_FE 0x00020000
153 #define UARTSTAT_PE 0x00010000
154 #define UARTSTAT_MA1F 0x00008000
155 #define UARTSTAT_M21F 0x00004000
157 #define UARTCTRL_R8T9 0x80000000
158 #define UARTCTRL_R9T8 0x40000000
159 #define UARTCTRL_TXDIR 0x20000000
160 #define UARTCTRL_TXINV 0x10000000
161 #define UARTCTRL_ORIE 0x08000000
162 #define UARTCTRL_NEIE 0x04000000
163 #define UARTCTRL_FEIE 0x02000000
164 #define UARTCTRL_PEIE 0x01000000
165 #define UARTCTRL_TIE 0x00800000
166 #define UARTCTRL_TCIE 0x00400000
167 #define UARTCTRL_RIE 0x00200000
168 #define UARTCTRL_ILIE 0x00100000
169 #define UARTCTRL_TE 0x00080000
170 #define UARTCTRL_RE 0x00040000
171 #define UARTCTRL_RWU 0x00020000
172 #define UARTCTRL_SBK 0x00010000
173 #define UARTCTRL_MA1IE 0x00008000
174 #define UARTCTRL_MA2IE 0x00004000
175 #define UARTCTRL_IDLECFG 0x00000100
176 #define UARTCTRL_LOOPS 0x00000080
177 #define UARTCTRL_DOZEEN 0x00000040
178 #define UARTCTRL_RSRC 0x00000020
179 #define UARTCTRL_M 0x00000010
180 #define UARTCTRL_WAKE 0x00000008
181 #define UARTCTRL_ILT 0x00000004
182 #define UARTCTRL_PE 0x00000002
183 #define UARTCTRL_PT 0x00000001
185 #define UARTDATA_NOISY 0x00008000
186 #define UARTDATA_PARITYE 0x00004000
187 #define UARTDATA_FRETSC 0x00002000
188 #define UARTDATA_RXEMPT 0x00001000
189 #define UARTDATA_IDLINE 0x00000800
190 #define UARTDATA_MASK 0x3ff
192 #define UARTMODIR_IREN 0x00020000
193 #define UARTMODIR_TXCTSSRC 0x00000020
194 #define UARTMODIR_TXCTSC 0x00000010
195 #define UARTMODIR_RXRTSE 0x00000008
196 #define UARTMODIR_TXRTSPOL 0x00000004
197 #define UARTMODIR_TXRTSE 0x00000002
198 #define UARTMODIR_TXCTSE 0x00000001
200 #define UARTFIFO_TXEMPT 0x00800000
201 #define UARTFIFO_RXEMPT 0x00400000
202 #define UARTFIFO_TXOF 0x00020000
203 #define UARTFIFO_RXUF 0x00010000
204 #define UARTFIFO_TXFLUSH 0x00008000
205 #define UARTFIFO_RXFLUSH 0x00004000
206 #define UARTFIFO_TXOFE 0x00000200
207 #define UARTFIFO_RXUFE 0x00000100
208 #define UARTFIFO_TXFE 0x00000080
209 #define UARTFIFO_FIFOSIZE_MASK 0x7
210 #define UARTFIFO_TXSIZE_OFF 4
211 #define UARTFIFO_RXFE 0x00000008
212 #define UARTFIFO_RXSIZE_OFF 0
213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
215 #define UARTWATER_COUNT_MASK 0xff
216 #define UARTWATER_TXCNT_OFF 8
217 #define UARTWATER_RXCNT_OFF 24
218 #define UARTWATER_WATER_MASK 0xff
219 #define UARTWATER_TXWATER_OFF 0
220 #define UARTWATER_RXWATER_OFF 16
222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
223 #define DMA_RX_TIMEOUT (10)
225 #define DRIVER_NAME "fsl-lpuart"
226 #define DEV_NAME "ttyLP"
229 /* IMX lpuart has four extra unused regs located at the beginning */
230 #define IMX_REG_OFF 0x10
232 static DEFINE_IDA(fsl_lpuart_ida);
243 struct uart_port port;
244 enum lpuart_type devtype;
246 struct clk *baud_clk;
247 unsigned int txfifo_size;
248 unsigned int rxfifo_size;
250 bool lpuart_dma_tx_use;
251 bool lpuart_dma_rx_use;
252 struct dma_chan *dma_tx_chan;
253 struct dma_chan *dma_rx_chan;
254 struct dma_async_tx_descriptor *dma_tx_desc;
255 struct dma_async_tx_descriptor *dma_rx_desc;
256 dma_cookie_t dma_tx_cookie;
257 dma_cookie_t dma_rx_cookie;
258 unsigned int dma_tx_bytes;
259 unsigned int dma_rx_bytes;
260 bool dma_tx_in_progress;
261 unsigned int dma_rx_timeout;
262 struct timer_list lpuart_timer;
263 struct scatterlist rx_sgl, tx_sgl[2];
264 struct circ_buf rx_ring;
265 int rx_dma_rng_buf_len;
266 unsigned int dma_tx_nents;
267 wait_queue_head_t dma_wait;
271 struct lpuart_soc_data {
272 enum lpuart_type devtype;
277 static const struct lpuart_soc_data vf_data = {
278 .devtype = VF610_LPUART,
282 static const struct lpuart_soc_data ls1021a_data = {
283 .devtype = LS1021A_LPUART,
284 .iotype = UPIO_MEM32BE,
287 static const struct lpuart_soc_data ls1028a_data = {
288 .devtype = LS1028A_LPUART,
289 .iotype = UPIO_MEM32,
292 static struct lpuart_soc_data imx7ulp_data = {
293 .devtype = IMX7ULP_LPUART,
294 .iotype = UPIO_MEM32,
295 .reg_off = IMX_REG_OFF,
298 static struct lpuart_soc_data imx8qxp_data = {
299 .devtype = IMX8QXP_LPUART,
300 .iotype = UPIO_MEM32,
301 .reg_off = IMX_REG_OFF,
304 static const struct of_device_id lpuart_dt_ids[] = {
305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
314 /* Forward declare this for the dma callbacks*/
315 static void lpuart_dma_tx_complete(void *arg);
317 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
319 return (sport->devtype == LS1021A_LPUART ||
320 sport->devtype == LS1028A_LPUART);
323 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
325 return sport->devtype == IMX8QXP_LPUART;
328 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
330 switch (port->iotype) {
332 return readl(port->membase + off);
334 return ioread32be(port->membase + off);
340 static inline void lpuart32_write(struct uart_port *port, u32 val,
343 switch (port->iotype) {
345 writel(val, port->membase + off);
348 iowrite32be(val, port->membase + off);
353 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
358 ret = clk_prepare_enable(sport->ipg_clk);
362 ret = clk_prepare_enable(sport->baud_clk);
364 clk_disable_unprepare(sport->ipg_clk);
368 clk_disable_unprepare(sport->baud_clk);
369 clk_disable_unprepare(sport->ipg_clk);
375 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
377 if (is_imx8qxp_lpuart(sport))
378 return clk_get_rate(sport->baud_clk);
380 return clk_get_rate(sport->ipg_clk);
383 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
384 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
386 static void lpuart_stop_tx(struct uart_port *port)
390 temp = readb(port->membase + UARTCR2);
391 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
392 writeb(temp, port->membase + UARTCR2);
395 static void lpuart32_stop_tx(struct uart_port *port)
399 temp = lpuart32_read(port, UARTCTRL);
400 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
401 lpuart32_write(port, temp, UARTCTRL);
404 static void lpuart_stop_rx(struct uart_port *port)
408 temp = readb(port->membase + UARTCR2);
409 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
412 static void lpuart32_stop_rx(struct uart_port *port)
416 temp = lpuart32_read(port, UARTCTRL);
417 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
420 static void lpuart_dma_tx(struct lpuart_port *sport)
422 struct circ_buf *xmit = &sport->port.state->xmit;
423 struct scatterlist *sgl = sport->tx_sgl;
424 struct device *dev = sport->port.dev;
425 struct dma_chan *chan = sport->dma_tx_chan;
428 if (sport->dma_tx_in_progress)
431 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
433 if (xmit->tail < xmit->head || xmit->head == 0) {
434 sport->dma_tx_nents = 1;
435 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
437 sport->dma_tx_nents = 2;
438 sg_init_table(sgl, 2);
439 sg_set_buf(sgl, xmit->buf + xmit->tail,
440 UART_XMIT_SIZE - xmit->tail);
441 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
444 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
447 dev_err(dev, "DMA mapping error for TX.\n");
451 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
454 if (!sport->dma_tx_desc) {
455 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
457 dev_err(dev, "Cannot prepare TX slave DMA!\n");
461 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
462 sport->dma_tx_desc->callback_param = sport;
463 sport->dma_tx_in_progress = true;
464 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
465 dma_async_issue_pending(chan);
468 static bool lpuart_stopped_or_empty(struct uart_port *port)
470 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
473 static void lpuart_dma_tx_complete(void *arg)
475 struct lpuart_port *sport = arg;
476 struct scatterlist *sgl = &sport->tx_sgl[0];
477 struct circ_buf *xmit = &sport->port.state->xmit;
478 struct dma_chan *chan = sport->dma_tx_chan;
481 spin_lock_irqsave(&sport->port.lock, flags);
483 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
486 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
488 sport->port.icount.tx += sport->dma_tx_bytes;
489 sport->dma_tx_in_progress = false;
490 spin_unlock_irqrestore(&sport->port.lock, flags);
492 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
493 uart_write_wakeup(&sport->port);
495 if (waitqueue_active(&sport->dma_wait)) {
496 wake_up(&sport->dma_wait);
500 spin_lock_irqsave(&sport->port.lock, flags);
502 if (!lpuart_stopped_or_empty(&sport->port))
503 lpuart_dma_tx(sport);
505 spin_unlock_irqrestore(&sport->port.lock, flags);
508 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
510 switch (sport->port.iotype) {
512 return sport->port.mapbase + UARTDATA;
514 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
516 return sport->port.mapbase + UARTDR;
519 static int lpuart_dma_tx_request(struct uart_port *port)
521 struct lpuart_port *sport = container_of(port,
522 struct lpuart_port, port);
523 struct dma_slave_config dma_tx_sconfig = {};
526 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
527 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
528 dma_tx_sconfig.dst_maxburst = 1;
529 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
530 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
533 dev_err(sport->port.dev,
534 "DMA slave config failed, err = %d\n", ret);
541 static bool lpuart_is_32(struct lpuart_port *sport)
543 return sport->port.iotype == UPIO_MEM32 ||
544 sport->port.iotype == UPIO_MEM32BE;
547 static void lpuart_flush_buffer(struct uart_port *port)
549 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
550 struct dma_chan *chan = sport->dma_tx_chan;
553 if (sport->lpuart_dma_tx_use) {
554 if (sport->dma_tx_in_progress) {
555 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
556 sport->dma_tx_nents, DMA_TO_DEVICE);
557 sport->dma_tx_in_progress = false;
559 dmaengine_terminate_all(chan);
562 if (lpuart_is_32(sport)) {
563 val = lpuart32_read(&sport->port, UARTFIFO);
564 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
565 lpuart32_write(&sport->port, val, UARTFIFO);
567 val = readb(sport->port.membase + UARTCFIFO);
568 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
569 writeb(val, sport->port.membase + UARTCFIFO);
573 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
576 while (!(readb(port->membase + offset) & bit))
580 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
583 while (!(lpuart32_read(port, offset) & bit))
587 #if defined(CONFIG_CONSOLE_POLL)
589 static int lpuart_poll_init(struct uart_port *port)
591 struct lpuart_port *sport = container_of(port,
592 struct lpuart_port, port);
596 sport->port.fifosize = 0;
598 spin_lock_irqsave(&sport->port.lock, flags);
599 /* Disable Rx & Tx */
600 writeb(0, sport->port.membase + UARTCR2);
602 temp = readb(sport->port.membase + UARTPFIFO);
603 /* Enable Rx and Tx FIFO */
604 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
605 sport->port.membase + UARTPFIFO);
607 /* flush Tx and Rx FIFO */
608 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
609 sport->port.membase + UARTCFIFO);
611 /* explicitly clear RDRF */
612 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
613 readb(sport->port.membase + UARTDR);
614 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
617 writeb(0, sport->port.membase + UARTTWFIFO);
618 writeb(1, sport->port.membase + UARTRWFIFO);
620 /* Enable Rx and Tx */
621 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
622 spin_unlock_irqrestore(&sport->port.lock, flags);
627 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
630 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
631 writeb(c, port->membase + UARTDR);
634 static int lpuart_poll_get_char(struct uart_port *port)
636 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
639 return readb(port->membase + UARTDR);
642 static int lpuart32_poll_init(struct uart_port *port)
645 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
648 sport->port.fifosize = 0;
650 spin_lock_irqsave(&sport->port.lock, flags);
652 /* Disable Rx & Tx */
653 lpuart32_write(&sport->port, 0, UARTCTRL);
655 temp = lpuart32_read(&sport->port, UARTFIFO);
657 /* Enable Rx and Tx FIFO */
658 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
660 /* flush Tx and Rx FIFO */
661 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
663 /* explicitly clear RDRF */
664 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
665 lpuart32_read(&sport->port, UARTDATA);
666 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
669 /* Enable Rx and Tx */
670 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
671 spin_unlock_irqrestore(&sport->port.lock, flags);
676 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
678 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
679 lpuart32_write(port, c, UARTDATA);
682 static int lpuart32_poll_get_char(struct uart_port *port)
684 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
687 return lpuart32_read(port, UARTDATA);
691 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
693 struct circ_buf *xmit = &sport->port.state->xmit;
695 if (sport->port.x_char) {
696 writeb(sport->port.x_char, sport->port.membase + UARTDR);
697 sport->port.icount.tx++;
698 sport->port.x_char = 0;
702 if (lpuart_stopped_or_empty(&sport->port)) {
703 lpuart_stop_tx(&sport->port);
707 while (!uart_circ_empty(xmit) &&
708 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
709 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
710 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
711 sport->port.icount.tx++;
714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
715 uart_write_wakeup(&sport->port);
717 if (uart_circ_empty(xmit))
718 lpuart_stop_tx(&sport->port);
721 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
723 struct circ_buf *xmit = &sport->port.state->xmit;
726 if (sport->port.x_char) {
727 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
728 sport->port.icount.tx++;
729 sport->port.x_char = 0;
733 if (lpuart_stopped_or_empty(&sport->port)) {
734 lpuart32_stop_tx(&sport->port);
738 txcnt = lpuart32_read(&sport->port, UARTWATER);
739 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
740 txcnt &= UARTWATER_COUNT_MASK;
741 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
742 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
743 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
744 sport->port.icount.tx++;
745 txcnt = lpuart32_read(&sport->port, UARTWATER);
746 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
747 txcnt &= UARTWATER_COUNT_MASK;
750 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
751 uart_write_wakeup(&sport->port);
753 if (uart_circ_empty(xmit))
754 lpuart32_stop_tx(&sport->port);
757 static void lpuart_start_tx(struct uart_port *port)
759 struct lpuart_port *sport = container_of(port,
760 struct lpuart_port, port);
763 temp = readb(port->membase + UARTCR2);
764 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
766 if (sport->lpuart_dma_tx_use) {
767 if (!lpuart_stopped_or_empty(port))
768 lpuart_dma_tx(sport);
770 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
771 lpuart_transmit_buffer(sport);
775 static void lpuart32_start_tx(struct uart_port *port)
777 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
780 if (sport->lpuart_dma_tx_use) {
781 if (!lpuart_stopped_or_empty(port))
782 lpuart_dma_tx(sport);
784 temp = lpuart32_read(port, UARTCTRL);
785 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
787 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
788 lpuart32_transmit_buffer(sport);
792 /* return TIOCSER_TEMT when transmitter is not busy */
793 static unsigned int lpuart_tx_empty(struct uart_port *port)
795 struct lpuart_port *sport = container_of(port,
796 struct lpuart_port, port);
797 unsigned char sr1 = readb(port->membase + UARTSR1);
798 unsigned char sfifo = readb(port->membase + UARTSFIFO);
800 if (sport->dma_tx_in_progress)
803 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
809 static unsigned int lpuart32_tx_empty(struct uart_port *port)
811 struct lpuart_port *sport = container_of(port,
812 struct lpuart_port, port);
813 unsigned long stat = lpuart32_read(port, UARTSTAT);
814 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
816 if (sport->dma_tx_in_progress)
819 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
825 static void lpuart_txint(struct lpuart_port *sport)
827 spin_lock(&sport->port.lock);
828 lpuart_transmit_buffer(sport);
829 spin_unlock(&sport->port.lock);
832 static void lpuart_rxint(struct lpuart_port *sport)
834 unsigned int flg, ignored = 0, overrun = 0;
835 struct tty_port *port = &sport->port.state->port;
836 unsigned char rx, sr;
838 spin_lock(&sport->port.lock);
840 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
842 sport->port.icount.rx++;
844 * to clear the FE, OR, NF, FE, PE flags,
845 * read SR1 then read DR
847 sr = readb(sport->port.membase + UARTSR1);
848 rx = readb(sport->port.membase + UARTDR);
850 if (uart_prepare_sysrq_char(&sport->port, rx))
853 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
855 sport->port.icount.parity++;
856 else if (sr & UARTSR1_FE)
857 sport->port.icount.frame++;
862 if (sr & sport->port.ignore_status_mask) {
868 sr &= sport->port.read_status_mask;
872 else if (sr & UARTSR1_FE)
878 sport->port.sysrq = 0;
881 tty_insert_flip_char(port, rx, flg);
886 sport->port.icount.overrun += overrun;
889 * Overruns cause FIFO pointers to become missaligned.
890 * Flushing the receive FIFO reinitializes the pointers.
892 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
893 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
896 uart_unlock_and_check_sysrq(&sport->port);
898 tty_flip_buffer_push(port);
901 static void lpuart32_txint(struct lpuart_port *sport)
903 spin_lock(&sport->port.lock);
904 lpuart32_transmit_buffer(sport);
905 spin_unlock(&sport->port.lock);
908 static void lpuart32_rxint(struct lpuart_port *sport)
910 unsigned int flg, ignored = 0;
911 struct tty_port *port = &sport->port.state->port;
912 unsigned long rx, sr;
915 spin_lock(&sport->port.lock);
917 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
919 sport->port.icount.rx++;
921 * to clear the FE, OR, NF, FE, PE flags,
922 * read STAT then read DATA reg
924 sr = lpuart32_read(&sport->port, UARTSTAT);
925 rx = lpuart32_read(&sport->port, UARTDATA);
929 * The LPUART can't distinguish between a break and a framing error,
930 * thus we assume it is a break if the received data is zero.
932 is_break = (sr & UARTSTAT_FE) && !rx;
934 if (is_break && uart_handle_break(&sport->port))
937 if (uart_prepare_sysrq_char(&sport->port, rx))
940 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
941 if (sr & UARTSTAT_PE) {
943 sport->port.icount.brk++;
945 sport->port.icount.parity++;
946 } else if (sr & UARTSTAT_FE) {
947 sport->port.icount.frame++;
950 if (sr & UARTSTAT_OR)
951 sport->port.icount.overrun++;
953 if (sr & sport->port.ignore_status_mask) {
959 sr &= sport->port.read_status_mask;
961 if (sr & UARTSTAT_PE) {
966 } else if (sr & UARTSTAT_FE) {
970 if (sr & UARTSTAT_OR)
974 tty_insert_flip_char(port, rx, flg);
978 uart_unlock_and_check_sysrq(&sport->port);
980 tty_flip_buffer_push(port);
983 static irqreturn_t lpuart_int(int irq, void *dev_id)
985 struct lpuart_port *sport = dev_id;
988 sts = readb(sport->port.membase + UARTSR1);
990 /* SysRq, using dma, check for linebreak by framing err. */
991 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
992 readb(sport->port.membase + UARTDR);
993 uart_handle_break(&sport->port);
994 /* linebreak produces some garbage, removing it */
995 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
999 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1000 lpuart_rxint(sport);
1002 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1003 lpuart_txint(sport);
1008 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1010 struct lpuart_port *sport = dev_id;
1011 unsigned long sts, rxcount;
1013 sts = lpuart32_read(&sport->port, UARTSTAT);
1014 rxcount = lpuart32_read(&sport->port, UARTWATER);
1015 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1017 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1018 lpuart32_rxint(sport);
1020 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1021 lpuart32_txint(sport);
1023 lpuart32_write(&sport->port, sts, UARTSTAT);
1028 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1029 unsigned char *p, int count)
1032 if (*p && uart_handle_sysrq_char(port, *p))
1038 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1040 struct circ_buf *ring = &sport->rx_ring;
1043 if (ring->head < ring->tail) {
1044 count = sport->rx_sgl.length - ring->tail;
1045 lpuart_handle_sysrq_chars(&sport->port,
1046 ring->buf + ring->tail, count);
1050 if (ring->head > ring->tail) {
1051 count = ring->head - ring->tail;
1052 lpuart_handle_sysrq_chars(&sport->port,
1053 ring->buf + ring->tail, count);
1054 ring->tail = ring->head;
1058 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1060 struct tty_port *port = &sport->port.state->port;
1061 struct dma_tx_state state;
1062 enum dma_status dmastat;
1063 struct dma_chan *chan = sport->dma_rx_chan;
1064 struct circ_buf *ring = &sport->rx_ring;
1065 unsigned long flags;
1068 if (lpuart_is_32(sport)) {
1069 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1071 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1072 /* Read DR to clear the error flags */
1073 lpuart32_read(&sport->port, UARTDATA);
1075 if (sr & UARTSTAT_PE)
1076 sport->port.icount.parity++;
1077 else if (sr & UARTSTAT_FE)
1078 sport->port.icount.frame++;
1081 unsigned char sr = readb(sport->port.membase + UARTSR1);
1083 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1086 /* Disable receiver during this operation... */
1087 cr2 = readb(sport->port.membase + UARTCR2);
1089 writeb(cr2, sport->port.membase + UARTCR2);
1091 /* Read DR to clear the error flags */
1092 readb(sport->port.membase + UARTDR);
1094 if (sr & UARTSR1_PE)
1095 sport->port.icount.parity++;
1096 else if (sr & UARTSR1_FE)
1097 sport->port.icount.frame++;
1099 * At this point parity/framing error is
1100 * cleared However, since the DMA already read
1101 * the data register and we had to read it
1102 * again after reading the status register to
1103 * properly clear the flags, the FIFO actually
1104 * underflowed... This requires a clearing of
1107 if (readb(sport->port.membase + UARTSFIFO) &
1109 writeb(UARTSFIFO_RXUF,
1110 sport->port.membase + UARTSFIFO);
1111 writeb(UARTCFIFO_RXFLUSH,
1112 sport->port.membase + UARTCFIFO);
1116 writeb(cr2, sport->port.membase + UARTCR2);
1120 async_tx_ack(sport->dma_rx_desc);
1122 spin_lock_irqsave(&sport->port.lock, flags);
1124 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1125 if (dmastat == DMA_ERROR) {
1126 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1127 spin_unlock_irqrestore(&sport->port.lock, flags);
1131 /* CPU claims ownership of RX DMA buffer */
1132 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1136 * ring->head points to the end of data already written by the DMA.
1137 * ring->tail points to the beginning of data to be read by the
1139 * The current transfer size should not be larger than the dma buffer
1142 ring->head = sport->rx_sgl.length - state.residue;
1143 BUG_ON(ring->head > sport->rx_sgl.length);
1146 * Silent handling of keys pressed in the sysrq timeframe
1148 if (sport->port.sysrq) {
1149 lpuart_handle_sysrq(sport);
1154 * At this point ring->head may point to the first byte right after the
1155 * last byte of the dma buffer:
1156 * 0 <= ring->head <= sport->rx_sgl.length
1158 * However ring->tail must always points inside the dma buffer:
1159 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1161 * Since we use a ring buffer, we have to handle the case
1162 * where head is lower than tail. In such a case, we first read from
1163 * tail to the end of the buffer then reset tail.
1165 if (ring->head < ring->tail) {
1166 count = sport->rx_sgl.length - ring->tail;
1168 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1170 sport->port.icount.rx += count;
1173 /* Finally we read data from tail to head */
1174 if (ring->tail < ring->head) {
1175 count = ring->head - ring->tail;
1176 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1177 /* Wrap ring->head if needed */
1178 if (ring->head >= sport->rx_sgl.length)
1180 ring->tail = ring->head;
1181 sport->port.icount.rx += count;
1185 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1188 spin_unlock_irqrestore(&sport->port.lock, flags);
1190 tty_flip_buffer_push(port);
1191 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1194 static void lpuart_dma_rx_complete(void *arg)
1196 struct lpuart_port *sport = arg;
1198 lpuart_copy_rx_to_tty(sport);
1201 static void lpuart_timer_func(struct timer_list *t)
1203 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1205 lpuart_copy_rx_to_tty(sport);
1208 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1210 struct dma_slave_config dma_rx_sconfig = {};
1211 struct circ_buf *ring = &sport->rx_ring;
1214 struct tty_port *port = &sport->port.state->port;
1215 struct tty_struct *tty = port->tty;
1216 struct ktermios *termios = &tty->termios;
1217 struct dma_chan *chan = sport->dma_rx_chan;
1219 baud = tty_get_baud_rate(tty);
1221 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1222 if (termios->c_cflag & PARENB)
1226 * Calculate length of one DMA buffer size to keep latency below
1227 * 10ms at any baud rate.
1229 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1230 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1231 if (sport->rx_dma_rng_buf_len < 16)
1232 sport->rx_dma_rng_buf_len = 16;
1234 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1238 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1239 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1243 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1247 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1248 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1249 dma_rx_sconfig.src_maxburst = 1;
1250 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1251 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1254 dev_err(sport->port.dev,
1255 "DMA Rx slave config failed, err = %d\n", ret);
1259 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1260 sg_dma_address(&sport->rx_sgl),
1261 sport->rx_sgl.length,
1262 sport->rx_sgl.length / 2,
1264 DMA_PREP_INTERRUPT);
1265 if (!sport->dma_rx_desc) {
1266 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1270 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1271 sport->dma_rx_desc->callback_param = sport;
1272 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1273 dma_async_issue_pending(chan);
1275 if (lpuart_is_32(sport)) {
1276 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1278 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1280 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1281 sport->port.membase + UARTCR5);
1287 static void lpuart_dma_rx_free(struct uart_port *port)
1289 struct lpuart_port *sport = container_of(port,
1290 struct lpuart_port, port);
1291 struct dma_chan *chan = sport->dma_rx_chan;
1293 dmaengine_terminate_all(chan);
1294 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1295 kfree(sport->rx_ring.buf);
1296 sport->rx_ring.tail = 0;
1297 sport->rx_ring.head = 0;
1298 sport->dma_rx_desc = NULL;
1299 sport->dma_rx_cookie = -EINVAL;
1302 static int lpuart_config_rs485(struct uart_port *port,
1303 struct serial_rs485 *rs485)
1305 struct lpuart_port *sport = container_of(port,
1306 struct lpuart_port, port);
1308 u8 modem = readb(sport->port.membase + UARTMODEM) &
1309 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1310 writeb(modem, sport->port.membase + UARTMODEM);
1312 /* clear unsupported configurations */
1313 rs485->delay_rts_before_send = 0;
1314 rs485->delay_rts_after_send = 0;
1315 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1317 if (rs485->flags & SER_RS485_ENABLED) {
1318 /* Enable auto RS-485 RTS mode */
1319 modem |= UARTMODEM_TXRTSE;
1322 * RTS needs to be logic HIGH either during transfer _or_ after
1323 * transfer, other variants are not supported by the hardware.
1326 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1327 SER_RS485_RTS_AFTER_SEND)))
1328 rs485->flags |= SER_RS485_RTS_ON_SEND;
1330 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1331 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1332 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1335 * The hardware defaults to RTS logic HIGH while transfer.
1336 * Switch polarity in case RTS shall be logic HIGH
1338 * Note: UART is assumed to be active high.
1340 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1341 modem &= ~UARTMODEM_TXRTSPOL;
1342 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1343 modem |= UARTMODEM_TXRTSPOL;
1346 /* Store the new configuration */
1347 sport->port.rs485 = *rs485;
1349 writeb(modem, sport->port.membase + UARTMODEM);
1353 static int lpuart32_config_rs485(struct uart_port *port,
1354 struct serial_rs485 *rs485)
1356 struct lpuart_port *sport = container_of(port,
1357 struct lpuart_port, port);
1359 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1360 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1361 lpuart32_write(&sport->port, modem, UARTMODIR);
1363 /* clear unsupported configurations */
1364 rs485->delay_rts_before_send = 0;
1365 rs485->delay_rts_after_send = 0;
1366 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1368 if (rs485->flags & SER_RS485_ENABLED) {
1369 /* Enable auto RS-485 RTS mode */
1370 modem |= UARTMODEM_TXRTSE;
1373 * RTS needs to be logic HIGH either during transfer _or_ after
1374 * transfer, other variants are not supported by the hardware.
1377 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1378 SER_RS485_RTS_AFTER_SEND)))
1379 rs485->flags |= SER_RS485_RTS_ON_SEND;
1381 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1382 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1383 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1386 * The hardware defaults to RTS logic HIGH while transfer.
1387 * Switch polarity in case RTS shall be logic HIGH
1389 * Note: UART is assumed to be active high.
1391 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1392 modem &= ~UARTMODEM_TXRTSPOL;
1393 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1394 modem |= UARTMODEM_TXRTSPOL;
1397 /* Store the new configuration */
1398 sport->port.rs485 = *rs485;
1400 lpuart32_write(&sport->port, modem, UARTMODIR);
1404 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1406 unsigned int mctrl = 0;
1409 reg = readb(port->membase + UARTCR1);
1410 if (reg & UARTCR1_LOOPS)
1411 mctrl |= TIOCM_LOOP;
1416 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1418 unsigned int mctrl = 0;
1421 reg = lpuart32_read(port, UARTCTRL);
1422 if (reg & UARTCTRL_LOOPS)
1423 mctrl |= TIOCM_LOOP;
1428 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1432 reg = readb(port->membase + UARTCR1);
1434 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1435 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1436 if (mctrl & TIOCM_LOOP)
1437 reg |= UARTCR1_LOOPS;
1439 writeb(reg, port->membase + UARTCR1);
1442 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1446 reg = lpuart32_read(port, UARTCTRL);
1448 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1449 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1450 if (mctrl & TIOCM_LOOP)
1451 reg |= UARTCTRL_LOOPS;
1453 lpuart32_write(port, reg, UARTCTRL);
1456 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1460 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1462 if (break_state != 0)
1463 temp |= UARTCR2_SBK;
1465 writeb(temp, port->membase + UARTCR2);
1468 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1472 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1474 if (break_state != 0)
1475 temp |= UARTCTRL_SBK;
1477 lpuart32_write(port, temp, UARTCTRL);
1480 static void lpuart_setup_watermark(struct lpuart_port *sport)
1482 unsigned char val, cr2;
1483 unsigned char cr2_saved;
1485 cr2 = readb(sport->port.membase + UARTCR2);
1487 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1488 UARTCR2_RIE | UARTCR2_RE);
1489 writeb(cr2, sport->port.membase + UARTCR2);
1491 val = readb(sport->port.membase + UARTPFIFO);
1492 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1493 sport->port.membase + UARTPFIFO);
1495 /* flush Tx and Rx FIFO */
1496 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1497 sport->port.membase + UARTCFIFO);
1499 /* explicitly clear RDRF */
1500 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1501 readb(sport->port.membase + UARTDR);
1502 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1505 writeb(0, sport->port.membase + UARTTWFIFO);
1506 writeb(1, sport->port.membase + UARTRWFIFO);
1509 writeb(cr2_saved, sport->port.membase + UARTCR2);
1512 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1516 lpuart_setup_watermark(sport);
1518 cr2 = readb(sport->port.membase + UARTCR2);
1519 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1520 writeb(cr2, sport->port.membase + UARTCR2);
1523 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1525 unsigned long val, ctrl;
1526 unsigned long ctrl_saved;
1528 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1530 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1531 UARTCTRL_RIE | UARTCTRL_RE);
1532 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1534 /* enable FIFO mode */
1535 val = lpuart32_read(&sport->port, UARTFIFO);
1536 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1537 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1538 lpuart32_write(&sport->port, val, UARTFIFO);
1540 /* set the watermark */
1541 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1542 lpuart32_write(&sport->port, val, UARTWATER);
1545 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1548 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1552 lpuart32_setup_watermark(sport);
1554 temp = lpuart32_read(&sport->port, UARTCTRL);
1555 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1556 lpuart32_write(&sport->port, temp, UARTCTRL);
1559 static void rx_dma_timer_init(struct lpuart_port *sport)
1561 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1562 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1563 add_timer(&sport->lpuart_timer);
1566 static void lpuart_request_dma(struct lpuart_port *sport)
1568 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1569 if (IS_ERR(sport->dma_tx_chan)) {
1570 dev_dbg_once(sport->port.dev,
1571 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1572 PTR_ERR(sport->dma_tx_chan));
1573 sport->dma_tx_chan = NULL;
1576 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1577 if (IS_ERR(sport->dma_rx_chan)) {
1578 dev_dbg_once(sport->port.dev,
1579 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1580 PTR_ERR(sport->dma_rx_chan));
1581 sport->dma_rx_chan = NULL;
1585 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1590 if (uart_console(&sport->port))
1593 if (!sport->dma_tx_chan)
1596 ret = lpuart_dma_tx_request(&sport->port);
1600 init_waitqueue_head(&sport->dma_wait);
1601 sport->lpuart_dma_tx_use = true;
1602 if (lpuart_is_32(sport)) {
1603 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1604 lpuart32_write(&sport->port,
1605 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1607 writeb(readb(sport->port.membase + UARTCR5) |
1608 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1614 sport->lpuart_dma_tx_use = false;
1617 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1622 if (uart_console(&sport->port))
1625 if (!sport->dma_rx_chan)
1628 ret = lpuart_start_rx_dma(sport);
1632 /* set Rx DMA timeout */
1633 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1634 if (!sport->dma_rx_timeout)
1635 sport->dma_rx_timeout = 1;
1637 sport->lpuart_dma_rx_use = true;
1638 rx_dma_timer_init(sport);
1640 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1641 cr3 = readb(sport->port.membase + UARTCR3);
1642 cr3 |= UARTCR3_FEIE;
1643 writeb(cr3, sport->port.membase + UARTCR3);
1649 sport->lpuart_dma_rx_use = false;
1652 static int lpuart_startup(struct uart_port *port)
1654 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1655 unsigned long flags;
1658 /* determine FIFO size and enable FIFO mode */
1659 temp = readb(sport->port.membase + UARTPFIFO);
1661 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1662 UARTPFIFO_FIFOSIZE_MASK);
1663 sport->port.fifosize = sport->txfifo_size;
1665 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1666 UARTPFIFO_FIFOSIZE_MASK);
1668 lpuart_request_dma(sport);
1670 spin_lock_irqsave(&sport->port.lock, flags);
1672 lpuart_setup_watermark_enable(sport);
1674 lpuart_rx_dma_startup(sport);
1675 lpuart_tx_dma_startup(sport);
1677 spin_unlock_irqrestore(&sport->port.lock, flags);
1682 static void lpuart32_configure(struct lpuart_port *sport)
1686 if (sport->lpuart_dma_rx_use) {
1687 /* RXWATER must be 0 */
1688 temp = lpuart32_read(&sport->port, UARTWATER);
1689 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1690 lpuart32_write(&sport->port, temp, UARTWATER);
1692 temp = lpuart32_read(&sport->port, UARTCTRL);
1693 if (!sport->lpuart_dma_rx_use)
1694 temp |= UARTCTRL_RIE;
1695 if (!sport->lpuart_dma_tx_use)
1696 temp |= UARTCTRL_TIE;
1697 lpuart32_write(&sport->port, temp, UARTCTRL);
1700 static int lpuart32_startup(struct uart_port *port)
1702 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1703 unsigned long flags;
1706 /* determine FIFO size */
1707 temp = lpuart32_read(&sport->port, UARTFIFO);
1709 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1710 UARTFIFO_FIFOSIZE_MASK);
1711 sport->port.fifosize = sport->txfifo_size;
1713 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1714 UARTFIFO_FIFOSIZE_MASK);
1717 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1718 * Although they support the RX/TXSIZE fields, their encoding is
1719 * different. Eg the reference manual states 0b101 is 16 words.
1721 if (is_layerscape_lpuart(sport)) {
1722 sport->rxfifo_size = 16;
1723 sport->txfifo_size = 16;
1724 sport->port.fifosize = sport->txfifo_size;
1727 lpuart_request_dma(sport);
1729 spin_lock_irqsave(&sport->port.lock, flags);
1731 lpuart32_setup_watermark_enable(sport);
1733 lpuart_rx_dma_startup(sport);
1734 lpuart_tx_dma_startup(sport);
1736 lpuart32_configure(sport);
1738 spin_unlock_irqrestore(&sport->port.lock, flags);
1742 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1744 if (sport->lpuart_dma_rx_use) {
1745 del_timer_sync(&sport->lpuart_timer);
1746 lpuart_dma_rx_free(&sport->port);
1749 if (sport->lpuart_dma_tx_use) {
1750 if (wait_event_interruptible(sport->dma_wait,
1751 !sport->dma_tx_in_progress) != false) {
1752 sport->dma_tx_in_progress = false;
1753 dmaengine_terminate_all(sport->dma_tx_chan);
1757 if (sport->dma_tx_chan)
1758 dma_release_channel(sport->dma_tx_chan);
1759 if (sport->dma_rx_chan)
1760 dma_release_channel(sport->dma_rx_chan);
1763 static void lpuart_shutdown(struct uart_port *port)
1765 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1767 unsigned long flags;
1769 spin_lock_irqsave(&port->lock, flags);
1771 /* disable Rx/Tx and interrupts */
1772 temp = readb(port->membase + UARTCR2);
1773 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1774 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1775 writeb(temp, port->membase + UARTCR2);
1777 spin_unlock_irqrestore(&port->lock, flags);
1779 lpuart_dma_shutdown(sport);
1782 static void lpuart32_shutdown(struct uart_port *port)
1784 struct lpuart_port *sport =
1785 container_of(port, struct lpuart_port, port);
1787 unsigned long flags;
1789 spin_lock_irqsave(&port->lock, flags);
1791 /* disable Rx/Tx and interrupts */
1792 temp = lpuart32_read(port, UARTCTRL);
1793 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1794 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1795 lpuart32_write(port, temp, UARTCTRL);
1797 spin_unlock_irqrestore(&port->lock, flags);
1799 lpuart_dma_shutdown(sport);
1803 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1804 struct ktermios *old)
1806 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1807 unsigned long flags;
1808 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1810 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1811 unsigned int sbr, brfa;
1813 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1814 old_cr2 = readb(sport->port.membase + UARTCR2);
1815 cr3 = readb(sport->port.membase + UARTCR3);
1816 cr4 = readb(sport->port.membase + UARTCR4);
1817 bdh = readb(sport->port.membase + UARTBDH);
1818 modem = readb(sport->port.membase + UARTMODEM);
1820 * only support CS8 and CS7, and for CS7 must enable PE.
1827 while ((termios->c_cflag & CSIZE) != CS8 &&
1828 (termios->c_cflag & CSIZE) != CS7) {
1829 termios->c_cflag &= ~CSIZE;
1830 termios->c_cflag |= old_csize;
1834 if ((termios->c_cflag & CSIZE) == CS8 ||
1835 (termios->c_cflag & CSIZE) == CS7)
1836 cr1 = old_cr1 & ~UARTCR1_M;
1838 if (termios->c_cflag & CMSPAR) {
1839 if ((termios->c_cflag & CSIZE) != CS8) {
1840 termios->c_cflag &= ~CSIZE;
1841 termios->c_cflag |= CS8;
1847 * When auto RS-485 RTS mode is enabled,
1848 * hardware flow control need to be disabled.
1850 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1851 termios->c_cflag &= ~CRTSCTS;
1853 if (termios->c_cflag & CRTSCTS)
1854 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1856 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1858 termios->c_cflag &= ~CSTOPB;
1860 /* parity must be enabled when CS7 to match 8-bits format */
1861 if ((termios->c_cflag & CSIZE) == CS7)
1862 termios->c_cflag |= PARENB;
1864 if (termios->c_cflag & PARENB) {
1865 if (termios->c_cflag & CMSPAR) {
1867 if (termios->c_cflag & PARODD)
1873 if ((termios->c_cflag & CSIZE) == CS8)
1875 if (termios->c_cflag & PARODD)
1884 /* ask the core to calculate the divisor */
1885 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1888 * Need to update the Ring buffer length according to the selected
1889 * baud rate and restart Rx DMA path.
1891 * Since timer function acqures sport->port.lock, need to stop before
1892 * acquring same lock because otherwise del_timer_sync() can deadlock.
1894 if (old && sport->lpuart_dma_rx_use) {
1895 del_timer_sync(&sport->lpuart_timer);
1896 lpuart_dma_rx_free(&sport->port);
1899 spin_lock_irqsave(&sport->port.lock, flags);
1901 sport->port.read_status_mask = 0;
1902 if (termios->c_iflag & INPCK)
1903 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1904 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1905 sport->port.read_status_mask |= UARTSR1_FE;
1907 /* characters to ignore */
1908 sport->port.ignore_status_mask = 0;
1909 if (termios->c_iflag & IGNPAR)
1910 sport->port.ignore_status_mask |= UARTSR1_PE;
1911 if (termios->c_iflag & IGNBRK) {
1912 sport->port.ignore_status_mask |= UARTSR1_FE;
1914 * if we're ignoring parity and break indicators,
1915 * ignore overruns too (for real raw support).
1917 if (termios->c_iflag & IGNPAR)
1918 sport->port.ignore_status_mask |= UARTSR1_OR;
1921 /* update the per-port timeout */
1922 uart_update_timeout(port, termios->c_cflag, baud);
1924 /* wait transmit engin complete */
1925 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1927 /* disable transmit and receive */
1928 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1929 sport->port.membase + UARTCR2);
1931 sbr = sport->port.uartclk / (16 * baud);
1932 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1933 bdh &= ~UARTBDH_SBR_MASK;
1934 bdh |= (sbr >> 8) & 0x1F;
1935 cr4 &= ~UARTCR4_BRFA_MASK;
1936 brfa &= UARTCR4_BRFA_MASK;
1937 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1938 writeb(bdh, sport->port.membase + UARTBDH);
1939 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1940 writeb(cr3, sport->port.membase + UARTCR3);
1941 writeb(cr1, sport->port.membase + UARTCR1);
1942 writeb(modem, sport->port.membase + UARTMODEM);
1944 /* restore control register */
1945 writeb(old_cr2, sport->port.membase + UARTCR2);
1947 if (old && sport->lpuart_dma_rx_use) {
1948 if (!lpuart_start_rx_dma(sport))
1949 rx_dma_timer_init(sport);
1951 sport->lpuart_dma_rx_use = false;
1954 spin_unlock_irqrestore(&sport->port.lock, flags);
1957 static void __lpuart32_serial_setbrg(struct uart_port *port,
1958 unsigned int baudrate, bool use_rx_dma,
1961 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1962 u32 clk = port->uartclk;
1965 * The idea is to use the best OSR (over-sampling rate) possible.
1966 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1967 * Loop to find the best OSR value possible, one that generates minimum
1968 * baud_diff iterate through the rest of the supported values of OSR.
1970 * Calculation Formula:
1971 * Baud Rate = baud clock / ((OSR+1) × SBR)
1973 baud_diff = baudrate;
1977 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1978 /* calculate the temporary sbr value */
1979 tmp_sbr = (clk / (baudrate * tmp_osr));
1984 * calculate the baud rate difference based on the temporary
1985 * osr and sbr values
1987 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1989 /* select best values between sbr and sbr+1 */
1990 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1991 if (tmp_diff > (baudrate - tmp)) {
1992 tmp_diff = baudrate - tmp;
1996 if (tmp_sbr > UARTBAUD_SBR_MASK)
1999 if (tmp_diff <= baud_diff) {
2000 baud_diff = tmp_diff;
2009 /* handle buadrate outside acceptable rate */
2010 if (baud_diff > ((baudrate / 100) * 3))
2012 "unacceptable baud rate difference of more than 3%%\n");
2014 tmp = lpuart32_read(port, UARTBAUD);
2016 if ((osr > 3) && (osr < 8))
2017 tmp |= UARTBAUD_BOTHEDGE;
2019 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2020 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2022 tmp &= ~UARTBAUD_SBR_MASK;
2023 tmp |= sbr & UARTBAUD_SBR_MASK;
2026 tmp &= ~UARTBAUD_RDMAE;
2028 tmp &= ~UARTBAUD_TDMAE;
2030 lpuart32_write(port, tmp, UARTBAUD);
2033 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2034 unsigned int baudrate)
2036 __lpuart32_serial_setbrg(&sport->port, baudrate,
2037 sport->lpuart_dma_rx_use,
2038 sport->lpuart_dma_tx_use);
2043 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2044 struct ktermios *old)
2046 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2047 unsigned long flags;
2048 unsigned long ctrl, old_ctrl, modem;
2050 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2052 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2053 modem = lpuart32_read(&sport->port, UARTMODIR);
2055 * only support CS8 and CS7, and for CS7 must enable PE.
2062 while ((termios->c_cflag & CSIZE) != CS8 &&
2063 (termios->c_cflag & CSIZE) != CS7) {
2064 termios->c_cflag &= ~CSIZE;
2065 termios->c_cflag |= old_csize;
2069 if ((termios->c_cflag & CSIZE) == CS8 ||
2070 (termios->c_cflag & CSIZE) == CS7)
2071 ctrl = old_ctrl & ~UARTCTRL_M;
2073 if (termios->c_cflag & CMSPAR) {
2074 if ((termios->c_cflag & CSIZE) != CS8) {
2075 termios->c_cflag &= ~CSIZE;
2076 termios->c_cflag |= CS8;
2082 * When auto RS-485 RTS mode is enabled,
2083 * hardware flow control need to be disabled.
2085 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2086 termios->c_cflag &= ~CRTSCTS;
2088 if (termios->c_cflag & CRTSCTS) {
2089 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2091 termios->c_cflag &= ~CRTSCTS;
2092 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2095 if (termios->c_cflag & CSTOPB)
2096 termios->c_cflag &= ~CSTOPB;
2098 /* parity must be enabled when CS7 to match 8-bits format */
2099 if ((termios->c_cflag & CSIZE) == CS7)
2100 termios->c_cflag |= PARENB;
2102 if ((termios->c_cflag & PARENB)) {
2103 if (termios->c_cflag & CMSPAR) {
2104 ctrl &= ~UARTCTRL_PE;
2107 ctrl |= UARTCTRL_PE;
2108 if ((termios->c_cflag & CSIZE) == CS8)
2110 if (termios->c_cflag & PARODD)
2111 ctrl |= UARTCTRL_PT;
2113 ctrl &= ~UARTCTRL_PT;
2116 ctrl &= ~UARTCTRL_PE;
2119 /* ask the core to calculate the divisor */
2120 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2123 * Need to update the Ring buffer length according to the selected
2124 * baud rate and restart Rx DMA path.
2126 * Since timer function acqures sport->port.lock, need to stop before
2127 * acquring same lock because otherwise del_timer_sync() can deadlock.
2129 if (old && sport->lpuart_dma_rx_use) {
2130 del_timer_sync(&sport->lpuart_timer);
2131 lpuart_dma_rx_free(&sport->port);
2134 spin_lock_irqsave(&sport->port.lock, flags);
2136 sport->port.read_status_mask = 0;
2137 if (termios->c_iflag & INPCK)
2138 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2139 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2140 sport->port.read_status_mask |= UARTSTAT_FE;
2142 /* characters to ignore */
2143 sport->port.ignore_status_mask = 0;
2144 if (termios->c_iflag & IGNPAR)
2145 sport->port.ignore_status_mask |= UARTSTAT_PE;
2146 if (termios->c_iflag & IGNBRK) {
2147 sport->port.ignore_status_mask |= UARTSTAT_FE;
2149 * if we're ignoring parity and break indicators,
2150 * ignore overruns too (for real raw support).
2152 if (termios->c_iflag & IGNPAR)
2153 sport->port.ignore_status_mask |= UARTSTAT_OR;
2156 /* update the per-port timeout */
2157 uart_update_timeout(port, termios->c_cflag, baud);
2159 /* wait transmit engin complete */
2160 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2162 /* disable transmit and receive */
2163 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2166 lpuart32_serial_setbrg(sport, baud);
2167 lpuart32_write(&sport->port, modem, UARTMODIR);
2168 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2169 /* restore control register */
2171 if (old && sport->lpuart_dma_rx_use) {
2172 if (!lpuart_start_rx_dma(sport))
2173 rx_dma_timer_init(sport);
2175 sport->lpuart_dma_rx_use = false;
2178 spin_unlock_irqrestore(&sport->port.lock, flags);
2181 static const char *lpuart_type(struct uart_port *port)
2183 return "FSL_LPUART";
2186 static void lpuart_release_port(struct uart_port *port)
2191 static int lpuart_request_port(struct uart_port *port)
2196 /* configure/autoconfigure the port */
2197 static void lpuart_config_port(struct uart_port *port, int flags)
2199 if (flags & UART_CONFIG_TYPE)
2200 port->type = PORT_LPUART;
2203 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2207 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2209 if (port->irq != ser->irq)
2211 if (ser->io_type != UPIO_MEM)
2213 if (port->uartclk / 16 != ser->baud_base)
2215 if (port->iobase != ser->port)
2222 static const struct uart_ops lpuart_pops = {
2223 .tx_empty = lpuart_tx_empty,
2224 .set_mctrl = lpuart_set_mctrl,
2225 .get_mctrl = lpuart_get_mctrl,
2226 .stop_tx = lpuart_stop_tx,
2227 .start_tx = lpuart_start_tx,
2228 .stop_rx = lpuart_stop_rx,
2229 .break_ctl = lpuart_break_ctl,
2230 .startup = lpuart_startup,
2231 .shutdown = lpuart_shutdown,
2232 .set_termios = lpuart_set_termios,
2233 .type = lpuart_type,
2234 .request_port = lpuart_request_port,
2235 .release_port = lpuart_release_port,
2236 .config_port = lpuart_config_port,
2237 .verify_port = lpuart_verify_port,
2238 .flush_buffer = lpuart_flush_buffer,
2239 #if defined(CONFIG_CONSOLE_POLL)
2240 .poll_init = lpuart_poll_init,
2241 .poll_get_char = lpuart_poll_get_char,
2242 .poll_put_char = lpuart_poll_put_char,
2246 static const struct uart_ops lpuart32_pops = {
2247 .tx_empty = lpuart32_tx_empty,
2248 .set_mctrl = lpuart32_set_mctrl,
2249 .get_mctrl = lpuart32_get_mctrl,
2250 .stop_tx = lpuart32_stop_tx,
2251 .start_tx = lpuart32_start_tx,
2252 .stop_rx = lpuart32_stop_rx,
2253 .break_ctl = lpuart32_break_ctl,
2254 .startup = lpuart32_startup,
2255 .shutdown = lpuart32_shutdown,
2256 .set_termios = lpuart32_set_termios,
2257 .type = lpuart_type,
2258 .request_port = lpuart_request_port,
2259 .release_port = lpuart_release_port,
2260 .config_port = lpuart_config_port,
2261 .verify_port = lpuart_verify_port,
2262 .flush_buffer = lpuart_flush_buffer,
2263 #if defined(CONFIG_CONSOLE_POLL)
2264 .poll_init = lpuart32_poll_init,
2265 .poll_get_char = lpuart32_poll_get_char,
2266 .poll_put_char = lpuart32_poll_put_char,
2270 static struct lpuart_port *lpuart_ports[UART_NR];
2272 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2273 static void lpuart_console_putchar(struct uart_port *port, int ch)
2275 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2276 writeb(ch, port->membase + UARTDR);
2279 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2281 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2282 lpuart32_write(port, ch, UARTDATA);
2286 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2288 struct lpuart_port *sport = lpuart_ports[co->index];
2289 unsigned char old_cr2, cr2;
2290 unsigned long flags;
2293 if (oops_in_progress)
2294 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2296 spin_lock_irqsave(&sport->port.lock, flags);
2298 /* first save CR2 and then disable interrupts */
2299 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2300 cr2 |= UARTCR2_TE | UARTCR2_RE;
2301 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2302 writeb(cr2, sport->port.membase + UARTCR2);
2304 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2306 /* wait for transmitter finish complete and restore CR2 */
2307 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2309 writeb(old_cr2, sport->port.membase + UARTCR2);
2312 spin_unlock_irqrestore(&sport->port.lock, flags);
2316 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2318 struct lpuart_port *sport = lpuart_ports[co->index];
2319 unsigned long old_cr, cr;
2320 unsigned long flags;
2323 if (oops_in_progress)
2324 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2326 spin_lock_irqsave(&sport->port.lock, flags);
2328 /* first save CR2 and then disable interrupts */
2329 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2330 cr |= UARTCTRL_TE | UARTCTRL_RE;
2331 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2332 lpuart32_write(&sport->port, cr, UARTCTRL);
2334 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2336 /* wait for transmitter finish complete and restore CR2 */
2337 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2339 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2342 spin_unlock_irqrestore(&sport->port.lock, flags);
2346 * if the port was already initialised (eg, by a boot loader),
2347 * try to determine the current setup.
2350 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2351 int *parity, int *bits)
2353 unsigned char cr, bdh, bdl, brfa;
2354 unsigned int sbr, uartclk, baud_raw;
2356 cr = readb(sport->port.membase + UARTCR2);
2357 cr &= UARTCR2_TE | UARTCR2_RE;
2361 /* ok, the port was enabled */
2363 cr = readb(sport->port.membase + UARTCR1);
2366 if (cr & UARTCR1_PE) {
2367 if (cr & UARTCR1_PT)
2378 bdh = readb(sport->port.membase + UARTBDH);
2379 bdh &= UARTBDH_SBR_MASK;
2380 bdl = readb(sport->port.membase + UARTBDL);
2384 brfa = readb(sport->port.membase + UARTCR4);
2385 brfa &= UARTCR4_BRFA_MASK;
2387 uartclk = lpuart_get_baud_clk_rate(sport);
2389 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2391 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2393 if (*baud != baud_raw)
2394 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2395 "from %d to %d\n", baud_raw, *baud);
2399 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2400 int *parity, int *bits)
2402 unsigned long cr, bd;
2403 unsigned int sbr, uartclk, baud_raw;
2405 cr = lpuart32_read(&sport->port, UARTCTRL);
2406 cr &= UARTCTRL_TE | UARTCTRL_RE;
2410 /* ok, the port was enabled */
2412 cr = lpuart32_read(&sport->port, UARTCTRL);
2415 if (cr & UARTCTRL_PE) {
2416 if (cr & UARTCTRL_PT)
2422 if (cr & UARTCTRL_M)
2427 bd = lpuart32_read(&sport->port, UARTBAUD);
2428 bd &= UARTBAUD_SBR_MASK;
2433 uartclk = lpuart_get_baud_clk_rate(sport);
2435 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2437 baud_raw = uartclk / (16 * sbr);
2439 if (*baud != baud_raw)
2440 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2441 "from %d to %d\n", baud_raw, *baud);
2444 static int __init lpuart_console_setup(struct console *co, char *options)
2446 struct lpuart_port *sport;
2453 * check whether an invalid uart number has been specified, and
2454 * if so, search for the first available port that does have
2457 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2460 sport = lpuart_ports[co->index];
2465 uart_parse_options(options, &baud, &parity, &bits, &flow);
2467 if (lpuart_is_32(sport))
2468 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2470 lpuart_console_get_options(sport, &baud, &parity, &bits);
2472 if (lpuart_is_32(sport))
2473 lpuart32_setup_watermark(sport);
2475 lpuart_setup_watermark(sport);
2477 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2480 static struct uart_driver lpuart_reg;
2481 static struct console lpuart_console = {
2483 .write = lpuart_console_write,
2484 .device = uart_console_device,
2485 .setup = lpuart_console_setup,
2486 .flags = CON_PRINTBUFFER,
2488 .data = &lpuart_reg,
2491 static struct console lpuart32_console = {
2493 .write = lpuart32_console_write,
2494 .device = uart_console_device,
2495 .setup = lpuart_console_setup,
2496 .flags = CON_PRINTBUFFER,
2498 .data = &lpuart_reg,
2501 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2503 struct earlycon_device *dev = con->data;
2505 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2508 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2510 struct earlycon_device *dev = con->data;
2512 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2515 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2518 if (!device->port.membase)
2521 device->con->write = lpuart_early_write;
2525 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2528 if (!device->port.membase)
2531 if (device->port.iotype != UPIO_MEM32)
2532 device->port.iotype = UPIO_MEM32BE;
2534 device->con->write = lpuart32_early_write;
2538 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2543 if (!device->port.membase)
2546 device->port.iotype = UPIO_MEM32;
2547 device->con->write = lpuart32_early_write;
2549 /* set the baudrate */
2550 if (device->port.uartclk && device->baud)
2551 __lpuart32_serial_setbrg(&device->port, device->baud,
2554 /* enable transmitter */
2555 cr = lpuart32_read(&device->port, UARTCTRL);
2557 lpuart32_write(&device->port, cr, UARTCTRL);
2562 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2565 if (!device->port.membase)
2568 device->port.iotype = UPIO_MEM32;
2569 device->port.membase += IMX_REG_OFF;
2570 device->con->write = lpuart32_early_write;
2574 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2575 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2576 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2577 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2578 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2579 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2581 #define LPUART_CONSOLE (&lpuart_console)
2582 #define LPUART32_CONSOLE (&lpuart32_console)
2584 #define LPUART_CONSOLE NULL
2585 #define LPUART32_CONSOLE NULL
2588 static struct uart_driver lpuart_reg = {
2589 .owner = THIS_MODULE,
2590 .driver_name = DRIVER_NAME,
2591 .dev_name = DEV_NAME,
2592 .nr = ARRAY_SIZE(lpuart_ports),
2593 .cons = LPUART_CONSOLE,
2596 static int lpuart_probe(struct platform_device *pdev)
2598 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2599 struct device_node *np = pdev->dev.of_node;
2600 struct lpuart_port *sport;
2601 struct resource *res;
2604 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2609 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2610 if (IS_ERR(sport->port.membase))
2611 return PTR_ERR(sport->port.membase);
2613 sport->port.membase += sdata->reg_off;
2614 sport->port.mapbase = res->start;
2615 sport->port.dev = &pdev->dev;
2616 sport->port.type = PORT_LPUART;
2617 sport->devtype = sdata->devtype;
2618 ret = platform_get_irq(pdev, 0);
2621 sport->port.irq = ret;
2622 sport->port.iotype = sdata->iotype;
2623 if (lpuart_is_32(sport))
2624 sport->port.ops = &lpuart32_pops;
2626 sport->port.ops = &lpuart_pops;
2627 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2628 sport->port.flags = UPF_BOOT_AUTOCONF;
2630 if (lpuart_is_32(sport))
2631 sport->port.rs485_config = lpuart32_config_rs485;
2633 sport->port.rs485_config = lpuart_config_rs485;
2635 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2636 if (IS_ERR(sport->ipg_clk)) {
2637 ret = PTR_ERR(sport->ipg_clk);
2638 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2642 sport->baud_clk = NULL;
2643 if (is_imx8qxp_lpuart(sport)) {
2644 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2645 if (IS_ERR(sport->baud_clk)) {
2646 ret = PTR_ERR(sport->baud_clk);
2647 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2652 ret = of_alias_get_id(np, "serial");
2654 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2656 dev_err(&pdev->dev, "port line is full, add device failed\n");
2659 sport->id_allocated = true;
2661 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2662 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2664 goto failed_out_of_range;
2666 sport->port.line = ret;
2668 ret = lpuart_enable_clks(sport);
2670 goto failed_clock_enable;
2671 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2673 lpuart_ports[sport->port.line] = sport;
2675 platform_set_drvdata(pdev, &sport->port);
2677 if (lpuart_is_32(sport)) {
2678 lpuart_reg.cons = LPUART32_CONSOLE;
2679 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2680 DRIVER_NAME, sport);
2682 lpuart_reg.cons = LPUART_CONSOLE;
2683 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2684 DRIVER_NAME, sport);
2688 goto failed_irq_request;
2690 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2692 goto failed_attach_port;
2694 ret = uart_get_rs485_mode(&sport->port);
2696 goto failed_get_rs485;
2698 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2699 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2701 if (sport->port.rs485.delay_rts_before_send ||
2702 sport->port.rs485.delay_rts_after_send)
2703 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2705 sport->port.rs485_config(&sport->port, &sport->port.rs485);
2712 lpuart_disable_clks(sport);
2713 failed_clock_enable:
2714 failed_out_of_range:
2715 if (sport->id_allocated)
2716 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2720 static int lpuart_remove(struct platform_device *pdev)
2722 struct lpuart_port *sport = platform_get_drvdata(pdev);
2724 uart_remove_one_port(&lpuart_reg, &sport->port);
2726 if (sport->id_allocated)
2727 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2729 lpuart_disable_clks(sport);
2731 if (sport->dma_tx_chan)
2732 dma_release_channel(sport->dma_tx_chan);
2734 if (sport->dma_rx_chan)
2735 dma_release_channel(sport->dma_rx_chan);
2740 static int __maybe_unused lpuart_suspend(struct device *dev)
2742 struct lpuart_port *sport = dev_get_drvdata(dev);
2746 if (lpuart_is_32(sport)) {
2747 /* disable Rx/Tx and interrupts */
2748 temp = lpuart32_read(&sport->port, UARTCTRL);
2749 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2750 lpuart32_write(&sport->port, temp, UARTCTRL);
2752 /* disable Rx/Tx and interrupts */
2753 temp = readb(sport->port.membase + UARTCR2);
2754 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2755 writeb(temp, sport->port.membase + UARTCR2);
2758 uart_suspend_port(&lpuart_reg, &sport->port);
2760 /* uart_suspend_port() might set wakeup flag */
2761 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2763 if (sport->lpuart_dma_rx_use) {
2765 * EDMA driver during suspend will forcefully release any
2766 * non-idle DMA channels. If port wakeup is enabled or if port
2767 * is console port or 'no_console_suspend' is set the Rx DMA
2768 * cannot resume as as expected, hence gracefully release the
2769 * Rx DMA path before suspend and start Rx DMA path on resume.
2772 del_timer_sync(&sport->lpuart_timer);
2773 lpuart_dma_rx_free(&sport->port);
2776 /* Disable Rx DMA to use UART port as wakeup source */
2777 if (lpuart_is_32(sport)) {
2778 temp = lpuart32_read(&sport->port, UARTBAUD);
2779 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2782 writeb(readb(sport->port.membase + UARTCR5) &
2783 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2787 if (sport->lpuart_dma_tx_use) {
2788 sport->dma_tx_in_progress = false;
2789 dmaengine_terminate_all(sport->dma_tx_chan);
2792 if (sport->port.suspended && !irq_wake)
2793 lpuart_disable_clks(sport);
2798 static int __maybe_unused lpuart_resume(struct device *dev)
2800 struct lpuart_port *sport = dev_get_drvdata(dev);
2801 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2803 if (sport->port.suspended && !irq_wake)
2804 lpuart_enable_clks(sport);
2806 if (lpuart_is_32(sport))
2807 lpuart32_setup_watermark_enable(sport);
2809 lpuart_setup_watermark_enable(sport);
2811 if (sport->lpuart_dma_rx_use) {
2813 if (!lpuart_start_rx_dma(sport))
2814 rx_dma_timer_init(sport);
2816 sport->lpuart_dma_rx_use = false;
2820 lpuart_tx_dma_startup(sport);
2822 if (lpuart_is_32(sport))
2823 lpuart32_configure(sport);
2825 uart_resume_port(&lpuart_reg, &sport->port);
2830 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2832 static struct platform_driver lpuart_driver = {
2833 .probe = lpuart_probe,
2834 .remove = lpuart_remove,
2836 .name = "fsl-lpuart",
2837 .of_match_table = lpuart_dt_ids,
2838 .pm = &lpuart_pm_ops,
2842 static int __init lpuart_serial_init(void)
2844 int ret = uart_register_driver(&lpuart_reg);
2849 ret = platform_driver_register(&lpuart_driver);
2851 uart_unregister_driver(&lpuart_reg);
2856 static void __exit lpuart_serial_exit(void)
2858 ida_destroy(&fsl_lpuart_ida);
2859 platform_driver_unregister(&lpuart_driver);
2860 uart_unregister_driver(&lpuart_reg);
2863 module_init(lpuart_serial_init);
2864 module_exit(lpuart_serial_exit);
2866 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2867 MODULE_LICENSE("GPL v2");